Signal processing circuit and control device

Abstract

To provide a signal processing circuit and a control device, capable of restricting occurrence of chattering on output to a microcomputer.SOLUTION: A signal processing circuit according to an embodiment includes a comparator, a first path, a second path, and a holding circuit. The comparator shapes a detection signal in sinusoidal wave inputted from a sensor to a rectangular wave. The first path outputs an output signal of the comparator to a microcomputer. The second path blanches from the first path, differentiates the output signal of the comparator, and feeds it back to an input side of the comparator. The holding circuit is provided on the first path, holds a state of the output signal of the comparator until the state of the signal on the second path inverts if the state of the output signal of the comparator inverts, and outputs the output signal at the held state if the state of the signal on the second path inverts.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The disclosed embodiments relate to a signal processing circuit and a control device. [Background technology]

[0002] To detect the rotational state of an engine, etc., a sensor whose output changes in a sinusoidal manner, such as an MPU (Magnetic Pick Up) sensor that detects the state of the object being measured, is used. In order to use a microcomputer to detect the state of the object being measured from the output of such a sensor, the sensor output must be shaped into a square wave by a comparator and then input to the microcomputer.

[0003] In this case, to prevent chattering, the output of the comparator is differentiated via a path separate from the output from the comparator to the microcomputer, and positive feedback is provided to the input side of the comparator, thereby adding hysteresis to the output of the sensor (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-154094 Summary of the Invention [Problem to be solved by the invention]

[0005] However, when the comparator output shows a response that inverts, a discrepancy may occur between the output response to the microcomputer and the output response for hysteresis. This is caused by the response speed and individual differences of the components present in the output path from the comparator to the microcomputer and the output path from the comparator to the hysteresis setting.

[0006] If the output response to the microcomputer is faster than the output response for hysteresis, and noise is superimposed on the input of the comparator, chattering will occur in the output to the microcomputer before hysteresis is applied.

[0007] One aspect of the embodiment has been made in view of the above, and aims to provide a signal processing circuit and a control device that can suppress the occurrence of chattering in the output to a microcomputer. [Means for solving the problem]

[0008] According to one embodiment, a signal processing circuit includes a comparator, a first path, a second path, and a holding circuit. The comparator shapes a sine-wave detection signal input from a sensor into a rectangular wave. The first path outputs an output signal of the comparator to a microcomputer. The second path branches off from the first path, differentiates the output signal of the comparator, and feeds the differentiated signal back to the input side of the comparator. The holding circuit is provided in the first path, and when the state of the output signal of the comparator is inverted, holds the state of the output signal of the comparator until the state of the signal of the second path is inverted. When the state of the signal of the second path is inverted, the holding circuit outputs the output signal in the held state. [Effects of the Invention]

[0009] In a signal processing circuit and a control device according to one aspect of the embodiment, the output state to the microcomputer is held by a holding circuit until the output state for hysteresis is inverted and hysteresis occurs, thereby preventing chattering from occurring in the output to the microcomputer. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a circuit diagram showing a signal processing circuit according to a comparative example. [Figure 2] FIG. 2 is a diagram illustrating the operation of a signal processing circuit according to a comparative example. [Figure 3] FIG. 3 is a diagram illustrating the operation of a signal processing circuit according to a comparative example. [Figure 4]FIG. 4 is an explanatory diagram showing transitions of the voltages of the sensor signal, the input terminal, the first output terminal, and the second output terminal of a signal processing circuit according to a comparative example. [Figure 5] FIG. 5 is an explanatory diagram showing transitions of the voltages of the sensor signal, the input terminal, the first output terminal, and the second output terminal of a signal processing circuit according to a comparative example. [Figure 6] FIG. 6 is an explanatory diagram showing transitions of the voltages of the sensor signal, the input terminal, the first output terminal, and the second output terminal of a signal processing circuit according to a comparative example. [Figure 7] FIG. 7 is a circuit diagram showing a control device according to the embodiment. [Figure 8] FIG. 8 is a diagram illustrating the operation of the signal processing circuit according to the embodiment. [Figure 9] FIG. 9 is a diagram illustrating the operation of the signal processing circuit according to the embodiment. [Figure 10] FIG. 10 is an explanatory diagram showing transitions of the voltages of the sensor signal, the input terminal, the first output terminal, and the second output terminal of the signal processing circuit according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of a signal processing circuit and a control device will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the embodiments described below. In the following, in order to clarify the characteristics of the signal processing circuit and the control device according to the embodiments, a general signal processing circuit according to a comparative example will be described first, followed by a description of the signal processing circuit and the control device according to the embodiments.

[0012] [1. Configuration of signal processing circuit related to comparison] 1 is a circuit diagram showing a signal processing circuit 100 according to a comparative example. The signal processing circuit 100 according to the comparative example is a circuit that is mounted on, for example, a vehicle, and that shapes a sine wave detection signal input from a sensor into a rectangular wave and outputs the square wave to a microcomputer (hereinafter referred to as "microcomputer").

[0013] The sensor is, for example, an MPU (Magnetic Pick Up) sensor. The MPU sensor outputs a sine wave detection signal corresponding to the state of the engine, such as the crank angle and cam position, to the signal processing circuit 100. The microcomputer 10 detects the state of the engine based on the rectangular wave detection signal input from the sensor via the signal processing circuit 100.

[0014] 1, the signal processing circuit 100 includes an input terminal IN, a first output terminal OUT1, and a second output terminal OUT2. A detection signal (hereinafter referred to as a "sensor signal") is input to the input terminal IN from a sensor via a first resistor R1.

[0015] The first output terminal OUT1 is connected to the input terminal IN via a differentiating circuit 101 consisting of a capacitor C and a second resistor R2 connected in series. A power supply line that supplies a power supply voltage VCC is connected to a connection line that connects the first output terminal OUT1 and the capacitor C via a third resistor R3. The second output terminal OUT2 is connected to an input terminal of the microcomputer 10.

[0016] The signal processing circuit 100 also includes a comparator CMP, a first NOT circuit N1, a second NOT circuit N2, a first transistor TR1, a second transistor TR2, a fourth resistor R4, and a fifth resistor R5.

[0017] The comparator CMP has a positive input terminal (+) connected to the input terminal IN, a negative input terminal (-) connected to a reference voltage VT, and an output terminal connected to the input terminal of the first NOT circuit N1. The reference voltage VT inputs a threshold voltage Vth to the negative input terminal (-) of the comparator CMP.

[0018] The comparator CMP outputs a low-level signal when the voltage of the sensor signal input from the input terminal IN is less than the threshold voltage Vth. The comparator CMP outputs a high-level signal when the voltage of the sensor signal input from the input terminal IN is equal to or greater than the threshold voltage Vth. In other words, the comparator CMP shapes the sine-wave sensor signal input from the sensor into a rectangular wave and outputs it.

[0019] The first NOT circuit N1 and the second NOT circuit N2 are logical negation circuits. The output terminal of the first NOT circuit N1 is connected to the input terminal of the second NOT circuit N2 and the gate of the first transistor TR1. Furthermore, the output terminal of the first NOT circuit N1 is connected to ground via a fourth resistor R4.

[0020] The first transistor TR1 is, for example, an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The first transistor TR1 has a source connected to ground and a drain connected to the first output terminal OUT1.

[0021] The second NOT circuit N2 has an output terminal connected to the gate of the second transistor TR2. The second transistor TR2 is, for example, an N-channel MOSFET. The source of the second transistor TR2 is connected to ground and the drain is connected to the second output terminal OUT2. The drain of the second transistor TR2 is also connected to a power supply line that supplies a power supply voltage VCC via a fifth resistor R5.

[0022] In the signal processing circuit 100, the path from the comparator CMP to the second output terminal OUT2 via the first NOT circuit N1, the second NOT circuit N2, and the second transistor TR2 is the first path for outputting the output signal of the comparator CMP to the microcomputer 10.

[0023] In the signal processing circuit 100, the path from the comparator CMP to the input terminal IN via the first NOT circuit N1, the first transistor TR1, the first output terminal OUT1, the capacitor C, and the second resistor R2 is the second path. The second path branches off from the first path, differentiates the output signal of the comparator CMP, and returns the differentiated signal to the input side of the comparator CMP.

[0024] [2. Operation of the signal processing circuit for comparison] Next, the operation of the signal processing circuit 100 according to the comparative example will be described with reference to Fig. 2 and Fig. 3. Fig. 2 and Fig. 3 are explanatory diagrams of the operation of the signal processing circuit 100 according to the comparative example. Fig. 4 to Fig. 6 are explanatory diagrams showing transitions of the voltages of the sensor signal, the input terminal IN, the first output terminal OUT1, and the second output terminal OUT2.

[0025] In the following, for convenience, the voltage state of each signal will be expressed as (0) or (1). A signal in the (1) state is a high-level signal. A signal in the (0) state is a low-level signal.

[0026] Fig. 2 shows a case where the voltage of the sensor signal input to the signal processing circuit 100 is less than the threshold voltage Vth. Fig. 3 shows a case where the voltage of the sensor signal input to the signal processing circuit 100 is equal to or greater than the threshold voltage Vth. In addition, Figs. 2 and 3 show the state of the signal on the signal transmission line by (0) or (1).

[0027] As shown in FIG. 2, when the voltage of the input sensor signal is less than the threshold voltage Vth, the comparator CMP outputs a signal whose state is (0). Therefore, the first NOT circuit N1 outputs a signal whose state is (1). The second NOT circuit N2 outputs a signal whose state is (0). This turns off the second transistor TR2, and an output signal whose state is (1) is output from the second output terminal OUT2. Note that the first transistor TR1 is on because a signal whose state is (1) is applied to its gate.

[0028] At this time, chattering may occur if high-frequency noise is mixed into the sensor signal. Specifically, if high-frequency noise is superimposed on the sensor signal, the voltage may oscillate across the threshold voltage Vth. In this case, the state of the output signal from the signal processing circuit 100 frequently inverts, causing chattering.

[0029] For this reason, the signal processing circuit 100 suppresses the occurrence of chattering by providing a path that branches off from the output line of the comparator CMP, differentiates the output signal of the comparator CMP, and returns it to the input side of the comparator CMP.

[0030] Specifically, when the voltage of the input sensor signal changes from less than the threshold voltage Vth to equal to or greater than the threshold voltage Vth, the comparator CMP outputs a signal whose state is (1), as shown in Figure 3. This causes the first NOT circuit N1 to output a signal whose state is (0). The second NOT circuit N2 outputs a signal whose state is (1). This turns on the second transistor TR2, and an output signal whose state is (0) is output from the second output terminal OUT2.

[0031] At this time, the first transistor TR1 is turned off because a signal in the state (0) is applied to its gate, and thus a voltage obtained by differentiating the power supply voltage VCC by the differentiating circuit 101 is applied to the input terminal IN.

[0032] That is, when the voltage of the input sensor signal changes from less than the threshold voltage Vth to equal to or greater than the threshold voltage Vth, a voltage higher than the voltage of the sensor signal is applied to the input terminal IN. Therefore, even if the voltage of the input sensor signal oscillates across the threshold voltage Vth immediately after the voltage of the input sensor signal changes from less than the threshold voltage Vth to equal to or greater than the threshold voltage Vth, the voltage input to the positive input terminal of the comparator CMP will not become less than the threshold voltage Vth.

[0033] For example, as shown in FIG. 4, when the voltage of the input sensor signal at time t1 changes from less than the threshold voltage Vth to greater than or equal to the threshold voltage Vth, the voltage state of the first output terminal OUT1 changes from (0) to (1), and the voltage state of the second output terminal OUT2 changes from (1) to (0).

[0034] At this time, the voltage at the input terminal IN is added with the voltage differentiated by the differentiation circuit 101. As a result, dynamic hysteresis is formed in the voltage waveform at the input terminal IN. As a result, even if the voltage of the sensor signal oscillates across the threshold voltage Vth, the signal processing circuit 100 prevents the voltage input to the positive input terminal of the comparator CMP from becoming less than the threshold voltage Vth, thereby suppressing the occurrence of chattering.

[0035] Note that even when the voltage of the input sensor signal changes from equal to or greater than the threshold voltage Vth to less than the threshold voltage Vth, dynamic hysteresis is formed in the voltage waveform at the input terminal IN. As a result, even if the voltage of the sensor signal oscillates across the threshold voltage Vth, the signal processing circuit 100 prevents the voltage input to the positive input terminal of the comparator CMP from exceeding the threshold voltage Vth, thereby suppressing the occurrence of chattering.

[0036] The width Vup of the positive dynamic hysteresis is Vup = (R1 / (R1+R2+R3)) × power supply voltage VCC. The width Vdown of the negative dynamic hysteresis is Vdown = (R1 / (R1+R2)) × power supply voltage VCC.

[0037] However, in the signal processing circuit 100, chattering may occur when the response of the second output terminal OUT2 supplied to the microcomputer 10 becomes faster than the voltage of the first output terminal OUT1, which is the output response for generating dynamic hysteresis. In this case, an unnecessary inversion occurs in the voltage of the second output terminal OUT2 supplied to the microcomputer 10, which may result in erroneous detection of engine rotation or abnormal engine control, leading to a stall.

[0038] Figures 5 and 6 show waveforms that are enlarged from the area enclosed by the dashed line in Figure 4. As shown in Figure 5, in the signal processing circuit 100, the voltage state of the second output terminal OUT2 may change from (1) to (0) at time t1 before the voltage state of the first output terminal OUT1 changes from (0) to (1) at time t2.

[0039] In this case, the state of the voltage at the second output terminal OUT2 changes from (1) to (0) at time t1 before dynamic hysteresis is applied to the voltage at the input terminal IN at time t2.

[0040] Therefore, for example, as shown in FIG. 6, in the signal processing circuit 100, chattering occurs when noise is superimposed on the sensor signal between times t1 and t2 before the voltage state of the first output terminal OUT1 changes from (0) to (1) at time t2.

[0041] In other words, if the voltage at the input terminal IN oscillates across the threshold voltage Vth between times t1 and t2, the comparator CMP reacts to it, causing the state of the voltage at the second output terminal OUT2 to frequently invert, resulting in chattering.

[0042] The reason why the response of the second output terminal OUT2 is faster than the response of the first output terminal OUT1 is due to response variations of elements included in the paths from the comparator CMP to the first output terminal OUT1 and the second output terminal OUT2.

[0043] Furthermore, since the first output terminal OUT1 and the second output terminal OUT2 have an open-drain configuration (pull-up resistor configuration), the response speed at which the output logic changes from (0) to (1) is slower than the response speed at which the output logic changes from (1) to (0).

[0044] Therefore, in a situation where the voltage state of the first output terminal OUT1 changes from (0) to (1) and the voltage state of the second output terminal OUT2 changes from (1) to (0), the change in voltage of the second output terminal OUT2 responds quickly to the change in voltage of the first output terminal OUT1.

[0045] When noise due to engine ignition or vibration is superimposed on the sensor signal, chattering is likely to occur if the situations shown in Figures 5 and 6 overlap. Therefore, the control device according to the embodiment has a configuration that suppresses the occurrence of chattering. The control device according to the embodiment will be described below.

[0046] [3. Configuration of the control device according to the embodiment] Fig. 7 is a circuit diagram showing a control device 1 according to an embodiment. As shown in Fig. 7, the control device 1 includes a signal processing circuit 2 and a microcomputer 10. The microcomputer 10 is the same device as the microcomputer 10 connected to the signal processing circuit 100 according to the comparative example. The microcomputer 10 includes a microcomputer having a CPU (Central Processing Unit), ROM (Read Only Memory), RAM (Random Access Memory), etc., and various circuits.

[0047] The microcomputer 10 detects the engine state based on the rectangular wave detection signal input via the signal processing circuit 2 by the CPU executing a program stored in the ROM using the RAM as a work area. The program may be stored in a storage device from an external source via a communication line, etc. Note that the microcomputer 10 may be configured in part or in whole using hardware such as an ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable Gate Array).

[0048] The signal processing circuit 2 includes a holding circuit 21 in addition to the components included in the signal processing circuit 100 according to the comparative example. The holding circuit 21 includes a comparator CMP2, a NOT circuit N3, a NOR circuit NR, and a flip-flop FF. Note that the signal processing circuit 2 does not include the second NOT circuit N2 (see FIG. 1) included in the signal processing circuit 100 according to the comparative example.

[0049] The comparator CMP1 of the signal processing circuit 2 is a comparator corresponding to the comparator CMP of the signal processing circuit 100 according to the comparative example. Here, the comparator CMP1 is referred to as the first comparator CMP1, and the comparator CMP2 is referred to as the second comparator CMP2. Also, here, the NOT circuit N3 is referred to as the second NOT circuit N3.

[0050] The second comparator CMP2 has a positive input terminal (+) connected to the first output terminal OUT1, a negative input terminal (-) connected to a reference voltage source VT2, and an output terminal connected to an input terminal of the second NOT circuit N3. The reference voltage source VT2 inputs a threshold voltage Vbias to the negative input terminal (-) of the second comparator CMP2.

[0051] The output terminal of the second NOT circuit N3 is connected to one input terminal of the NOR circuit NO and the reset terminal R of the flip-flop FF. The other input terminal of the NOR circuit NR is connected to the output terminal of the first NOT circuit N1. The NOR circuit NR is a NOR circuit. The output terminal of the NOR circuit NR is connected to the set terminal S of the flip-flop FF. The output terminal Q of the flip-flop FF is connected to the gate of the second transistor TR2.

[0052] In the signal processing circuit 2, the path from the first comparator CMP1 through the first NOT circuit N1, the NOR circuit NR, the flip-flop FF, and the second transistor TR2 to the second output terminal OUT2 is the first path for outputting the output signal of the first comparator CMP1 to the microcontroller 10.

[0053] In the signal processing circuit 2, the path from the first comparator CMP1 to the input terminal IN via the first NOT circuit N1, the first transistor TR1, the first output terminal OUT1, the capacitor C, and the second resistor R2 is the second path. The second path branches off from the first path, differentiates the output signal of the first comparator CMP1 in a differentiating circuit 101 made up of the capacitor C and the second resistor R2, and returns the signal to the input side of the first comparator CMP1.

[0054] In this embodiment, an example is shown in which the differentiated signal is fed back to the input terminal IN to which the sensor signal is input in the first comparator CMP1, but the differentiated signal may also be fed back to the reference voltage VT side. When the differentiated signal is fed back to the reference voltage VT side, it is applied in the opposite direction to when the differentiated signal is applied to the input terminal IN. In other words, dynamic hysteresis may be applied to either the sensor signal input or the reference voltage of the first comparator CMP1 so that the difference between the input signal and the reference voltage becomes relatively large the moment the output of the first comparator CMP1 is inverted.

[0055] The holding circuit 21 is provided on the first path, and when the state of the output signal of the first comparator CMP1 is inverted, it holds the state of the output signal of the first comparator CMP1 until the state of the signal on the second path is inverted, and when the state of the signal on the second path is inverted, it outputs an output signal in the held state.

[0056] The second comparator CMP2 outputs a signal whose state is (0) when the voltage at the first output terminal OUT1 is less than the threshold voltage Vbias. The second comparator CMP2 outputs a signal whose state is (1) when the voltage at the first output terminal OUT1 is equal to or greater than the threshold voltage Vbias. In other words, the second comparator CMP2 is a circuit that shapes the differentiated signal in the second path into a rectangular wave. The NOR circuit NR outputs a signal whose state is (1) when the signals input to its two input terminals are both in the state (0).

[0057] 4. Operation of the signal processing circuit according to the embodiment Next, the operation of the signal processing circuit 2 according to the embodiment will be described with reference to Fig. 8 to Fig. 10. Fig. 8 and Fig. 9 are explanatory diagrams illustrating the operation of the signal processing circuit 2 according to the embodiment. Fig. 10 is an explanatory diagram showing transitions of the sensor signal, the voltages of the input terminal IN, the first output terminal OUT1, and the second output terminal OUT2 of the signal processing circuit 2 according to the embodiment.

[0058] Fig. 8 shows a case where the voltage of the sensor signal input to the signal processing circuit 2 is less than the threshold voltage Vth. Fig. 9 shows a case where the voltage of the sensor signal input to the signal processing circuit 2 is equal to or greater than the threshold voltage Vth. In Figs. 8 and 9, the state of the signal on the signal transmission line is indicated by (0) or (1).

[0059] 8, when the voltage of the input sensor signal is less than the threshold voltage Vth, the first comparator CMP1 outputs a signal whose state is (0), and therefore the first NOT circuit N1 outputs a signal whose state is (1) to the NOR circuit NR.

[0060] At this time, the first transistor TR1 is turned on because a signal in the state (1) is applied to its gate, which connects the first output terminal OUT1 to ground, causing the voltage state of the first output terminal OUT1 to become (0) and become less than the threshold voltage Vbias.

[0061] Therefore, the second comparator CMP2 outputs a signal whose state is (0). The second NOT circuit N3 inputs a signal whose state is (1) to the NOR circuit NR and the reset terminal R of the flip-flop FF. Furthermore, since the states of the two input signals to the NOR circuit NR are both (1), it outputs a signal whose state is (0) to the set terminal S of the flip-flop FF.

[0062] The flip-flop FF resets the state of its output signal to (0) because the state of the signal input to its set terminal S is (0) and the state of the signal input to its reset terminal R is (1). This turns off the second transistor TR2, and an output signal in the state (1) is output from the second output terminal OUT2 to the microcomputer 10.

[0063] Furthermore, when the voltage of the input sensor signal changes from less than the threshold voltage Vth to equal to or greater than the threshold voltage Vth, the first comparator CMP1 outputs a signal whose state is (1), as shown in Fig. 9. Therefore, the first NOT circuit N1 outputs a signal whose state is (0) to the NOR circuit NR.

[0064] At this time, the first transistor TR1 is turned off because a signal in the state (0) is applied to its gate. This disconnects the first output terminal OUT1 from ground, causing the voltage at the first output terminal OUT1 to change to the state (1) and become equal to or higher than the threshold voltage Vbias. Furthermore, when the voltage at the first output terminal OUT1 changes to the state (1), a voltage obtained by differentiating the power supply voltage VCC by the differentiating circuit 101 is superimposed on the input terminal IN, providing dynamic hysteresis.

[0065] Therefore, the second comparator CMP2 outputs a signal whose state is (1). The second NOT circuit N3 inputs a signal whose state is (0) to the NOR circuit NR and the reset terminal R of the flip-flop FF. Furthermore, since the states of the two input signals to the NOR circuit NR are both (0), it outputs a signal whose state is (1) to the set terminal S of the flip-flop FF.

[0066] Since the state of the signal input to the set terminal S of the flip-flop FF is (1) and the state of the signal input to the reset terminal R is (0), the flip-flop FF sets and holds the state of its output signal at (1).

[0067] In this case, even if the voltage at the input terminal IN oscillates across the threshold voltage Vth due to high-frequency noise, the flip-flop FF will maintain the output state at (0) and will not output a signal in the state (1) until the state of the set terminal S becomes (1) and the state of the reset terminal R becomes (0).

[0068] In other words, even if the state of the set terminal S becomes (1), the flip-flop FF will not output a signal in the state (1) until the state of the first output terminal OUT1 becomes (1) and dynamic hysteresis is applied to the voltage of the input terminal IN.

[0069] Therefore, the second transistor TR2 does not turn on and invert the state of the voltage at the second output terminal OUT2 from (1) to (0) until dynamic hysteresis is applied to the voltage at the input terminal IN.

[0070] As a result, as shown in FIG. 10, even if the voltage at the input terminal IN becomes equal to or higher than the threshold voltage Vth at time t11, the signal processing circuit 2 does not invert the state of the second output terminal OUT2 from (1) to (0) until the state of the first output terminal OUT1 changes from (0) to (1) at time t12 due to a response delay of components, etc.

[0071] Furthermore, even if high-frequency noise is superimposed on the sensor signal and the voltage at the input terminal IN oscillates across the threshold voltage Vth, the signal processing circuit 2 does not invert the state of the second output terminal OUT2 from (1) to (0) until the state of the first output terminal OUT1 changes from (0) to (1) at time t12.

[0072] In other words, even if the voltage at the input terminal IN becomes equal to or greater than the threshold voltage Vth, the signal processing circuit 2 does not invert the state of the second output terminal OUT2 from (1) to (0) until after it has imparted dynamic hysteresis to the voltage at the input terminal IN.

[0073] Then, after the voltage at the input terminal IN becomes equal to or greater than the threshold voltage Vth and dynamic hysteresis is applied to the voltage at the input terminal IN, the signal processing circuit 2 inverts the state of the second output terminal OUT2 from (1) to (0) at time t13.

[0074] In this way, the signal processing circuit 2 maintains the output state to the microcontroller 10 by the holding circuit 21 until the output state for hysteresis is inverted and hysteresis occurs, thereby preventing chattering from occurring in the output to the microcontroller 10.

[0075] Further advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described above. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. [Explanation of symbols]

[0076] 1. Control device 2,100 signal processing circuit 10 Microcomputer 21 Holding circuit VT,VT2 reference voltage C capacitor CMP comparator CMP1 1st comparator CMP2 2nd comparator FF flip-flop IN input terminal N1 First NOT circuit N2,N3 2nd NOT circuit NR NOR circuit OUT1 First output terminal OUT2 Second output terminal Q output terminal R Reset terminal R1 First resistor R2 2nd resistor R3 3rd resistor R4 4th resistor R5 5th resistor S Set Terminal TR1 First transistor TR2 Second transistor VCC power supply voltage Vth,Vbias threshold voltage

Claims

1. a comparator that shapes a sine wave detection signal input from the sensor into a square wave; a first path for outputting an output signal of the comparator to a microcomputer; a second path branching from the first path, differentiating the output signal of the comparator, and feeding the differentiated signal back to the input side of the comparator; a holding circuit that is provided in the first path, and that holds the state of the output signal of the comparator until the state of the signal of the second path is inverted when the state of the output signal of the comparator is inverted, and outputs the output signal in the held state when the state of the signal of the second path is inverted; A signal processing circuit comprising:

2. a first NOT circuit that inverts the output signal of the comparator and outputs the inverted signal; a second NOT circuit that inverts and outputs an output signal of a comparator that shapes the differentiated signal in the second path into a square wave; a NOR circuit having one input terminal to which the output signal of the first NOT circuit is input and the other input terminal to which the output signal of the second NOT circuit is input; a flip-flop circuit having a set terminal to which the output signal of the NOR circuit is input, a reset terminal to which the output signal of the second NOT circuit is input, and an output terminal to which the output signal is output; The signal processing circuit according to claim 1 , comprising:

3. a comparator that shapes a sine wave detection signal input from a sensor according to the state of the controlled object into a square wave; a first path for outputting an output signal of the comparator to the outside; a second path branching from the first path, differentiating the output signal of the comparator, and feeding the differentiated signal back to the input side of the comparator; a holding circuit that is provided in the first path, and that holds the state of the output signal of the comparator until the state of the signal of the second path is inverted when the state of the output signal of the comparator is inverted, and outputs the output signal in the held state when the state of the signal of the second path is inverted; a signal processing circuit comprising: a microcomputer that detects the state of the controlled object based on the output signal output from the holding circuit; A control device having:

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