Memory device

Abstract

To suppress an increase in an area of a memory device.SOLUTION: A memory device according to an embodiment includes: a first chip including a memory cell array having a word line and a bit line; a second chip including a first substrate and a first circuit provided on the first substrate and in contact with a first chip; a third chip including a second substrate and a second circuit provided on the second substrate and in contact with the first chip or the second chip; and an input / output pad. The first chip and the second chip are arranged in this order in a first direction from the word line toward the bit line. The first circuit includes: a first transistor connected to the bit line; and a second transistor connected to the word line. The second circuit includes a third transistor connected to the input / output pad.SELECTED DRAWING: Figure 12

Description

[Technical Field]

[0001] Embodiments relate to memory devices. [Background technology]

[0002] NAND flash memory is known as a memory device capable of nonvolatile data storage. Memory devices such as NAND flash memory employ a three-dimensional memory structure to achieve high integration and large capacity. The three-dimensional memory structure and the CMOS circuitry for controlling the memory structure may be provided on separate chips. In this case, the memory device is formed by bonding a memory chip with the three-dimensional memory structure and a circuit chip with the CMOS circuitry. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2022 / 0122932 [Patent Document 2] US Patent Application Publication No. 2023 / 0005862 [Patent Document 3] US Patent Application Publication No. 2022 / 0359441 Summary of the Invention [Problem to be solved by the invention]

[0004] To suppress an increase in the area of ​​a memory device. [Means for solving the problem]

[0005] A memory device according to an embodiment includes a first chip including a memory cell array having word lines and bit lines, a second chip including a first substrate and a first circuit provided on the first substrate and in contact with the first chip, a third chip including a second substrate and a second circuit provided on the second substrate and in contact with the first chip or the second chip, and an input / output pad. The first chip and the second chip are arranged in this order in a first direction from the word lines to the bit lines. The first circuit includes a first transistor connected to the bit lines and a second transistor connected to the word lines. The second circuit includes a third transistor connected to the input / output pad. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing the configuration of a memory system including a memory device according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of the configuration of a memory cell array according to the first embodiment. [Figure 3] FIG. 2 is a circuit diagram showing an example of connections between a memory cell array, a row decoder module, and a driver module according to the first embodiment. [Figure 4] FIG. 2 is a block diagram showing an example of connections between a memory cell array and sense amplifier modules according to the first embodiment. [Figure 5] FIG. 2 is a circuit diagram showing an example of the configuration of a sense amplifier module according to the first embodiment. [Figure 6] FIG. 2 is a plan view showing an example of a planar layout of the memory cell array according to the first embodiment. [Figure 7] FIG. 2 is a plan view showing an example of a planar layout in a memory region of the memory cell array according to the first embodiment. [Figure 8] 8 is a cross-sectional view taken along line VIII-VIII in FIG. 7, showing an example of a cross-sectional structure in a memory region of the memory cell array according to the first embodiment. [Figure 9] 9 is a cross-sectional view taken along line IX-IX in FIG. 8, showing an example of the cross-sectional structure of the memory pillar according to the first embodiment. [Figure 10]FIG. 2 is a plan view showing an example of a planar layout in a lead-out region of the memory cell array according to the first embodiment. [Figure 11] 11 is a cross-sectional view taken along line XI-XI in FIG. 10, showing an example of a cross-sectional structure in a lead-out region of the memory cell array according to the first embodiment. [Figure 12] FIG. 2 is a perspective view showing an example of a laminated structure of the memory device according to the first embodiment and a planar layout of each chip. [Figure 13] 13 is a cross-sectional view taken along plane XIII of FIG. 12, showing an example of the cross-sectional structure of the memory device according to the first embodiment. [Figure 14] 14 is a cross-sectional view taken along plane XIV in FIG. 12, showing an example of the cross-sectional structure of the memory device according to the first embodiment. [Figure 15] FIG. 10 is a perspective view showing an example of a laminated structure of a memory device according to a modified example of the first embodiment and a planar layout of each chip. [Figure 16] 16 is a cross-sectional view taken along the XVI plane of FIG. 15, showing an example of a cross-sectional structure of a memory device according to a modified example of the first embodiment. [Figure 17] FIG. 10 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to a second embodiment. [Figure 18] FIG. 10 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to a second embodiment. [Figure 19] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure of a memory device according to a modified example of the second embodiment. [Figure 20] FIG. 11 is a perspective view showing an example of a laminated structure of a memory device according to a third embodiment and a planar layout of each chip. [Figure 21] 21 is a cross-sectional view taken along plane XXI of FIG. 20, showing an example of the cross-sectional structure of the memory device according to the third embodiment. [Figure 22] 22 is a cross-sectional view taken along the plane XXII of FIG. 20, showing an example of the cross-sectional structure of the memory device according to the third embodiment. [Figure 23] FIG. 11 is a perspective view showing an example of a laminated structure of a memory device according to a modified example of the third embodiment and a planar layout of each chip. [Figure 24]FIG. 24 is a cross-sectional view taken along the XIV plane of FIG. 23, showing an example of a cross-sectional structure of a memory device according to a modified example of the third embodiment. [Figure 25] FIG. 10 is a perspective view showing an example of a laminated structure of memory devices and a planar layout of each chip according to a fourth embodiment. [Figure 26] 26 is a cross-sectional view taken along the plane XXVI of FIG. 25, showing an example of the cross-sectional structure of the memory device according to the fourth embodiment. [Figure 27] 27 is a cross-sectional view taken along plane XXVII of FIG. 25, showing an example of the cross-sectional structure of the memory device according to the fourth embodiment. [Figure 28] FIG. 10 is a schematic diagram showing an example of a wiring structure of a memory device according to a fourth embodiment. [Figure 29] FIG. 11 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to a fifth embodiment. [Figure 30] FIG. 11 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. The dimensions and proportions of the drawings are not necessarily the same as those in reality.

[0008] In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. When elements having similar configurations are to be particularly distinguished from one another, different letters or numbers may be added to the end of the same reference numerals.

[0009] 1. First embodiment A first embodiment will be described.

[0010] 1.1 Functional configuration The functional configuration according to the first embodiment will be described.

[0011] 1.1.1 Memory System FIG. 1 is a block diagram showing an example of the configuration of a memory system including a memory device according to the first embodiment. The memory system is a storage device configured to be connected to an external host device (not shown). The memory system 1 includes, for example, an SD TM The memory system 1 includes a memory controller 2 and a memory device 3. The memory system 1 may be a memory card, a universal flash storage (UFS), or a solid state drive (SSD).

[0012] The memory controller 2 is configured by an integrated circuit such as a system-on-a-chip (SoC). The memory controller 2 controls the memory device 3 based on a request from the host. Specifically, for example, the memory controller 2 writes data requested to be written by the host to the memory device 3. In addition, the memory controller 2 reads data requested to be read by the host from the memory device 3 and transmits the data to the host.

[0013] The memory device 3 is a nonvolatile memory, such as a NAND flash memory, that stores data in a nonvolatile manner.

[0014] The communication between the memory controller 2 and the memory device 3 is compliant with, for example, an SDR (single data rate) interface, a toggle DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0015] 1.1.2 Memory Devices <Overall structure> The internal configuration of the memory device according to the first embodiment will now be described with reference to the block diagram shown in Fig. 1. The memory device 3 includes, for example, a memory cell array 10, an input / output module 11, a register 12, a sequencer 13, a voltage generation circuit 14, a driver module 15, a row decoder module 16, and a sense amplifier module 17.

[0016] The memory cell array 10 includes a plurality of blocks BLK0 to BLK(n-1) (n is an integer equal to or greater than 2). The number of blocks BLK included in the memory cell array 10 may be one. A block BLK is a set of a plurality of memory cells. A block BLK is used, for example, as a unit for erasing data. The memory cell array 10 is also provided with a plurality of bit lines and a plurality of word lines. Each memory cell is associated with, for example, one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0017] The input / output module 11 includes an input / output circuit 11-1 and a logic control circuit 11-2. The input / output circuit 11-1 and the logic control circuit 11-2 transmit and receive various signals to and from the memory controller 2. The signals transmitted and received by the input / output circuit 11-1 include, for example, the signals IO<7:0>. The signals transmitted and received by the logic control circuit 11-2 include, for example, the signals CEn, CLE, ALE, WEn, REn, and RBn. In this specification, the suffix n in the name of a signal means that the signal is asserted when it is at the "L (Low)" level.

[0018] The signal IO<7:0> is an 8-bit signal. The signal IO<7:0> is the entity of data DAT transmitted and received between the memory device 3 and the memory controller 2. Hereinafter, the signal IO<7:0> transmitted from the memory controller 2 to the memory device 3 is referred to as the input signal IO<7:0>. The signal IO<7:0> transmitted from the memory device 3 to the memory controller 2 is referred to as the output signal IO<7:0>. The input signal IO<7:0> includes, for example, write data DAT, address information ADD, and a command CMD. The output signal IO<7:0> includes, for example, read data DAT.

[0019] The signal CEn is a signal for enabling the memory device 3 .

[0020] The signals CLE and ALE are signals that notify the memory device 3 that the input signal IO<7:0> is a command CMD and address information ADD, respectively.

[0021] The signal WEn is a signal for causing the memory device 3 to take in the input signal IO<7:0>.

[0022] The signal REn is a signal for reading the output signal IO<7:0> from the memory device 3.

[0023] The signal RBn indicates whether the memory device 3 is in a ready state or a busy state. The ready state is a state in which the memory device 3 can receive commands from the memory controller 2. The busy state is a state in which the memory device 3 cannot receive commands from the memory controller 2. The signal RBn at the "L" level indicates a busy state.

[0024] The input / output circuit 11-1 transmits address information ADD and command CMD, and write data DAT in the input signal IO<7:0>, respectively, to the register 12 and the sense amplifier module 17. The input / output circuit 11-1 receives read data DAT in the output signal IO<7:0> from the register 12 and the sense amplifier module 17, respectively.

[0025] The logic control circuit 11-2 receives signals CEn, CLE, ALE, WEn, and REn from the memory controller 2. The logic control circuit 11-2 transmits a signal RBn to the memory controller 2.

[0026] The register 12 stores address information ADD and a command CMD. The address information ADD includes, for example, a column address, a block address, and a page address. The sequencer 13 controls the operation of the memory device 3 as a whole.

[0027] The voltage generating circuit 14 generates voltages used in write operations, read operations, erase operations, and the like.

[0028] The driver module 15 generates voltages used in read operations, write operations, erase operations, etc. Then, the driver module 15 applies the generated voltages to signal lines corresponding to selected word lines based on, for example, a page address stored in the register 12.

[0029] The row decoder module 16 selects one block BLK in the corresponding memory cell array 10 based on the block address stored in the register 12. Then, the row decoder module 16 transfers, for example, a voltage applied to a signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0030] In a write operation, the sense amplifier module 17 applies a desired voltage to each bit line in accordance with the write data DAT received from the memory controller 2. In a read operation, the sense amplifier module 17 determines the data stored in the memory cell based on the voltage of the bit line, and transfers the determination result to the memory controller 2 as read data DAT.

[0031] <Memory cell array> Next, the configuration of the memory cell array according to the first embodiment will be described.

[0032] Fig. 2 is a circuit diagram showing an example of a circuit configuration of the memory cell array according to the first embodiment. Fig. 2 shows one block BLK among multiple blocks BLK included in the memory cell array 10. As shown in Fig. 2, the block BLK includes, for example, four string units SU0, SU1, SU2, and SU3.

[0033] Each of the string units SU0 to SU3 includes a plurality of NAND strings NS associated with bit lines BL0 to BL(m-1) (m is an integer equal to or greater than 2), respectively. The number of bit lines BL may be one. Each NAND string NS includes, for example, memory cell transistors MT0 to MT7 and select transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge storage section, and stores data in a non-volatile manner. Each of the select transistors ST1 and ST2 is used to select a string unit SU during various operations.

[0034] In each NAND string NS, the memory cell transistors MT0 to MT7 are connected in series. The drain of the select transistor ST1 is connected to the associated bit line BL. The source of the select transistor ST1 is connected to one end of the memory cell transistors MT0 to MT7 connected in series. The drain of the select transistor ST2 is connected to the other end of the memory cell transistors MT0 to MT7 connected in series. The source of the select transistor ST2 is connected to a source line SL.

[0035] In the same block BLK, the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The gates of select transistors ST1 in string units SU0 to SU3 are connected to select gate lines SGD0 to SGD3, respectively. The gates of select transistors ST2 in string units SU0 to SU3 are connected to select gate line SGS.

[0036] A different column address is assigned to each of the bit lines BL0 to BL(m-1). Each bit line BL is shared by NAND strings NS that are assigned the same column address among multiple blocks BLK. Each of the word lines WL0 to WL7 is provided for each block BLK. The source line SL is shared, for example, among multiple blocks BLK.

[0037] A set of memory cell transistors MT connected to a common word line WL within one string unit SU is called, for example, a cell unit CU. For example, the storage capacity of a cell unit CU including memory cell transistors MT each storing one bit of data is defined as "one page of data." A cell unit CU may have a storage capacity of two or more pages of data depending on the number of bits of data stored in the memory cell transistors MT.

[0038] The circuit configuration of the memory cell array 10 included in the memory device 3 according to the first embodiment is not limited to the configuration described above. For example, the number of string units SU included in each block BLK can be designed to be any number. The number of memory cell transistors MT and select transistors ST1 and ST2 included in each NAND string NS can be designed to be any number.

[0039] <Row decoder module> 3 is a circuit diagram showing an example of connections between a memory cell array, a row decoder module, and a driver module according to the first embodiment. As shown in FIG. 3, the row decoder module 16 includes a plurality of row decoders RD (RD0, RD1, ...). The number of row decoders RD corresponds to the number of blocks BLK. Each of the plurality of row decoders RD has the same configuration. In the example of FIG. 3, the configuration of row decoder RD0 corresponding to block BLK0 is shown. Row decoder RD0 includes a block decoder BD and transistors TR0 to TR17.

[0040] Each of the transistors TR0 to TR12 is, for example, an N-type transistor. A first terminal of each of the transistors TR0 to TR7 is connected to the block BLK0 via word lines WL0 to WL7, respectively. A second terminal of each of the transistors TR0 to TR7 is connected to the driver module 15 via wirings CG0 to CG7, respectively. A gate of each of the transistors TR0 to TR7 is connected to the block decoder BD via wiring BLKSEL.

[0041] For example, in a write operation, the transistors TR0 to TR7 can transfer a write voltage to the word lines WL0 to WL7, respectively. The write voltage is high enough to increase the threshold voltage of the memory cell transistors MT. Therefore, the transistors TR0 to TR7 have a high enough breakdown voltage to transfer the write voltage. Hereinafter, transistors having a high enough breakdown voltage to transfer the write voltage are also referred to as "high breakdown voltage transistors" or "HV transistors." HV transistors are designed to have a gate oxide film thickness of at least 10 nm, for example, approximately 40 nm for transistors that can operate up to 30 V. Transistors having a lower breakdown voltage than HV transistors are also referred to as "low breakdown voltage transistors" or "LV transistors." LV transistors are designed to have a gate oxide film thickness of, for example, 5 nm to 7 nm. Transistors having an even lower breakdown voltage than LV transistors are also referred to as "very low breakdown voltage transistors" or "VLV transistors." The VLV transistor is designed so that the thickness of the gate oxide film is, for example, 2.5 nm or more and 3.5 nm or less.

[0042] The transistor TR8 is, for example, an N-type HV transistor. A first terminal of the transistor TR8 is connected to the block BLK0 via a select gate line SGS. A second terminal of the transistor TR8 is connected to the driver module 15 via a line SGSD. A gate of the transistor TR8 is connected to the block decoder BD via a line BLKSEL.

[0043] Each of the transistors TR9 to TR12 is, for example, an N-type HV transistor. A first terminal of each of the transistors TR9 to TR12 is connected to the block BLK0 via select gate lines SGD0 to SGD3, respectively. A second terminal of each of the transistors TR9 to TR12 is connected to the driver module 15 via lines SGDD0 to SGDD3, respectively. A gate of each of the transistors TR9 to TR12 is connected to the block decoder BD via a line BLKSEL.

[0044] The transistor TR13 is, for example, an N-type LV transistor. A first terminal of the transistor TR13 is connected to the block BLK0 via a select gate line SGS. A second terminal of the transistor TR13 is connected to the driver module 15 via a line USGS. A gate of the transistor TR13 is connected to the block decoder BD via a line BLKSELn.

[0045] Each of the transistors TR14 to TR17 is, for example, an N-type LV transistor. A first terminal of each of the transistors TR14 to TR17 is connected to the block BLK0 via the select gate lines SGD0 to SGD3, respectively. A second terminal of each of the transistors TR14 to TR17 is connected to the driver module 15 via a line USGD. A gate of each of the transistors TR14 to TR17 is connected to the block decoder BD via a line BLKSELn.

[0046] The block decoder BD supplies voltages of different logic levels to the lines BLKSEL and BLKSELn. When the block BLK0 is selected, the block decoder BD supplies a "H" level voltage to the line BLKSEL and a "L" level voltage to the line BLKSELn. When the block BLK0 is not selected, the block decoder BD supplies a "L" level voltage to the line BLKSEL and a "H" level voltage to the line BLKSELn.

[0047] <Sense amplifier module> 4 is a block diagram showing an example of connections between the memory cell array and the sense amplifier modules according to the first embodiment. As shown in FIG. 4, the sense amplifier module 17 includes a sense amplifier 17-1, a data register 17-2, and a column decoder 17-3.

[0048] The sense amplifier 17-1 includes a plurality of sense amplifier units SAU provided for each bit line BL, and the data register 17-2 includes a plurality of latch circuits XDL provided for each sense amplifier unit SAU.

[0049] The sense amplifier unit SAU includes, for example, a sense circuit SA, latch circuits SDL, ADL, BDL, and CDL, and a bus switch BSW. The sense circuit SA, latch circuits SDL, ADL, BDL, and CDL, and bus switch BSW are connected via a bus LBUS. The bus switch BSW is connected to the latch circuit XDL via a bus DBUS. The latch circuit XDL, sense circuit SA, and latch circuits SDL, ADL, BDL, and CDL are configured to be able to transmit and receive data to and from each other via the bus switch BSW.

[0050] During a read operation, the sense circuit SA senses the threshold voltage of the memory cell transistor MT via the corresponding bit line BL to determine whether the data stored in the memory cell transistor MT is "0" or "1." During a write operation, the sense circuit SA applies a voltage to the bit line BL based on the write data.

[0051] The latch circuits SDL, ADL, BDL, and CDL temporarily store read data DAT or write data DAT. For example, in the case of a read process, the read data DAT is stored in one of the latch circuits SDL, ADL, BDL, and CDL. Also, for example, in the case of a write process, the write data DAT of the latch circuit XDL is stored in one of the latch circuits SDL, ADL, BDL, and CDL.

[0052] The bus switch BSW is a switch that controls the transmission and reception of data between the sense amplifier 17-1 and the data register 17-2.

[0053] The latch circuit XDL is used as a cache memory between the sense amplifier unit SAU and the column decoder 17-3. More specifically, the write data DAT received from the column decoder 17-3 is transmitted to the latch circuits SDL, ADL, BDL, and CDL or the sense circuit SA via the latch circuit XDL. Also, the read data DAT stored in the latch circuits SDL, ADL, BDL, and CDL or the sense circuit SA is transmitted to the column decoder 17-3 via the latch circuit XDL.

[0054] The column decoder 17-3 is connected to a corresponding plurality of latch circuits XDL via a plurality of buses XBUS. During a write process, the column decoder 17-3 receives write data DAT from the input / output module 11. Then, the column decoder 17-3 transmits the write data DAT to the latch circuit XDL corresponding to the column address. During a read process, the column decoder 17-3 receives read data DAT from the latch circuit XDL corresponding to the column address. Then, the column decoder 17-3 transmits the read data DAT to the input / output module 11.

[0055] FIG. 5 is a circuit diagram showing an example of the configuration of a sense amplifier module according to the first embodiment. As shown in FIG. 5, the sense circuit SA in the sense amplifier unit SAU includes nine transistors T0 to T8 and a capacitor CP. The bus switch BSW includes a transistor T9. The latch circuit SDL includes transistors T10 and T11 and inverters IV0 and IV1. The transistor T0 is, for example, a P-type LV transistor. The transistors T1 to T7 and T9 are, for example, N-type LV transistors. The transistor T8 is, for example, an N-type HV transistor. The transistors T10 and T11 are, for example, N-type LV transistors or VLV transistors. Although omitted in FIG. 5, the latch circuits ADL, BDL, CDL, and XDL have the same configuration as the latch circuit SDL.

[0056] A power supply voltage VDD is supplied to a first terminal of the transistor T0, a second terminal of the transistor T0 is connected to a node ND1, and a control terminal of the transistor T0 is connected to a node SINV.

[0057] A first terminal of the transistor T1 is connected to the node ND1, a second terminal of the transistor T1 is connected to the node ND2, and a control terminal of the transistor T1 is connected to the node BLX.

[0058] A first end of the transistor T2 is connected to the node ND1, a second end of the transistor T2 is connected to the node SEN, and a control end of the transistor T2 is connected to the node HLL.

[0059] A first end of the transistor T3 is connected to the node SEN, a second end of the transistor T3 is connected to the node ND2, and a control end of the transistor T3 is connected to the node XXL.

[0060] A first terminal of the transistor T4 is connected to the node ND2. A second terminal of the transistor T4 is connected to a first terminal of the transistor T8. A second terminal of the transistor T8 is connected to the bit line BL. A control terminal of the transistor T4 is connected to the node BLC. A control terminal of the transistor T8 is connected to the node BLS.

[0061] A first terminal of the transistor T5 is connected to the node ND2, a second terminal of the transistor T5 is connected to the node SRC, and a control terminal of the transistor T5 is connected to the node SINV.

[0062] A first terminal of the transistor T6 is connected to ground. A second terminal of the transistor T6 is connected to a first terminal of the transistor T7. A second terminal of the transistor T7 is connected to the bus LBUS. A control terminal of the transistor T6 is connected to the node SEN. A control terminal of the transistor T7 is connected to the node STB.

[0063] A first end of the capacitor CP is connected to the node SEN, and a second end of the capacitor CP is supplied with the clock signal CLK.

[0064] A first terminal of the transistor T9 is connected to the bus LBUS, and a second terminal of the transistor T9 is connected to the bus DBUS.

[0065] A first terminal of the transistor T10 and a first terminal of the transistor T11 are connected to the bus LBUS. A second terminal of the transistor T10 is connected to the output terminal of the inverter IV0 and the input terminal of the inverter IV1. A second terminal of the transistor T11 is connected to the input terminal of the inverter IV0 and the output terminal of the inverter IV1.

[0066] With the above configuration, the sense circuit SA can determine the data stored in the memory cell transistor MT based on the voltage of the node SEN during a read process. As a result of the determination, the data read to the node SEN is transferred to the latch circuits SDL, ADL, BDL, and CDL. In addition, the data transferred to the latch circuits SDL, ADL, BDL, and CDL is transferred to the latch circuit XDL via the bus switch BSW.

[0067] 1.2 Structure Next, the structure of the memory device according to the first embodiment will be described.

[0068] In the following, the direction in which the word lines WL extend is referred to as the X direction. The direction in which the bit lines BL extend is referred to as the Y direction. The direction intersecting with the plane (XY plane) including the X and Y directions is referred to as the Z direction. Within the Z direction, the direction from the word lines WL to the bit lines BL is referred to as the Z1 direction. The direction from the bit lines BL to the word lines WL is referred to as the Z2 direction.

[0069] 1.2.1 Memory Cell Array First, the detailed structure of the memory cell array 10 will be described.

[0070] <Overall floor plan layout> Fig. 6 is a plan view showing an example of a planar layout of the memory cell array according to the first embodiment. Fig. 6 illustrates a case where the memory cell array 10 includes eight blocks BLK0 to BLK7.

[0071] 6, the memory cell array 10 has memory regions MRa and MRb arranged in the X direction, and a lead-out region HR. The memory regions MRa and MRb are regions where memory cell transistors MT are provided. The lead-out region HR is a region where contacts are provided that electrically connect the word lines WL0 to WL7 and the select gate lines SGS and SGD to the row decoder module 16. The lead-out region HR is located between the memory regions MRa and MRb.

[0072] Each of the plurality of blocks BLK extends in the X direction so as to cross the memory region MRa, the lead-out region HR, and the memory region MRb. The plurality of blocks BLK are arranged in the Y direction. The memory cell array 10 includes, for example, a plurality of slits SLT and a plurality of slits SHE.

[0073] Each slit SLT extends in the X direction so as to cross the memory region MRa, the lead-out region HR, and the memory region MRb. A plurality of slits SLT are arranged in the Y direction. Each slit SLT has a structure in which an insulator is embedded, for example. Each slit SLT separates adjacent wirings (for example, word lines WL0 to WL7 and select gate lines SGD and SGS) through the slit SLT. In the memory cell array 10, each of the regions separated by the slit SLT corresponds to one block BLK.

[0074] The multiple slits SHE include multiple slits SHE aligned in the Y direction in the memory region MRa and multiple slits SHE aligned in the Y direction in the memory region MRb. Each slit SHE located in the memory region MRa extends in the X direction across the memory region MRa. Each slit SHE located in the memory region MRb extends in the X direction across the memory region MRb. In the example of FIG. 6, three slits SHE are arranged between two slits SLT adjacent to each other in the Y direction in each of the memory regions MRa and MRb. Each slit SHE has a structure in which an insulator is embedded, for example. Each slit SHE separates adjacent wirings (at least select gate lines SGD) via the slit SHE. In the memory cell array 10, each pair of adjacent slits SLT and SHE or each area partitioned by a pair of adjacent two slits SHE corresponds to one string unit SU.

[0075] The lead-out region HR includes sub-lead-out regions SHRa and SHRb, which are divided into two in the X direction. The sub-lead-out region SHRa is adjacent to the memory region MRa. The sub-lead-out region SHRb is adjacent to the memory region MRb. The stacked wiring of each block BLK is connected to the row decoder module 16, for example, via contacts arranged in the sub-lead-out region SHRa or SHRb. In the following, a case will be described in which the stacked wiring of each of the blocks BLK(i*4) and BLK(i*4+3) ("i" is an integer greater than or equal to 0) is connected to a contact provided in the sub-lead-out region SHRa, and the stacked wiring of each of the blocks BLK(i*4+1) and BLK(i*4+2) is connected to a contact provided in the sub-lead-out region SHRb. In this case, in the lead-out region HR, the structure of the portions corresponding to the blocks BLK0 to BLK3 is repeatedly arranged in the Y direction.

[0076] The planar layout of the memory cell array 10 may be other layouts. For example, the number of slits SHE arranged between two adjacent slits SLT can be designed to be any number. The number of string units SU included in each block BLK can be changed based on the number of slits SHE arranged between two adjacent slits SLT.

[0077] <Plane layout in memory area> 7 is a plan view showing an example of a planar layout of a memory region MR of the memory cell array according to the first embodiment. A region including one block BLK (string units SU0 to SU3) is shown in FIG. 7. As shown in FIG. 7, the memory device 3 includes, in the memory region MR, for example, a plurality of memory pillars MP, a plurality of contacts CV, and a plurality of bit lines BL.

[0078] Each memory pillar MP functions as one NAND string NS. The memory pillars MP are arranged in a staggered pattern of, for example, 19 rows in the region between two adjacent slits SLT. For example, counting from the top of the page, one slit SHE is arranged to overlap the fifth row of memory pillar MP, the tenth row of memory pillar MP, and the fifteenth row of memory pillar MP.

[0079] The multiple bit lines BL are aligned in the X direction. Each bit line BL is arranged so as to overlap at least one memory pillar MP for each string unit SU. In the example of FIG. 7, two bit lines BL are arranged to overlap one memory pillar MP. The memory pillar MP is electrically connected to one of the multiple overlapping bit lines BL via a contact CV. Note that the contact CV between the memory pillar MP and the bit line BL that contacts two different select gate lines SGD (i.e., that is arranged overlapping with the slit SHE) can be omitted.

[0080] The planar layout of the memory region MR may be other layouts. For example, the number and arrangement of memory pillars MP and slits SHE arranged between two adjacent slits SLT may be changed as appropriate. The number of bit lines BL overlapping each memory pillar MP may be designed to be any number.

[0081] <Cross-sectional structure in the memory area> 8 is a cross-sectional view taken along line VIII-VIII in FIG. 7, showing an example of a cross-sectional structure in the memory region MR of the memory cell array according to the first embodiment. As shown in FIG. 8, in the memory region MR, the memory cell array 10 includes, for example, a semiconductor layer 20, conductor layers 21, 22, 23, and 24a, and insulator layers 31, 32, 33, 34, 35, and 36. The insulator layers 31 to 36 include, for example, silicon oxide. In FIG. 8, the Z1 direction corresponds to the upward direction of the paper.

[0082] The semiconductor layer 20 is provided on the insulator layer 31. The semiconductor layer 20 is formed, for example, in the shape of a plate extending along the XY plane. The semiconductor layer 20 includes, for example, silicon, and is used as the source line SL.

[0083] An insulator layer 32 is provided on the semiconductor layer 20. A conductor layer 21 is provided on the insulator layer 32. The conductor layer 21 is formed, for example, in the shape of a plate extending along the XY plane. The conductor layer 21 includes, for example, tungsten, and is used as the select gate line SGS.

[0084] A plurality of insulating layers 33 and conductive layers 22 are alternately provided on a conductive layer 21. The plurality of conductive layers 22 are formed, for example, in the shape of plates extending along the XY plane. The plurality of conductive layers 22 include, for example, tungsten, and are used as word lines WL0 to WL7, respectively, in order from the bottom up.

[0085] An insulator layer 34 is provided on the uppermost conductor layer 22. A conductor layer 23 is provided on the insulator layer 34. The conductor layer 23 is formed, for example, in the shape of a plate extending along the XY plane. The conductor layer 23 includes, for example, tungsten and is used as a select gate line SGD.

[0086] An insulator layer 35 is provided on the conductor layer 23. A conductor layer 24a is provided on the insulator layer 35. The upper surface of the conductor layer 24a is covered with an insulator layer 36. The conductor layer 24a is formed, for example, in a line shape extending in the Y direction. The conductor layer 24a contains, for example, copper and is used as the bit line BL.

[0087] The slit SLT has a plate-like portion extending along the XZ plane. The slit SLT divides the insulator layers 32 to 34 and the conductor layers 21 to 23. Each memory pillar MP extends in the Z direction and penetrates the insulator layers 32 to 34 and the conductor layers 21 to 23. Each memory pillar MP includes, for example, a core film 40, a semiconductor film 41, and a stacked film 42. The core film 40 is an insulator extending in the Z direction. The semiconductor film 41 covers the core film 40. The lower part of the semiconductor film 41 contacts the semiconductor layer 20. The stacked film 42 covers the side surface of the semiconductor film 41. A contact CV is provided on the upper surface of the semiconductor film 41. The semiconductor film 41 and the conductor layer 24a are connected via the contact CV.

[0088] In the illustrated region, a contact CV corresponding to one of the two memory pillars MP is shown. A contact CV is connected to a memory pillar MP that is not connected to a contact CV in the illustrated region in a region not illustrated. The intersection of the memory pillar MP and the conductive layer 21 functions as a select transistor ST2. The intersection of the memory pillar MP and the conductive layer 22 functions as a memory cell transistor MT. The intersection of the memory pillar MP and the conductive layer 23 functions as a select transistor ST1.

[0089] 9 is a cross-sectional view taken along line IX-IX in FIG. 8, showing an example of the cross-sectional structure of the memory pillar according to the first embodiment. A cross section including the memory pillar MP and the conductive layer 22 and parallel to the surface of the source line SL is shown in FIG. 9. As shown in FIG. 9, the stacked film 42 includes, for example, a tunnel insulating film 43, a charge storage film 44, and a block insulating film 45.

[0090] The core film 40 is provided, for example, in the center of the memory pillar MP. The semiconductor film 41 surrounds the side surfaces of the core film 40. The tunnel insulating film 43 surrounds the side surfaces of the semiconductor film 41. The charge storage film 44 surrounds the side surfaces of the tunnel insulating film 43. The block insulating film 45 surrounds the side surfaces of the charge storage film 44. The conductor layer 22 surrounds the side surfaces of the block insulating film 45. The semiconductor film 41 is used as the channels (current paths) of the memory cell transistors MT0 to MT7 and the select transistors ST1 and ST2. Each of the tunnel insulating film 43 and the block insulating film 45 contains, for example, silicon oxide. The charge storage film 44 contains, for example, silicon nitride. As a result, each of the memory pillar MP functions as one NAND string NS.

[0091] <Plane layout in the drawer area> 10 is a plan view showing an example of a planar layout in the lead-out region of the memory cell array according to the first embodiment. FIG. 10 shows an extracted portion of the lead-out region HR corresponding to the sub-lead-out region SHRb and a portion of the memory region MRb, which correspond to the block BLK1. As shown in FIG. 10, in the sub-lead-out region SHRb, the stacked wiring of the block BLK1 (select gate line SGS, word lines WL0 to WL7, and select gate line SGD) has terrace portions that do not overlap with the stacked wiring in the upper layer when viewed in the Z1 direction. Furthermore, the memory cell array 10 includes a plurality of contacts CC in the sub-lead-out region SHRb.

[0092] The terrace portion forms a staircase structure having steps in the X direction. Specifically, in the lead-out region HR, steps are formed along the X direction between the select gate line SGS and the word line WL0, between the word line WL0 and the word line WL1, ..., between the word line WL6 and the word line WL7, and between the word line WL7 and the select gate line SGD. The select gate line SGS and the word lines WL0 to WL7 of the memory regions MR1 ​​and MR2 are continuously provided via a highway portion HW in the lead-out region HR. The highway portion HW corresponds to the portion of the conductor layer continuously provided between the memory regions MRa and MRb along the slit SLT.

[0093] The contacts CC are conductors used for connection between the row decoder module 16 and stacked wiring. The contacts CC associated with the block BLK1 are connected to the select gate lines SGS and SGD provided in the sub-lead region SHRb and to the terrace portions of the word lines WL0 to WL7. When the select gate line SGD in the memory region MRa and the select gate line SGD in the memory region MRb are associated with the same string unit SU, they are short-circuited, for example, via the contacts CC and an upper wiring layer.

[0094] The layout of the overlapping portion of the sub-drawer region SHRa and block BLK0 is the same as the layout of the overlapping portion of the sub-drawer region SHRb and block BLK1, which is flipped in the X and Y directions. The layout of the overlapping portion of the drawer region HR and blocks BLK2 and BLK3 is the same as the layout of the overlapping portion of the drawer region HR and blocks BLK0 and BLK1, which is flipped in the Y direction. However, the planar layout of the drawer region HR may be changed as appropriate.

[0095] <Cross-sectional structure in the extraction area> 11 is a cross-sectional view taken along line XI-XI in FIG. 10, showing an example of a cross-sectional structure in the lead-out region of the memory cell array according to the first embodiment. As shown in FIG. 11, the memory cell array 10 includes, for example, a plurality of conductor layers 24b in the sub-lead-out region SHRb. In FIG. 11, the Z1 direction corresponds to the upward direction of the page.

[0096] In the sub-leading region SHRb, the ends of the conductive layers 21 to 23 in the X direction are provided in a stepped shape and are covered with an insulating layer 35. An insulating layer 36 is also provided in the sub-leading region SHRb, similar to the memory region MR.

[0097] A plurality of contacts CC are provided on the upper surfaces of the terrace portions of the select gate line SGS, the word lines WL0 to WL7, and the select gate line SGD. Each contact CC penetrates the insulating layer 35. One conductor layer 24b is provided on the upper surface of each of the plurality of contacts CC. The conductor layer 24b is located in the same layer as the conductor layer 24a.

[0098] A pair of the conductor layer 24b and the contact CC corresponds to a wiring and a contact for connecting one of the conductor layers 21 to 23 to the row decoder module 16. Although not shown in the figure, each of the conductor layers 22 and 23 is similarly connected to the row decoder module 16 via the corresponding pair of the conductor layer 24b and the contact CC.

[0099] 1.2.2 Memory Devices Next, the detailed structure of the memory device 3 will be described.

[0100] <Lamination structure and plan layout> 12 is a perspective view showing an example of a laminated structure of memory devices and a planar layout of each chip according to the first embodiment, in which the Z2 direction corresponds to the upper side of the paper.

[0101] 12, the memory device 3 has a structure in which, for example, a circuit chip DC1, a circuit chip DC2, and a memory chip DC0 are stacked in this order from the bottom up. The circuit chip DC1 and the circuit chip DC2, and the circuit chip DC2 and the memory chip DC0 are bonded together by a plurality of bonding pads BP.

[0102] The circuit chips DC1 and DC2 include CMOS circuits. The circuit chip DC1 mainly includes LV transistors and VLV transistors. The circuit chip DC2 mainly includes HV transistors and LV transistors. The memory chip DC0 includes memory cell transistors MT.

[0103] For example, when viewed in the Z direction, the memory chip DC0 further has an input / output area IOR0 in addition to the memory areas MRa and MRb and the draw-out area HR described above. The input / output area IOR0 is an area where circuits and wiring for supplying power supply voltages and the like to the memory chip DC0 are formed. The input / output area IOR0 is aligned with the memory areas MRa and MRb and the draw-out area HR in the Y direction.

[0104] The circuit chip DC1 is divided into, for example, a transfer region XR1, sense regions SRa1 and SRb1, peripheral circuit regions PRa1 and PRb1, and an input / output region IOR1 when viewed in the Z direction.

[0105] The transfer region XR1 is a region where the LV transistors and VLV transistors that make up the row decoder module 16 are arranged. When viewed in the Z direction, the transfer region XR1 is arranged so as to overlap the entire draw-out region HR, the portion of the memory region MRa that is adjacent to the draw-out region HR, and the portion of the memory region MRb that is adjacent to the draw-out region HR. In other words, the length of the transfer region XR1 in the X direction is longer than the length of the draw-out region HR in the X direction.

[0106] The sense regions SRa1 and SRb1 are regions where the LV transistors and VLV transistors that make up the sense amplifier module 17 are arranged. The sense regions SRa1 and SRb1 sandwich the transfer region XR1 in the X direction. The sense regions SRa1 and SRb1 are arranged so as to overlap the memory regions MRa and MRb, respectively, when viewed in the Z direction.

[0107] The peripheral circuit regions PRa1 and PRb1 are regions where the LV transistors and VLV transistors that make up the register 12, sequencer 13, voltage generation circuit 14, and driver module 15 are arranged. The peripheral circuit regions PRa1 and PRb1 sandwich the transfer region XR1 in the X direction. The peripheral circuit regions PRa1 and PRb1 are aligned with the sense regions SRa1 and SRb1, respectively, in the Y direction. The peripheral circuit regions PRa1 and PRb1 are arranged so as to overlap with the memory regions MRa and MRb, respectively, when viewed in the Z direction.

[0108] The input / output region IOR1 is an area where circuits and wiring for supplying power supply voltages and the like to the circuit chip DC1 are formed. The input / output region IOR1 is aligned in the Y direction with the peripheral circuit regions PRa1 and PRb1 and the transfer region XR1. The input / output region IOR1 is arranged so as to overlap with the input / output region IOR0 when viewed in the Z direction.

[0109] The circuit chip DC2 is divided, for example, in the Z direction into a transfer region XR2, sense regions SRa2 and SRb2, peripheral circuit regions PRa2 and PRb2, and an input / output region IOR2.

[0110] The transfer region XR2 is a region where the HV transistors and LV transistors that make up the row decoder module 16 are arranged. When viewed in the Z direction, the transfer region XR2 is arranged so as to overlap the entire draw-out region HR, the portion of the memory region MRa that is adjacent to the draw-out region HR, and the portion of the memory region MRb that is adjacent to the draw-out region HR. In other words, the length of the transfer region XR2 in the X direction is longer than the length of the draw-out region HR in the X direction.

[0111] The sense regions SRa2 and SRb2 are regions where HV transistors and LV transistors that configure the sense amplifier module 17 are arranged. The sense regions SRa2 and SRb2 sandwich the transfer region XR2 in the X direction. The sense regions SRa2 and SRb2 are arranged to overlap the memory regions MRa and MRb, respectively, when viewed in the Z direction.

[0112] The peripheral circuit regions PRa2 and PRb2 are regions where the HV transistors and LV transistors that make up the register 12, sequencer 13, voltage generation circuit 14, and driver module 15 are arranged. The peripheral circuit regions PRa2 and PRb2 sandwich the transfer region XR2 in the X direction. The peripheral circuit regions PRa2 and PRb2 are aligned with the sense regions SRa2 and SRb2, respectively, in the Y direction. The peripheral circuit regions PRa2 and PRb2 are arranged to overlap the memory regions MRa and MRb, respectively, when viewed in the Z direction.

[0113] The input / output region IOR2 is a region where circuits and wiring for supplying power supply voltages and the like to the circuit chip DC2 are formed. The input / output region IOR2 is aligned in the Y direction with the peripheral circuit regions PRa2 and PRb2 and the transfer region XR2. The input / output region IOR2 is arranged so as to overlap the input / output regions IOR0 and IOR1 when viewed in the Z direction.

[0114] <Cross-sectional structure> 13 is a cross-sectional view taken along plane XIII of FIG. 12, showing an example of the cross-sectional structure of the memory device according to the first embodiment. FIG. 14 is a cross-sectional view taken along plane XIV of FIG. 12, showing an example of the cross-sectional structure of the memory device according to the first embodiment. Plane XIII is a plane including the memory region MRb and lead-out region HR of memory chip DC0, the sense region SRb1 and transfer region XR1 of circuit chip DC1, and the sense region SRb2 and transfer region XR2 of circuit chip DC2. Plane XIV is a plane including the memory region MRb and input / output region IOR0 of memory chip DC0, the transfer region XR1 and input / output region IOR1 of circuit chip DC1, and the transfer region XR2 and input / output region IOR2 of circuit chip DC2.

[0115] 13 and 14, the memory device 3 includes, in memory chip DC0, a surface protection layer 30, insulator layers 31 and 37, a semiconductor layer 20A, conductor layers 25, 26, and 27, and contacts CC0, V0, and V1. In circuit chip DC1, the memory device 3 includes a substrate 50, insulator layers 51 and 52, conductor layers GC1 and 53-56, and contacts CS1 and C0-C3. In circuit chip DC2, the memory device 3 includes a substrate 60, insulator layers 61-64, conductor layers GC2 and 65-69, and contacts CS2 and C4-C8.

[0116] In the input / output region IOR0, the semiconductor layer 20A is provided in the same layer as the semiconductor layer 20. The semiconductor layer 20A is electrically insulated from the semiconductor layer 20. A conductor layer 27 is provided on the semiconductor layer 20A on the opposite side of the semiconductor layer 20A from the memory cell array 10. A part of the conductor layer 27 is exposed on the surface of the memory device 3 and is used as an input / output pad PAD.

[0117] The insulator layer 31 is provided on the semiconductor layer 20 on the opposite side of the semiconductor layer 20 from the memory cell array 10. A conductor layer 27 is provided in the insulator layer 31. The surface protection layer 30 is provided on the insulator layer 31. The surface protection layer 30 is a layer corresponding to the surface of the memory device 3 and contains, for example, a resin material such as polyimide. In the input / output region IOR0, a portion of the surface protection layer 30 is removed. The conductor layer 27 is exposed from the portion where the surface protection layer 30 has been removed.

[0118] A contact CC0 is provided on the semiconductor layer 20A on the memory cell array 10 side of the semiconductor layer 20A. A conductor layer 24c is provided on the contact CC0. The conductor layer 24c is provided in the same layer as the conductor layers 24a and 24b. Hereinafter, the layer at the height where the conductor layers 24a and 24b are provided will be referred to as the wiring layer M0.

[0119] A contact V0 is provided on each of the conductor layers 24a, 24b, and 24c. A conductor layer 25 is provided on the contact V0. The conductor layer 25 extends in a direction (e.g., the X direction) that intersects with the conductor layer 24 in the XY plane. A contact V1 is provided on the conductor layer 25. A conductor layer 26 is provided on the contact V1. That is, the contacts V0 and V1 are arranged so as not to overlap when viewed in the Z direction. Therefore, when viewed in the Z direction, the conductor layer 26 is arranged at a position shifted in the X direction relative to the corresponding conductor layer 24a.

[0120] The contact V0, the conductive layer 25, and the contact V1 are covered with an insulator layer 36. An insulator layer 37 is provided on the insulator layer 36. The conductive layer 26 is provided within the insulator layer 37. The insulator layer 37 is, for example, a silicon oxide film.

[0121] Hereinafter, the layer at the height where the conductive layer 25 is provided will be referred to as the wiring layer M1, and the layer at the height where the conductive layer 26 and the insulating layer 37 are provided will be referred to as the bonding layer B1.

[0122] The substrate 50 is a silicon substrate and has a thickness of, for example, about 1 micrometer (μm).

[0123] The insulator layer 51 is provided on the substrate 50. The insulator layer 51 covers the circuits (e.g., the conductor layers 53 to 55 and the contacts CS1 and C0 to C3) provided on the substrate 50. The insulator layer 51 may be composed of a plurality of insulator layers. The insulator layer 51 also includes, in order from the substrate 50 side, wiring layers D0, D1, and D2. Wiring for the circuit chip DC1 is provided on the wiring layers D0, D1, and D2.

[0124] The insulator layer 52 is provided on the insulator layer 51. The insulator layer 52 contacts the insulator layer 64 included in the circuit chip DC2. The boundary between the insulator layer 52 and the insulator layer 64 corresponds to the bonding surface between the circuit chip DC1 and the circuit chip DC2. The insulator layer 52 is, for example, a silicon oxide film. Hereinafter, the layer including the insulator layer 52 will be referred to as the bonding layer B4.

[0125] The substrate 60 is a silicon substrate. The substrate 60 may have a thickness of, for example, about 10 μm. From the viewpoint of ease of processing through vias that provide electrical connection between the circuit chips DC1 and DC2, it is preferable that the thickness of the substrate 60 is as thin as possible. Therefore, the substrate 60 may have a thickness similar to that of the substrate 50 (i.e., about 1 μm).

[0126] The insulator layer 61 is provided on the substrate 60. The insulator layer 61 covers the circuits provided on the substrate 60 (for example, the conductor layers 65 to 67, part of the contact C4, and the contacts CS2 and C5 to C8). The insulator layer 61 may be composed of a plurality of insulator layers. The insulator layer 61 also includes, in order from the substrate 60 side, wiring layers MD0, MD1, and MD2. Wiring for the circuit chip DC2 is provided on the wiring layers MD0, MD1, and MD2.

[0127] The insulator layer 62 is provided on the insulator layer 61. The insulator layer 62 contacts the insulator layer 37 included in the memory chip DC0. The boundary between the insulator layer 62 and the insulator layer 37 corresponds to the bonding surface between the circuit chip DC2 and the memory chip DC0. The insulator layer 62 is, for example, a silicon oxide film. Hereinafter, the layer including the insulator layer 62 will be referred to as the bonding layer B2. The bonding layer B2 contacts the bonding layer B1.

[0128] The insulator layer 63 is provided on the substrate 60 on the opposite side of the substrate 60 to the insulator layer 61. An insulator layer 64 is provided on the insulator layer 63. Hereinafter, the layer including the insulator layer 64 will be referred to as a bonding layer B3. The bonding layer B3 is in contact with the bonding layer B4.

[0129] The conductor layer GC1 is provided on a gate insulating film provided on the substrate 50. The conductor layer GC1 in the sense region SRb1 is used, for example, as the gate electrodes of the LV transistor and the VLV transistor (e.g., transistor T10) included in the sense amplifier module 17. The conductor layer GC1 in the transfer region XR1 is used, for example, as the gate electrodes of the LV transistor and the VLV transistor (e.g., transistor TR13) included in the row decoder module 16. The conductor layer GC1 in the input / output region IOR1 is used, for example, as the gate electrodes of the LV transistor and the VLV transistor included in the input / output module 11.

[0130] The contact C0 is provided on the conductive layer GC1. Two contacts CS1 belonging to a certain transistor are connected to two impurity diffusion regions (not shown) provided in the substrate 50. For example, these two impurity diffusion regions correspond to the source and drain of the transistor, respectively. Shallow trench isolation (STI) is provided in the substrate 50 as appropriate depending on the layout of the transistor.

[0131] Conductor layers 53 are provided on contacts CS1 and C0, respectively. Conductor layer 53 is included in wiring layer D0. Conductor layer 54 is provided on conductive layer 53 via contact C1. Conductor layer 54 is included in wiring layer D2. Conductor layer 55 is provided on conductive layer 54 via contact C2. Conductor layer 55 is included in wiring layer D2. Conductor layer 56 is provided on conductive layer 55 via contact C3. A conductive layer 69 disposed opposite to conductive layer 56 contacts the conductive layer 56. Conductor layers 56 and 69 correspond to bonding pads BP used for bonding between circuit chips DC1 and DC2. Conductor layers 56 and 69 include, for example, copper.

[0132] A contact C4 is provided on the conductive layer 69. The contact C4 penetrates the insulator layer 63 and the substrate 60. The contact C4 and the substrate 60 are insulated from each other by an insulating film INS. The contact C4 corresponds to a through silicon via (TSV).

[0133] The conductor layer GC2 is provided on a gate insulating film provided on the substrate 60. The conductor layer GC2 in the sense region SRb2 is used, for example, as the gate electrodes of the HV transistor and the LV transistor (for example, transistor T8) included in the sense amplifier module 17. The conductor layer GC2 in the transfer region XR2 is used, for example, as the gate electrodes of the HV transistor and the LV transistor (for example, transistor TR0) included in the row decoder module 16.

[0134] The contact C5 is provided on the conductive layer GC2. Two contacts CS2 belonging to a transistor are connected to two impurity diffusion regions (not shown) provided in the substrate 60. For example, these two impurity diffusion regions correspond to the source and drain of the transistor, respectively. STI is provided in the substrate 60 as appropriate depending on the transistor layout. The contacts C5 and CS2 are longer than the contacts C0 and CS1.

[0135] Conductor layers 65 are provided on contacts CS2, C4, and C5, respectively. The conductive layer 65 is included in the wiring layer MD0. A conductive layer 66 is provided on the conductive layer 65 via a contact C6. The conductive layer 66 is included in the wiring layer MD1. The conductive layer 66 may be provided in the current path between contacts CS2 and C4, or in the current path between contacts CS2 and C7. A conductive layer 67 is provided on the conductive layer 66 via a contact C7. The conductive layer 67 is included in the wiring layer MD2. A conductive layer 68 is provided on the conductive layer 67 via a contact C8. The conductive layer 26, which is disposed opposite to the conductive layer 68, is in contact with the conductive layer 68. The conductive layers 68 and 26 correspond to bonding pads BP used for bonding between the memory chip DC0 and the circuit chip DC2. The conductive layers 68 and 26 include, for example, copper.

[0136] In this way, in the first embodiment, the substrate 50, the circuit provided on the substrate 50, the substrate 60, and the circuit provided on the substrate 60 are arranged in this order in the Z2 direction.

[0137] With the above configuration, the conductor layer 24a (bit line BL) in the memory region MRb is electrically connected to the HV transistors and LV transistors provided in the sense region SRb2 and the LV transistors and VLV transistors provided in the sense region SRb1. The conductor layer 24b in the lead-out region HR is electrically connected to the HV transistors and LV transistors provided in the transfer region XR2 and the LV transistors and VLV transistors provided in the transfer region XR1. The conductor layer 24c in the input / output region IOR0 is electrically connected to the LV transistors and VLV transistors provided in the input / output region IOR1.

[0138] 1.3 Effects of the First Embodiment According to the first embodiment, the memory chip DC0 includes a memory cell array 10 having word lines WL and bit lines BL. The circuit chip DC2 includes a substrate 60 and a first circuit provided on the substrate 60, and is in contact with the memory chip DC0. The circuit chip DC1 includes a substrate 50 and a second circuit provided on the substrate 50, and is in contact with the circuit chip DC2. The memory chip DC0 and the circuit chip DC2 are arranged in this order in the Z1 direction from the word lines WL to the bit lines BL. The first circuit includes a transistor (e.g., transistor T8) in the sense amplifier module 17, which is an HV transistor connected to the bit lines BL, and a transistor (e.g., transistor TR0) in the row decoder module 16, which is an HV transistor connected to the word lines WL. The second circuit includes a transistor in the input / output module 11, which is a VLV transistor connected to the input / output pad PAD. This allows the transistors to be distributed across two chips. This reduces the area of ​​one chip compared to when the transistors are arranged on a single chip. Therefore, it is possible to avoid a situation where the size of the circuit chip limits the size of the memory device, and to suppress an increase in the area of ​​the memory device.

[0139] Furthermore, by arranging the drivers that drive the memory cell array 10 on the circuit chip DC2, the wiring length, the number of contacts, and the number of bonding pads BP can be reduced compared to when the drivers are arranged on the circuit chip DC1, thereby preventing a decrease in yield.

[0140] Furthermore, by placing the HV transistors on the circuit chip DC2 and the VLV transistors on the circuit chip DC1, the HV transistors and the VLV transistors can be placed on different chips. This allows the length of the contact CS1 of the VLV transistor to be shorter than the contact CS2 of the HV transistor, compared to when the HV transistors and the VLV transistors are placed on the same chip. This allows the size of the VLV transistor to be smaller than the size of the HV transistor.

[0141] 1.4 Modification of the first embodiment In the first embodiment described above, the input / output pads PAD are provided on the memory chip DC0, but this is not limiting. For example, the input / output pads PAD may be provided on the circuit chip DC1. The following mainly describes configurations that differ from the first embodiment. Descriptions of configurations equivalent to those of the first embodiment will be omitted as appropriate.

[0142] Fig. 15 is a perspective view showing an example of a laminated structure of memory devices and a planar layout of each chip according to a modified example of Embodiment 1. Fig. 15 corresponds to Fig. 12 in the first embodiment.

[0143] As shown in FIG. 15, the memory chip DC0 and each of the circuit chips DC1 and DC2 may not have an input / output region.

[0144] Fig. 16 is a cross-sectional view taken along plane XVI of Fig. 15, showing an example of the cross-sectional structure of a memory device according to a modified example of the first embodiment. Plane XVI is a plane including the memory region MRb of memory chip DC0, the transfer region XR1 of circuit chip DC1, and the transfer region XR2 of circuit chip DC2. Fig. 16 corresponds to Fig. 14 in the first embodiment.

[0145] 16, the memory device 3 may include a surface protection layer 58, an insulator layer 57, a conductor layer 59, and a contact C9 in the circuit chip DC1 instead of the surface protection layer 30, the insulator layer 31, the conductor layer 27, and the contact CC0. The memory device 3 may further include a substrate 28 in the memory chip DC0.

[0146] The substrate 28 is, for example, a silicon substrate. The substrate 28 is provided on the semiconductor layer 20, for example, on the opposite side of the semiconductor layer 20 from the memory cell array 10. The substrate 28 may be provided on the semiconductor layer 20 via an insulating layer (not shown).

[0147] The insulating layer 57 is provided on the substrate 50 on the opposite side of the substrate 50 from the circuit provided on the substrate 50. A surface protective layer 58 is provided on the insulating layer 57. The surface protective layer 58 is a layer corresponding to the surface of the memory device 3 and contains, for example, a resin material such as polyimide. In the transfer region XR1 (or the peripheral circuit region PR1, not shown), a portion of the surface protective layer 58 is removed. The conductive layer 59 is exposed from the portion where the surface protective layer 58 has been removed.

[0148] The conductive layer 59 is provided in the insulating layer 57. The portion of the conductive layer 59 exposed from the portion where the surface protection layer 58 has been removed is used as an input / output pad PAD.

[0149] A contact C9 is provided on the surface of the conductive layer 59 facing the substrate 50. The contact C9 penetrates the substrate 50. The contact C9 and the substrate 50 are insulated by an insulating film INS. The contact C9 corresponds to a through via.

[0150] The contact C9 is connected to the LV transistor and VLV transistor included in the input / output module 11 in the transfer region XR1 (or the peripheral circuit region PR1, not shown) via, for example, the conductive layers 53 and 54 and the contacts C1 and CS1.

[0151] With the above configuration, the LV transistor and VLV transistor included in the input / output module 11 are connected to the input / output pad PAD without going through the memory chip DC0 and the circuit chip DC2.

[0152] According to the modification of the first embodiment, the input / output pads PAD are arranged on the surface of the circuit chip DC1 opposite to the bonding surface with the circuit chip DC2, at positions overlapping the memory cell array 10 when viewed in the Z direction. This makes it possible to reduce the input / output regions IOR0 to IOR2 from the memory chip DC0 and the circuit chips DC1 and DC2, respectively. This allows the area of ​​the memory device 3 to be reduced.

[0153] In the modification of the first embodiment, the thickness of the substrate 60 is about 10 μm due to the inclusion of HV transistors, as in the first embodiment, whereas the thickness of the substrate 50 can be made about 1 μm because it does not include HV transistors, thereby reducing the cost of forming through vias in the substrate 50.

[0154] 2. Second embodiment Next, a memory device according to a second embodiment will be described. In the second embodiment, the direction from the substrate 50 toward the circuit provided on the substrate 50 is the Z2 direction, while the circuit chips DC1 and DC2 are bonded so that the direction from the substrate 60 toward the circuit provided on the substrate 60 is the Z1 direction. The following mainly describes the configuration different from the first embodiment. Explanations of the configuration equivalent to the first embodiment will be omitted as appropriate.

[0155] 2.1 Memory Device Structure Figures 17 and 18 are cross-sectional views showing an example of the cross-sectional structure of a memory device according to the second embodiment, which correspond to Figures 13 and 14 in the first embodiment, respectively.

[0156] As shown in FIGS. 17 and 18, in the second embodiment, the substrate 50, the circuit provided on the substrate 50, the circuit provided on the substrate 60, and the substrate 60 are arranged in this order in the Z2 direction.

[0157] Specifically, the insulator layer 52 contacts the insulator layer 62 included in the circuit chip DC2. The boundary between the insulator layer 52 and the insulator layer 62 corresponds to the bonding surface between the circuit chip DC1 and the circuit chip DC2. The conductive layer 68 in the opposing insulator layer 62 contacts the conductive layer 56 in the insulator layer 52. That is, the bonding layer B4 contacts the bonding layer B2.

[0158] Furthermore, the insulator layer 64 contacts the insulator layer 37 included in the memory chip DC0. The boundary between the insulator layer 64 and the insulator layer 37 corresponds to the bonding surface between the circuit chip DC2 and the memory chip DC0. The conductor layer 26 in the opposing insulator layer 37 contacts the conductor layer 69 in the insulator layer 64. That is, the bonding layer B3 contacts the bonding layer B1.

[0159] With the above configuration, the conductor layer 24a (bit line BL) in the memory region MRb is electrically connected to the HV transistors and LV transistors provided in the sense region SRb2 or the LV transistors and VLV transistors provided in the sense region SRb1. The conductor layer 24b in the lead-out region HR is electrically connected to the HV transistors and LV transistors provided in the transfer region XR2 and the LV transistors and VLV transistors provided in the transfer region XR1. The conductor layer 24c in the input / output region IOR0 is electrically connected to the LV transistors and VLV transistors provided in the input / output region IOR1.

[0160] 2.2 Effects of the Second Embodiment According to the second embodiment, the first circuit provided on the substrate 60, the substrate 60, the second circuit provided on the substrate 50, and the substrate 50 are arranged in this order in the Z1 direction. In this way, even with a structure in which the circuit chips DC1 and DC2 face each other (face-to-face), it is possible to achieve the same effect as the structure in which the circuit chips DC1 and DC2 face the same direction (face-to-back) as in the first embodiment.

[0161] 2.3 Modification of the second embodiment In the second embodiment described above, the input / output pads PAD are provided on the memory chip DC0, but this is not limiting. For example, the input / output pads PAD may be provided on the circuit chip DC1. The following mainly describes the configuration that differs from the second embodiment. Explanations of the configuration equivalent to the second embodiment will be omitted as appropriate.

[0162] In the modification of the second embodiment, similarly to the modification of the first embodiment, the memory chip DC0 and the circuit chips DC1 and DC2 may not have an input / output region.

[0163] Fig. 19 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to a modification of the second embodiment, which corresponds to Fig. 16 in the modification of the first embodiment.

[0164] 19, the memory device 3 may include a surface protection layer 58, an insulator layer 57, a conductor layer 27, and a contact C9 in the circuit chip DC1 instead of the surface protection layer 30, the insulator layer 31, the conductor layer 27, and the contact CC0. The memory device 3 may further include a substrate 28 in the memory chip DC0.

[0165] The substrate 28 is, for example, a silicon substrate. The substrate 28 is provided on the semiconductor layer 20, for example, on the opposite side of the semiconductor layer 20 from the memory cell array 10. The substrate 28 may be provided on the semiconductor layer 20 via an insulating layer (not shown).

[0166] The insulating layer 57 is provided on the substrate 50 on the opposite side of the substrate 50 from the circuit provided on the substrate 50. A surface protective layer 58 is provided on the insulating layer 57. The surface protective layer 58 is a layer corresponding to the surface of the memory device 3 and contains, for example, a resin material such as polyimide. In the transfer region XR1 (or the peripheral circuit region PR1, not shown), a portion of the surface protective layer 58 is removed. The conductive layer 59 is exposed from the portion where the surface protective layer 58 has been removed.

[0167] The conductive layer 59 is provided in the insulating layer 57. The portion of the conductive layer 59 exposed from the portion where the surface protection layer 58 has been removed is used as an input / output pad PAD.

[0168] A contact C9 is provided on the surface of the conductive layer 59 facing the substrate 50. The contact C9 penetrates the substrate 50. The contact C9 and the substrate 50 are insulated by an insulating film INS. The contact C9 corresponds to a through via.

[0169] The contact C9 is connected to the LV transistor and VLV transistor included in the input / output module 11 in the transfer region XR1 (or the peripheral circuit region PR1, not shown) via, for example, the conductive layers 53 and 54 and the contacts C1 and CS1.

[0170] With the above configuration, the LV transistor and VLV transistor included in the input / output module 11 are connected to the input / output pad PAD without going through the memory chip DC0 and the circuit chip DC2.

[0171] According to the modification of the second embodiment, the input / output pads PAD are arranged on the surface of the circuit chip DC1 opposite to the bonding surface with the circuit chip DC2, at positions overlapping the memory cell array 10 when viewed in the Z direction. This makes it possible to reduce the input / output regions IOR0 to IOR2 from the memory chip DC0 and the circuit chips DC1 and DC2, respectively. This allows the area of ​​the memory device 3 to be reduced.

[0172] Furthermore, since the substrate 50 does not include an HV transistor, the thickness can be reduced to about 1 μm, which reduces the cost of forming through vias in the substrate 50.

[0173] 3. Third embodiment Next, a memory device according to a third embodiment will be described. In the third embodiment, the circuit chip DC1 is joined to the memory chip MC on the side opposite to the circuit chip DC2. The following mainly describes the configuration different from the first embodiment. A separate description of the configuration equivalent to the first embodiment will be omitted.

[0174] 3.1 Memory Device Structure Fig. 20 is a perspective view showing an example of a laminated structure of memory devices and a planar layout of each chip according to the third embodiment, which corresponds to Fig. 12 in the first embodiment.

[0175] 20, the memory device 3 has a structure in which, for example, from the bottom up, a circuit chip DC2, a memory chip DC0, and a circuit chip DC1 are stacked. The circuit chip DC2 and the memory chip DC0, and the memory chip DC0 and the circuit chip DC1 are bonded together by a plurality of bonding pads BP. The individual planar layouts of the memory chip DC0 and the circuit chips DC1 and DC2 are the same as those in the first embodiment.

[0176] FIG. 21 is a cross-sectional view taken along plane XXI of FIG. 20, showing an example of the cross-sectional structure of a memory device according to the third embodiment. FIG. 22 is a cross-sectional view taken along plane XXII of FIG. 20, showing an example of the cross-sectional structure of a memory device according to the third embodiment. Plane XXI is a plane including the memory region MRb and lead-out region HR of memory chip DC0, the sense region SRb1 and transfer region XR1 of circuit chip DC1, and the sense region SRb2 and transfer region XR2 of circuit chip DC2. Plane XXII is a plane including the memory region MRb and input / output region IOR0 of memory chip DC0, the transfer region XR1 and input / output region IOR1 of circuit chip DC1, and the transfer region XR2 and input / output region IOR2 of circuit chip DC2. FIGS. 20 and 21 correspond to FIGS. 13 and 14, respectively, in the first embodiment.

[0177] 21 and 22, the memory device 3 includes an insulator layer 38, a conductor layer 29, and a contact C10 instead of the surface protection layer 30, the semiconductor layer 20A, and the conductor layer 27 in the memory chip DC0. The memory device 3 includes a circuit chip DC1 with a configuration equivalent to that of the first embodiment. The memory device 3 includes a surface protection layer 70 and a conductor layer 71 instead of the insulator layer 64 and the conductor layer 69 in the circuit chip DC2.

[0178] In the input / output region IOR2, the conductive layer 71 is provided in the insulating layer 63. A part of the conductive layer 71 is exposed to the surface of the memory device 3 and is used as an input / output pad PAD.

[0179] The surface protection layer 70 is provided on the insulator layer 63. The surface protection layer 70 is a layer corresponding to the surface of the memory device 3 and contains, for example, a resin material such as polyimide. In the input / output region IOR2, a portion of the surface protection layer 30 is removed. The conductive layer 71 is exposed from the portion where the surface protection layer 30 has been removed.

[0180] A contact C4 is provided on the surface of the conductive layer 71 facing the substrate 60. The contact C4 is connected to the conductive layer 26 included in the memory chip DC0 via conductive layers 65 to 68 and contacts C6 to C8.

[0181] In the input / output region IOR0, the conductor layer 26 is connected to the contact CC0 via the conductor layers 24c and 25 and the contacts V0 and V1. The contact CC0 penetrates the semiconductor layer 20. The contact CC0 and the semiconductor layer 20 are insulated from each other by an insulating film.

[0182] A contact C10 is provided on the contact CC0. The contact C10 passes through the insulating layer 31. A conductive layer 29 is provided on the contact C10.

[0183] An insulator layer 38 is provided on the insulator layer 31 so as to include the conductor layer 29 in the same layer. The insulator layer 38 contacts an insulator layer 52 included in the circuit chip DC1. The boundary between the insulator layer 38 and the insulator layer 52 corresponds to the bonding surface between the memory chip DC0 and the circuit chip DC1. The insulator layer 38 is, for example, a silicon oxide film. Hereinafter, the layer at the height where the conductor layer 29 and the insulator layer 38 are provided will be referred to as the bonding layer B5.

[0184] A conductive layer 29 is provided within the insulating layer 38. A conductive layer 56 is disposed opposite the conductive layer 29. The conductive layers 29 and 56 correspond to the bonding pads BP used for bonding between the memory chip DC0 and the circuit chip DC1. The conductive layers 29 and 56 include, for example, copper.

[0185] In the input / output region IOR1, the conductive layer 56 is connected to transistors provided on the substrate 50 via contacts CS1 and C1 to C3, conductive layers 53 to 55, and the like.

[0186] With the above configuration, the input / output pads PAD provided on the circuit chip DC2 are connected to the transistors provided on the circuit chip DC1 via the memory chip DC0.

[0187] Also, similar to the first embodiment, in the circuit chip DC2, the sense region SRb2 is provided with HV transistors and LV transistors included in the sense amplifier module 17. The transfer region XR2 is provided with HV transistors and LV transistors included in the row decoder module 16. Also, in the circuit chip DC1, the sense region SRb1 may be provided with LV transistors and VLV transistors included in the sense amplifier module 17. The transfer region XR1 may be provided with LV transistors and VLV transistors included in the row decoder module 16.

[0188] 3.2 Effects of the third embodiment According to the third embodiment, the circuit chip DC1 contacts the memory chip DC0. The circuit chip DC1, memory chip DC0, and circuit chip DC2 are arranged in this order in the Z1 direction. In this way, even with a structure in which the memory chip DC0 is sandwiched between the circuit chips DC1 and DC2, it is possible to achieve the same effects as with the structures in which the circuit chips DC1 and DC2 stacked on the memory chip DC0 are joined, as in the first and second embodiments.

[0189] 3.3 Modification of the third embodiment In the third embodiment described above, the input / output pads PAD are provided on the circuit chip DC2, but this is not limiting. For example, the input / output pads PAD may be provided on the circuit chip DC1. The following mainly describes the configuration different from the third embodiment. Explanations of the configuration equivalent to the third embodiment will be omitted as appropriate.

[0190] Fig. 23 is a perspective view showing an example of a laminated structure of memory devices and a planar layout of each chip according to a modification of the third embodiment, which corresponds to Fig. 20 in the third embodiment.

[0191] As shown in FIG. 23, the memory chip DC0 and each of the circuit chips DC1 and DC2 may not have an input / output region.

[0192] Fig. 24 is a cross-sectional view taken along plane XXIV of Fig. 23, showing an example of the cross-sectional structure of a memory device according to a modified example of the third embodiment. Plane XXIV is a plane including the memory region MRb of memory chip DC0, the transfer region XR1 of circuit chip DC1, and the transfer region XR2 of circuit chip DC2. Fig. 24 corresponds to Fig. 22 in the third embodiment.

[0193] As shown in FIG. 24, the memory device 3 may include a surface protection layer 58, an insulator layer 57, a conductor layer 59, and a contact C9 in the circuit chip DC1 instead of the surface protection layer 70, the insulator layer 63, the conductor layer 71, and the contacts CC0, C4, and C10.

[0194] The insulating layer 57 is provided on the substrate 50 on the opposite side of the substrate 50 from the circuit provided on the substrate 50. A surface protective layer 58 is provided on the insulating layer 57. The surface protective layer 58 is a layer corresponding to the surface of the memory device 3 and contains, for example, a resin material such as polyimide. In the transfer region XR1 (or the peripheral circuit region PR1, not shown), a portion of the surface protective layer 58 is removed. The conductive layer 59 is exposed from the portion where the surface protective layer 58 has been removed.

[0195] The conductive layer 59 is provided in the insulating layer 57. The portion of the conductive layer 59 exposed from the portion where the surface protection layer 58 has been removed is used as an input / output pad PAD.

[0196] A contact C9 is provided on the surface of the conductive layer 59 facing the substrate 50. The contact C9 penetrates the substrate 50. The contact C9 and the substrate 50 are insulated by an insulating film INS. The contact C9 corresponds to a through via.

[0197] The contact C9 is connected to the LV transistor and VLV transistor included in the input / output module 11 in the transfer region XR1 (or the peripheral circuit region PR1, not shown) via, for example, the conductive layers 53 and 54 and the contacts C1 and CS1.

[0198] With the above configuration, the LV transistor and VLV transistor included in the input / output module 11 are connected to the input / output pad PAD without going through the memory chip DC0 and the circuit chip DC2.

[0199] According to the modification of the third embodiment, the input / output pads PAD are arranged on the surface of the circuit chip DC1 opposite to the bonding surface with the circuit chip DC2, at positions overlapping the memory cell array 10 when viewed in the Z direction. This makes it possible to reduce the input / output regions IOR0 to IOR2 from the memory chip DC0 and the circuit chips DC1 and DC2, respectively. This allows the area of ​​the memory device 3 to be reduced.

[0200] Furthermore, since the substrate 50 does not include an HV transistor, the thickness can be reduced to about 1 μm, which reduces the cost of forming through vias in the substrate 50.

[0201] 4. Fourth embodiment Next, a memory device according to a fourth embodiment will be described. In the fourth embodiment, an HV transistor and an LV transistor are provided on a circuit chip DC1, and an N-type HV transistor, an LV transistor, and a VLV transistor are provided on a circuit chip DC2. The following mainly describes the configuration different from the first embodiment. Explanations of the configuration equivalent to the first embodiment will be omitted as appropriate.

[0202] 4.1 Memory Device Structure <Lamination structure and plan layout> Fig. 25 is a perspective view showing an example of a laminated structure of memory devices and a planar layout of each chip according to the fourth embodiment, which corresponds to Fig. 12 in the first embodiment.

[0203] 25, the memory device 3 has a structure in which, for example, a circuit chip DC1, a circuit chip DC2, and a memory chip DC0 are stacked in this order from the bottom up. The circuit chip DC1 and the circuit chip DC2, and the circuit chip DC2 and the memory chip DC0 are bonded together by a plurality of bonding pads BP.

[0204] The circuit chips DC1 and DC2 include CMOS circuits. The circuit chip DC1 mainly includes HV transistors and LV transistors. The circuit chip DC2 mainly includes N-type HV transistors, LV transistors, and VLV transistors. The memory chip DC0 includes memory cell transistors MT.

[0205] The planar layout of the memory chip DC0 is the same as that of the first embodiment.

[0206] The circuit chip DC1 is divided into, for example, a transfer region XR1, peripheral circuit regions PRa1 and PRb1, and an input / output region IOR1 when viewed in the Z direction.

[0207] The transfer region XR1 is a region in which the HV transistors and LV transistors that constitute the row decoder module 16 are arranged. All of the transistors that constitute the row decoder module 16 may be arranged in the transfer region XR1. When viewed in the Z direction, the transfer region XR1 is arranged to overlap the entire draw-out region HR, the portion of the memory region MRa that is adjacent to the draw-out region HR, and the portion of the memory region MRb that is adjacent to the draw-out region HR. In other words, the length of the transfer region XR1 in the X direction is longer than the length of the draw-out region HR in the X direction. Note that the portion of the transfer region XR1 that overlaps with the draw-out region HR does not overlap with the sense regions SRa2 and SRb2 of the circuit chip DC2, which will be described later.

[0208] The peripheral circuit regions PRa1 and PRb1 are regions where the HV transistors and LV transistors that make up the register 12, the sequencer 13, the voltage generation circuit 14, and the driver module 15 are arranged. The peripheral circuit regions PRa1 and PRb1 sandwich the transfer region XR1 in the X direction. The peripheral circuit regions PRa1 and PRb1 are arranged so as to overlap the memory regions MRa and MRb, respectively, when viewed in the Z direction.

[0209] The input / output region IOR1 is an area where circuits and wiring for supplying power supply voltages and the like to the circuit chip DC1 are formed. The input / output region IOR1 is aligned in the Y direction with the peripheral circuit regions PRa1 and PRb1 and the transfer region XR1. The input / output region IOR1 is arranged so as to overlap with the input / output region IOR0 when viewed in the Z direction.

[0210] The circuit chip DC2 is divided, for example, in the Z direction into a transfer region XR2, sense regions SRa2 and SRb2, peripheral circuit regions PRa2 and PRb2, and an input / output region IOR2.

[0211] The transfer region XR2 is almost free of transistors constituting the row decoder module 16. Some of the LV transistors and VLV transistors constituting the row decoder module 16 may be arranged in the transfer region XR2. The transfer region XR2 overlaps with the draw-out region HR when viewed in the Z direction, but is arranged so as not to overlap with the memory regions MRa and MRb. In other words, the length of the transfer region XR2 in the X direction is equal to the length of the draw-out region HR in the X direction and shorter than the length of the transfer region XR1 in the X direction.

[0212] The sense regions SRa2 and SRb2 are regions where the N-type HV transistors, LV transistors, and VLV transistors that make up the sense amplifier module 17 are arranged. All of the transistors that make up the sense amplifier module 17 may be arranged in the sense region SR1. The sense regions SRa2 and SRb2 sandwich the transfer region XR2 in the X direction. The sense regions SRa2 and SRb2 are arranged to overlap with the memory regions MRa and MRb, respectively, when viewed in the Z direction. Furthermore, the portions of the sense regions SRa2 and SRb2 adjacent to the transfer region XR2 are arranged to overlap with the transfer region XR1 when viewed in the Z direction.

[0213] The peripheral circuit regions PRa2 and PRb2 are regions where the LV transistors and VLV transistors that make up the register 12, sequencer 13, voltage generation circuit 14, and driver module 15 are arranged. The peripheral circuit regions PRa2 and PRb2 sandwich the transfer region XR2 in the X direction. The peripheral circuit regions PRa2 and PRb2 are aligned with the sense regions SRa2 and SRb2, respectively, in the Y direction. The peripheral circuit regions PRa2 and PRb2 are arranged to overlap the memory regions MRa and MRb, respectively, when viewed in the Z direction.

[0214] The input / output region IOR2 is a region where circuits and wiring for supplying power supply voltages and the like to the circuit chip DC2 are formed. The input / output region IOR2 is aligned in the Y direction with the peripheral circuit regions PRa2 and PRb2 and the transfer region XR2. The input / output region IOR2 is arranged so as to overlap the input / output regions IOR0 and IOR1 when viewed in the Z direction. .

[0215] <Cross-sectional structure> FIG. 26 is a cross-sectional view taken along the XXVI plane of FIG. 25, showing an example of the cross-sectional structure of a memory device according to the fourth embodiment. FIG. 27 is a cross-sectional view taken along the XVII plane of FIG. 25, showing an example of the cross-sectional structure of a memory device according to the fourth embodiment. The XXVI plane is a plane including the memory region MRb and lead-out region HR of the memory chip DC0, the peripheral circuit region PRb1 and transfer region XR1 of the circuit chip DC1, and the sense region SRb2 and transfer region XR2 of the circuit chip DC2. The XXVII plane is a plane including the memory region MRb and input / output region IOR0 of the memory chip DC0, the transfer region XR1 and input / output region IOR1 of the circuit chip DC1, and the sense region SRb2, peripheral circuit region PRb2, and input / output region IOR2 of the circuit chip DC2.

[0216] As shown in FIGS. 26 and 27, the memory device 3 includes a conductive layer 25 and a contact V01 instead of the contacts V0 and V1 in the memory chip DC0.

[0217] A contact V01 is provided on each of the conductive layers 24a, 24b, and 24c. A conductive layer 26 is provided on the contact V01. Therefore, the conductive layer 26 is disposed so as to overlap the corresponding conductive layer 24a when viewed in the Z direction.

[0218] The circuit chip DC1 is provided with HV transistors and LV transistors. Therefore, the conductor layer GC1 in the transfer region XR1 is used, for example, as the gate electrodes of the HV transistors and LV transistors (e.g., transistors TR0 and TR13) included in the row decoder module 16. Multiple wirings (e.g., conductor layers 53 and 54 in the transfer region XR1) used for the HV transistors and LV transistors included in the row decoder module 16 are aligned in the Y direction within the circuit chip DC1. Although not shown, the HV transistors provided in the circuit chip DC1 may have a triple well structure. The triple well structure is a structure in which well regions covering the impurity diffusion regions within the substrate 50 are triple-layered.

[0219] The circuit chip DC2 is provided with N-type HV transistors, LV transistors, and VLV transistors. Therefore, the conductor layer GC2 in the sense region SRb is used, for example, as the gate electrodes of the N-type HV transistors, LV transistors, and VLV transistors (e.g., transistors T8 and T10) included in the sense amplifier module 17. Multiple wirings (e.g., conductor layers 65 and 66 in the sense region SRb) used for the N-type HV transistors, LV transistors, and VLV transistors included in the sense amplifier module 17 are aligned in the X direction in the circuit chip DC2. Furthermore, the conductor layer GC2 in the input / output region IOR2 is used, for example, as the gate electrodes of the LV transistors and VLV transistors included in the input / output module 11.

[0220] The height H2 of the contact CS2 in the sense region SRb is smaller than the height H1 of the contact CS1 in the transfer region XR1. The diameter of the contact CS2 in the sense region SRb is smaller than the diameter of the contact CS1 in the transfer region XR1. The size of the transistor in the sense region SRb is smaller than the size of the transistor in the transfer region XR1.

[0221] Furthermore, the pitch P1 in the Y direction between the conductor layers 53 or 54 in the wiring layer D0 of the transfer region XR1 is the minimum pitch in the circuit chip DC1. The pitch P2 in the X direction between the conductor layers 65 or 66 in the wiring layer MD0 of the sense region SRb is the minimum pitch in the circuit chip DC2. Here, the pitches P1 and P2 are designed independently of each other. The pitches P1 and P2 may be equal or different.

[0222] The HV transistors and LV transistors of the transfer region XR1 in such a circuit chip DC1, the N-type HV transistors, LV transistors, and VLV transistors in the sense region SRb in the circuit chip DC2, and the memory cell transistors MT in the memory region MRb in the memory chip DC0 can be arranged in overlapping positions when viewed in the Z direction.

[0223] <Wiring structure> Fig. 28 is a schematic diagram showing an example of the wiring structure of a memory device according to the fourth embodiment. Fig. 28 shows the planar layout of the memory chip DC0 and the circuit chips DC1 and DC2 shown in Fig. 25, and representative wirings W1 and W2 provided on the circuit chips DC1 and DC2, respectively.

[0224] 28, wirings W1a and W1b are provided in the peripheral circuit regions PRa1 and PRb1 of the circuit chip DC1, respectively. In the peripheral circuit regions PRa2 and PRb2 of the circuit chip DC2, wirings W2 are provided so as to cross the transfer region XR2 in the X direction.

[0225] The wirings W1a and W1b include, for example, wiring for supplying a reference voltage and power wiring for supplying a high voltage such as that applied to an HV transistor, such as wiring CG. This allows these power wirings to be located farther from the bit lines BL and source lines SL than if they were located on the circuit chip DC2. This makes it possible to suppress fluctuations in the power supply voltage due to the influence of coupling with the bit lines BL and source lines SL.

[0226] Furthermore, the wirings W1a and W1b include, for example, global wiring extending in the Y direction. The global wiring includes, for example, wiring that transmits signals for cooperation between various circuits in the memory device 3. As described above, the circuit chip DC1 does not have a sense region SR. As a result, the circuit chip DC1 has few circuits that cross the memory device 3 in the X direction when viewed in the Z direction. Therefore, it is relatively easy to secure areas in the peripheral circuit regions PRa1 and PRb1 of the circuit chip DC1 for providing the wirings W1a and W1b, which are part of the global wiring and extend in the Y direction.

[0227] Furthermore, the wiring W2 includes, for example, a global wiring extending in the X direction. As described above, the transfer region XR2 of the circuit chip DC2 is provided with almost no transistors included in the row decoder module 16. As a result, the circuit chip DC2 has few circuits that cross the memory device 3 in the Y direction when viewed in the Z direction. For this reason, it is relatively easy to secure an area in the peripheral circuit regions PRa2 and PRb2 of the circuit chip DC2 and the transfer region XR2 for providing the wiring W2 of the global wiring extending in the X direction.

[0228] 4.2 Effects of the Fourth Embodiment According to the fourth embodiment, a first circuit provided on a substrate 60 includes a sense amplifier module 17 connected to a plurality of bit lines BL. A second circuit provided on a substrate 50 includes a row decoder module 16 connected to a plurality of word lines WL. The row decoder module 16 has a first portion that overlaps the sense amplifier module 17 and the memory region MR of the memory cell array 10 when viewed in the Z direction. This allows the width of the sense amplifier module 17 in the X direction to be approximately the same as the memory region MR, compared to when the row decoder module 16 and the sense amplifier module 17 are arranged on a single chip. This allows the bonding pads between the memory chip DC0 and the circuit chip DC2 to be linearly connected to the corresponding bit lines BL in the Z direction without being shifted in the X direction. This reduces the wiring layout cost and wiring length.

[0229] As described above, the row decoder module 16 and the sense amplifier module 17 are disposed on different circuit chips DC1 and DC2, respectively. Regarding the wiring of the row decoder module 16, the first circuit includes a plurality of conductor layers 65 or 66 arranged in the X direction on the wiring layer MD0 closest to the substrate 60 or the next closest wiring layer MD1, each extending in the Y direction. The second circuit includes a plurality of conductor layers 53 or 54 arranged in the Y direction on the wiring layer D0 closest to the substrate 50 or the next closest wiring layer D1, each extending in the X direction. The pitch P2 of the plurality of conductor layers 65 or 66 is the smallest within the circuit chip DC2. The pitch P1 of the plurality of conductor layers 53 or 54 is the smallest within the circuit chip DC1 and is independent of the pitch P2. This allows for an optimal pitch to be applied, compared to when the row decoder module 16 and the sense amplifier module 17 are disposed on a single circuit chip, where it is difficult to simultaneously minimize the pitches P1 and P2.

[0230] 5. Fifth embodiment Next, a memory device according to a fifth embodiment will be described. In the fifth embodiment, the direction from the substrate 50 toward the circuit provided on the substrate 50 is the Z2 direction, while the circuit chips DC1 and DC2 are bonded so that the direction from the substrate 60 toward the circuit provided on the substrate 60 is the Z1 direction. The following mainly describes the configuration different from the fourth embodiment. Explanations of the configuration equivalent to the fourth embodiment will be omitted as appropriate.

[0231] 5.1 Memory Device Structure Figures 29 and 30 are cross-sectional views showing an example of the cross-sectional structure of the memory device according to the second embodiment. Figures 29 and 30 correspond to Figures 26 and 27 in the fourth embodiment, respectively.

[0232] As shown in FIGS. 29 and 30, in the fifth embodiment, the substrate 50, the circuit provided on the substrate 50, the circuit provided on the substrate 60, and the substrate 60 are arranged in this order in the Z2 direction.

[0233] Specifically, the insulator layer 52 contacts the insulator layer 62 included in the circuit chip DC2. The boundary between the insulator layer 52 and the insulator layer 62 corresponds to the bonding surface between the circuit chip DC1 and the circuit chip DC2. The conductive layer 68 in the opposing insulator layer 62 contacts the conductive layer 56 in the insulator layer 52. That is, the bonding layer B4 contacts the bonding layer B2.

[0234] Furthermore, the insulator layer 64 contacts the insulator layer 37 included in the memory chip DC0. The boundary between the insulator layer 64 and the insulator layer 37 corresponds to the bonding surface between the circuit chip DC2 and the memory chip DC0. The conductor layer 26 in the opposing insulator layer 37 contacts the conductor layer 69 in the insulator layer 64. That is, the bonding layer B3 contacts the bonding layer B1.

[0235] With the above configuration, the conductor layer 24a (bit line BL) in the memory region MRb is electrically connected to the N-type HV transistor, LV transistor, and VLV transistor provided in the sense region SRb. The conductor layer 24b in the lead-out region HR is electrically connected to the HV transistor and LV transistor provided in the transfer region XR1. The conductor layer 24c in the input / output region IOR0 is electrically connected to the LV transistor and VLV transistor provided in the input / output region IOR2.

[0236] 5.2 Effects of the Fifth Embodiment According to the fifth embodiment, the first circuit provided on the substrate 60, the substrate 60, the second circuit provided on the substrate 50, and the substrate 50 are arranged in this order in the Z1 direction. In this way, even with a structure in which the circuit chips DC1 and DC2 face each other (face-to-face), it is possible to achieve the same effect as the structure in which the circuit chips DC1 and DC2 face the same direction (face-to-back) as in the fourth embodiment.

[0237] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents as defined in the claims. [Explanation of symbols]

[0238] 1. Memory system 2...Memory controller 3...Memory device 10...Memory cell array 11... Input / output module 12...Register 13...Sequencer 14...Voltage generation circuit 15...Driver module 16...Row decoder module 17...Sense amplifier module 20, 20A...Semiconductor layer 21, 22, 23, 24, 25, 26, 27, 53, 54, 55, 56, 59, 65, 66, 67, 68, 69, 71...Conductor layers 28, 50, 60... PCB 30,58,70…Surface protective layer 31, 32, 33, 34, 35, 36, 37, 38, 51, 52, 57, 61, 62, 63, 64...Insulator layers 40...Core membrane 41...Semiconductor film 42...Laminated film 43...Tunnel insulating film 44...Charge storage film 45...Block insulating film

Claims

1. a first chip including a memory cell array having word lines and bit lines; a second chip including a first substrate and a first circuit provided on the first substrate and in contact with the first chip; a third chip including a second substrate and a second circuit provided on the second substrate, the third chip being in contact with the first chip or the second chip; an input / output pad; Equipped with the first chip and the second chip are arranged in this order in a first direction from the word line to the bit line; the first circuit includes a first transistor connected to the bit line and a second transistor connected to the word line; the second circuit includes a third transistor connected to the input / output pad; Memory device.

2. the first transistor and the second transistor have a gate oxide film with a thickness of 10 nm or more; the third transistor has a gate oxide film with a thickness of 2.5 nm or more and 3.5 nm or less; The memory device of claim 1 .

3. the third chip is in contact with the second chip; the first chip, the second chip, and the third chip are arranged in this order in the first direction; The memory device of claim 1 .

4. the input / output pads are provided on a surface of the third chip opposite to a surface bonded to the second chip, at positions overlapping with the memory cell array when viewed in the first direction; The memory device of claim 3.

5. the first circuit, the first substrate, the second circuit, and the second substrate are arranged in this order in the first direction; The memory device of claim 3.

6. the first substrate, the first circuit, the second circuit, and the second substrate are arranged in this order in the first direction; The memory device of claim 3.

7. the third chip is in contact with the first chip; the third chip, the first chip, and the second chip are arranged in this order in the first direction; The memory device of claim 1 .

8. the input / output pad is provided on a surface of the third chip opposite to a surface bonded to the first chip, at a position overlapping the memory cell array when viewed in the first direction; The memory device of claim 7.

9. a first chip including a memory cell array having a plurality of word lines and a plurality of bit lines; a second chip including a first substrate and a first circuit provided on the first substrate and in contact with the first chip; a third chip including a second substrate and a second circuit provided on the second substrate and in contact with the second chip; Equipped with the first chip, the second chip, and the third chip are arranged in this order in a first direction from the word line toward the bit line; the first circuit includes a sense amplifier module connected to the plurality of bit lines; the second circuit includes a row decoder module connected to the plurality of word lines; the row decoder module has a first portion that overlaps with the sense amplifier module when viewed in the first direction; Memory device.

10. the memory cell array has a first region in which each of the plurality of word lines faces the second chip without interfering with other word lines; the row decoder module further includes a second portion that overlaps the first region when viewed in the first direction and does not overlap the sense amplifier module; The memory device of claim 9.

11. the memory cell array further includes a second region different from the first region; the first portion overlaps with the second region when viewed in the first direction; The memory device of claim 10.

12. the plurality of bit lines are aligned in a second direction intersecting the first direction, the plurality of word lines are aligned in a third direction intersecting the first direction and the second direction, the first circuit includes a plurality of first conductor layers aligned in the second direction at the same position in the first direction and each extending in the third direction; the second circuit includes a plurality of second conductor layers aligned in the third direction at the same position in the first direction and each extending in the second direction; a first pitch of the plurality of first conductor layers is smallest within the second chip; a second pitch of the plurality of second conductive layers is smallest within the third chip and is independent of the first pitch; The memory device of claim 9.

13. the sense amplifier module further includes a first contact connecting between the first substrate and each of the plurality of first conductive layers; the row decoder module further includes a second contact connecting between the second substrate and each of the plurality of second conductive layers; The length of the first contact in the first direction is shorter than the length of the second contact in the first direction. The memory device of claim 12.

14. the plurality of bit lines are aligned in a second direction intersecting the first direction, the plurality of word lines are aligned in a third direction intersecting the first direction and the second direction, the second chip includes a third conductor layer that includes copper and extends in the third direction in a region that overlaps with the row decoder module when viewed in the first direction; the third chip includes a fourth conductive layer including copper and extending in the second direction in a region overlapping with the sense amplifier module when viewed in the first direction; The memory device of claim 9.

15. The length of the power supply wiring provided in the third chip is longer than the length of the power supply wiring provided in the second chip. The memory device of claim 9.

16. The first circuit comprises: a fourth transistor having a gate oxide film with a thickness of 10 nm or more; a fifth transistor having a gate oxide film with a thickness of 5 nm to 7 nm; a sixth transistor having a gate oxide film with a thickness of 2.5 nm to 3.5 nm; Including, the second circuit includes a seventh transistor having a gate oxide film with a thickness of 10 nm or more; The memory device of claim 9.

17. the seventh transistor has a triple well structure; 17. The memory device of claim 16.

18. the first chip further includes a plurality of bond pads respectively connecting the plurality of bit lines and the second chip; each of the plurality of bond pads is disposed at a position overlapping a corresponding bit line when viewed in the first direction; The memory device of claim 9.

19. the first circuit, the first substrate, the second circuit, and the second substrate are arranged in this order in the first direction; The memory device of claim 9.

20. the first substrate, the first circuit, the second circuit, and the second substrate are arranged in this order in the first direction; The memory device of claim 9.

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