Quantum bit and quantum computing device

Abstract

To provide a method for manufacturing quantum bit and a quantum computing device that can achieve good crystallinity in a transition metal ditelluride layer.SOLUTION: A quantum bit includes an s-wave superconductor layer, a Te layer disposed on the s-wave superconductor layer, a high-order topological insulator layer disposed on the Te layer, a first ferromagnetic insulator layer disposed on the high-order topological insulator layer, and a first gate electrode disposed on the first ferromagnetic insulator layer, and the high-order topological insulator layer has a first region having a first hinge helical channel and a second region having a second hinge helical channel spaced from the first hinge helical channel, and the first ferromagnetic insulator layer covers the first hinge helical channel and the second hinge helical channel.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to qubits and quantum processing devices. [Background technology]

[0002] Research is being conducted on quantum computing devices using Majorana particles. A structure combining a two-dimensional topological insulator and an s-wave superconductor has been proposed as a structure for generating Majorana particles. A single layer of WTe2, a layered material of transition metal ditelluride, has been used as the two-dimensional topological insulator. Research is also being conducted on higher-order topological insulator layers made of multilayered WTe2. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2019 / 0131129 [Patent Document 2] Japanese Patent Application Publication No. 2018-9201 [Non-patent literature]

[0004] [Non-Patent Document 1] N. Read and D. Green, Phys. Rev. B 61, 10267 (2000) [Non-patent document 2] V. Mourik et al., Science 336, 25 (2012) [Non-patent document 3] J. Alicea, Rep. Prog. Phys. 75, 076501 (2012) [Non-patent document 4] S. Wu et al., Science 359, 76 (2018) [Non-Patent Document 5] Y.-B. Choi et al., Nat. Mater 19, 974 (2020) Summary of the Invention [Problem to be solved by the invention]

[0005] Although theoretical proposals have been made, it is not easy to stably obtain a layer of a transition metal ditelluride such as WTe2 with good crystallinity.

[0006] An object of the present disclosure is to provide a quantum bit and a quantum processing device that can obtain good crystallinity in a transition metal ditelluride layer. [Means for solving the problem]

[0007] According to one aspect of the present disclosure, a quantum bit is provided, comprising: an s-wave superconductor layer; a Te layer disposed on the s-wave superconductor layer; a high-order topological insulator layer disposed on the Te layer; a first ferromagnetic insulator layer disposed on the high-order topological insulator layer; and a first gate electrode disposed on the first ferromagnetic insulator layer, wherein the high-order topological insulator layer has a first region having a first hinged helical channel and a second region having a second hinged helical channel spaced from the first hinged helical channel, and the first ferromagnetic insulator layer covers the first hinged helical channel and the second hinged helical channel. [Effects of the Invention]

[0008] According to the present disclosure, good crystallinity can be obtained in the transition metal ditelluride layer. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a cross-sectional view showing a structure according to the first embodiment. [Figure 2] FIG. 2 is a diagram showing the results of Raman spectroscopy measurement according to the first embodiment. [Figure 3]FIG. 3 is a cross-sectional view showing a structure according to the second embodiment. [Figure 4] FIG. 4 is a diagram showing the results of Raman spectroscopy measurement according to the second embodiment. [Figure 5] FIG. 5 is a cross-sectional view showing a structure according to the third embodiment. [Figure 6] FIG. 6 is a diagram showing the results of Raman spectroscopy measurement according to the third embodiment. [Figure 7] FIG. 7 is a top view showing a quantum bit according to the fourth embodiment. [Figure 8] FIG. 8 is a cross-sectional view (part 1) showing a quantum bit according to the fourth embodiment. [Figure 9] FIG. 9 is a cross-sectional view (part 2) showing a quantum bit according to the fourth embodiment. [Figure 10] FIG. 10 is a perspective view showing a higher-order topological insulator layer. [Figure 11] FIG. 11 is a top view (part 1) showing a method for manufacturing a quantum bit according to the fourth embodiment. [Figure 12] FIG. 12 is a top view (part 2) showing the method for manufacturing a quantum bit according to the fourth embodiment. [Figure 13] FIG. 13 is a top view (part 3) showing the method for manufacturing a quantum bit according to the fourth embodiment. [Figure 14] FIG. 14 is a top view (part 4) showing the method for manufacturing a quantum bit according to the fourth embodiment. [Figure 15] FIG. 15 is a top view (part 5) illustrating the method for manufacturing a quantum bit according to the fourth embodiment. [Figure 16] FIG. 16 is a top view (part 6) showing the method for manufacturing a quantum bit according to the fourth embodiment. [Figure 17] FIG. 17 is a cross-sectional view (part 1) showing a method for manufacturing a quantum bit according to the fourth embodiment. [Figure 18] FIG. 18 is a cross-sectional view (part 2) showing the method for manufacturing a quantum bit according to the fourth embodiment. [Figure 19]FIG. 19 is a cross-sectional view (part 3) showing a method for manufacturing a quantum bit according to the fourth embodiment. [Figure 20] FIG. 20 is a cross-sectional view (part 4) showing the method for manufacturing a quantum bit according to the fourth embodiment. [Figure 21] FIG. 21 is a cross-sectional view (part 5) illustrating the method for manufacturing a quantum bit according to the fourth embodiment. [Figure 22] FIG. 22 is a cross-sectional view (part 6) showing the method for manufacturing a quantum bit according to the fourth embodiment. [Figure 23] FIG. 23 is a diagram illustrating a quantum processing device according to the fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that in this specification and drawings, components having substantially the same functional configurations may be denoted by the same reference numerals to avoid redundant description. In this disclosure, the X1-X2 direction, the Y1-Y2 direction, and the Z1-Z2 direction are defined as mutually orthogonal directions. A plane including the X1-X2 direction and the Y1-Y2 direction will be referred to as the XY plane, a plane including the Y1-Y2 direction and the Z1-Z2 direction will be referred to as the YZ plane, and a plane including the Z1-Z2 direction and the X1-X2 direction will be referred to as the ZX plane. For convenience, the Z1-Z2 direction will be defined as the up-down direction, with the Z1 side referred to as the upper side and the Z2 side referred to as the lower side. Furthermore, a planar view refers to viewing an object from the Z1 side, and a planar shape refers to the shape of an object viewed from the Z1 side.

[0011] (First embodiment) First, a first embodiment will be described. The first embodiment relates to a structure. Fig. 1 is a cross-sectional view showing a structure according to the first embodiment.

[0012] The structure 100 according to the first embodiment includes a substrate 110, a first layer 120, and a second layer 130. The first layer 120 is formed on the substrate 110. The second layer 130 is formed on the first layer 120.

[0013] The substrate 110 is, for example, a single crystal substrate with a surface Miller index of (100). The material of the substrate 110 is, for example, MgO. In the first embodiment, the substrate 110 is an example of a base material.

[0014] The first layer 120 is a Te layer that does not contain W. The thickness of the first layer 120 is, for example, 1 nm to 20 nm.

[0015] The second layer 130 is, for example, a multi-layer WTe2. For example, the multi-layer WTe2 has 5 to 100 layers, preferably 10 to 50 layers, of WTe2, which is a two-dimensional material. Since the thickness of a single layer of WTe2 is 0.7 nm, when the second layer 130 includes 70 layers of WTe2, the thickness of the second layer 130 is approximately 50 nm.

[0016] Next, a method for manufacturing the structure 100 according to the first embodiment will be described. Here, the description will be given assuming that an MgO single crystal substrate with Miller indices (100) is used as the substrate 110, a Te layer is formed as the first layer 120, and a multilayer WTe2 is formed as the second layer 130.

[0017] First, the substrate 110 is prepared and annealed at approximately 1200°C for 3 to 4 hours in an oxygen atmosphere at atmospheric pressure. Next, the substrate 110 is immersed in methanol for 20 to 30 minutes and rinsed with ultrapure water. These treatments can improve the flatness of the surface of the substrate 110.

[0018] Next, a first layer 120 is formed on the substrate 110, and a second layer 130 is formed on the first layer 120. The first layer 120 and the second layer 130 can be epitaxially grown in situ in the same vacuum chamber by, for example, pulsed laser deposition (PLD). The basic vacuum level during the formation of the first layer 120 and the second layer 130 is, for example, 5×10 -6Pa or less. When forming the first layer 120 and the second layer 130 by the PLD method, a KrF excimer laser (λ=248 nm) light source can be used as the laser light source. The method for forming the first layer 120 and the second layer 130 is not limited to the PLD method. For example, the first layer 120 and the second layer 130 may be formed by a sputtering method, or the first layer 120 may be formed by a vapor deposition method and the second layer 130 may be formed by a co-evaporation method. In this way, the first layer 120 and the second layer 130 can be formed by a physical vapor deposition method in a consistent vacuum process.

[0019] When forming the first layer 120, for example, a Te pure metal target can be used as the target. When forming the first layer 120, for example, the temperature of the substrate 110 is maintained at about 200° C., and the laser energy density is set to 1.0 J / cm 2 2 The irradiation frequency is 1 Hz, the distance between the substrate 110 and the target is about 5 cm, and the film formation rate is 1.0 nm / min.

[0020] When forming the second layer 130 by PLD using a multilayer WTe2, a WTe2 sintered compact target can be used as the target. When forming the second layer 130, for example, the temperature of the substrate 110 is maintained at 325°C, and the laser energy density is set to 1.0 J / cm. 2 The irradiation frequency was 10 Hz, the distance between the substrate 110 and the target was about 5 cm, and the deposition rate was 1.0 nm / min. The second layer 130 (multilayer WTe2) was oriented in the c-axis direction on the first layer 120, and the crystal structure of the second layer 130 was T d The structure is shown.

[0021] In this manner, the structure 100 according to the first embodiment can be manufactured.

[0022] In the structure 100, the first layer 120 is formed between the substrate 110 and the second layer 130. Although the lattice mismatch between MgO, whose surface has a Miller index of (100), and WTe2 is 33%, the first layer 120 functions as a seed layer when forming the second layer 130. Therefore, good crystallinity can be obtained in the second layer 130.

[0023] After the multilayer WTe2 is formed, it is preferable to perform post-annealing at about 300° C. for 30 minutes to 1 hour, in order to improve the crystallinity of the multilayer WTe2.

[0024] Next, the results of Raman spectroscopy measurements performed by the present inventors on the first embodiment will be described. In this measurement, a sample was prepared following the procedure of the first embodiment, and Raman spectroscopy measurements were performed on this sample. The thickness of the first layer 120 was 10 nm, and the thickness of the second layer 130 was 50 nm. For reference, a sample (first reference example) in which the second layer 130 was formed on the substrate 110 without forming the first layer 120, and a sample (second reference example) with only the substrate 110 were also prepared, and Raman spectroscopy measurements were also performed on these samples. FIG. 2 shows the results of Raman spectroscopy measurements on the first embodiment.

[0025] As shown in FIG. 2, in the sample of the first embodiment, the lattice vibration mode (A1 2 , A1 5 , A1 8 , A1 9 , A2 4 ) can be confirmed, whereas the sample of the first reference example shows a sharp peak of A1 2 Mode and A1 5 Only a broad peak of the mode is observed. These results confirm that the provision of the first layer 120 improves the crystallinity of the second layer 130.

[0026] The material of the substrate 110 may be mica, sapphire, SiC, or the like.

[0027] (Second embodiment) Next, a second embodiment will be described. The second embodiment differs from the first embodiment mainly in the configuration of the substrate. Fig. 3 is a cross-sectional view showing a structure according to the second embodiment.

[0028] The structure 200 according to the second embodiment includes a substrate 210, a first layer 120, and a second layer 130. The first layer 120 is formed on the substrate 210. The second layer 130 is formed on the first layer 120.

[0029] The substrate 210 has a Si substrate 211 and a SiO2 film 212 formed on the Si substrate 211. The SiO2 film 212 is formed by, for example, thermal oxidation of the Si substrate 211. That is, the substrate 210 is a Si substrate with a thermal oxide film. The first layer 120 is provided on the SiO2 film 212. In the second embodiment, the substrate 210 is an example of a base material.

[0030] The other configurations are the same as those in the first embodiment.

[0031] Next, a method for manufacturing the structure 200 according to the second embodiment will be described.

[0032] First, the substrate 210 is prepared and annealed at about 800° C. for 15 minutes in an oxygen atmosphere at atmospheric pressure. By the annealing, organic deposits on the surface of the SiO 2 film 212 can be removed.

[0033] Next, the first layer 120 is formed on the substrate 210, and the second layer 130 is formed on the first layer 120. The first layer 120 and the second layer 130 can be formed by the same method as in the first embodiment.

[0034] In this manner, the structure 200 according to the second embodiment can be manufactured.

[0035] In the structure 200, the first layer 120 is formed between the substrate 210 and the second layer 130. The SiO2 film 212 present on the surface of the substrate 210 is amorphous, but functions as a seed layer when the first layer 120 forms the second layer 130. Therefore, good crystallinity can be obtained in the second layer 130.

[0036] Next, the results of Raman spectroscopy measurements performed by the present inventors on the second embodiment will be described. In this measurement, a sample was prepared following the procedure of the second embodiment, and Raman spectroscopy was performed on this sample. The thickness of the first layer 120 was 10 nm, and the thickness of the second layer 130 was 50 nm. For reference, a sample (third reference example) in which the second layer 130 was formed on the substrate 210 without forming the first layer 120, and a sample (fourth reference example) with only the substrate 210 were also prepared, and Raman spectroscopy was also performed on these samples. FIG. 4 shows the results of Raman spectroscopy measurements on the second embodiment.

[0037] As shown in FIG. 4, in the sample of the second embodiment, the lattice vibration mode (A1 2 , A1 5 , A1 8 , A1 9 , A2 4 ) can be confirmed, whereas the sample of the third reference example shows a sharp peak of A1 2 Mode and A1 5 Only a broad peak of the mode is observed. These results confirm that the provision of the first layer 120 improves the crystallinity of the second layer 130.

[0038] (Third embodiment) Next, a third embodiment will be described. The third embodiment differs from the first embodiment mainly in that an s-wave superconducting layer is included. Fig. 5 is a cross-sectional view showing a structure according to the third embodiment.

[0039] The structure 300 according to the third embodiment includes a substrate 110, an s-wave superconductor layer 340, a first layer 120, and a second layer 130. The s-wave superconductor layer 340 is formed on the substrate 110. The first layer 120 is formed on the s-wave superconductor layer 340. The second layer 130 is formed on the first layer 120.

[0040] The s-wave superconductor layer 340 is, for example, an Nb layer with a surface Miller index of (110). The thickness of the s-wave superconductor layer 340 is, for example, about 100 nm to 200 nm. In the third embodiment, the laminate 310 of the substrate 110 and the s-wave superconductor layer 340 is an example of a base material.

[0041] The other configurations are the same as those in the first embodiment.

[0042] Next, a method for manufacturing the structure 300 according to the third embodiment will be described.

[0043] First, the substrate 110 is prepared, and then annealed and rinsed in the same manner as in the first embodiment.

[0044] Next, an s-wave superconductor layer 340 is formed on the substrate 110, a first layer 120 is formed on the s-wave superconductor layer 340, and a second layer 130 is formed on the first layer 120. In the following, an Nb layer is formed as the s-wave superconductor layer 340. The s-wave superconductor layer 340, the first layer 120, and the second layer 130 can be epitaxially grown in situ in the same vacuum chamber by, for example, PLD. The basic vacuum level during the formation of the s-wave superconductor layer 340, the first layer 120, and the second layer 130 is, for example, 5×10 -6 Pa or less. When forming the s-wave superconductor layer 340, the first layer 120, and the second layer 130 by the PLD method, a KrF excimer laser (λ=248 nm) light source can be used as the laser light source. Note that the method for forming the s-wave superconductor layer 340, the first layer 120, and the second layer 130 is not limited to the PLD method. For example, the s-wave superconductor layer 340, the first layer 120, and the second layer 130 may be formed by a sputtering method, or the s-wave superconductor layer 340 and the first layer 120 may be formed by a vapor deposition method, and the second layer 130 may be formed by a co-evaporation method.

[0045] When forming an Nb layer as the s-wave superconductor layer 340 by the PLD method, for example, a Nb pure metal target can be used as the target. When forming the s-wave superconductor layer 340, for example, the temperature of the substrate 110 is kept at about 400°C, and the laser energy density is set to 2.0 J / cm.2 The irradiation frequency is 10 Hz, the distance between the substrate 110 and the target is about 5 cm, and the film formation rate is 1.0 nm / min. On the substrate 110 maintained at about 400°C, the Nb layer grows epitaxially while being oriented in the

[0110] direction.

[0046] Next, the first layer 120 is formed on the s-wave superconductor layer 340, and the second layer 130 is formed on the first layer 120. The first layer 120 and the second layer 130 can be formed by the same method as in the first embodiment. The s-wave superconductor layer 340, the first layer 120, and the second layer 130 can be formed by physical vapor deposition in a vacuum integrated process.

[0047] In this manner, the structure 300 according to the third embodiment can be manufactured.

[0048] In the structure 300, the first layer 120 is formed between the s-wave superconductor layer 340 and the second layer 130. Although the lattice mismatch between Nb, whose surface has Miller indices (110), and WTe2 is 25%, the first layer 120 functions as a seed layer when forming the second layer 130. Therefore, good crystallinity can be obtained in the second layer 130.

[0049] Next, the results of Raman spectroscopy measurements performed by the present inventors on the third embodiment will be described. In this measurement, a sample was prepared following the procedure of the third embodiment, and Raman spectroscopy was performed on this sample. The thickness of the s-wave superconductor layer 340 was 150 nm, the thickness of the first layer 120 was 5 nm, and the thickness of the second layer 130 was 20 nm. For reference, a sample (fifth reference example) in which the first layer 120 was not formed and the second layer 130 was formed on the s-wave superconductor layer 340, and a sample (sixth reference example) in which only the s-wave superconductor layer 340 was formed on the substrate 110 were also prepared, and Raman spectroscopy was also performed on these samples. FIG. 6 shows the results of Raman spectroscopy measurements on the third embodiment.

[0050] As shown in FIG. 6, in the sample of the third embodiment, the lattice vibration mode (A1 2 , A1 5 , A18 , A1 9 , A2 4 ) can be confirmed, whereas the sample of Reference Example 5 shows a sharp peak of A1 2 Mode and A1 5 Only a broad peak of the mode is observed. These results confirm that the provision of the first layer 120 improves the crystallinity of the second layer 130.

[0051] In the present disclosure, the material of the layered transition metal ditelluride layer included in the second layer is not limited to WTe2. The transition metal ditelluride layer may contain Mo, Nb, W, Ta, Ti, Zr, Fe, Pd, Ir, or Pt as a transition metal, or any combination thereof. The layered transition metal ditelluride layer included in the second layer may be a single layer.

[0052] In the present disclosure, the thickness of the first layer is preferably 1 nm to 20 nm. If the thickness of the first layer is less than 1 nm, it may be difficult to obtain excellent crystallinity in the second layer. If the thickness of the first layer is more than 20 nm, the electrical properties of the first layer may change. Furthermore, when the first layer is provided between the s-wave superconductor layer and the second layer as in the third embodiment, if the first layer is excessively thick, the proximity effect of superconductivity may decrease. The thickness of the first layer is more preferably 2 nm to 15 nm, and even more preferably 3 nm to 10 nm.

[0053] (Fourth embodiment) Next, a fourth embodiment will be described. The fourth embodiment relates to a quantum bit. The quantum bit according to the fourth embodiment is used in a quantum operation device such as a quantum computer. FIG. 7 is a top view showing the quantum bit according to the fourth embodiment. FIGS. 8 and 9 are cross-sectional views showing the quantum bit according to the fourth embodiment. FIG. 8 corresponds to a cross-sectional view taken along line VIII-VIII in FIG. 7. FIG. 9 corresponds to a cross-sectional view taken along line IX-IX in FIG. 7.

[0054] The quantum bit 1 according to the fourth embodiment includes a substrate 90, an s-wave superconductor layer 10, a Te layer 70, a higher-order topological insulator layer 20, a first ferromagnetic insulator layer 31, a second ferromagnetic insulator layer 32, and a third ferromagnetic insulator layer 33. The quantum bit 1 further includes a first gate electrode 41, a second gate electrode 42, a third gate electrode 43, a first superconducting quantum interference device (SQUID) 61, a second SQUID 62, and a third SQUID 63.

[0055] The substrate 90 is, for example, a single crystal substrate with a surface Miller index of (100). Materials for the substrate 90 include MgO, mica, sapphire, and SiC. The substrate 90 may also be a Si substrate with a thermal oxide film.

[0056] The s-wave superconductor layer 10 is provided on a portion of the surface of the substrate 90. The s-wave superconductor layer 10 is, for example, an Nb layer with a surface Miller index of (110). The thickness of the s-wave superconductor layer 10 is, for example, about 100 nm to 200 nm. The planar shape of the s-wave superconductor layer 10 is a rectangle with two sides parallel to the X1-X2 direction and two sides parallel to the Y1-Y2 direction.

[0057] The Te layer 70 is provided on the s-wave superconductor layer 10. The thickness of the Te layer 70 is preferably 1 nm to 20 nm, more preferably 2 nm to 15 nm, and even more preferably 3 nm to 10 nm. The thickness of the Te layer 70 is, for example, 5 nm.

[0058] The high-order topological insulator layer 20 is provided on the Te layer 70. The high-order topological insulator layer 20 is, for example, a multilayer WTe2. For example, the multilayer WTe2 has 5 to 100 layers, preferably 10 to 50 layers, of WTe2, which is a two-dimensional material. The thickness of the high-order topological insulator layer 20 is, for example, 20 nm.

[0059] 10 is a perspective view showing a high-order topological insulator layer 20. The shape of the high-order topological insulator layer 20 is an approximately rectangular parallelepiped. The a-axis direction of the high-order topological insulator layer 20 is parallel to the Y1-Y2 direction, the b-axis direction is parallel to the X1-X2 direction, and the c-axis direction is parallel to the Z1-Z2 direction. The Miller indices of the top surface of the high-order topological insulator layer 20 are (001), the Miller indices of the side surface on the Y2 side are (100), and the Miller indices of the side surface on the X2 side are (010).

[0060] A T-shaped groove 50 is formed in a planar view on the surface of the high-order topological insulator layer 20. The groove 50 includes a first groove 51, a second groove 52, and a third groove 53. For example, the widths of the first groove 51, the second groove 52, and the third groove 53 are 20 nm and 10 nm, respectively. The first groove 51 and the third groove 53 extend parallel to the X1-X2 direction, and the second groove 52 extends parallel to the Y1-Y2 direction. The first groove 51 is provided near the center of the high-order topological insulator layer 20 in the Y1-Y2 direction, and extends from the X2-side end of the high-order topological insulator layer 20 to the center in the X1-X2 direction. The third groove 53 is provided near the center of the high-order topological insulator layer 20 in the Y1-Y2 direction, and extends from the X1-side end of the high-order topological insulator layer 20 to the center in the X1-X2 direction. Therefore, the first groove 51 and the third groove 53 are formed in a straight line. The second groove 52 is provided near the center of the high-order topological insulator layer 20 in the X1-X2 direction, and extends from the Y1-side end of the high-order topological insulator layer 20 to the center in the Y1-Y2 direction. Therefore, the second groove 52 is perpendicular to the first groove 51 and the third groove 53.

[0061] The higher-order topological insulator layer 20 has a first region 21 on the Y2 side of the first groove 51 and the third groove 53. The higher-order topological insulator layer 20 has a second region 22 on the Y1 side of the first groove 51 and the X2 side of the second groove 52. The higher-order topological insulator layer 20 has a third region 23 on the Y1 side of the third groove 53 and the X1 side of the second groove 52.

[0062] The first region 21, the second region 22, and the third region 23 each have a hinge helical channel on one of two intersecting lines between a plane perpendicular to the a-axis direction and a plane perpendicular to the c-axis direction. The hinge helical channel is parallel to the b-axis direction. Specifically, the first region 21 has a first hinge helical channel 11 on the intersecting line (ridge line) between the top surface and the side surface on the Y1 side. The second region 22 has a second hinge helical channel 12 on the intersecting line between the side surface on the Y2 side and the bottom surface of the first groove 51. The third region 23 has a third hinge helical channel 13 on the intersecting line between the side surface on the Y2 side and the bottom surface of the third groove 53. The first hinge helical channel 11 may be located at the intersection of the Y1 side surface of the first region 21 and the bottom surface of the groove 50, the second hinge helical channel 12 may be located at the intersection of the top surface of the second region 22 and the Y2 side surface, and the third hinge helical channel 13 may be located at the intersection of the top surface of the third region 23 and the Y2 side surface.

[0063] The first ferromagnetic insulator layer 31 is provided on a portion of the first region 21, the second region 22, and the groove 50, and covers a portion of the first hinge helical channel 11 and the second hinge helical channel 12. The second ferromagnetic insulator layer 32 is provided on a portion of the second region 22, the third region 23, and the groove 50, and covers a portion of the second hinge helical channel 12 and the third hinge helical channel 13. The third ferromagnetic insulator layer 33 is provided on a portion of the third region 23, the first region 21, and the groove 50, and covers a portion of the third hinge helical channel 13 and the first hinge helical channel 11. Examples of materials for the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, and the third ferromagnetic insulator layer 33 include Cr2Ga2Te6. However, the materials for the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, and the third ferromagnetic insulator layer 33 may also be other diluted magnetic semiconductors. The first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, and the third ferromagnetic insulator layer 33 each have a thickness of, for example, about 30 nm.

[0064] The second ferromagnetic insulator layer 32 is spaced from the first ferromagnetic insulator layer 31 on the X1 side in the X1-X2 direction on the second hinge helical channel 12. The third ferromagnetic insulator layer 33 is spaced from the second ferromagnetic insulator layer 32 on the X1 side in the X1-X2 direction on the third hinge helical channel 13. The third ferromagnetic insulator layer 33 is spaced from the first ferromagnetic insulator layer 31 on the X1 side in the X1-X2 direction on the first hinge helical channel 11.

[0065] The first gate electrode 41 is provided on the first ferromagnetic insulator layer 31. The second gate electrode 42 is provided on the second ferromagnetic insulator layer 32. The third gate electrode 43 is provided on the third ferromagnetic insulator layer 33. Examples of materials for the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 include Au. The thicknesses of the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 are, for example, about 100 nm.

[0066] The first SQUID 61 has a lower superconductor layer 61A, a lower superconductor layer 61B, a tunnel barrier layer 61C, and an upper superconductor layer 61D.

[0067] The lower superconductor layer 61A and the lower superconductor layer 61B protrude toward the X2 side from the X2-side side surface of the s-wave superconductor layer 10. The lower superconductor layer 61A is located on the Y2 side of the lower superconductor layer 61B. In a plan view, the lower superconductor layer 61A protrudes toward the X2 side from the first region 21, and the lower superconductor layer 61B protrudes toward the X2 side from the second region 22. The lower superconductor layer 61A and the lower superconductor layer 61B are formed integrally with the s-wave superconductor layer 10 from the same material as the s-wave superconductor layer 10. The lower superconductor layer 61A and the lower superconductor layer 61B are connected to the s-wave superconductor layer 10. The lower superconductor layer 61A and the lower superconductor layer 61B are, for example, Nb layers having a thickness of about 100 nm to 200 nm.

[0068] The tunnel barrier layer 61C and the upper superconductor layer 61D have a U-shaped planar shape. The material of the tunnel barrier layer 61C is NbO xThe upper superconductor layer 61D may be made of Nb. The tunnel barrier layer 61C has a thickness of, for example, about 1 nm to 5 nm, and the upper superconductor layer 61D has a thickness of, for example, about 100 nm to 200 nm. One end of the tunnel barrier layer 61C contacts the lower superconductor layer 61A, and the other end contacts the lower superconductor layer 61B. The upper superconductor layer 61D is provided on the tunnel barrier layer 61C.

[0069] A tunnel barrier layer 61C is sandwiched between lower superconductor layer 61A and upper superconductor layer 61D, and between lower superconductor layer 61B and upper superconductor layer 61D. First SQUID 61 is configured with such Josephson junctions. First SQUID 61 detects changes in magnetic flux between first hinge helical channel 11 and second hinge helical channel 12.

[0070] The second SQUID 62 has a lower superconductor layer 62A, a lower superconductor layer 62B, a tunnel barrier layer 62C, and an upper superconductor layer 62D.

[0071] The lower superconductor layer 62A and the lower superconductor layer 62B protrude toward the Y1 side from the Y1-side side surface of the s-wave superconductor layer 10. The lower superconductor layer 62A is located on the X2 side of the lower superconductor layer 62B. In a plan view, the lower superconductor layer 62A protrudes toward the Y1 side from the second region 22, and the lower superconductor layer 62B protrudes toward the Y1 side from the third region 23. The lower superconductor layer 62A and the lower superconductor layer 62B are formed integrally with the s-wave superconductor layer 10 from the same material as the s-wave superconductor layer 10. The lower superconductor layer 62A and the lower superconductor layer 62B are connected to the s-wave superconductor layer 10. The lower superconductor layer 62A and the lower superconductor layer 62B are, for example, Nb layers with a thickness of approximately 100 nm to 200 nm.

[0072] The tunnel barrier layer 62C and the upper superconductor layer 62D have a U-shaped planar shape. The material of the tunnel barrier layer 62C is NbO xThe upper superconductor layer 62D may be made of Nb. The tunnel barrier layer 62C has a thickness of, for example, about 1 nm to 5 nm, and the upper superconductor layer 62D has a thickness of, for example, about 100 nm to 200 nm. One end of the tunnel barrier layer 62C contacts the lower superconductor layer 62A, and the other end contacts the lower superconductor layer 62B. The upper superconductor layer 62D is provided on the tunnel barrier layer 62C.

[0073] A tunnel barrier layer 62C is sandwiched between lower superconductor layer 62A and upper superconductor layer 62D, and between lower superconductor layer 62B and upper superconductor layer 62D. Second SQUID 62 is configured with such Josephson junctions. Second SQUID 62 detects changes in magnetic flux between second hinge helical channel 12 and third hinge helical channel 13.

[0074] The third SQUID 63 has a lower superconductor layer 63A, a lower superconductor layer 63B, a tunnel barrier layer 63C, and an upper superconductor layer 63D.

[0075] The lower superconductor layer 63A and the lower superconductor layer 63B protrude toward the X1 side from the X1-side side surface of the s-wave superconductor layer 10. The lower superconductor layer 63A is located on the Y1 side of the lower superconductor layer 63B. In a plan view, the lower superconductor layer 63A protrudes toward the X1 side from the third region 23, and the lower superconductor layer 63B protrudes toward the X1 side from the first region 21. The lower superconductor layer 63A and the lower superconductor layer 63B are formed integrally with the s-wave superconductor layer 10 from the same material as the s-wave superconductor layer 10. The lower superconductor layer 63A and the lower superconductor layer 63B are connected to the s-wave superconductor layer 10. The lower superconductor layer 63A and the lower superconductor layer 63B are, for example, Nb layers with a thickness of approximately 100 nm to 200 nm.

[0076] The tunnel barrier layer 63C and the upper superconductor layer 63D have a U-shaped planar shape. The material of the tunnel barrier layer 63C is NbO xThe upper superconductor layer 63D may be made of Nb. The tunnel barrier layer 63C has a thickness of, for example, about 1 nm to 5 nm, and the upper superconductor layer 63D has a thickness of, for example, about 100 nm to 200 nm. One end of the tunnel barrier layer 63C contacts the lower superconductor layer 63A, and the other end contacts the lower superconductor layer 63B. The upper superconductor layer 63D is provided on the tunnel barrier layer 63C.

[0077] Tunnel barrier layer 63C is sandwiched between lower superconductor layer 63A and upper superconductor layer 63D, and between lower superconductor layer 63B and upper superconductor layer 63D. Third SQUID 63 is configured with such Josephson junctions. Third SQUID 63 detects changes in magnetic flux between third hinge helical channel 13 and first hinge helical channel 11.

[0078] In the quantum bit 1 configured in this manner, four Majorana particles γ1, γ2, γ3, and γ4 are generated. For example, Majorana particle γ1 is stably generated near the first gate electrode 41 of the first hinge helical channel 11, and Majorana particle γ4 is stably generated near the third gate electrode 43 of the first hinge helical channel 11. Furthermore, for example, Majorana particle γ2 is stably generated between the first gate electrode 41 and the second gate electrode 42 of the second hinge helical channel 12, and Majorana particle γ3 is stably generated between the second gate electrode 42 and the third gate electrode 43 of the third hinge helical channel 13. The Majorana particles γ1 to γ4 are exchanged by a change in electrostatic potential caused by application of gate voltages to the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43.

[0079] For example, in the exchange between Majorana fermions γ1 and γ2, an electric field is applied from the first gate electrode 41, and a minute change in magnetic flux during the exchange between Majorana fermions γ1 and γ2 is detected by the first SQUID 61 as a minute change in voltage signal. In the exchange between Majorana fermions γ2 and γ3, an electric field is applied from the second gate electrode 42, and a minute change in magnetic flux during the exchange between Majorana fermions γ2 and γ3 is detected by the second SQUID 62 as a minute change in voltage signal. In addition, in the exchange between Majorana fermions γ3 and γ4, an electric field is applied from the third gate electrode 43, and a minute change in magnetic flux during the exchange between Majorana fermions γ3 and γ4 is detected by the third SQUID 63 as a minute change in voltage signal.

[0080] A single-layer film of WTe2, a layered material of transition metal dichalcogenide, is easily oxidized and its properties change when exposed to the atmosphere. While it is possible to suppress oxidation by sandwiching the WTe2 single-layer film between chemically stable materials such as hexagonal boron nitride (h-BN) or graphene, this complicates the quantum bit manufacturing process. Furthermore, adjusting the size of the WTe2 single-layer film is also difficult. In contrast, this embodiment uses a higher-order topological insulator layer 20 such as a multilayer WTe2, so no structure for suppressing oxidation is required. Furthermore, adjusting the size of the higher-order topological insulator layer 20 is easier than adjusting the size of a WTe2 single-layer film.

[0081] It is also possible to provide multiple quantum bits 1 on the substrate 90 to achieve a multi-qubit configuration, or to mount a semiconductor integrated circuit on the substrate 90. Therefore, according to this embodiment, it is possible to accelerate research and development toward realizing a practical error-tolerant quantum computer.

[0082] Next, a method for manufacturing the quantum bit 1 according to the fourth embodiment will be described. Figures 11 to 16 are top views showing the method for manufacturing the quantum bit 1 according to the fourth embodiment. Figures 17 to 22 are cross-sectional views showing the method for manufacturing the quantum bit 1 according to the fourth embodiment.

[0083] First, as shown in Figures 11 and 17, a substrate 90 is prepared and annealed at approximately 1200°C for 3 to 4 hours in an oxygen atmosphere at atmospheric pressure. Next, the substrate 90 is immersed in methanol for 20 to 30 minutes and rinsed with ultrapure water. These treatments can improve the flatness of the surface of the substrate 90. Figure 17 corresponds to a cross-sectional view taken along line XVII-XVII in Figure 11.

[0084] Thereafter, an s-wave superconductor layer 19 is formed on the substrate 90, a Te layer 79 is formed on the s-wave superconductor layer 19, and a high-order topological insulator layer 29 is formed on the Te layer 79. In the following, an Nb layer is formed as the s-wave superconductor layer 19, and a multilayer WTe2 is formed as the high-order topological insulator layer 29. The s-wave superconductor layer 19, the Te layer 79, and the high-order topological insulator layer 29 can be epitaxially grown in situ in the same vacuum chamber by, for example, the PLD method. The basic vacuum level during the formation of the s-wave superconductor layer 19, the Te layer 79, and the high-order topological insulator layer 29 is, for example, 5×10 -6 Pa or less. When forming the s-wave superconductor layer 19, the Te layer 79, and the high-order topological insulator layer 29 by the PLD method, a KrF excimer laser (λ = 248 nm) light source can be used as the laser light source. Note that the method for forming the s-wave superconductor layer 19, the Te layer 79, and the high-order topological insulator layer 29 is not limited to the PLD method. For example, the s-wave superconductor layer 19, the Te layer 79, and the high-order topological insulator layer 29 may be formed by a sputtering method, or the s-wave superconductor layer 19 and the Te layer 79 may be formed by a vapor deposition method, and the high-order topological insulator layer 29 may be formed by a co-evaporation method. In this way, the s-wave superconductor layer 19, the Te layer 79, and the high-order topological insulator layer 29 can be formed by a physical vapor deposition method in a vacuum-integrated process.

[0085] When forming an Nb layer as the s-wave superconductor layer 19 by the PLD method, for example, a Nb pure metal target can be used as the target. When forming the s-wave superconductor layer 19, for example, the temperature of the substrate 90 is kept at about 400°C, and the laser energy density is set to 2.0 J / cm. 2 ~5.0J / cm2 The irradiation frequency is 10 Hz, the distance between the substrate 90 and the target is about 5 cm, and the film formation rate is 0.5 nm / min to 1.0 nm / min. On the substrate 90 maintained at about 400°C, the Nb layer grows epitaxially while being oriented in the

[0110] direction.

[0086] When forming the Te layer 79, for example, a Te pure metal target can be used as the target. When forming the Te layer 79, for example, the temperature of the substrate 90 is maintained at about 200° C., and the laser energy density is set to 1.0 J / cm 2 2 ~2.0J / cm 2 The irradiation frequency is set to 1 Hz, the distance between the substrate 110 and the target is set to about 5 cm, and the film formation rate is set to 0.5 nm / min to 1.5 nm / min.

[0087] When forming a multilayer WTe2 as the higher-order topological insulator layer 29 by the PLD method, for example, a WTe2 sintered target can be used as the target. When forming the higher-order topological insulator layer 29, for example, the temperature of the substrate 90 is kept at about 325°C, and the laser energy density is 1.0 J / cm 2 ~2.0J / cm 2 The irradiation frequency is 10 Hz, the distance between the substrate 90 and the target is approximately 5 cm, and the deposition rate is 0.5 nm / min to 1.5 nm / min. The high-order topological insulator layer 29 (multilayer WTe2) is oriented in the c-axis direction on the s-wave superconductor layer 19 (Nb layer), and the crystal structure of the high-order topological insulator layer 29 is T d The structure is shown.

[0088] After the multilayer WTe2 is formed, it is preferable to perform post-annealing at about 300° C. for 30 minutes to 1 hour, in order to improve the crystallinity of the multilayer WTe2.

[0089] After the formation of the higher-order topological insulator layer 29, the s-wave superconductor layer 19, the Te layer 79, and the higher-order topological insulator layer 29 are processed to form an s-wave superconductor layer 10, a lower superconductor layer 61A, a lower superconductor layer 61B, a lower superconductor layer 62A, a lower superconductor layer 62B, a lower superconductor layer 63A, and a lower superconductor layer 63B from the s-wave superconductor layer 19, as shown in Figures 12 and 18. Figure 18 corresponds to a cross-sectional view taken along line XVIII-XVIII in Figure 12.

[0090] When processing the s-wave superconductor layer 19, the Te layer 79, and the high-order topological insulator layer 29, a first electron beam resist is first spin-coated onto the high-order topological insulator layer 29. Next, a first mask pattern is formed from the first electron beam resist by electron beam lithography. The first mask pattern covers the portions of the s-wave superconductor layer 19 where the s-wave superconductor layer 10, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, and the lower superconductor layer 63B are to be formed, from above the high-order topological insulator layer 29, and leaves the other portions exposed. As the first electron beam resist, for example, a resist obtained by diluting ZEP 520A (manufactured by Zeon Corporation) with ZEP-A (manufactured by Zeon Corporation) at a ratio of 1:1 can be used. After the first mask pattern is formed, Ar ion milling is performed to process the s-wave superconductor layer 19, the Te layer 79, and the high-order topological insulator layer 29. In the Ar ion milling, for example, the beam acceleration voltage is set to 280 V and the beam current is set to 150 mA.

[0091] After processing the s-wave superconductor layer 19, the Te layer 79, and the high-order topological insulator layer 29, the first mask pattern is removed, and the high-order topological insulator layer 29 and the Te layer 79 are processed as shown in Figures 13 and 19. A high-order topological insulator layer 29A having a rectangular planar shape and a flat upper surface is formed from the high-order topological insulator layer 29, and a Te layer 70 having a rectangular planar shape is formed from the Te layer 79. Figure 19 corresponds to a cross-sectional view taken along line XIX-XIX in Figure 13.

[0092] When processing the higher-order topological insulator layer 29 and the Te layer 79, a second electron beam resist is first spin-coated onto the higher-order topological insulator layer 29 and the substrate 90. Next, a second mask pattern is formed from the second electron beam resist by electron beam lithography. The second mask pattern covers the portion of the higher-order topological insulator layer 29 above the s-wave superconductor layer 10 and exposes the portions above the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, and the lower superconductor layer 63B. For example, a resist obtained by diluting ZEP 520A (manufactured by Zeon Corporation) with ZEP-A (manufactured by Zeon Corporation) at a ratio of 1:1 can be used as the second electron beam resist. After forming the second mask pattern, the higher-order topological insulator layer 29 and the Te layer 79 are processed by Ar ion milling. As a result, the higher-order topological insulator layer 29A and the Te layer 70 are formed, and the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, and the lower superconductor layer 63B are exposed from the higher-order topological insulator layer 29A and the Te layer 70. In the Ar ion milling, for example, the beam acceleration voltage is set to 280 V and the beam current to 150 mA.

[0093] After the formation of the higher-order topological insulator layer 29A and the Te layer 70, the second mask pattern is removed, and the higher-order topological insulator layer 29A is processed to form a higher-order topological insulator layer 20 including a first region 21, a second region 22, and a third region 23 from the higher-order topological insulator layer 29A, as shown in Figures 14 and 20. Figure 20 corresponds to a cross-sectional view taken along line XX-XX in Figure 14.

[0094] When processing the higher-order topological insulator layer 29A, a third electron beam resist is first spin-coated onto the higher-order topological insulator layer 29A, substrate 90, lower superconductor layer 61A, lower superconductor layer 61B, lower superconductor layer 62A, lower superconductor layer 62B, lower superconductor layer 63A, and lower superconductor layer 63B. Next, a third mask pattern is formed from the third electron beam resist by electron beam lithography. The third mask pattern exposes the portions of the higher-order topological insulator layer 29A where the grooves 50 are to be formed and covers the other portions. For example, a resist obtained by diluting ZEP 520A (manufactured by Zeon Corporation) with ZEP-A (manufactured by Zeon Corporation) at a ratio of 1:1 can be used as the third electron beam resist. After forming the third mask pattern, the higher-order topological insulator layer 29A is processed by Ar ion milling. As a result, a groove 50 including a first groove 51, a second groove 52, and a third groove 53 is formed, and a highly-ordered topological insulator layer 20 including a first region 21, a second region 22, and a third region 23 is obtained. The first region 21 includes a first hinge helical channel 11, the second region 22 includes a second hinge helical channel 12, and the third region 23 includes a third hinge helical channel 13 (see FIG. 10). In Ar ion milling, for example, the beam acceleration voltage is set to 280 V and the beam current to 150 mA.

[0095] After the formation of the higher-order topological insulator layer 20, the third mask pattern is removed, and the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, the third ferromagnetic insulator layer 33, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 are formed as shown in Figures 15 and 21. Figure 21 corresponds to a cross-sectional view taken along line XXI-XXI in Figure 15.

[0096] When forming the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, the third ferromagnetic insulator layer 33, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43, a fourth electron beam resist is first spin-coated on the higher-order topological insulator layer 20, the substrate 90, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, and the lower superconductor layer 63B. Next, a fourth mask pattern is formed from the fourth electron beam resist by electron beam lithography. The fourth mask pattern exposes portions where the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, the third ferromagnetic insulator layer 33, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 will be formed, and covers other portions. As the fourth electron beam resist, for example, a resist obtained by diluting ZEP 520A (manufactured by Zeon Corporation) with ZEP-A (manufactured by Zeon Corporation) at a ratio of 1:1 can be used. After forming the fourth mask pattern, a Cr2Ga2Te6 layer and an Au layer are formed by PLD.

[0097] When forming the Cr2Ga2Te6 layer by the PLD method, for example, the temperature of the substrate 90 is kept at 200°C, and the laser energy density is set to 1.0 J / cm 2 ~2.0J / cm 2 The irradiation frequency is set to 1 Hz, the distance between the substrate 90 and the target is set to about 5 cm, and the film formation rate is set to 1.0 nm / min to 2.0 nm / min.

[0098] When the Au layer is formed by the PLD method, for example, the temperature of the substrate 90 is kept at room temperature, and the laser energy density is set to 1.0 J / cm 2 . 2 ~2.0J / cm 2 The irradiation frequency is set to 5 Hz, the distance between the substrate 90 and the target is set to about 5 cm, and the film formation rate is set to 5.0 nm / min to 10.0 nm / min.

[0099] After the Cr2Ga2Te6 layer and the Au layer are formed, the fourth mask pattern is removed together with the Cr2Ga2Te6 layer and the Au layer deposited thereon. This is called lift-off. As a result, the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, the third ferromagnetic insulator layer 33, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 are obtained. Furthermore, four Majorana particles γ1, γ2, γ3, and γ4 are generated.

[0100] Next, tunnel barrier layers 61C to 63C and upper superconductor layers 61D to 63D are formed as shown in Fig. 16 and Fig. 22. Fig. 22 corresponds to a cross-sectional view taken along line XXII-XXII in Fig. 16.

[0101] When forming the tunnel barrier layers 61C to 63C and the upper superconductor layers 61D to 63D, a fifth electron beam resist is first spin-coated onto the high-order topological insulator layer 20, the substrate 90, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, the lower superconductor layer 63B, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43. Next, a fifth mask pattern is formed from the fifth electron beam resist by electron beam lithography. The fifth mask pattern exposes portions where the tunnel barrier layers 61C to 63C and the upper superconductor layers 61D to 63D will be formed and covers other portions. As the fifth electron beam resist, for example, a resist obtained by diluting ZEP 520A (manufactured by Zeon Corporation) with ZEP-A (manufactured by Zeon Corporation) at a ratio of 1:1 can be used. After forming the fifth mask pattern, NbO x A layer and an Nb layer are formed.

[0102] NbO x When forming the layer by the PLD method, for example, a Nb metal target is used, the temperature of the substrate 90 is maintained at room temperature, and the oxygen partial pressure in the vacuum chamber is adjusted to about 50 Pa to 55 Pa. The Nb layer can be formed under the same conditions as those for the s-wave superconductor layer 19.

[0103] NbO xAfter the formation of the Nb layer and the Nb layer, a fifth mask pattern is formed on the NbO layer. x The Nb layer and the Nb layer are removed together. That is, lift-off is performed. As a result, tunnel barrier layers 61C to 63C and upper superconductor layers 61D to 63D are obtained, and the first SQUID 61, the second SQUID 62, and the third SQUID 63 are formed.

[0104] In this way, the quantum bit 1 according to the fourth embodiment can be manufactured.

[0105] The material of the high-order topological insulator layer 20 is not limited to multilayer WTe2. The high-order topological insulator layer 20 may contain Mo, Nb, W, Ta, Ti, Zr, Fe, Pd, Ir, or Pt, or any combination thereof, as a transition metal. Furthermore, the material of the s-wave superconductor layer 10 is not limited to Nb and may be, for example, Al or Pd.

[0106] The thickness of the Te layer 70 is preferably 1 nm to 20 nm, more preferably 2 nm to 15 nm, and even more preferably 3 nm to 10 nm. If the Te layer 70 is too thick, the proximity effect of superconductivity due to the s-wave superconductor layer may be reduced.

[0107] (Fifth embodiment) Next, a fifth embodiment will be described. The fifth embodiment relates to a quantum processing device including the quantum bit 1 according to the fourth embodiment. Fig. 23 is a diagram showing the quantum processing device according to the fifth embodiment.

[0108] As shown in FIG. 23 , the quantum processing device 2 according to the fifth embodiment includes a quantum bit chip 81, a signal generator 82, a signal demodulator 83, and a cryogenic dilution refrigerator 84. The quantum bit chip 81 includes a plurality of quantum bits 1 according to the fourth embodiment. The quantum bit chip 81 is housed in the cryogenic dilution refrigerator 84 and cooled to a temperature of 10 mK or less. The signal generator 82 generates a microwave pulse signal, and the microwave pulse signal is input to the quantum bit chip 81. The quantum bit chip 81 outputs a signal corresponding to the microwave pulse signal, and the signal demodulator 83 demodulates the signal output from the quantum bit chip 81. The signal generator 82 and the signal demodulator 83 are used at a temperature around room temperature, for example.

[0109] Since the quantum processing device 2 according to the fifth embodiment includes the quantum bit 1 according to the fourth embodiment, it is possible to stably generate Majorana particles and perform stable operations.

[0110] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. [Explanation of symbols]

[0111] 1: Quantum bit 2: Quantum computing device 10: s-wave superconductor layer 11: First hinge helical channel 12: Second hinge helical channel 13: Third hinge helical channel 20: High-order topological insulator layer 21:First area 22:Second area 23: Third area 31: First ferromagnetic insulator layer 32: Second ferromagnetic insulator layer 33: Third ferromagnetic insulator layer 41: First gate electrode 42: Second gate electrode 43: Third gate electrode 50: Groove 51: 1st groove 52:Second groove 53: Third groove 61: First SQUID 62:2nd SQUID 63: The Third SQUID 100, 200, 300: Structure 110, 210: Substrate 120: 1st layer 130: 2nd layer 211: Si substrate 212:SiO2 film 310: Laminate 340: s-wave superconductor layer

Claims

1. an s-wave superconductor layer; a Te layer provided on the s-wave superconductor layer; a high-order topological insulator layer provided on the Te layer; a first ferromagnetic insulator layer provided on the higher-order topological insulator layer; a first gate electrode provided on the first ferromagnetic insulator layer; and The higher-order topological insulator layer is a first region having a first hinge helical channel; a second region having a second hinge helical channel spaced from the first hinge helical channel; and The quantum bit, wherein the first ferromagnetic insulator layer covers the first hinge helical channel and the second hinge helical channel.

2. 10. The quantum bit of claim 1, further comprising a first superconducting quantum interferometer that detects changes in magnetic flux between the first hinged helical channel and the second hinged helical channel.

3. the higher-order topological insulator layer has a third region with a third hinged helical channel spaced from the first hinged helical channel and the second hinged helical channel; a second ferromagnetic insulator layer covering the second hinge helical channel and the third hinge helical channel; a second gate electrode provided on the second ferromagnetic insulator layer; a third ferromagnetic insulator layer covering the third hinge helical channel and the first hinge helical channel; a third gate electrode provided on the third ferromagnetic insulator layer; 3. The quantum bit of claim 1, wherein:

4. a second superconducting quantum interference detector; a third superconducting quantum interference detector; and a second superconducting quantum interferometer for detecting a change in magnetic flux between the second hinged helical channel and the third hinged helical channel; 4. The quantum bit of claim 3, wherein a third superconducting quantum interferometer detects changes in magnetic flux between the third hinged helical channel and the first hinged helical channel.

5. The higher-order topological insulator layer is a first groove defining the first region and the second region; a second groove defining the second region and the third region; a third groove defining the third region and the first region; 5. The quantum bit according to claim 3, wherein:

6. the first groove and the third groove extend in a common first direction, the second groove extends in a second direction perpendicular to the first direction, 6. The quantum bit according to claim 5, wherein the first groove, the second groove, and the third groove are connected to each other.

7. 7. The quantum bit of claim 1, wherein the high-order topological insulator layer comprises Mo, Nb, W, Ta, Ti, Zr, Fe, Pd, Ir, or Pt.

8. A quantum processing device comprising the quantum bit according to any one of claims 1 to 7.

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