Semiconductor device and method for manufacturing semiconductor device

Abstract

To provide a semiconductor device that has a high degree of freedom in the layout of a circuit element, can prevent deterioration of performance caused by self heating, and can prevent a reduction in withstand voltage.SOLUTION: A semiconductor device 1 includes: an insulating layer 20 having a first surface 20a and a second surface 20b; a first semiconductor layer 30 and a first heat conduction part 40 provided separated from each other on a side of the first surface 20a; and a first element separation layer 50 defining the first semiconductor layer 30 and covering the first heat conduction part 40. The first heat conduction part 40 has a third surface 40a directed to a first direction D1 parallel to the first surface 20a and facing the first semiconductor layer 30, and a fourth surface 40b directed to a second direction D2 orthogonal to the first direction D1 and separated from the first surface 20a. In the semiconductor device 1, the thickness T1 of a first portion 51 of the first element separation layer 50 between the first semiconductor layer 30 and the third surface 40a, is smaller than the thickness T2 between the first surface 20a and the second surface 20b of the insulating layer 20.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Semiconductor devices using substrates with an SOI (Silicon On Insulator) structure are known. For example, a semiconductor device is known in which an island-shaped silicon region in which an LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor is formed is surrounded by an insulating film including a buried silicon oxide film and a silicon oxide film formed in an isolation trench, thereby improving the breakdown voltage and isolation performance.

[0003] Furthermore, with regard to such semiconductor devices, there are known techniques such as a technique for thinning a portion of the buried silicon oxide film, a technique for placing polycrystalline silicon in the thinned portion, and a technique for filling polycrystalline silicon inside the silicon oxide film formed in the element isolation trench (Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 9-97832 Summary of the Invention [Problem to be solved by the invention]

[0005] A known semiconductor device uses a substrate having an SOI structure, and on the insulating layer, a semiconductor layer of an active region in which a transistor element is formed and an element isolation layer provided around the semiconductor layer to define the semiconductor layer are provided.

[0006] In such semiconductor devices, the thermal conductivity of the insulating layer and element isolation layer surrounding the semiconductor layer is lower than that of the material used in the semiconductor layer in the active region. Therefore, heat generated by self-heating in the semiconductor layer surrounded by the insulating layer and element isolation layer is difficult to dissipate to the outside, and a rise in temperature in the semiconductor layer may lead to performance degradation of the semiconductor device.

[0007] On the other hand, if the thickness of the insulating layer provided under the semiconductor layer is reduced in order to improve heat dissipation, this may result in a decrease in the breakdown voltage of the semiconductor device. Furthermore, when polycrystalline silicon or the like is provided in an element isolation layer provided around a semiconductor layer, depending on its arrangement and connection with other parts, this may result in a reduction in the degree of freedom in the layout of circuit elements such as electrodes and wiring, or a reduction in the breakdown voltage.

[0008] In one aspect, the present invention aims to provide a semiconductor device that allows a high degree of freedom in the layout of circuit elements, suppresses performance degradation due to self-heating, and suppresses a decrease in breakdown voltage. [Means for solving the problem]

[0009] In one aspect, a semiconductor device is provided, comprising: an insulating layer having a first surface and a second surface opposite the first surface; a first semiconductor layer provided on the first surface side of the insulating layer; a first thermal conduction portion provided on the first surface side of the insulating layer and separated from the first semiconductor layer, the first thermal conduction portion having a third surface facing a first direction parallel to the first surface and facing the first semiconductor layer, and a fourth surface facing a second direction perpendicular to the first direction and away from the first surface; and a first element isolation layer provided on the first surface side of the insulating layer so as to define the first semiconductor layer and covering the third surface and the fourth surface of the first thermal conduction portion, wherein a thickness of a first portion of the first element isolation layer between the first semiconductor layer and the third surface is smaller than a thickness of the insulating layer between the first surface and the second surface.

[0010] In another aspect, there is provided a method for manufacturing a semiconductor device, the method including the steps of: forming a first semiconductor layer on the first surface side of an insulating layer having a first surface and a second surface opposite the first surface as described above; forming a first thermal conduction portion on the first surface side of the insulating layer, the first thermal conduction portion being separated from the first semiconductor layer, the first thermal conduction portion having a third surface facing a first direction parallel to the first surface and facing the first semiconductor layer, and a fourth surface facing a second direction perpendicular to the first direction and away from the first surface; and forming a first element isolation layer on the first surface side of the insulating layer so as to define the first semiconductor layer, the first element isolation layer covering the third surface and the fourth surface of the first thermal conduction portion, wherein a thickness of a first portion of the first element isolation layer between the first semiconductor layer and the third surface is smaller than a thickness of the insulating layer between the first surface and the second surface. [Effects of the Invention]

[0011] In one aspect, it is possible to realize a semiconductor device that has a high degree of freedom in the layout of circuit elements, suppresses performance degradation due to self-heating, and suppresses a decrease in breakdown voltage. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a diagram (part 1) illustrating an example of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a diagram (part 2) illustrating an example of the semiconductor device according to the first embodiment. [Figure 3] 10A and 10B are diagrams illustrating an example of a semiconductor device according to a second embodiment. [Figure 4] 10A and 10B are diagrams illustrating an example of a semiconductor device according to a third embodiment. [Figure 5] 10A and 10B are diagrams illustrating an example of a semiconductor device according to a fourth embodiment. [Figure 6] 10A to 10C are diagrams (part 1) illustrating an example of a method for manufacturing a semiconductor device according to a fifth embodiment. [Figure 7] 13A to 13C are diagrams (part 2) illustrating an example of a method for manufacturing a semiconductor device according to a fifth embodiment. [Figure 8] 13A to 13C are views (part 3) illustrating an example of a method for manufacturing a semiconductor device according to a fifth embodiment. [Figure 9] 13A and 13B are views (part 4) illustrating an example of a method for manufacturing a semiconductor device according to a fifth embodiment. [Figure 10] 13A to 13C are diagrams (part 5) illustrating an example of a method for manufacturing a semiconductor device according to the fifth embodiment. [Figure 11] 13A and 13B are diagrams (part 6) illustrating an example of a method for manufacturing a semiconductor device according to the fifth embodiment. [Figure 12] FIG. 13 is a diagram (part 7) illustrating an example of a method for manufacturing a semiconductor device according to the fifth embodiment. [Figure 13] FIG. 13 is a diagram (part 8) illustrating an example of a method for manufacturing a semiconductor device according to the fifth embodiment. [Figure 14] FIG. 9 is a diagram for explaining an example of a method for manufacturing a semiconductor device according to the fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] [First embodiment] 1 and 2 are diagrams illustrating an example of a semiconductor device according to a first embodiment. Fig. 1 is a schematic plan view of a main part of the example of the semiconductor device. Fig. 2 is a schematic cross-sectional view of a main part of the example of the semiconductor device. Fig. 2 is a schematic cross-sectional view taken along II-II in Fig. 1.

[0014] 1 and 2, for the sake of convenience, an example of heat 100 generated in the semiconductor device 1 and its propagation is schematically shown by thick arrows. 1 and 2 is an example of a semiconductor device including a transistor element formed using a substrate having an SOI structure (referred to as an "SOI substrate"). Here, the semiconductor device 1 includes an LDMOS transistor 10, which is a type of high-voltage transistor, as the transistor element.

[0015] As shown in FIGS. 1 and 2, the semiconductor device 1 includes an insulating layer 20, a first semiconductor layer 30, a first thermal conduction portion 40, and a first element isolation layer 50. 2, the insulating layer 20 has a first surface 20a (upper surface) and an opposite second surface 20b (lower surface). Various insulating materials, such as silicon oxide (SiO2 or SiO), are used for the insulating layer 20. The insulating layer 20 is a BOX (Buried Oxide) layer in an SOI substrate.

[0016] As shown in Fig. 2, the first semiconductor layer 30 is provided on the first surface 20a side of the insulating layer 20. For example, as shown in Fig. 2, the first semiconductor layer 30 is provided so as to be in contact with the first surface 20a of the insulating layer 20. Various semiconductor materials, for example, silicon (Si), are used for the first semiconductor layer 30. For example, the first semiconductor layer 30 is formed by patterning a predetermined semiconductor material formed on the first surface 20a side of the insulating layer 20 by etching.

[0017] As shown in FIG. 2, the first element isolation layer 50 is provided on the first surface 20a side of the insulating layer 20. As shown in FIGS. 1 and 2, the first element isolation layer 50 is provided so as to define the first semiconductor layer 30. The first element isolation layer 50 may be made of various insulating materials, such as silicon oxide. The first element isolation layer 50 is formed, for example, by STI (Shallow Trench Isolation), which fills the periphery of the first semiconductor layer 30, which has been patterned by etching, with a predetermined insulating material.

[0018] 1 and 2 is formed in the first semiconductor layer 30 defined by the first element isolation layer 50. The first semiconductor layer 30 is an active region or device region in the semiconductor device 1 where the LDMOS transistor 10 is formed.

[0019] 2, the LDMOS transistor 10 includes a body region 11 of a first conductivity type and a drift region 12 of a second conductivity type opposite to the first conductivity type and adjacent to the body region 11. For example, the first conductivity type is p-type and the second conductivity type is n-type.

[0020] 1 and 2, a body contact region 13 of a first conductivity type and a source region 14 of a second conductivity type are provided in a surface layer portion of the body region 11. A drain region 15 of a second conductivity type is provided in a surface layer portion of the drift region 12, as shown in FIGS. 1 and 2. The source region 14 is separated from the drift region 12 by the body region 11. A deep well layer 16 of a second conductivity type is provided in lower layers of the body region 11 and the drift region 12 on the insulating layer 20 side, as shown in FIG.

[0021] 1 and 2, a gate electrode 18 is provided on the side of the body region 11 and the drift region 12 opposite to the insulating layer 20, i.e., on the body region 11 and the drift region 12, via a gate insulating film 17. The gate insulating film 17 may be made of various insulating materials, such as silicon oxide. The gate electrode 18 may be made of various conductive materials, such as polysilicon.

[0022] 1 and 2, contacts 19 are connected to the body contact region 13, the source region 14, the drain region 15, and the gate electrode 18 (the gate electrode 18 is not shown). The contacts 19 are made of various conductive materials, such as tungsten (W). Although not shown here, the contacts 19 are electrically connected to a wiring layer of a multilayer wiring structure that is provided to cover the LDMOS transistor 10.

[0023] A metal silicide layer (not shown) may be provided on the surface layer of the body contact region 13, the source region 14, the drain region 15 and the gate electrode 18, and a contact 19 may be connected to the metal silicide layer.

[0024] A second element isolation layer 60 may be provided in the first semiconductor layer 30 to increase the withstand voltage by extending the drift distance of carriers in the drift region 12 between the gate electrode 18 and the drain region 15. The second element isolation layer 60 may be continuous with the first element isolation layer 50. The second element isolation layer 60 may be a part of the first element isolation layer 50, that is, a part of the first element isolation layer 50 that extends from directly below the gate electrode 18 to a position that reaches the drain region 15.

[0025] 2, a second semiconductor layer 70 that functions as a support substrate may be provided on the second surface 20b side of the insulating layer 20. The second semiconductor layer 70 may be made of various semiconductor materials, such as silicon. For example, the second semiconductor layer 70 may be connected to a ground potential.

[0026] The stack of the insulating layer 20 and the first semiconductor layer 30, or the stack of the insulating layer 20, the first semiconductor layer 30, and the second semiconductor layer 70 corresponds to an SOI substrate. In an SOI substrate, the insulating layer 20 is called a BOX layer. The BOX layer is also called a buried insulating layer.

[0027] For example, the LDMOS transistor 10 may be an n-type LDMOS transistor, where the first conductivity type is p-type and the second conductivity type is n-type. Alternatively, the LDMOS transistor 10 may be a p-type LDMOS transistor, where the first conductivity type is n-type and the second conductivity type is p-type.

[0028] The semiconductor device 1 is provided with a first thermally conductive portion 40. As shown in FIG. 2, the first thermally conductive portion 40 is provided on the first surface 20a side of the insulating layer 20. As shown in FIGS. 1 and 2, the first thermally conductive portion 40 is provided separated from the first semiconductor layer 30. As an example, as shown in FIGS. 1 and 2, the first thermally conductive portion 40 is provided so as to surround the entire periphery of the first semiconductor layer 30 in which the LDMOS transistor 10 is formed.

[0029] 2, the first thermally conductive member 40 is provided separated from the first semiconductor layer 30 so as to be in contact with the first surface 20a of the insulating layer 20. The first thermally conductive member 40 and the first semiconductor layer 30 are provided so that their surfaces facing the insulating layer 20 are located in the same plane parallel to the first surface 20a, in this example, within the first surface 20a, as shown in FIG.

[0030] The first thermally conductive member 40 is made of various materials having thermal conductivity. For example, the first thermally conductive member 40 is made of a semiconductor material such as silicon. As an example, the first thermally conductive member 40 is made of the same semiconductor material as the first semiconductor layer 30. For example, both the first thermally conductive member 40 and the first semiconductor layer 30 are made of silicon. For example, the first thermally conductive member 40 is formed by patterning by etching together with the first semiconductor layer 30 in the device region.

[0031] As shown in Figures 1 and 2, the first thermal conduction member 40 has a third surface 40a (side surface) facing a first direction D1 parallel to the first surface 20a of the insulating layer 20 and facing the first semiconductor layer 30, and a fourth surface 40b (top surface) facing a second direction D2 perpendicular to the first direction D1 and away from the first surface 20a.

[0032] 1 and 2, the third surface 40a of the first thermal conductive member 40 is provided at a position spaced a certain distance from the first semiconductor layer 30, that is, a distance corresponding to a thickness T1 of a first portion 51 of a first element isolation layer 50 described later. As shown in Fig. 2, a height H1 of the fourth surface 40b of the first thermal conductive member 40 from the first surface 20a of the insulating layer 20 is provided at a position lower than a height H2 of a fifth surface 30a (upper surface) of the first semiconductor layer 30 on the side opposite to the insulating layer 20 side from the first surface 20a of the insulating layer 20. The fifth surface 30a of the first semiconductor layer 30 is not covered by the first element isolation layer 50 and the second element isolation layer 60, but is exposed therefrom.

[0033] As shown in FIGS. 1 and 2, a first element isolation layer 50 is provided so as to cover the third surface 40a and the fourth surface 40b of the first thermal conductive portion 40. Still, as shown in FIGS. 1 and 2, the first heat conduction part 40 has, as a surface facing in the first direction D1 parallel to the first surface 20a of the insulating layer 20, in addition to the third surface 40a, a surface 40c (side surface) on the side opposite to the third surface 40a. The first element isolation layer 50 is provided so as to cover the third surface 40a and the fourth surface 40b of the first heat conduction part 40, as well as such a surface 40c. It can also be said that the first heat conduction part 40 is provided within the first element isolation layer 50.

[0034] In the semiconductor device 1, the thickness T1 of the first part 51 between the first semiconductor layer 30 and the third surface 40a of the first heat conduction part 40 of the first element isolation layer 50 is smaller than the thickness T2 between the first surface 20a and the second surface 20b of the insulating layer 20, as shown in FIG. 2. In the semiconductor device 1, the distance between the first semiconductor layer 30 and the first heat conduction part 40 (its third surface 40a) separated therefrom, and the thickness T1 of the first part 51 of the first element isolation layer 50 provided therebetween are adjusted so that such a relationship of thickness T1 < T2 can be obtained.

[0035] In the first element isolation layer 50, as shown in FIGS. 1 and 2, a second heat conduction part 80 connected to the first heat conduction part 40 may be provided. For example, the second heat conduction part 80 is provided so as to extend in the second direction D2 from the fourth surface 40b of the first heat conduction part 40, and further, a part thereof is provided so as to extend outside the first element isolation layer 50. As shown in FIGS. 1 and 2, a contact 19 such as tungsten may be connected to the part of the second heat conduction part 80 extending outside the first element isolation layer 50.

[0036] In the semiconductor device 1, when the first heat conduction part 40 or the second heat conduction part 80 is connected, the first heat conduction part 40 and the second heat conduction part 80 are provided so as to be electrically floating, that is, electrically separated from the LDMOS transistor 10 and other circuit elements of the semiconductor device 1.

[0037] In the semiconductor device 1 using an SOI substrate, the first semiconductor layer 30 in the device region where the LDMOS transistor 10 is formed is isolated from the surroundings by the insulating layer 20 and the first element isolation layer 50. This ensures a breakdown voltage between the LDMOS transistor 10 and the second semiconductor layer 70 provided on the second surface 20b side of the insulating layer 20, and between the LDMOS transistor 10 and other transistors, etc., provided via the first element isolation layer 50.

[0038] In the semiconductor device 1 having the above-described configuration, the LDMOS transistor 10 formed in the first semiconductor layer 30 in the device region generates heat during its operation. Such heat generation is also called self-heating.

[0039] In the semiconductor device 1 described above, the thermal conductivity of the material used for the insulating layer 20 and first element isolation layer 50 surrounding the first semiconductor layer 30 in the device region may be lower than that of the material used for the first semiconductor layer 30. For example, if silicon is used for the first semiconductor layer 30 and silicon oxide is used for the insulating layer 20 and the first element isolation layer 50, the thermal conductivity of silicon is 168 [W / (m·K)], while the thermal conductivity of silicon oxide is 1.38 [W / (m·K)].

[0040] Here, we will consider a case where the first thermally conductive member 40 (and the second thermally conductive member 80 connected thereto) described in the semiconductor device 1 above is not provided. Even in this case, as described above, the first semiconductor layer 30 in which the LDMOS transistor 10 is formed is isolated from the surroundings by the insulating layer 20 and the first element isolation layer 50, ensuring a sufficient breakdown voltage. However, because the first semiconductor layer 30 is surrounded by the insulating layer 20 and the first element isolation layer 50, which have lower thermal conductivity than the first semiconductor layer 30, heat generated during operation of the LDMOS transistor 10 is less likely to be dissipated to the outside of the first semiconductor layer 30. If heat dissipation is suppressed and the temperature of the first semiconductor layer 30 rises, the driving capability of the LDMOS transistor 10 may deteriorate. Note that reducing the thickness T2 of the insulating layer 20 improves heat dissipation from the first semiconductor layer 30 through the insulating layer 20. However, reducing the thickness T2 of the insulating layer 20 leads to a decrease in the breakdown voltage, and this decrease in the breakdown voltage is more likely to occur particularly when the second semiconductor layer 70 is provided on the side of the insulating layer 20 opposite the first semiconductor layer 30 and the second semiconductor layer 70 is at ground potential. Although increasing the thickness T2 of the insulating layer 20 can suppress such a decrease in the breakdown voltage, it also reduces the heat dissipation from the first semiconductor layer 30 through the insulating layer 20.

[0041] 1 and 2, in the semiconductor device 1, a first thermally conductive member 40 is provided in the first element isolation layer 50, spaced apart from the first semiconductor layer 30 in the device region where the LDMOS transistor 10 is formed. Alternatively, a second thermally conductive member 80 is further provided in the first element isolation layer 50, connected to the first thermally conductive member 40 and partially extending outside the first element isolation layer 50. The first element isolation layer 50 is provided so as to cover the first thermally conductive member 40, i.e., so as to cover its third surface 40a and fourth surface 40b (and surface 40c). The first thermally conductive member 40 and the first element isolation layer 50 are provided so that a thickness T1 of a first portion 51 of the first element isolation layer 50 provided between the third surface 40a of the first thermally conductive member 40 and the first semiconductor layer 30 is smaller than a thickness T2 of the insulating layer 20.

[0042] As a result, in the semiconductor device 1, the breakdown voltage is ensured by the relatively thick insulating layer 20 and first element isolation layer 50 that surround the first semiconductor layer 30. On the other hand, in the semiconductor device 1, heat 100 generated by self-heating of the LDMOS transistor 10 formed in the first semiconductor layer 30 is propagated to the first thermal conductive portion 40 via the relatively thin first portion 51, as shown in FIGS.

[0043] In the semiconductor device 1, even though the relatively thick insulating layer 20 suppresses the propagation and dissipation of heat 100 from the first surface 20a to the second surface 20b, the heat 100 propagates to the first thermally conductive member 40 via the relatively thin first portion 51. The heat 100 propagated to the first thermally conductive member 40 is propagated, diffused, or dispersed within the first thermally conductive member 40. This suppresses a temperature rise in the first semiconductor layer 30 due to self-heating of the LDMOS transistor 10, and suppresses a deterioration in the driving capability of the LDMOS transistor 10 caused by the temperature rise.

[0044] In the semiconductor device 1, a decrease in the withstand voltage is suppressed by the relatively thick insulating layer 20, and further, even when the second semiconductor layer 70 is provided on the second surface 20b side of the insulating layer 20 and is set to earth potential, the decrease in the withstand voltage is suppressed. Furthermore, in the semiconductor device 1, the first heat conduction portion 40, to which the heat 100 from the first semiconductor layer 30 is propagated, is made electrically floating, thereby effectively suppressing a decrease in the withstand voltage.

[0045] In the semiconductor device 1, in addition to the first thermally conductive member 40, a second thermally conductive member 80 connected thereto is provided, so that heat 100 propagated from the first semiconductor layer 30 to the first thermally conductive member 40 is further propagated, diffused, or dispersed to the second thermally conductive member 80. This effectively suppresses a temperature rise in the first semiconductor layer 30 due to self-heating of the LDMOS transistor 10. Furthermore, by extending a portion of the second thermally conductive member 80 outside the first element isolation layer 50, the heat 100 is dissipated from that portion of the first element isolation layer 50. This further effectively suppresses a temperature rise in the first semiconductor layer 30 due to self-heating of the LDMOS transistor 10. Furthermore, by electrically floating the second thermally conductive member 80 as well as the first thermally conductive member 40, a decrease in the breakdown voltage is suppressed.

[0046] In the semiconductor device 1, the region where the second heat conducting portion 80 connected to the first heat conducting portion 40 is provided can be called a heat sink region. In the semiconductor device 1, as shown in FIG. 1 (and FIG. 2 ), the gate electrode 18 of the LDMOS transistor 10 overlaps the first semiconductor layer 30 in a plan view. When the second element isolation layer 60 is provided, the gate electrode 18 overlaps the first semiconductor layer 30 and the second element isolation layer 60. As shown in FIG. 1 , the gate electrode 18 may also overlap the first element isolation layer 50 and the first thermal conductive portion 40 covered by the first element isolation layer 50 in a plan view. In the semiconductor device 1, the first element isolation layer 50 is provided so as to cover the first thermal conductive portion 40, which reduces the reduction in the degree of freedom in layout of the gate electrode 18 when the gate electrode 18 is provided (or routed) on the first element isolation layer 50. In other words, the presence of the first thermal conductive portion 40 is prevented from restricting the layout (or routing) of the gate electrode 18.

[0047] While the gate electrode 18 is used as an example here, in the semiconductor device 1, various circuit elements, such as an electrode or a portion thereof, a wiring or a portion thereof, a resistor or a portion thereof, a capacitor or a portion thereof, and an inductor or a portion thereof, can be provided on the first element isolation layer 50. In such cases, a decrease in the degree of freedom in the layout of the various circuit elements is similarly suppressed. That is, in the semiconductor device 1, it is possible to provide the various circuit elements in a layout that overlaps the first element isolation layer 50 and the first thermal conduction portion 40 covered by the first element isolation layer 50 in a planar view.

[0048] According to the configuration described above, the semiconductor device 1 is realized which has a high degree of freedom in the layout of circuit elements, suppresses performance degradation due to self-heating, and suppresses a decrease in breakdown voltage.

[0049] In the semiconductor device 1 having the above-described configuration, the first thermally conductive member 40 is provided so as to be in contact with the first surface 20a of the insulating layer 20, for example, as shown in Fig. 2. Alternatively, when a depression is provided in the first surface 20a of the insulating layer 20, the first thermally conductive member 40 may be provided so as to be in contact with the inner surface of the depression in the first surface 20a.

[0050] 2, the first semiconductor layer 30 is provided so as to be in contact with the first surface 20a of the insulating layer 20. In addition, when a depression is provided in the first surface 20a of the insulating layer 20, the first semiconductor layer 30 may be provided so as to be in contact with the inner surface of the depression in the first surface 20a.

[0051] Furthermore, in the semiconductor device 1, the first thermally conductive member 40 and the first semiconductor layer 30 do not necessarily need to be in contact with the first surface 20a of the insulating layer 20, and another layer (such as an insulating layer) may be interposed between them. Regardless of whether another layer is interposed between the first thermally conductive member 40 and the first semiconductor layer 30 and the first surface 20a of the insulating layer 20 or not, the surfaces of the first thermally conductive member 40 and the first semiconductor layer 30 facing the insulating layer 20 may be located in the same plane parallel to the first surface 20a.

[0052] 1 and 2, the first element isolation layer 50 of the semiconductor device 1 may be provided to have a second portion 52 extending closer to the first semiconductor layer 30 than the first portion 51. The second portion 52 is located on the opposite side of the first portion 51 from the insulating layer 20 side and is provided continuously with the first portion 51. As shown in FIG. 2, the second portion 52 has a sixth surface 50a (lower surface) facing the insulating layer 20 and spaced apart from the first surface 20a. A portion of the first semiconductor layer 30 is interposed between the sixth surface 50a and the first surface 20a, and this portion is in contact with the sixth surface 50a. The first element isolation layer 50 may be arranged so that the height of the sixth surface 50a from the first surface 20a, i.e., the height of the portion of the first semiconductor layer 30 interposed therebetween from the first surface 20a, is the same as the height H1 of the fourth surface 40b of the first thermal conduction portion 40 from the first surface 20a.

[0053] 1 and 2 is provided in the first semiconductor layer 30 of the semiconductor device 1, the second element isolation layer 60 is provided to have a seventh surface 60a (lower surface) facing the insulating layer 20 and spaced from the first surface 20a, as shown in FIG. 2. A portion of the first semiconductor layer 30 is interposed between the seventh surface 60a and the first surface 20a, and this portion is in contact with the seventh surface 60a. The second element isolation layer 60 may be provided such that the height of the seventh surface 60a from the first surface 20a, i.e., the height of the portion of the first semiconductor layer 30 interposed therebetween from the first surface 20a, is the same as the height H1 of the fourth surface 40b of the first thermal conductive member 40 from the first surface 20a.

[0054] Furthermore, with regard to the semiconductor device 1, the first surface 20a and the second surface 20b of the insulating layer 20 do not necessarily have to be flat surfaces, but may be surfaces having recesses, protrusions, or uneven portions.

[0055] Furthermore, in the semiconductor device 1, the third surface 40a of the first thermal conductive member 40 does not necessarily have to be a flat surface perpendicular to the first surface 20a of the insulating layer 20, and may be a surface having recesses, protrusions, or unevenness within the surface. Even if the third surface 40a is not a flat surface perpendicular to the first surface 20a, heat 100 can be propagated between the first semiconductor layer 30 and the third surface 40a via the first portion 51 of the first element isolation layer 50, and it is possible to suppress a temperature rise in the first semiconductor layer 30.

[0056] Furthermore, with regard to the semiconductor device 1, the fourth surface 40b of the first thermal conductive member 40 does not necessarily have to be a flat surface parallel to the first surface 20a of the insulating layer 20, and may be a surface having concave portions, convex portions, or uneven portions within the surface. Even if the fourth surface 40b is not a flat surface parallel to the first surface 20a, the first thermal conductive member 40 can be covered with the first element isolation layer 50, and various circuit elements can be provided on the first element isolation layer 50 covering the first thermal conductive member 40.

[0057] Furthermore, with regard to the semiconductor device 1, the fifth surface 30a of the first semiconductor layer 30 does not necessarily need to be a flat surface parallel to the first surface 20a of the insulating layer 20, but may be a surface having recesses, protrusions, or uneven portions within the surface.

[0058] Furthermore, with regard to the semiconductor device 1, the sixth surface 50a of the second portion 52 of the first element isolation layer 50 (or the surface of a portion of the first semiconductor layer 30 in contact therewith) does not necessarily need to be a flat surface parallel to the first surface 20a of the insulating layer 20, but may be a surface having recesses, protrusions, uneven portions, etc. within the surface.

[0059] Furthermore, with regard to the semiconductor device 1, the seventh surface 60a of the second element isolation layer 60 (or a portion of the surface of the first semiconductor layer 30 in contact therewith) does not necessarily need to be a flat surface parallel to the first surface 20a of the insulating layer 20, but may be a surface having recesses, protrusions, or uneven portions within the surface.

[0060] For convenience, in FIG. 2, the insulating layer 20 is illustrated as being thinner than the first semiconductor layer 30, but the thickness relationship between the first semiconductor layer 30 and the insulating layer 20 is not limited to the illustrated form.

[0061] Although not shown here, the semiconductor device 1 may further be provided with an area in which alignment marks used in the manufacturing process are formed. Details of the manufacturing process of the semiconductor device 1 will be described later (fifth embodiment). In the semiconductor device 1, the area in which such alignment marks are formed can be referred to as an alignment mark area.

[0062] [Second embodiment] In the first embodiment, the semiconductor device 1 is exemplified as including the LDMOS transistor 10, which is one type of high-voltage transistor, as the transistor element, but the type of the transistor element is not limited to this.

[0063] Fig. 3 is a diagram illustrating an example of a semiconductor device according to the second embodiment, which diagrammatically shows a cross-sectional view of a main part of the example of the semiconductor device. For convenience, FIG. 3 shows an example of heat 100A generated in the semiconductor device 1A and how it propagates, schematically indicated by thick arrows.

[0064] 3 differs from the semiconductor device 1 described in the first embodiment in that a MOS transistor 10A is provided in a first semiconductor layer 30 in a device region defined by a first element isolation layer 50. Other configurations of the semiconductor device 1A are similar to those of the semiconductor device 1 described above.

[0065] The MOS transistor 10A includes a source region 14A, a drain region 15A, a gate insulating film 17A, a gate electrode 18A, and a sidewall insulating film 17Aa. The source region 14A and the drain region 15A are provided in a first semiconductor layer 30 and are separated from each other. A gate electrode 18A is provided on the first semiconductor layer 30 between the source region 14A and the drain region 15A with the gate insulating film 17A interposed therebetween, and a sidewall insulating film 17Aa is provided on the sidewall of the gate electrode 18A. Contacts 19 are connected to the source region 14A, the drain region 15A, and the gate electrode 18A (the gate electrode 18A is not shown).

[0066] As in this semiconductor device 1A, a transistor element formed in a device region may have a configuration like that of a MOS transistor 10A that is not limited to high-voltage applications.

[0067] The MOS transistor 10A generates heat during operation. In the semiconductor device 1A, heat 100A generated by the MOS transistor 10A formed in the first semiconductor layer 30 is propagated to the first heat conductive portion 40 through the first portion 51 of the first element isolation layer 50, which has a thickness T1 that is thinner than the thickness T2 of the insulating layer 20. The heat 100A propagated to the first heat conductive portion 40 is further propagated to the second heat conductive portion 80 connected to the first heat conductive portion 40, and is dissipated through a portion extending outside the first element isolation layer 50 or through the contact 19 connected thereto. This suppresses a temperature rise in the first semiconductor layer 30 due to self-heating of the MOS transistor 10A, and suppresses deterioration of the driving capability of the MOS transistor 10A due to the temperature rise.

[0068] Also, in the semiconductor device 1A, a decrease in breakdown voltage is suppressed by adopting a configuration in which the first semiconductor layer 30, in which the MOS transistor 10A is formed, is surrounded by the insulating layer 20 and the first element isolation layer 50. Furthermore, a configuration in which the first heat conduction portion 40 is covered by the first element isolation layer 50 is adopted, so a decrease in the degree of freedom in the layout of various circuit elements provided on the first element isolation layer 50, including the gate electrode 18A, is suppressed.

[0069] This second embodiment also realizes a semiconductor device 1A that has a high degree of freedom in the layout of circuit elements, suppresses performance degradation due to self-heating, and suppresses a decrease in breakdown voltage.

[0070] For convenience, in FIG. 3, the insulating layer 20 is illustrated as being thinner than the first semiconductor layer 30, but the thickness relationship between the first semiconductor layer 30 and the insulating layer 20 is not limited to the illustrated form.

[0071] [Third embodiment] In the above first embodiment, a semiconductor device 1 having a first thermal conduction portion 40 that surrounds the entire periphery of the first semiconductor layer 30 in a planar view is exemplified, but the arrangement and shape of the first thermal conduction portion 40 are not limited to this.

[0072] Fig. 4 is a diagram illustrating an example of a semiconductor device according to the third embodiment, which diagrammatically shows a plan view of a main part of the example of the semiconductor device. 4 differs from the semiconductor device 1 described in the first embodiment in that the first thermal conductive portion 40 provided in the first element isolation layer 50 is provided only on a portion of the entire periphery of the first semiconductor layer 30 in which the LDMOS transistor 10 is formed. The other configurations of the semiconductor device 1B are the same as those of the semiconductor device 1 described above.

[0073] As in this semiconductor device 1B, the first heat conducting portion 40 does not necessarily have to be provided so as to surround the entire periphery of the first semiconductor layer 30. In the semiconductor device 1B, too, heat generated in the LDMOS transistor 10 is propagated to the first thermally conductive member 40 via the first portion 51 of the relatively thin first element isolation layer 50. The heat propagated to the first thermally conductive member 40 is then further propagated to the second thermally conductive member 80 connected to the first thermally conductive member 40, and is dissipated through a portion extending outside the first element isolation layer 50 or through the contact 19 connected thereto. This suppresses a temperature rise in the first semiconductor layer 30 due to self-heating of the LDMOS transistor 10, and suppresses deterioration of the driving capability of the LDMOS transistor 10 due to the temperature rise.

[0074] Furthermore, the same can be said about the degree of freedom in layout of various circuit elements and the withstand voltage of the semiconductor device 1B as for the semiconductor device 1 described above. This third embodiment also realizes a semiconductor device 1B that has a high degree of freedom in the layout of circuit elements, suppresses performance degradation due to self-heating, and suppresses a decrease in breakdown voltage.

[0075] [Fourth embodiment] In the first embodiment, one LDMOS transistor 10 is exemplified as a transistor element, but the semiconductor device 1 may have a configuration in which a plurality of transistor elements are integrated.

[0076] Fig. 5 is a diagram illustrating an example of a semiconductor device according to the fourth embodiment, which is a schematic plan view of a main part of the example of the semiconductor device. 5, similarly to the above, includes a first semiconductor layer 30 in a device region on an insulating layer 20 of an SOI substrate and defined by a first element isolation layer 50. For example, the device region includes two LDMOS transistors 10 connected in parallel and sharing a drift region 12 (not shown) and a drain region 15, two sets of CMOS (Complementary Metal Oxide Semiconductor) transistors 200, and two wirings 260.

[0077] Each CMOS transistor 200 includes an n-channel MOS (nMOS) transistor 200n and a p-channel MOS (pMOS) transistor 200p. The nMOS transistor 200n has an n-type source region 210n, an n-type drain region 220n adjacent thereto, and a p-type body region (p-type well region) 230p facing the n-type source region 210n and the n-type drain region 220n. The nMOS transistor 200n has a separate gate 240 located between the n-type source region 210n, the n-type drain region 220n, and the p-type body region 230p, and a gate electrode 250 located between the n-type source region 210n and the n-type drain region 220n. Contacts 19 are connected to the n-type source region 210n, the n-type drain region 220n, and the p-type body region 230p, respectively.

[0078] The pMOS transistor 200p has a p-type source region 210p, a p-type drain region 220p adjacent to the p-type source region 210p, and an n-type body region (n-type well region) 230n facing the p-type source region 210p and the p-type drain region 220p. The pMOS transistor 200p has a separate gate 240 located between the p-type source region 210p, the p-type drain region 220p, and the n-type body region 230n, and a gate electrode 250 located between the p-type source region 210p and the p-type drain region 220p. Contacts 19 are connected to the p-type source region 210p, the p-type drain region 220p, and the n-type body region 230n, respectively.

[0079] The LDMOS transistor 10, nMOS transistor 200n, and pMOS transistor 200p having the above-described configuration are formed in respective device regions defined by the first element isolation layer 50.

[0080] In the semiconductor device 1C, a first thermally conductive portion 40 is provided so as to surround the two LDMOS transistors 10 in a planar view. In the semiconductor device 1C, a first thermally conductive portion 40 is further provided so as to surround the nMOS transistor 200n and the pMOS transistor 200p of the CMOS transistor 200 in a planar view. The first thermally conductive portions 40 surrounding the LDMOS transistor 10, the nMOS transistor 200n, and the pMOS transistor 200p are connected to each other by further first thermally conductive portions 40 connecting them. A first element isolation layer 50 is provided so as to cover the first thermally conductive portion 40 thus provided. Then, a second thermally conductive portion 80 is connected to predetermined locations of the first thermally conductive portion 40 (two locations in this example), and a contact 19 is connected to a portion of the second thermally conductive portion 40 extending outside the first element isolation layer 50.

[0081] The gate electrode 18 of the LDMOS transistor 10, as well as wiring 18a routed from the gate electrode 18 and contacts 19 connected thereto, are provided on the first element isolation layer 50 covering the first thermal conduction portion 40. In addition, the separate gate 240 and gate electrode 250 of the CMOS transistor 200, as well as wiring 250a routed from the gate electrode 250 and contacts 19 connected thereto, are provided on the first element isolation layer 50. Furthermore, a conductor pattern having a predetermined shape, in this example, two linear wirings 260 and contacts 19 connected thereto, is provided on the first element isolation layer 50. For example, the wiring 260, which is a conductor pattern, may be formed from the same material as the gate electrode 18, the wiring 18a routed from the gate electrode 18, the separate gate 240 and gate electrode 250, and the wiring 250a routed from the gate electrode 250. The wiring 260 may be used not only as a simple wiring but also as, for example, a resistor. For example, the gate electrode 18, the wiring 18a routed from the gate electrode 18, the separate gate 240, the gate electrode 250, the wiring 250a routed from the gate electrode 250, and the wiring 260 can be made of polycrystalline silicon. The wiring 260 can be made into a resistive element by appropriately adjusting its width and length. When polycrystalline silicon is used, the wiring 260 can be made into a polycrystalline silicon resistor.

[0082] During operation of the semiconductor device 1C, the LDMOS transistor 10, the nMOS transistor 200n, and the pMOS transistor 200p each generate heat. The heat generated in each transistor element is propagated to the first thermally conductive portion 40 through the first portion 51 of the relatively thin first element isolation layer 50, and further to the second thermally conductive portion 80, where it is dissipated through the contacts 19 connected thereto. This suppresses a temperature rise in the first semiconductor layer 30 due to self-heating of each transistor element, and suppresses deterioration of the driving capability of each transistor element due to the temperature rise.

[0083] Furthermore, in the semiconductor device 1C, the first heat conducting portion 40, which surrounds each of the transistor elements, the LDMOS transistor 10, the nMOS transistor 200n, and the pMOS transistor 200p in plan view and which is further connected to each other, is covered with the first element isolation layer 50. Therefore, in the semiconductor device 1C, a reduction in the degree of freedom in layout of various circuit elements provided on the first element isolation layer 50, such as the gate electrode 18, the wiring 18a, the separate gate 240, the gate electrode 250, the wiring 250a, and the wiring 260 in this example, is suppressed.

[0084] Here, the gate electrode 18, the wiring 18a, the separate gate 240, the gate electrode 250, the wiring 250a, and the wiring 260 are exemplified as circuit elements provided on the first element isolation layer 50. In addition to the exemplified resistors or parts thereof formed using polycrystalline silicon or the like, various circuit elements such as a capacitor or part thereof having a dielectric between an electrode pair, and an inductor or part thereof having a conductor in a predetermined pattern shape may be provided on the first element isolation layer 50. Even when such circuit elements are provided, a reduction in layout freedom is suppressed, as described above.

[0085] Also in the semiconductor device 1C, the first semiconductor layer 30 in which the transistor elements of the LDMOS transistor 10, the nMOS transistor 200n, and the pMOS transistor 200p are formed is surrounded by the insulating layer 20 and the first element isolation layer 50, thereby suppressing a decrease in breakdown voltage.

[0086] This fourth embodiment also realizes a semiconductor device 1C that has a high degree of freedom in the layout of circuit elements, suppresses performance degradation due to self-heating, and suppresses a decrease in breakdown voltage.

[0087] [Fifth embodiment] An example of a method for manufacturing a semiconductor device will be described as a fifth embodiment, in which a method for manufacturing a semiconductor device 1 including an LDMOS transistor 10 as described in the first embodiment will be taken as an example.

[0088] 6 to 14 are diagrams illustrating an example of a method for manufacturing a semiconductor device according to the fifth embodiment. Each of Fig. 6 to 14 is a schematic cross-sectional view of a main part of an example of each step in manufacturing a semiconductor device. Each step in manufacturing a semiconductor device will be described below in order with reference to Fig. 6 to 14.

[0089] FIG. 6 is a diagram illustrating an example of the first etching step. First, an SOI substrate is prepared. FIG. 6 illustrates an SOI substrate in which a first semiconductor layer 30 (semiconductor material) is provided on the first surface 20a side of an insulating layer 20 (BOX layer), and a second semiconductor layer 70 (support substrate or semiconductor substrate) is provided on the second surface 20b side of the insulating layer 20. The insulating layer 20 is, for example, a silicon oxide layer having a thickness T2 of 300 nm (0.3 μm) to 600 nm (0.6 μm). The first semiconductor layer 30 is, for example, a silicon layer having a thickness T3 of 100 nm to 150 nm. The second semiconductor layer 70 is, for example, a silicon substrate.

[0090] 6, for convenience, the insulating layer 20 is illustrated as being thinner than the first semiconductor layer 30, but the relationship in thickness between the first semiconductor layer 30 and the insulating layer 20 is not limited to the illustrated form. The same applies to the relationship in thickness between the first semiconductor layer 30 and the insulating layer 20 in the following FIGS. 7 to 14.

[0091] A silicon oxide film (not shown) having a thickness of 7 nm to 14 nm is formed on the surface of the first semiconductor layer 30 of such an SOI substrate by hydrochloric acid oxidation at a temperature of 900°C to 1000°C. A resist 400 is formed thereon, as shown in FIG. 6. The resist 400 is formed by exposure using a mask with openings in predetermined regions and subsequent development. Using the resist 400 as a mask, the silicon oxide film is anisotropically etched with a trifluoromethane (CHF3) / tetrafluoromethane (CF4)-based mixed gas. Furthermore, using the resist 400 and the etched silicon oxide film as masks, the first semiconductor layer 30 is anisotropically etched to a depth of approximately 50 nm to 70 nm with a chlorine (Cl2)-based gas. As a result, a first groove 401 for defining the device region 300 and the heat sink region 301, and a second groove 402 for defining the alignment mark region 302, as shown in FIG. 6, are formed.

[0092] After the first groove 401 and the second groove 402 are formed, the resist 400 is removed by ashing, leaving the silicon oxide film formed on the surface of the first semiconductor layer 30. FIG. 7 is a diagram illustrating an example of a deep well layer forming step.

[0093] 7, a resist 403 is formed on the first semiconductor layer 30 (the silicon oxide film remaining on its surface) etched as described above. The resist 403 has an opening in the region where the deep well layer 16 is to be formed. The resist 403 is formed by photolithography using the second groove 402 formed in the alignment mark region 302 for alignment.

[0094] Using the formed resist 403 as a mask, n-type impurities, for example, phosphorus (P), are ion-implanted to form an n-type deep well layer 16 in the lower layer portion of the first semiconductor layer 30, as shown in FIG. 7. As an example, when the acceleration energy is 1.5 MeV or more and 2.5 MeV or less, and the implantation amount (dose amount) is 4.5×10 12 cm -2 Over 5.5 x 10 12 cm -2 Phosphorus ions are implanted under the following conditions to form the n-type deep well layer 16.

[0095] After the deep well layer 16 is formed, the resist 403 is removed by ashing. FIG. 8 is a diagram illustrating an example of the second etching step. After the deep well layer 16 is formed, a silicon oxide film (not shown) having a thickness of 7 nm to 14 nm is formed on the surface of the first semiconductor layer 30 by hydrochloric acid oxidation at a temperature of 900° C. to 1000° C. A silicon nitride film 404 having a thickness of 100 nm to 150 nm is formed on the silicon oxide film by a CVD (Chemical Vapor Deposition) method, as shown in FIG. 8. Furthermore, a resist (not shown) is formed on the silicon nitride film 404.

[0096] Next, the formed resist is exposed using a mask having openings for forming an isolation layer pattern, and then developed after exposure. Then, using the developed resist as a mask, the silicon nitride film 404 and the silicon oxide film are anisotropically etched with a trifluoromethane / tetrafluoromethane-based mixed gas.

[0097] Next, the resist is removed by ashing. Using the silicon nitride film 404 remaining after the resist removal as a mask, the first semiconductor layer 30 is selectively anisotropically etched with a chlorine-based gas until the insulating layer 20 is exposed. As a result, as shown in FIG. 8 , a groove 405 defining the first semiconductor layer 30 in the device region 300 is formed, and a first thermal conductive portion 40 is formed in the groove 405, separated from the first semiconductor layer 30. Furthermore, a second thermal conductive portion 80 connected to the first thermal conductive portion 40 is formed in the heat sink region 301. For example, the first thermal conductive portion 40 is formed to surround the entire periphery of the first semiconductor layer 30 in the device region 300 defined by the groove 405 in a plan view, and the second thermal conductive portion 80 is formed to be connected to a portion of the first thermal conductive portion 40. Furthermore, an alignment mark 406 is formed in the alignment mark region 302.

[0098] The trenches 405 include a trench for forming a first element isolation layer 50 and a trench for forming a second element isolation layer 60, which will be described later. The first heat conducting member 40 has a third surface 40a which is a side surface facing the first semiconductor layer 30 of the device region 300, and a fourth surface 40b which is an upper surface. The groove 405 includes a first groove portion 405a which separates the first semiconductor layer 30 of the device region 300 from the third surface 40a of the first heat conducting member 40. The groove 405 further includes a second groove portion 405b which is provided on the side opposite to the insulating layer 20 side of the first groove portion 405a, communicates with the first groove portion 405a, and extends closer to the first semiconductor layer 30 of the device region 300 than the first groove portion 405a.

[0099] The width between the first semiconductor layer 30 in the device region 300 and the third surface 40a of the first thermal conductive member 40, i.e., the width W1 of the first groove 405a (corresponding to the thickness T1 of the first portion 51 of the first element isolation layer 50, which will be described later), is set to 0.15 μm to 0.2 μm. The width W1 of the first groove 405a is set to be smaller than the thickness T2 of the insulating layer 20, which is 0.3 μm (300 nm) to 0.6 μm (600 nm). The width of the first groove 401 described in the step of FIG. 6 is adjusted so that the first groove 405a having such width W1 is formed after etching.

[0100] The fourth surface 40b of the first thermal conductive member 40 is located at the bottom of the second groove 405b. The height H1 of the bottom of the second groove 405b from the first surface 20a, i.e., the height H1 of the fourth surface 40b of the first thermal conductive member 40 from the first surface 20a, is smaller than the height H2 of the fifth surface 30a of the first semiconductor layer 30 opposite the insulating layer 20 side from the first surface 20a. The second groove 405b and the first thermal conductive member 40 are formed by etching so as to have such height H1.

[0101] The bottom of the second groove portion 405b of the groove 405 becomes a sixth surface 50a of the second portion 52 of the first element isolation layer 50, which will be described later. The bottom of the groove 405 that does not communicate with the first groove portion 405a becomes a seventh surface 60a of the second element isolation layer 60, which will be described later.

[0102] Furthermore, alignment mark 406 has an eighth surface 406a that serves as its upper surface. Eighth surface 406a is located at the bottom of second groove 405b. For example, the height of eighth surface 406a from first surface 20a is the same as the height H1 of the bottom of second groove 405b from first surface 20a, i.e., the height H1 of fourth surface 40b of first thermal conductive member 40 from first surface 20a. For example, second groove 405b, first thermal conductive member 40, and alignment mark 406 are formed by etching so as to have such height H1.

[0103] It should be noted that, not limited to the above example, the groove 405 does not necessarily need to be formed so that the heights of the fourth surface 40b of the first heat conducting portion 40 and the eighth surface 406a of the alignment mark 406 relative to the first surface 20a of the insulating layer 20 are the same.

[0104] FIG. 9 is a diagram illustrating an example of an element isolation layer forming step. A silicon oxide film (not shown) having a thickness of 7 nm to 14 nm is formed on the surface of the first semiconductor layer 30 etched as described above by thermal oxidation at a temperature of 1050°C to 1150°C. A silicon oxide film having a thickness of 250 nm to 400 nm is further formed on the silicon oxide film by a CVD method, thereby filling the trenches 405. The silicon oxide film formed to fill the trenches 405 is polished until the silicon nitride film 404 is exposed. As a result, the first element isolation layer 50 and the second element isolation layer 60 as shown in FIG. 9 are formed.

[0105] The formed first element isolation layer 50 fills the first groove portion 405a and the second groove portion 405b of the groove 405 and covers the third surface 40a and the fourth surface 40b of the first heat conduction member 40. A first portion 51 of the first element isolation layer 50 is formed in the first groove portion 405a, and a second portion 52 of the first element isolation layer 50 is formed in the second groove portion 405b. A thickness T1 (corresponding to the width W1 of the first groove portion 405a) of the first portion 51 of the first element isolation layer 50 is smaller than a thickness T2 of the insulating layer 20. A bottom of the second portion 52 of the first element isolation layer 50 becomes a sixth surface 50a of the first element isolation layer 50. A bottom of the second element isolation layer 60 becomes a seventh surface 60a of the second element isolation layer 60. A part of the first semiconductor layer 30 is interposed between the sixth surface 50a and the first surface 20a and between the seventh surface 60a and the sixth surface 50a and the seventh surface 60a, respectively, and the part is in contact with the sixth surface 50a and the seventh surface 60a.

[0106] For example, the heights of the sixth surface 50a of the first element isolation layer 50 and the seventh surface 60a of the second element isolation layer 60 from the first surface 20a of the insulating layer 20 are the same as the height H1 of the fourth surface 40b of the first heat conducting portion 40 from the first surface 20a. For example, the formation of the grooves 405 by etching, as described in the step of FIG. 8 above, is performed so as to form the first element isolation layer 50 and the second element isolation layer 60 having such sixth surfaces 50a and seventh surfaces 60a, respectively.

[0107] After the first element isolation layer 50 and the second element isolation layer 60 are formed, the silicon nitride film 404 is removed by boiling phosphoric acid solution. It should be noted that, without being limited to the above example, the first thermally conductive member 40, the first element isolation layer 50, and the second element isolation layer 60 do not necessarily need to have the fourth surface 40b, the sixth surface 50a, and the seventh surface 60a thereof aligned with the first surface 20a of the insulating layer 20. In other words, without being limited to the above example, the groove 405 does not necessarily need to be formed so that the fourth surface 40b, the sixth surface 50a, and the seventh surface 60a thereof aligned with the first surface 20a of the insulating layer 20.

[0108] FIG. 10 is a diagram illustrating an example of a body region forming step. After the first element isolation layer 50 and the second element isolation layer 60 are formed and the silicon nitride film 404 is removed, a resist 407 having an opening in the region where the body region 11 of the first semiconductor layer 30 is to be formed is formed, as shown in FIG. 10.

[0109] Using the formed resist 407 as a mask, p-type impurities, for example, boron (B), are ion-implanted to form a p-type body region 11 in the first semiconductor layer 30, as shown in FIG. 10. For example, when the acceleration energy is 100 keV or more and 200 keV or less, and the implantation amount is 1.0×10 12 cm -2 Over 3.0 x 10 13 cm -2 Boron ions are implanted under the following conditions to form the p-type body region 11.

[0110] Furthermore, to control the threshold voltage of the transistor, ion implantation of p-type impurities may be further performed on the body region 11. For example, to control the threshold voltage, the acceleration energy is 5 keV or more and 30 keV or less, and the implantation amount is 9.5×10 12 cm -2 Over 1.05 x 10 13 cm -2 Boron ions are implanted under the following conditions:

[0111] After the body region 11 is formed, the resist 407 is removed by ashing. FIG. 11 is a diagram illustrating an example of the drift region forming step. After the body region 11 is formed, a resist 408 having an opening in the region where the drift region 12 of the first semiconductor layer 30 is to be formed is formed, as shown in FIG.

[0112] Using the resist 408 as a mask, n-type impurities such as phosphorus or arsenic (As) are ion-implanted to form an n-type drift region 12 in the first semiconductor layer 30, as shown in FIG. 11. For example, the acceleration energy is 0.5 MeV or more and 1.0 MeV or less, and the implantation dose is 4.5×10 12 cm -2 Over 5.5 x 10 12 cm -2 Phosphorus ions are implanted under the following conditions to form the n-type drift region 12.

[0113] After the drift region 12 is formed, the resist 408 is removed by ashing. FIG. 12 is a diagram illustrating an example of a gate electrode formation step. After the drift region 12 is formed, the silicon oxide film is removed by wet etching using hydrofluoric acid. Then, as shown in Fig. 12, a gate insulating film 17 is formed on the exposed surface of the first semiconductor layer 30 (body region 11 and drift region 12) in the device region 300 by thermal oxidation. The thickness of the gate insulating film 17 is, for example, 12 nm or more and 25 nm or less.

[0114] After the gate insulating film 17 is formed, a polysilicon film is deposited by CVD. The thickness of the polysilicon film is, for example, 100 nm or more and 200 nm or less. After the polysilicon film is formed, a resist 409 is formed on the polysilicon film by photolithography, and the polysilicon film is patterned by dry etching using the resist 409 as a mask. This forms the gate electrode 18.

[0115] The gate electrode 18 is formed so as to overlap, in plan view, the first semiconductor layer 30 and the second element isolation layer 60. Furthermore, the gate electrode 18 is formed so as to overlap, in plan view, the first thermal conduction portion 40, for example, as shown in FIG.

[0116] After the gate electrode 18 is formed, the resist 409 is removed by ashing. In addition to the gate electrode 18, wiring connected to or separated from the gate electrode 18 may be formed on the first element isolation layer 50. Alternatively, a resistor or a part thereof, a capacitor or a part thereof, or an inductor or a part thereof may be formed on the first element isolation layer 50. Various circuit elements such as electrodes including the gate electrode 18, wiring, resistors, capacitors, and inductors may be formed so as to overlap the first thermal conductive section 40 in a planar view.

[0117] FIG. 13 is a diagram illustrating an example of a step of forming an impurity region and a contact. After the gate electrode 18 is formed, a sidewall insulating film 17a is formed on the sidewall of the gate electrode 18 using a silicon oxide film or the like, as shown in FIG.

[0118] Next, n-type impurities such as phosphorus or arsenic are ion-implanted into the first semiconductor layer 30 of the device region 300, and as shown in FIG. 13, n-type source regions 14 and drain regions 15 are formed in the surface layer portions of the body region 11 and the drift region 12, respectively. As an example, the acceleration energy is 12 keV or more and 18 keV or less, and the implantation dose is 2.0×10 15 cm -2 Over 6.0 x 10 15 cm -2 Phosphorus ions are implanted under the following conditions to form n-type source region 14 and drain region 15.

[0119] Furthermore, p-type impurities such as boron are ion-implanted into the surface layer of the body region 11 to form a p-type body contact region 13 as shown in FIG. 13. For example, the acceleration energy is 4 keV or more and 10 keV or less, and the implantation dose is 1.0×10 15 cm -2 Over 4.0 x 10 15 cm -2 Boron ions are implanted under the following conditions to form the p-type body contact region 13.

[0120] After the ion implantation, a heat treatment is performed in an inert gas atmosphere to activate the impurities implanted into the body contact region 13, the source region 14, and the drain region 15. For example, a metal silicide layer (shown in the figure) is formed on the surface portions of the body contact region 13, the source region 14, and the drain region 15.

[0121] After the body contact region 13, the source region 14, and the drain region 15 are formed, an interlayer insulating film 410 is deposited as shown in Fig. 13. Then, openings leading to predetermined locations such as the body contact region 13, the source region 14, the drain region 15, the gate electrode 18 (not shown), and the second thermal conductive portion 80 are formed in the interlayer insulating film 410, and the openings are filled with a conductive material such as tungsten to form contacts 19 as shown in Fig. 13.

[0122] FIG. 14 is a diagram illustrating an example of a wiring layer forming step. 14, after the body contact region 13, the source region 14, the drain region 15, the interlayer insulating film 410, and the contacts 19 are formed, an interlayer insulating film 410 is further deposited. Then, a wiring layer 411 made of a conductive material such as copper (Cu) is formed on the interlayer insulating film 410 by, for example, a damascene method. The wiring layer 411 is connected to the contacts 19 formed in the device region 300 and the heat sink region 301.

[0123] Through the steps described above, the semiconductor device 1 including the n-type LDMOS transistor 10 is manufactured. Here, the manufacturing method has been described using an example in which the semiconductor device 1 includes an n-type LDMOS transistor 10. However, the p-type impurities and n-type impurities in the above example can be interchanged to similarly manufacture a semiconductor device 1 including a p-type LDMOS transistor 10.

[0124] As described above, in the semiconductor device 1, heat generated in the LDMOS transistor 10 in the device region 300 is easily propagated to the first heat conductive portion 40 via the first portion 51 of the first element isolation layer 50, which is relatively thin compared to the insulating layer 20. The heat propagated to the first heat conductive portion 40 is dissipated through the second heat conductive portion 80 connected to the first heat conductive portion 40 in the heat sink region 301, and further through the contact 19 and wiring layer 411 connected thereto. This suppresses deterioration of the driving capability of the LDMOS transistor 10 due to self-heating.

[0125] Furthermore, in the semiconductor device 1, the LDMOS transistor 10 is surrounded by the insulating layer 20 and the first element isolation layer 50, and the insulating layer 20 can be made relatively thick, so that a decrease in the breakdown voltage is suppressed.

[0126] Furthermore, since the first heat conducting section 40 is covered with the first element isolation layer 50, the degree of freedom in layout of the various circuit elements provided on the first element isolation layer 50 is prevented from decreasing. According to the above manufacturing method, it is possible to realize a semiconductor device 1 that has a high degree of freedom in the layout of circuit elements, that suppresses performance degradation due to self-heating, and that suppresses a decrease in breakdown voltage.

[0127] While the manufacturing method of the semiconductor device 1 described in the first embodiment has been taken as an example here, an example such as the fifth embodiment can also be used to manufacture a semiconductor device 1A (FIG. 3) that includes a MOS transistor 10A instead of the LDMOS transistor 10, as described in the second embodiment. Also, an example such as the fifth embodiment can also be used to manufacture a semiconductor device 1B (FIG. 4) that has a first thermal conductive portion 40 that does not surround the entire periphery of the first semiconductor layer 30 in a plan view, as described in the third embodiment. Also, an example such as the fifth embodiment can also be used to manufacture a semiconductor device 1C in which the LDMOS transistor 10 and a CMOS transistor 200 are integrated, as described in the fourth embodiment.

[0128] The following additional notes are provided regarding the above-described embodiment. (Supplementary Note 1) An insulating layer having a first surface and a second surface opposite to the first surface; a first semiconductor layer provided on the first surface side of the insulating layer; a first thermal conduction portion provided on the first surface side of the insulating layer and separated from the first semiconductor layer, the first thermal conduction portion having a third surface facing a first direction parallel to the first surface and facing the first semiconductor layer, and a fourth surface facing a second direction perpendicular to the first direction and spaced apart from the first surface; a first element isolation layer provided on the first surface side of the insulating layer so as to define the first semiconductor layer and covering the third surface and the fourth surface of the first thermal conductive part; Including, A semiconductor device, wherein the thickness of a first portion of the first element isolation layer between the first semiconductor layer and the third surface is smaller than the thickness of the insulating layer between the first surface and the second surface.

[0129] (Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein the first heat conduction portion surrounds the entire periphery of the first semiconductor layer in a plan view. (Appendix 3) The semiconductor device described in Appendix 1, wherein the height of the fourth surface from the first surface is lower than the height of a fifth surface of the first semiconductor layer opposite the insulating layer side from the first surface.

[0130] (Supplementary Note 4) The semiconductor device according to Supplementary Note 1, further comprising a second heat conduction portion provided in the first element isolation layer, connected to the first heat conduction portion, and having a portion extending outside the first element isolation layer. (Supplementary Note 5) The semiconductor device according to Supplementary Note 1, further comprising a second semiconductor layer provided on the second surface side of the insulating layer.

[0131] (Supplementary Note 6) The semiconductor device according to Supplementary Note 5, wherein the second semiconductor layer is connected to a ground potential. (Supplementary Note 7) The semiconductor device according to Supplementary Note 1, wherein the first heat conduction portion is electrically floating.

[0132] (Supplementary Note 8) The semiconductor device according to Supplementary Note 1, wherein the first heat conducting portion is in contact with the first surface. (Supplementary Note 9) The semiconductor device according to Supplementary Note 1, wherein the first heat conduction section and the first semiconductor layer have their respective surfaces facing the insulating layer positioned in the same plane parallel to the first surface.

[0133] (Supplementary Note 10) The semiconductor device according to Supplementary Note 1, wherein the first thermal conductive portion is made of the same semiconductor material as the first semiconductor layer. (Appendix 11) The semiconductor device described in Appendix 1, wherein the first element isolation layer has a second portion extending toward the first semiconductor layer side more than the first portion, the second portion having a sixth surface facing the insulating layer side and spaced apart from the first surface, a portion of the first semiconductor layer being interposed between the sixth surface and the first surface, and the portion being in contact with the sixth surface.

[0134] (Supplementary Note 12) The semiconductor device according to Supplementary Note 11, wherein the height of the sixth surface from the first surface is the same as the height of the fourth surface from the first surface. (Appendix 13) The semiconductor device described in Appendix 1 includes a second element isolation layer provided within the first semiconductor layer, having a seventh surface facing the insulating layer and spaced apart from the first surface, with a portion of the first semiconductor layer interposed between the seventh surface and the first surface, and the portion in contact with the seventh surface.

[0135] (Supplementary Note 14) The semiconductor device according to Supplementary Note 13, wherein the height of the seventh surface from the first surface is the same as the height of the fourth surface from the first surface. (Appendix 15) The semiconductor device according to Appendix 13, further comprising a gate electrode provided on the side of the first semiconductor layer opposite the insulating layer side, the gate electrode overlapping the first semiconductor layer and the second element isolation layer in a planar view.

[0136] (Supplementary Note 16) The semiconductor device according to Supplementary Note 1, further comprising: a circuit element provided on the side of the first element isolation layer opposite to the insulating layer side, the circuit element overlapping the first heat conduction portion in a plan view. (Supplementary Note 17) The semiconductor device according to Supplementary Note 16, wherein the circuit element is at least one of an electrode, a wiring, a resistor, a capacitor, and an inductor.

[0137] (Appendix 18) The semiconductor device described in Appendix 1, including an alignment mark provided on the first surface side of the insulating layer, having an eighth surface whose height from the first surface is the same as the height of the fourth surface from the first surface.

[0138] (Supplementary Note 19) A method for manufacturing a semiconductor device comprising: forming a first semiconductor layer on an insulating layer having a first surface and a second surface opposite to the first surface; forming a first thermal conduction portion on the first surface side of the insulating layer, the first thermal conduction portion being separated from the first semiconductor layer, the first thermal conduction portion having a third surface facing a first direction parallel to the first surface and facing the first semiconductor layer, and a fourth surface facing a second direction perpendicular to the first direction and spaced apart from the first surface; forming a first element isolation layer on the first surface side of the insulating layer so as to define the first semiconductor layer and cover the third surface and the fourth surface of the first thermal conductive part; Including, A method for manufacturing a semiconductor device, wherein the thickness of a first portion of the first element isolation layer between the first semiconductor layer and the third surface is smaller than the thickness of the insulating layer between the first surface and the second surface.

[0139] (Appendix 20) A method for manufacturing a semiconductor device according to Appendix 19, wherein the step of forming the first thermal conduction portion includes a step of forming the first thermal conduction portion so as to surround the entire periphery of the first semiconductor layer in a planar view.

[0140] (Supplementary Note 21) The step of forming the first thermally conductive portion includes the steps of: etching a semiconductor material provided on the first surface side of the insulating layer to form a groove that defines the first semiconductor layer; and forming the first thermally conductive portion in the groove so as to be separated from the first semiconductor layer; 20. The method for manufacturing a semiconductor device according to claim 19, wherein the step of forming the first element isolation layer includes the step of forming the first element isolation layer in the trench to cover the first heat conduction portion.

[0141] (Appendix 22) A method for manufacturing a semiconductor device according to Appendix 21, wherein the step of forming the first thermal conductive portion in the groove includes a step of forming the first thermal conductive portion so that the height of the fourth surface from the first surface is lower than the height of a fifth surface of the first semiconductor layer opposite the insulating layer side from the first surface.

[0142] (Supplementary Note 23) The step of forming the groove includes: forming a first groove separating the first semiconductor layer from the third surface; forming a second groove portion provided on the opposite side of the first groove portion from the insulating layer side, communicating with the first groove portion, and extending further toward the first semiconductor layer than the first groove portion; Including, In the step of forming the first element isolation layer, The first portion is formed in the first groove portion, 22. The method for manufacturing a semiconductor device described in Appendix 21, wherein a second portion is formed in the second groove portion, the second portion having a sixth surface facing the insulating layer and spaced apart from the first surface, a portion of the first semiconductor layer being interposed between the sixth surface and the first surface, and the portion being in contact with the sixth surface.

[0143] (Appendix 24) A method for manufacturing a semiconductor device according to Appendix 19, comprising forming a second thermal conduction portion within the first element isolation layer, the second thermal conduction portion being connected to the first element isolation layer and having a portion extending outside the first element isolation layer.

[0144] (Appendix 25) A method for manufacturing a semiconductor device according to Appendix 19, comprising the step of forming a second element isolation layer within the first semiconductor layer, the second element isolation layer having a seventh surface facing the insulating layer and spaced apart from the first surface, a portion of the first semiconductor layer interposed between the seventh surface and the first surface, and the portion in contact with the seventh surface.

[0145] (Appendix 26) A method for manufacturing a semiconductor device according to Appendix 25, comprising forming a gate electrode on the side of the first semiconductor layer opposite the insulating layer side, the gate electrode overlapping the first semiconductor layer and the second element isolation layer in a planar view.

[0146] (Appendix 27) A method for manufacturing a semiconductor device according to Appendix 19, comprising forming a circuit element on the side of the first element isolation layer opposite the insulating layer side, the circuit element overlapping the first heat conduction portion in a planar view.

[0147] (Supplementary Note 28) The method for manufacturing a semiconductor device according to Supplementary Note 27, wherein the circuit element is at least one of an electrode, a wiring, a resistor, a capacitor, and an inductor. (Appendix 29) A method for manufacturing a semiconductor device according to Appendix 19, comprising forming an alignment mark on the first surface side of the insulating layer, the alignment mark having an eighth surface whose height from the first surface is the same as the height of the fourth surface from the first surface. [Explanation of symbols]

[0148] 1, 1A, 1B, 1C Semiconductor Device 10 LDMOS transistors 10A MOS transistor 11 Body Region 12 Drift Region 13 Body Contact Area 14, 14A Source Region 15, 15A drain area 16 Deep well layer 17, 17A Gate insulating film 17a, 17Aa Sidewall insulating film 18, 18A gate electrode 18a, 250a, 260 wiring 19 Contacts 20 insulating layer 20a Page 1 20b 2nd side 30 First semiconductor layer 30a 5th page 40 First heat conduction section 40a Page 3 40b Side 4 40c side 50 First element isolation layer 50a Side 6 51 Part 1 52 Part 2 60 Second element isolation layer 60a Page 7 70 Second semiconductor layer 80 Second heat conduction section 100, 100A heat 200 CMOS transistors 200n nMOS transistor 200p pMOS transistor 210n n-type source region 210p p-type source region 220n n-type drain region 220p p-type drain region 230n n-type body region 230p p-type body region 240 Separate Gate 250 gate electrode 300 device regions 301 Heat sink area 302 Alignment mark area 400, 403, 407, 408, 409 Resist 401 First groove 402 2nd groove 404 Silicon nitride film 405 Groove 405a First groove 405b Second groove 406 Alignment Mark 406a Side 8 410 Interlayer insulating film 411 Wiring layer D1 1st direction D2 2nd direction H1, H2 height T1, T2, T3 thickness W1 width

Claims

1. an insulating layer having a first surface and a second surface opposite the first surface; a first semiconductor layer provided on the first surface side of the insulating layer; a first thermal conduction portion provided on the first surface side of the insulating layer and separated from the first semiconductor layer, the first thermal conduction portion having a third surface facing a first direction parallel to the first surface and facing the first semiconductor layer, and a fourth surface facing a second direction perpendicular to the first direction and spaced apart from the first surface; a first element isolation layer provided on the first surface side of the insulating layer so as to define the first semiconductor layer and covering the third surface and the fourth surface of the first thermal conductive part; Including, a thickness of a first portion of the first element isolation layer between the first semiconductor layer and the third surface is smaller than a thickness of the insulating layer between the first surface and the second surface;

2. 2 . The semiconductor device according to claim 1 , wherein a height of the fourth surface from the first surface is lower than a height of a fifth surface of the first semiconductor layer opposite to the insulating layer side from the first surface.

3. 2. The semiconductor device according to claim 1, further comprising a second heat conduction portion provided in said first element isolation layer, connected to said first heat conduction portion, and having a portion extending outside said first element isolation layer.

4. The semiconductor device according to claim 1 , wherein said first heat conducting portion is electrically floating.

5. 2. The semiconductor device according to claim 1, wherein the first element isolation layer has a second portion extending toward the first semiconductor layer side more than the first portion, the second portion having a sixth surface facing the insulating layer side and spaced apart from the first surface, a portion of the first semiconductor layer being interposed between the sixth surface and the first surface, and the portion being in contact with the sixth surface.

6. 2. The semiconductor device according to claim 1, further comprising: a second element isolation layer provided within the first semiconductor layer, the second element isolation layer having a seventh surface facing the insulating layer and spaced apart from the first surface, a portion of the first semiconductor layer interposed between the seventh surface and the first surface, the portion of the first semiconductor layer being in contact with the seventh surface.

7. The semiconductor device according to claim 1 , further comprising a circuit element provided on the side of said first element isolation layer opposite said insulating layer side and overlapping said first heat conducting portion in a plan view.

8. forming a first semiconductor layer on the first surface side of an insulating layer having a first surface and a second surface opposite to the first surface; forming a first thermal conduction portion on the first surface side of the insulating layer, the first thermal conduction portion being separated from the first semiconductor layer, the first thermal conduction portion having a third surface facing a first direction parallel to the first surface and facing the first semiconductor layer, and a fourth surface facing a second direction perpendicular to the first direction and spaced apart from the first surface; forming a first element isolation layer on the first surface side of the insulating layer so as to define the first semiconductor layer and cover the third surface and the fourth surface of the first thermal conductive part; Including, a thickness of a first portion of the first element isolation layer between the first semiconductor layer and the third surface is smaller than a thickness of the insulating layer between the first surface and the second surface.

9. the step of forming the first thermally conductive portion includes a step of forming a groove that defines the first semiconductor layer by etching a semiconductor material provided on the first surface side of the insulating layer, and forming the first thermally conductive portion that is provided in the groove and separated from the first semiconductor layer, 9. The method for manufacturing a semiconductor device according to claim 8, wherein the step of forming the first element isolation layer includes the step of forming the first element isolation layer in the trench to cover the first heat conduction portion.

10. 9. The method for manufacturing a semiconductor device according to claim 8, further comprising forming, in said first element isolation layer, a second heat conduction portion connected to said first heat conduction portion and having a portion extending outside said first element isolation layer.

11. 9. The method for manufacturing a semiconductor device according to claim 8, further comprising forming a circuit element that overlaps with said first heat conducting portion in a plan view on a side of said first element isolation layer opposite said insulating layer side.

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