Display and source driver

Abstract

To provide a display that can accurately detect a failure in a display panel, while preventing an increase in a device scale.SOLUTION: A plurality of source lines include a first source line and a second source line configured to be short-circuited to each other at the other ends. A source driver charges the first source line and the second source line in a state in which the first source line and the second source line are short-circuited via the other ends, and an output end of a first output amplifier, of a plurality of output amplifiers, which outputs a pixel drive voltage to the first source line is connected to the first source line, and subsequently, in a state in which a second input end of the first output amplifier and one end of the second source line are connected to each other, outputs a result of comparison between a voltage input to a first input end and a voltage input to the second input end performed by the first output amplifier.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a display device and a source driver. [Background technology]

[0002] In recent years, display panels such as liquid crystal display panels and organic EL (Electro Luminescence) display panels have been adopted as in-vehicle display panels for displaying navigation displays and various instruments. If a malfunction occurs in such an in-vehicle display panel while the vehicle is traveling and an incorrect display is displayed, it may cause a disruption to driving. In particular, display panels that display safety-critical information such as warning lights need to be quickly detected when a malfunction occurs.

[0003] Therefore, in order to check whether a fault has occurred in a display panel during operation, a liquid crystal display device has been proposed that is equipped with a fault inspection circuit that supplies a monitor input signal to one end of each of a plurality of source lines and compares the monitor output signal output from the other end of each line with a predetermined expected value, thereby detecting short and open abnormalities in the source lines (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] WO2018 / 079636 publication Summary of the Invention [Problem to be solved by the invention]

[0005] The display devices of the above-mentioned prior art require a fault detection circuit separate from the source driver and gate driver, resulting in a large device scale. In addition, comparison with expected values ​​cannot detect minute short circuits or high resistance, resulting in low inspection accuracy.

[0006] The present invention has been made in view of the above problems, and has as its object to provide a display device and a source driver that are capable of detecting a fault in a display panel with high accuracy while suppressing an increase in the device scale. [Means for solving the problem]

[0007] A display device according to the present invention includes a display panel having a plurality of source lines and a plurality of gate lines, and a plurality of pixel units arranged in a matrix at each intersection of the plurality of source lines and the plurality of gate lines; a gate driver that supplies gate signals to the plurality of gate lines; and a source driver that includes a plurality of output amplifiers, each of which receives a grayscale voltage at a first input terminal and outputs a pixel drive voltage based on the grayscale voltage to one end of the plurality of source lines, and applies the pixel drive voltage to the plurality of pixel units by the plurality of output amplifiers, wherein the plurality of source lines are configured to be short-circuitable with each other at the other end. the source driver charges the first source line and the second source line in a state where the first source line and the second source line are short-circuited via the other end of each other and an output end of a first output amplifier among the plurality of output amplifiers, which outputs the pixel drive voltage to the first source line, is connected to the first source line, and then, in a state where a second input end of the first output amplifier is connected to one end of the second source line, the source driver outputs a comparison result by the first output amplifier between a voltage input to the first input end and a voltage input to the second input end.

[0008] Furthermore, a source driver according to the present invention is a source driver connected to a display panel having a plurality of source lines including a first source line and a second source line, each of which has one end configured to be short-circuited to each other, a plurality of gate lines, and a plurality of pixel units arranged in a matrix at each of intersections of the plurality of source lines and the plurality of gate lines, and outputs a pixel driving voltage to be applied to the plurality of pixel units, the source driver comprising a plurality of output amplifiers, each of which receives a gradation voltage at a first input terminal and outputs the pixel driving voltage based on the gradation voltage to the other end of the plurality of source lines, wherein the first source line and the second source line are short-circuited via their respective one ends, and an output terminal of a first output amplifier of the plurality of output amplifiers, which outputs the pixel driving voltage to the first source line, is connected to the first source line, and then, after charging the first source line and the second source line, the source driver outputs a comparison result by the first output amplifier between the voltage input to the first input terminal and the voltage input to the second input terminal, with the second input terminal of the first output amplifier connected to the other end of the second source line. [Effects of the Invention]

[0009] The source driver according to the present invention makes it possible to perform highly accurate fault detection of the display panel while suppressing an increase in the device size. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a block diagram showing a configuration of a display device according to an embodiment of the present invention; [Figure 2] 10 is an enlarged view showing a far end portion of a source line and a part of a failure detection wiring; FIG. [Figure 3] FIG. 2 is a circuit diagram showing adjacent source lines and output amplifiers of source drivers connected thereto. [Figure 4A] 10A and 10B are diagrams illustrating the states of the switches when the output amplifier of the source driver operates as a normal amplifier. [Figure 4B]10A and 10B are diagrams illustrating the states of switches when the output amplifier of the source driver operates as a comparator. [Figure 5] FIG. 10 is a diagram illustrating switch control during normal operation. [Figure 6] FIG. 10 is a diagram illustrating switch control during discharge in the disconnection detection operation. [Figure 7] FIG. 10 is a diagram illustrating switch control during charging in a disconnection detection operation. [Figure 8] 10A and 10B are diagrams illustrating switch control upon detection in a disconnection detection operation. [Figure 9] 10 is a time chart showing changes in each signal during a disconnection detection operation. [Figure 10] FIG. 10 is a diagram showing the configuration of source lines and switches when the display panel is a source multiplex panel. [Figure 11] 10A and 10B are diagrams illustrating the states of switches during charging in a disconnection detection operation in a source multiplex panel. [Figure 12] 10A and 10B are diagrams illustrating the states of switches when a disconnection is detected in a source multiplex panel. [Figure 13] 10A and 10B are diagrams illustrating the states of the switches when measuring the discharge time in the load abnormality detection operation. [Figure 14] 10A and 10B are diagrams illustrating switch states during adjacent short-circuit detection operation. DETAILED DESCRIPTION OF THE INVENTION

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail. In the following description of the embodiments and the accompanying drawings, substantially the same or equivalent parts are designated by the same reference numerals.

[0012] 1 is a block diagram showing the configuration of a display device 100 according to a first embodiment of the present invention. The display device 100 is an active matrix liquid crystal display device. The display device 100 includes a display panel 11, a display controller 12, a gate driver 13, and a source driver 14.

[0013] The display panel 11 is composed of a semiconductor substrate on which a plurality of pixel units P11 to Pnm and pixel switches M11 to Mnm (n is an integer of 2 or greater, and m is an integer of 2 or greater) are arranged in a matrix of n rows and m columns. The display panel 11 has n gate lines GL1 to GLn which are horizontal scanning lines, and m source lines SL1 to SLm which are arranged orthogonally to intersect the gate lines GL1 to GLn. The pixel units P11 to Pnm and pixel switches M11 to Mnm are provided at the intersections of the gate lines GL1 to GLn and the source lines SL1 to SLm, and are arranged in a matrix.

[0014] The pixel switches M11 to Mnm are controlled to be on or off in response to gate signals Vg1 to Vgn supplied from the gate driver 13. The pixel units P11 to Pnm are supplied with pixel drive voltage signals Vd1 to Vdm corresponding to video data from the source driver 14. When the pixel switches M11 to Mnm are respectively on, the pixel drive voltage signals Vd1 to Vdm are applied to the pixel electrodes of the pixel units P11 to Pnm, and each pixel electrode is charged. The brightness of the pixel units P11 to Pnm is controlled in response to the pixel drive voltage signals Vd1 to Vdm at the pixel electrodes of the pixel units P11 to Pnm, and display is performed.

[0015] The display controller 12 receives the video signal VS and supplies a scan timing signal GS indicating the timing for applying a horizontal scan pulse to each scan line in response to the video signal VS to the gate driver 13. Furthermore, based on the video signal VS, the display controller 12 generates a video digital signal VD including various control signals FS and a series of display data fragments indicating the luminance level of each pixel, and supplies this to the source driver 14.

[0016] The gate driver 13 sequentially applies gate signals Vg1 to Vgn, which include horizontal scanning pulses synchronized with the scanning timing signal GS supplied from the display controller 12, to the gate lines GL1 to GLn of the display panel 11, respectively.

[0017] In response to the video digital signal VD, the source driver 14 first retrieves a series of display data fragments corresponding to each pixel included in the video digital signal VD, i.e., m fragments at a time equal to the number of source lines. Next, the source driver 14 converts each of the retrieved m display data fragments into a drive signal having an analog voltage value corresponding to the brightness level indicated by the display data fragment, and supplies the resulting m drive signals as pixel drive voltage signals Vd1 to Vdm to the source lines SL1 to SLm of the display panel 11. In the following description, one of the pixel drive voltage signals Vd1 to Vdm will be generalized and simply referred to as pixel drive voltage signal Vd.

[0018] Through the operation of the gate driver 13, m pixel units arranged along the extension direction of the gate lines (i.e., in a horizontal row) are selected as targets to which pixel drive voltage signals Vd1 to Vdm are supplied. The source drivers 14-1 to 14-k apply the pixel drive voltage signals Vd1 to Vdm to the selected pixel units in the horizontal row, causing them to display a color corresponding to the voltage. One frame of screen display is performed by selectively switching the pixel units in the horizontal row selected as targets to which pixel drive voltage signals Vd1 to Vdm are supplied, and repeating this process in the extension direction of the source lines (i.e., the vertical direction).

[0019] The display device 100 of this embodiment is provided with failure detection wiring FDL extending from the gate driver 13 in parallel with the gate lines GL1 to GLn. The failure detection wiring FDL is disposed close to the far ends of the source lines SL1 to SLm (i.e., the ends far from the source driver 14).

[0020] 2 is an enlarged view showing the far end portions of the source lines and a part of the failure detection wiring FDL, in which only the source lines SL1 to SL4 are extracted from the source lines SL1 to SLm and shown.

[0021] A switch ASW1 is provided between the end of source line SL1 and the end of source line SL2, and is configured to be switchable between connection and disconnection. That is, when the switch ASW1 is on (closed), the ends of source lines SL1 and SL2 are connected, i.e., short-circuited, and when the switch ASW1 is off (open), the ends are disconnected from each other.

[0022] Similarly, a switch ASW2 is provided between the end of source line SL3 and the end of source line SL4, and is configured to be switchable between connection and disconnection. That is, when switch ASW2 is on (closed), the ends of source lines SL3 and SL4 are connected, i.e., shorted, and when switch ASW2 is off (open), the ends are disconnected from each other.

[0023] The switches ASW1 and ASW2 are controlled to be turned on or off in response to a switching control signal SWC supplied from the gate driver 13 via the failure detection wiring FDL. The switching control signal SWC is, for example, a binary signal whose signal level changes between logical levels 1 and 0. The switches ASW1 and ASW2 are, for example, in an on state when the switching control signal SWC is at logical level 1 (high level) and in an off state when it is at logical level 0. Note that switches similar to the switches ASW1 and ASW2 are provided not only between the source lines SL1 and SL2 and between SL3 and SL4 but also between adjacent source lines SL(2k-1) and SL2k (k is a natural number). In the following description, these switches will be generalized and simply referred to as "switches ASW."

[0024] 3 is a circuit diagram showing the configuration of source lines SL1 and SL2 and an output circuit section including output amplifiers AP1 and AP2 that supply pixel drive voltage signals Vd to the source lines SL1 and SL2. Here, an example is shown in which, of the R, G, and B pixels, source line SL1 is responsible for displaying "R" pixels, and source line SL2 is responsible for displaying "G" pixels.

[0025] The output amplifier AP1 is a positive-polarity output amplifier, and the output amplifier AP2 is a negative-polarity output amplifier. The output amplifiers AP1 and AP2 are configured as voltage follower circuits made up of so-called operational amplifiers, with their output terminals connected to their inverting input terminals (-). The output amplifiers AP1 and AP2 amplify (by a factor of 1 in this embodiment) the analog grayscale voltages input to their non-inverting input terminals (+) and output them as pixel drive voltage signals Vd. The output amplifiers AP1 and AP2 are configured so that their output terminals can be switched between connected and disconnected from the source lines SL1 and SL2 via cross switches CSW.

[0026] The cross switch CSW is composed of switches S1s, S2s, S1x and S2x.

[0027] The switch S1s is provided between the output end of the output amplifier AP1 and an internal connection line L1 of the source driver 14, which is connected to the output terminal T1 of the source driver 14. When the switch S1s is turned on, the output end of the output amplifier AP1 is connected to the source line SL1 via the internal connection line L1 and the output terminal T1.

[0028] The switch S2s is provided between the output terminal of the output amplifier AP2 and an internal connection line L2 of the source driver 14, which is connected to the output terminal T2 of the source driver 14. When the switch S2s is turned on, the output terminal of the output amplifier AP2 is connected to the source line SL2 via the internal connection line L2 and the output terminal T2.

[0029] The switches S1x and S2x are provided on wiring that crosses and connects the output terminal of the output amplifier AP1 to the internal connection line L2 of the source driver 14, and the output terminal of the output amplifier AP2 to the internal connection line L1 of the source driver 14. That is, the switch S1x is provided between the output terminal of the output amplifier AP2 and the internal connection line L1 of the source driver 14. When the switch S1x is turned on, the output terminal of the output amplifier AP2 is connected to the source line SL1 via the internal connection line L1 and the output terminal T1. Furthermore, the switch S2x is provided between the output terminal of the output amplifier AP1 and the internal connection line L2 of the source driver 14. When the switch S2x is turned on, the output terminal of the output amplifier AP1 is connected to the source line SL2 via the internal connection line L2 and the output terminal T2.

[0030] Furthermore, switches S1D ​​and S2D are provided between the internal connection lines L1 and L2 of the source driver 14. One end of the switch S1D is connected to the internal connection line L1, and the other end is connected to a voltage supply line of a reference voltage VSS (ground potential in this embodiment). One end of the switch S2D is connected to the other end of the switch S1D and the voltage supply line of the reference voltage VSS, and the other end is connected to the internal connection line L2. When the switch S1D is turned on, the source line SL1 is connected to the voltage supply line of the reference voltage VSS via the output terminal T1 of the source driver 14 and the internal connection line L1. When the switch S2D is turned on, the source line SL2 is connected to the voltage supply line of the reference voltage VSS via the output terminal T2 of the source driver 14 and the internal connection line L2.

[0031] In this embodiment, the source driver 14 performs normal operations (hereinafter referred to as normal operations) to display images on the display panel 11, as well as operations (hereinafter referred to as break detection) to check whether any breaks have occurred in the source lines SL1 to SLm.

[0032] The output amplifiers AP1 and AP2 have switches connected to their output ends, and are configured to be switchable between a state in which they operate as output amplifiers in normal operation and a state in which they operate as comparators in disconnection detection.

[0033] FIG. 4A is a diagram showing the state of the output amplifier AP1 in normal operation, and FIG. 4B is a diagram showing the state of the output amplifier AP1 in disconnection detection.

[0034] Switches SWa and SWb are connected to the output terminal of the output amplifier AP1. The switch SWa is provided between the output terminal of the output amplifier AP1 and a signal output line LA that outputs the result of open circuit detection. The switch SWb is provided between the output terminal of the output amplifier AP1 and a node n1. The node n1 is connected to one end of each of the switches S1s and S2x, and is also connected to the inverting input terminal of the output amplifier AP1. The switches SWa and SWb are controlled to be turned on and off complementarily.

[0035] 4A, in the normal operation state, the switch SWa is controlled to be off and the switch SWb is controlled to be on. As a result, the output terminal of the output amplifier AP1 is connected to the node n1, and is connected to the source line SL1 or SL2 via the switch S1s or S2x. In addition, the output terminal of the output amplifier AP1 is feedback-connected to the inverting input terminal via the node n1, and the output amplifier AP1 operates as a normal output amplifier of a voltage follower.

[0036] On the other hand, as shown in Figure 4B, in the state where an open circuit is detected, the switch SWa is controlled to be on and the switch SWb is controlled to be off. As a result, the output terminal of the output amplifier AP1 is disconnected from the inverting input terminal and connected to the signal output line LA. The output amplifier AP1 operates as a comparator CP1 that compares the voltage input to its non-inverting input terminal with the voltage (signal) input to its inverting input terminal via node n1 and outputs the comparison result.

[0037] FIG. 5 is a diagram showing switch control between the output amplifiers AP1 and AP2 and the source lines SL1 and SL2 in normal operation.

[0038] As shown in the upper part of the diagram, in the straight polarity state, switches S1s and S2s are on, and switches S1x, S2x, S1D, and S2D are off. Also, switch ASW is off (open). As a result, the output terminal of output amplifier AP1 is connected to source line SL1, and a pixel drive voltage signal Vd is output from output amplifier AP1 to source line SL1. Also, the output terminal of output amplifier AP2 is connected to source line SL2, and a pixel drive voltage signal Vd is output from output amplifier AP2 to source line SL2.

[0039] On the other hand, as shown in the lower part of the figure, in the polarity cross state, switches S1x and S2x are on, and switches S1s, S2s, S1D, and S2D are off. Also, switch ASW is off (open). As a result, the output terminal of output amplifier AP1 is connected to source line SL2, and the pixel drive voltage signal Vd is output from output amplifier AP1 to source line SL2. Also, the output terminal of output amplifier AP2 is connected to source line SL1, and the pixel drive voltage signal Vd is output from output amplifier AP2 to source line SL1.

[0040] Next, the operation of the disconnection detection will be explained. The disconnection detection operation consists of three steps: "discharge," which is a step of discharging the charges of the source lines SL1 and SL2 to the voltage supply line of the reference voltage VSS; "charge," which is a step of charging the source lines SL1 and SL2 with the pixel drive voltage signal Vd from the output amplifier AP1; and "detection," which is a step of determining whether or not a disconnection has occurred in the source line SL1 or SL2.

[0041] 6 is a diagram showing the state of each switch and the flow of charge in the "discharge" step. The source driver 14 turns off all of the switches S1s, S2s, S1x, and S2x in accordance with the control of the display controller 12. The source driver 14 also turns on the switches ASW, S1D, and S2D.

[0042] As a result, the source lines SL1 and SL2 are connected to the voltage supply line of the reference voltage VSS. As shown by the dashed arrows in the figure, the charges on the source lines SL1 and SL2 flow toward the voltage supply line of the reference voltage VSS, causing discharge.

[0043] 7 is a diagram showing the state of each switch and the flow of charge in the step of “charging.” In response to the control of the display controller 12, the source driver 14 turns on the switch S1s and turns off the switches S1D ​​and S2D.

[0044] This causes the pixel drive voltage signal Vd to be output from the output amplifier AP1 to the source line SL1. Because the switch ASW is on (closed), the pixel drive voltage signal Vd from the output amplifier AP1 charges the source lines SL1 and SL2, as indicated by the dashed arrows in the figure.

[0045] 8 is a diagram showing the state of each switch and the flow of charge in the "detection" step. The source driver 14 turns off the switches S1s and S2s and turns on the switch S2x in accordance with the control of the display controller 12. The source driver 14 also controls the switch SWa connected to the output end of the output amplifier AP1 to turn on and the switch SWb to turn off, switching the state to operate as the comparator CP1 (i.e., the state shown in FIG. 4B).

[0046] As a result, the charge flowing from source line SL1 through SL2 is supplied to the second input terminal of comparator CP1 (the inverting input terminal of output amplifier AP1). Comparator CP1 compares the grayscale voltage input to its first input terminal (the non-inverting input terminal of output amplifier AP1) with the voltage input to its second input terminal (i.e., a voltage corresponding to the charge stored in source lines SL1 and SL2), and outputs the comparison result from its output terminal as a comparison result signal CV. Source driver 14 supplies comparison result signal CV to display controller 12.

[0047] The comparison result signal CV is a signal that has a signal level of, for example, logic level 1 (high level) when the two signals match, and logic level 0 (low level) when they do not match. When there is no open circuit in the source lines SL1 and SL2, the pixel drive voltage signal Vd output to the source line SL1 matches the voltage based on the charge that has been charged in the source line SL1 based on the pixel drive voltage signal Vd and that has moved (i.e., returned) through the source line SL2 to the inverting input terminal of the comparator CP1. Therefore, when there is no open circuit in the source lines SL1 and SL2, the comparison result signal CV has a logic level of 1.

[0048] On the other hand, if an open circuit occurs in the source line SL1 or SL2, the voltage input to the inverting input terminal of the comparator CP1 will be a voltage value different from the gradation voltage input to the non-inverting input terminal, and a comparison result signal CV with a logic level of 0 will be output.

[0049] Next, the operation of disconnection detection executed by the display device 100 of this embodiment will be described with reference to the time chart of FIG.

[0050] First, in the data period DP, the gate driver 13 and the source driver 14 perform normal operation to display an image based on the video digital signal VD on the display panel 11. At this time, the source driver 14 controls the switches S1s and S2s to be on and the switches S1x, S2x, S1D, and S2D to be off.

[0051] When the gate driver finishes supplying gate signals Vg1 to Vgn to the final line, i.e., when it finishes supplying gate signal Vgn to gate line GLn (shown as a pulse in the GLn row in the figure), the data period DP transitions to a V blank period VP. The V blank period VP is a vertical blanking period provided between when the gate driver 13 finishes scanning one frame and when it starts scanning the next frame. When the transition to the V blank period VBP begins, the source driver 14 turns off switches S1s and S2s.

[0052] The gate driver 13 outputs a switching control signal SWC of logic level 1 (high level) to the failure detection wiring FDL to turn on (close) the switch ASW. The source driver 14 turns on the switches S1D ​​and S2D. This results in the circuit state shown in Figure 6, and the source lines SL1 and SL2 are discharged.

[0053] The source driver 14 turns on the switch S1s and turns off the switches S1D ​​and S2D, resulting in the circuit state shown in Fig. 7, in which the source lines SL1 and SL2 are charged based on the pixel drive voltage signal Vd output from the output amplifier AP1.

[0054] The source driver 14 switches the switches SWa and SWb connected to the output terminal of the output amplifier AP1 (see FIG. 4B) to switch the output amplifier AP1 to a state where it operates as a comparator CP1. The source driver 14 turns on the switch S2x. This results in the circuit state shown in FIG.

[0055] If the gradation voltage input to the non-inverting input terminal matches the voltage input to the inverting input terminal (i.e., the voltage according to the charges on the source lines SL1 and SL2), the comparator CP1 outputs a comparison result signal CV with logic level 1 (high level), and if they do not match, with logic level 0. If there is no disconnection in the source lines SL1 and SL2, the comparison result signal CV with logic level 1 (high level) is output from the output terminal of the comparator CP1.

[0056] The gate driver 13 switches the switching control signal SWC to logic level 0 (low level) to turn the switch ASW off (open). The source driver 14 turns the switch S2x off. Thereafter, the source driver 14 turns the switches S1D ​​and S2D on, and turns them off again after a predetermined period of time has elapsed.

[0057] When the V-blank period VBP ends, the gate driver 13 and source driver 14 each return to normal operation. The gate driver 13 outputs a gate signal Vg1 to the gate line GL1. The source driver 14 turns on the switches S1x and S2x.

[0058] As described above, the display device 100 of this embodiment performs open circuit detection during the V blank period VBP, which is set between the timing of outputting the gate signal Vgn to the final line GLn of the gate lines and the timing of outputting the gate signal Vg1 to the first line GL1 of the gate lines.

[0059] In the display device 100 of this embodiment, two adjacent source lines are short-circuited, and disconnection detection is performed based on whether or not a pixel drive voltage signal Vd (charge based on the signal) output to one source line returns through the other source line. This type of disconnection detection operation allows for highly accurate disconnection detection, unlike when simply comparing the output from the other end of the source driver with an expected value.

[0060] Furthermore, in the display device 100 of this embodiment, there is no need to provide a separate fault inspection circuit outside the gate driver 13 or the source driver 14. Therefore, it is possible to detect disconnection while suppressing an increase in the device scale.

[0061] Next, a modification of this embodiment will be described.

[0062] FIG. 10 is a diagram showing a modified example of the connection configuration of the output amplifiers and source lines when the display panel 11 is a source multiplex panel (that is, when the display panel 11 is driven by multiplex driving of the source lines).

[0063] The source lines SL1, SL4, SL7 and SL10 are responsible for displaying "R" pixels, the source lines SL2, SL5, SL8 and SL11 are responsible for displaying "G" pixels, and the source lines SL3, SL6, SL9 and SL12 are responsible for displaying "B" pixels.

[0064] The output amplifiers AP1 and AP3 are positive-polarity output amplifiers. The output amplifiers AP2 and AP4 are negative-polarity output amplifiers. The output amplifiers AP1 and AP2 are configured to be switchable between connection and disconnection with the output terminals T1 and T2 of the source driver 14 via a cross switch CSW1. The output amplifiers AP3 and AP4 are configured to be switchable between connection and disconnection with the output terminals T3 and T4 of the source driver 14 via a cross switch CSW2. Note that the configurations of the cross switches CSW1 and CSW2 are similar to those of the cross switch CSW in the above embodiment, and therefore will not be described here.

[0065] Switches S1w, S2w, and S3w are provided between the output terminals T1 to T4 and the source lines SL1 to SL12. The switch S1w ​​is provided so as to be able to switch between connection and disconnection between each output terminal and a source line that carries an "R" pixel. That is, the output terminal T1 is connected to the source line SL1, the output terminal T2 is connected to the source line SL4, the output terminal T3 is connected to the source line SL7, and the output terminal T4 is connected to the source line SL10, each via the switch S1w.

[0066] The switch S2w is provided so as to be able to switch between connection and disconnection between each output terminal and a source line that carries a "G" pixel. That is, the output terminal T1 is connected to the source line SL5, the output terminal T2 is connected to the source line SL2, the output terminal T3 is connected to the source line SL11, and the output terminal T4 is connected to the source line SL8, each via the switch S2w.

[0067] The switch S3w is provided so as to be able to switch between connection and disconnection between each output terminal and a source line that carries a "G" pixel. That is, the output terminal T1 is connected to the source line SL3, the output terminal T2 is connected to the source line SL6, the output terminal T3 is connected to the source line SL9, and the output terminal T4 is connected to the source line SL12, each via the switch S3w.

[0068] A switch AS1 is provided between the end of source line SL1 and the end of source line SL4, and is configured to be switchable between connection and disconnection. A switch AS2 is provided between the end of source line SL2 and the end of source line SL5, and is configured to be switchable between connection and disconnection. A switch AS3 is provided between the end of source line SL3 and the end of source line SL6, and is configured to be switchable between connection and disconnection.

[0069] In this way, in the modified example, the ends of the source lines that serve the same pixel are connected via the switches ASW (AS1, AS2, AS3, etc.), so that in the modified example configuration, a pair of source lines that serve the same pixel are selected as targets for disconnection detection.

[0070] 11 is a diagram showing the state of each switch and the flow of charge in the "charging" step when disconnection detection is performed in the configuration of the modified example. Here, an example is described in which switch S1w ​​is on, switches S2w and S3w are off, and source lines SL1 and SL4 are selected as targets for disconnection detection.

[0071] The source driver 14 turns on the switch S1s and turns off the switches S1x, S2x, S2s, S1D, and S2D in accordance with the control of the display controller 12. This causes the output amplifier AP1 to output a pixel drive voltage signal Vd to the source line SL1. Because the switch AS1 is on (closed), the pixel drive voltage signal Vd from the output amplifier AP1 charges the source lines SL1 and SL4, as indicated by the dashed arrows in the figure.

[0072] FIG. 12 is a diagram showing the state of each switch and the flow of charge in the "detection" step of the modified disconnection detection.

[0073] The source driver 14 turns off the switch S1s and turns on the switch S2x in accordance with the control of the display controller 12. The source driver 14 also controls the switch SWa connected to the output terminal of the output amplifier AP1 to turn on and the switch Swb to turn off, thereby switching to a state in which it operates as the comparator CP1 (i.e., the state shown in FIG. 4B).

[0074] As a result, the charges flowing through the source lines SL1 to SL4 are supplied to the second input terminal of the comparator CP1. The comparator CP1 compares the grayscale voltage input to the first input terminal with the voltage input to the second input terminal (i.e., the voltage according to the charges stored in the source lines SL1 and SL4), and outputs the comparison result from the output terminal as a comparison result signal CV. The source driver 14 supplies the comparison result signal CV to the display controller 12.

[0075] As described above, when the display panel 11 is a source multiplex panel, the ends of source lines that carry the same pixel are short-circuited (connected) to perform disconnection detection. By controlling the on / off of the switches S1w, S2w, and S3w to appropriately switch the source line that is the target of disconnection detection, it becomes possible to detect disconnections in the source lines that carry the R, G, and B pixels.

[0076] Furthermore, the configuration of the output amplifier and source lines in the display device 100 of the embodiment described above makes it possible to detect load abnormalities in addition to detecting disconnections in the source lines. This will be described below.

[0077] The load abnormality is detected by measuring the discharge time when discharging the source lines SL1 and SL2 after the "detection" step in the disconnection detection.

[0078] FIG. 13 is a diagram showing the state of each switch and the flow of charge when measuring the discharge time.

[0079] The source driver 14 turns on the switch S1D in response to the control of the display controller 12. As a result, the source line SL1 is connected to the voltage supply line of the reference voltage VSS via the switch S1D, and the charges on the source lines SL1 and SL2 flow toward the voltage supply line of the reference voltage VSS, thereby discharging.

[0080] The discharge time is measured, for example, by measuring the time from when the switch S1D is switched until the potential of the source line SL2 (i.e., the potential at the second input terminal of the comparator CP1) reaches a predetermined threshold or less. The display controller 12 measures the discharge time using a timer or the like based on the output signal from the source driver 14, for example, and compares the measured discharge time with a predetermined threshold to determine whether a load abnormality has occurred in the source line SL1 or SL2. Note that the display controller 12 may be configured not to measure the discharge time itself, but to detect a load abnormality based on whether an output signal from the source driver (i.e., a signal indicating by a voltage level that the source lines SL1 and SL2 have been discharged) is received within a predetermined time.

[0081] Furthermore, the configuration of the output amplifier and source lines in the display device 100 of the above embodiment makes it possible to detect not only source line disconnections and load abnormalities, but also short circuits between adjacent source lines (hereinafter referred to as adjacent short circuits), as will be described below.

[0082] The adjacent short circuit is detected by turning the switch ASW off (open) and discharging the source line SL1 after the "detection" step in the disconnection detection.

[0083] FIG. 14 is a diagram showing the state of each switch and the flow of charge when an adjacent short circuit is detected.

[0084] The gate driver 13 switches the switch ASW off (open). Furthermore, the source driver 14 switches the switch S1D on in accordance with the control of the display controller 12. As a result, the source line SL1 is connected to the voltage supply line of the reference voltage VSS via the switch S1D, and the charge on the source line SL1 flows toward the voltage supply line of the reference voltage VSS, thereby discharging.

[0085] Since the switch ASW is in the off state, if there is no short circuit between the source lines SL1 and SL2, the source line SL2 is not discharged. On the other hand, if there is a short circuit between the source lines SL1 and SL2, the charge on the source line SL2 flows through the source line SL1, and the source line SL2 is discharged.

[0086] Therefore, it is possible to detect whether or not an adjacent short circuit has occurred based on the potential of the source line SL2, that is, the potential of the second input terminal of the comparator CP1.

[0087] As described above, the display device 100 of this embodiment can detect faults that occur in the display panel 11, such as source line breaks, load abnormalities, adjacent short circuits, etc. Since there is no need to provide a separate fault inspection circuit outside the gate driver 13 or source driver 14, fault detection can be performed while suppressing an increase in the device size.

[0088] The present invention is not limited to the above-described embodiments. For example, the above-described embodiments have been described with reference to an example in which the source driver 14 switches the switches in response to control by the display controller 12. However, the present invention is not limited to this, and the switches may be configured to switch in response to other external signals.

[0089] Furthermore, in the above embodiment, an example has been described in which a failure detection line FDL is provided extending from the gate driver 13 in parallel with the gate lines GL1 to GLn, and the gate driver 13 controls the switch ASW to be turned on and off by sending a switching control signal SWC to the failure detection line FDL. However, the method of controlling the switch ASW to be turned on and off is not limited to this, and, for example, the failure detection line FDL may be extended from the source driver 14, and the source driver 14 may switch the switch ASW between on and off. [Explanation of symbols]

[0090] 100 display device 11 Display panel 12 Display Controller 13 Gate Driver 14 Source Driver AP1, AP2 output amplifier

Claims

1. a display panel including a plurality of source lines and a plurality of gate lines, and a plurality of pixel units provided in a matrix at each intersection of the plurality of source lines and the plurality of gate lines; a gate driver that supplies gate signals to the plurality of gate lines; a source driver including a plurality of output amplifiers each receiving a grayscale voltage at a first input terminal and outputting a pixel drive voltage based on the grayscale voltage to one end of the plurality of source lines, and applying the pixel drive voltage to the plurality of pixel units by the plurality of output amplifiers; and the plurality of source lines include a first source line and a second source line configured to be short-circuitable with each other at the other end; The source driver charging the first source line and the second source line in a state where the first source line and the second source line are short-circuited via the other end thereof and an output end of a first output amplifier among the plurality of output amplifiers, which outputs the pixel drive voltage to the first source line, is connected to the first source line, and then outputting a comparison result by the first output amplifier between the voltage input to the first input end and the voltage input to the second input end in a state where a second input end of the first output amplifier is connected to one end of the second source line; A display device characterized by:

2. The first output amplifier In a first state in which the output terminal is connected to the first source line and is feedback-connected to the second input terminal, the amplifier operates as an output amplifier that outputs the pixel drive voltage to the first source line; In a second state in which the output terminal is disconnected from the first source line and the second input terminal and the second input terminal is connected to the second source line, the comparator operates as a comparator that compares input voltages at the first input terminal and the second input terminal and outputs a comparison result from the output terminal.

2. The display device according to claim 1.

3. a changeover switch provided between the other ends of the first source line and the second source line, for switching between connection and non-connection of the other ends of the first source line and the second source line; 3. The display device according to claim 1, wherein the changeover switch switches between the connection and non-connection states in response to a changeover control signal supplied from the gate driver.

4. 4. The display device according to claim 3, wherein the gate driver switches one end of each of the first source line and the second source line to a connected state during a blank period provided between data periods, which are periods during which the pixel drive voltage corresponding to video data for each frame is applied to the plurality of pixel units.

5. 2. The display device according to claim 1, wherein the first source line and the second source line are source lines arranged adjacent to each other.

6. 2. The display device according to claim 1, wherein the first source line and the second source line are source lines responsible for displaying pixels of the same type.

7. A source driver is connected to a display panel having a plurality of source lines including a first source line and a second source line, each of which has one end configured to be short-circuitable with each other, a plurality of gate lines, and a plurality of pixel units provided in a matrix at each of intersections of the plurality of source lines and the plurality of gate lines, the source driver outputting pixel voltages to be applied to the plurality of pixel units to the plurality of source lines, a plurality of output amplifiers each receiving a grayscale voltage at a first input terminal and outputting the pixel drive voltage based on the grayscale voltage to the other terminal of the plurality of source lines; the first source line and the second source line are charged in a state in which the first source line and the second source line are short-circuited via one end thereof and an output end of a first output amplifier among the plurality of output amplifiers, which outputs the pixel drive voltage to the first source line, is connected to the first source line, and then, in a state in which a second input end of the first output amplifier is connected to the other end of the second source line, the first output amplifier outputs a comparison result between the voltage input to the first input end and the voltage input to the second input end. A source driver comprising:

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