Memory system and control method

Abstract

To perform error correction with higher accuracy.SOLUTION: A memory system includes a nonvolatile memory storing a concatenated code consisting of a first error correction code and a second error correction code, and a memory controller. When first decoding processing using the first error correction code on read-out information read from the nonvolatile memory or verification processing for verifying that the read-out information does not contain any error is successful, the memory controller generates a first parity, which is a parity of the second error correction code, and calculates a first evaluation value for determining whether the read-out information contains any error using the generated first parity and a second parity, which is a parity of the second error correction code after the second decoding processing. The memory controller uses the first evaluation value to determine whether the read-out information contains an error.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a memory system and a control method. [Background technology]

[0002] In a memory system, in order to protect data stored in a memory such as a NAND flash memory, error correction coded data is stored in the memory. Therefore, when reading data stored in the memory, the error correction coded data (also called a received word) read from the memory is decoded to restore the data before being error correction coded. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2019 / 0089384 [Patent Document 2] US Patent Application Publication No. 2019 / 0288711 [Patent Document 3] US Patent Application Publication No. 2017 / 0093438 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the embodiments of the present invention is to provide a memory system and a control method that can perform error correction (decoding) with higher accuracy. [Means for solving the problem]

[0005] A memory system according to an embodiment includes a nonvolatile memory that stores a concatenated code formed by a first error correction code and a second error correction code, and a memory controller. When a first decoding process using the first error correction code on read information read from the nonvolatile memory or a check process for checking that the read information does not contain an error is successful, the memory controller generates a first parity, which is the parity of the second error correction code, and calculates a first evaluation value for determining whether the read information contains an error using the generated first parity and a second parity, which is the parity of the second error correction code after the second decoding process is performed. The memory controller uses the first evaluation value to determine whether the read information contains an error. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram of a memory system according to an embodiment. [Figure 2] 10A and 10B are diagrams for explaining examples of outer codes and inner codes; [Figure 3] FIG. 2 is a block diagram of a decoder according to the first embodiment. [Figure 4] 10 is a flowchart of a decoding process according to the first embodiment. [Figure 5] 10 is a flowchart of a determination process according to the first embodiment. [Figure 6] FIG. 10 is a diagram showing an example of successful decoding processing using an outer code. [Figure 7] FIG. 10 is a diagram showing an example in which decoding processing using an outer code fails. [Figure 8] FIG. 10 is a diagram for explaining an example of determining a false positive. [Figure 9] FIG. 10 is a diagram for explaining an example of a determination process using an evaluation value. [Figure 10] FIG. 10 is a diagram for explaining an example of a determination process using an evaluation value. [Figure 11] FIG. 10 is a block diagram of a decoder according to a second embodiment. [Figure 12] 10 is a flowchart of a determination process according to the second embodiment. [Figure 13] FIG. 10 is a diagram for explaining an example of a determination process using an evaluation value. [Figure 14] FIG. 10 is a block diagram of a decoder according to a third embodiment. [Figure 15] 10 is a flowchart of an inspection process according to a third embodiment. [Figure 16] FIG. 10 is a diagram for explaining an example of an inspection process according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A memory system according to an embodiment will be described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments.

[0008] (First embodiment) Fig. 1 is a block diagram showing a schematic configuration example of a memory system according to the first embodiment. As shown in Fig. 1, the memory system 1 includes a memory controller 10 and a nonvolatile memory 20. The memory system 1 can be connected to a host 30, and Fig. 1 shows the memory system 1 connected to the host 30. The host 30 may be, for example, an electronic device such as a personal computer or a mobile terminal.

[0009] The nonvolatile memory 20 is a nonvolatile memory that stores data nonvolatilely, such as a NAND memory. In the following description, a case where a NAND memory is used as the nonvolatile memory 20 will be exemplified, but it is also possible to use storage devices other than a NAND memory, such as a three-dimensional structure flash memory, a ReRAM (Resistance Random Access Memory), or an FeRAM (Ferroelectric Random Access Memory), as the nonvolatile memory 20. Furthermore, it is not essential that the nonvolatile memory 20 be a semiconductor memory, and this embodiment can also be applied to various storage media other than semiconductor memories.

[0010] The memory system 1 may be a memory card or the like in which the memory controller 10 and the nonvolatile memory 20 are configured as a single package, or may be an SSD (Solid State Drive) or the like.

[0011] The memory controller 10 controls writing to the nonvolatile memory 20 in accordance with a write request from the host 30. The memory controller 10 also controls reading from the nonvolatile memory 20 in accordance with a read request from the host 30. The memory controller 10 includes a host I / F (host interface) 15, a memory I / F (memory interface) 13, a control unit 11, an encoding / decoding unit (codec) 14, and a data buffer 12. The host I / F 15, the memory I / F 13, the control unit 11, the encoding / decoding unit 14, and the data buffer 12 are interconnected by an internal bus 16. Some or all of the operations of the components of the memory controller 10 may be realized by a CPU (Central Processing Unit) executing firmware, or may be realized by hardware.

[0012] The host I / F 15 performs processing in accordance with the interface standard with the host 30, and outputs commands received from the host 30, user data to be written, etc. to the internal bus 16. The host I / F 15 also transmits user data read and restored from the nonvolatile memory 20, responses from the control unit 11, etc. to the host 30.

[0013] The memory I / F 13 performs a write process to the nonvolatile memory 20 based on an instruction from the control unit 11. The memory I / F 13 also performs a read process from the nonvolatile memory 20 based on an instruction from the control unit 11.

[0014] The control unit 11 performs overall control of each component of the memory system 1. When the control unit 11 receives an instruction from the host 30 via the host I / F 15, it performs control in accordance with the instruction. For example, the control unit 11 instructs the memory I / F 13 to write user data and parity to the nonvolatile memory 20 in accordance with the instruction from the host 30. The control unit 11 also instructs the memory I / F 13 to read user data and parity from the nonvolatile memory 20 in accordance with the instruction from the host 30.

[0015] Furthermore, when the control unit 11 receives a write request for user data from the host 30, it accumulates the user data in the data buffer 12 and determines a storage area (memory area) for the user data in the nonvolatile memory 20. That is, the control unit 11 manages the write destination of the user data. The correspondence between the logical address of the user data received from the host 30 and the physical address indicating the storage area on the nonvolatile memory 20 where the user data is stored is stored as an address conversion table.

[0016] Furthermore, when the control unit 11 receives a read request from the host 30, it converts the logical address specified by the read request into a physical address using the address conversion table described above, and instructs the memory I / F 13 to read from the physical address.

[0017] In NAND memory, data is generally written and read in units of data called pages, and erased in units of data called blocks. In this embodiment, a plurality of memory cells connected to the same word line are called a memory cell group. If the memory cells are single-level cells (SLC), one memory cell group corresponds to one page. If the memory cells are multi-level cells (MLC), one memory cell group corresponds to multiple pages. Each memory cell is connected to both a word line and a bit line. Therefore, each memory cell can be identified by an address that identifies the word line and an address that identifies the bit line.

[0018] The data buffer 12 temporarily stores user data received by the memory controller 10 from the host 30 before storing the data in the nonvolatile memory 20. The data buffer 12 also temporarily stores user data read from the nonvolatile memory 20 before transmitting the data to the host 30. The data buffer 12 may be implemented using general-purpose memory such as an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory).

[0019] User data transmitted from the host 30 is transferred to the internal bus 16 and temporarily stored in the data buffer 12. The encoding / decoding unit 14 encodes the user data to generate code words. The encoding / decoding unit 14 also decodes received words, which are data read from the non-volatile memory 20, to restore the user data. Therefore, the encoding / decoding unit 14 includes an encoder 17 and a decoder 18. Note that the data encoded by the encoding / decoding unit 14 may include control data used inside the memory controller 10 in addition to the user data.

[0020] Next, the write process of this embodiment will be described. When writing user data to the nonvolatile memory 20, the control unit 11 instructs the encoder 17 to encode the user data. At that time, the control unit 11 determines a storage location (storage address) of the codeword in the nonvolatile memory 20, and also instructs the memory I / F 13 about the determined storage location.

[0021] The encoder 17 generates code words by encoding the user data in the data buffer 12 based on instructions from the control unit 11. Examples of encoding methods that can be used include encoding methods using algebraic codes such as BCH (Bose-Chaudhuri-Hocquenghem) codes and RS (Reed-Solomon) codes, as well as encoding methods (such as product codes) that use these codes as row- and column-oriented component codes. The memory I / F 13 controls the storage of code words in memory locations in the nonvolatile memory 20 as instructed by the control unit 11.

[0022] Next, a description will be given of the processing performed when reading data from the nonvolatile memory 20 in this embodiment. When reading data from the nonvolatile memory 20, the control unit 11 specifies an address on the nonvolatile memory 20 and instructs the memory I / F 13 to read. The control unit 11 also instructs the decoder 18 to start decoding. In accordance with the instruction from the control unit 11, the memory I / F 13 reads data from the specified address in the nonvolatile memory 20 and inputs the read data to the decoder 18 as a received word. The decoder 18 decodes the received word, which is the data read from the nonvolatile memory 20.

[0023] Next, the error correction code (codeword) used in this embodiment will be described. In this embodiment, the encoder 17 generates a concatenated code as the error correction code. The concatenated code is, for example, a code made up of an error correction code C1 (first error correction code) generated using data (user data) stored in the nonvolatile memory 20, and an error correction code C2 (second error correction code) generated using the error correction code C1. Hereinafter, the error correction code C1 will be referred to as an outer code, and the error correction code C2 will be referred to as an inner code.

[0024] The outer code is used to remove residual errors that cannot be corrected by error correction using the inner code. The outer code can be, for example, a BCH code capable of correcting 4 bits. Since there is a possibility of miscorrection occurring during decoding using the outer code (removal of residual errors), a determination process may be performed to determine whether miscorrection has occurred. The inner code can be, for example, a multidimensional error correction code.

[0025] Here, a multidimensional error-correcting code refers to one in which at least one symbol, which is a constituent unit of the error-correcting code, is multiply protected by multiple smaller component codes. One symbol is composed of, for example, one bit (an element of a binary field) or an alphabet element of a finite field other than a binary field. For ease of explanation, the following explanation will use an example of a binary error-correcting code in which one symbol is composed of one bit. While the terms symbol and bit may be used interchangeably in some places in the explanation, they both mean the same thing.

[0026] An example of a multidimensional error correcting code is a product code. A product code has a structure in which each information symbol, which is a constituent unit of user data, is protected by a Hamming code including parity symbols of a predetermined parity length in both the row and column directions. That is, in a product code, all symbols are doubly protected by component codes in the row direction (referred to as dimension 1) and the column direction (referred to as dimension 2). Note that the multidimensional error correcting code is not limited to this, and may be, for example, a generalized low density parity check code (LDPC code). In general multidimensional error correcting codes, including generalized LDPC codes, the degree of protection may differ for each symbol, and component codes cannot be grouped into dimension 1 and dimension 2, but the present technology can be applied to such code configurations.

[0027] For simplicity, the following describes an example using a two-dimensional error-correcting code (product code) in which each symbol is protected by two component codes that can be grouped into dimension 1 and dimension 2. Each component code for each dimension includes one or more component codes determined for that dimension. Hereinafter, component codes corresponding to each dimension and including one or more component codes may be referred to as a component code group. For example, the component code group for dimension 1 includes n1 component codes, and the component code group for dimension 2 includes n2 component codes. Applicable error-correcting codes are not limited to this, and may be an N-dimensional error-correcting code in which at least one symbol constituting the code is protected by N component code groups (N is an integer equal to or greater than 2). When expressed in terms of the number of component codes included in each component code group, an N-dimensional error-correcting code is protected by M component codes (M is the sum of n i (1≦i≦N), N is an integer equal to or greater than 2, and n i is the number of component codes in the i-th dimension).

[0028] An example of an outer code and an inner code will be described using Fig. 2. In Fig. 2 and the following figures, an example will be described in which a product code obtained by encoding 4 information bits in the column direction (column 1 to column 4) and 4 information bits in the row direction (row 1 to row 4) is used as the inner code.

[0029] 2, the encoder 17 first encodes the user data 210 into an outer code 220. The outer code 220 includes the user data 210 and an outer code parity 221. Next, the encoder 17 encodes the outer code 220 into an inner code 230. The inner code 230 includes the outer code 220, a row-wise parity 231 of the inner code, and a column-wise parity 232 of the inner code.

[0030] The inner code is a product code whose component codes are, for example, BCH codes capable of correcting 3 bits. In the example of Figure 2, the four component codes in the row direction (dimension 1) and the four component codes in the column direction (dimension 2) are each BCH codes capable of correcting 3 bits.

[0031] Next, a configuration example of the decoder 18 that decodes such concatenated codes will be described. Fig. 3 is a block diagram showing a schematic configuration example of the decoder 18 of the first embodiment. As shown in Fig. 3, the decoder 18 includes a read information memory 121, a syndrome memory 122, a decoder 101, an encoder 102, a calculation unit 103, and a determination unit 104.

[0032] The read information memory 121 is realized by, for example, an SRAM. The syndrome memory 122 is realized by, for example, a register. The decoder 101, the encoder 102, the calculation unit 103, and the determination unit 104 are realized by at least one of a register, an adder, a multiplier, and other computing units. The register is realized by, for example, a logic circuit such as a flip-flop. The adder, the multiplier, the selector, and other computing units are realized by, for example, a logic circuit.

[0033] The read information memory 121 is a memory that stores read information, which is data read from the nonvolatile memory 20.

[0034] The syndrome memory 122 is a memory that stores syndromes of error correcting codes. The syndromes are information that can be used to determine whether or not there is an error in the read information. For example, if all the syndrome values ​​are 0, it is determined that there is no error in the read information. The syndrome memory 122 stores a syndrome SD1 of the outer code calculated in a decoding process DEC1 (first decoding process) using the outer code, and multiple syndromes SD2 for multiple component codes calculated in a decoding process DEC2 (second decoding process) using the inner code.

[0035] The decoder 101 executes a decoding process DEC1 using an outer code and a decoding process DEC2 using an inner code. For example, the decoder 101 first executes the decoding process DEC2 using the inner code on the read information. If the decoding process DEC2 fails, the decoder 101 executes the decoding process DEC1 using the outer code on the read information. The decoder 101 stores the read information after executing each decoding process in the read information memory 121.

[0036] The encoder 102 performs inner code encoding on information bits of the inner code stored in the read information memory 121, and regenerates the parity P1 (first parity) of the inner code. For example, the encoder 102 regenerates the parity P1 for each of a plurality of component codes that make up the product code, which is the inner code. Note that the function of the encoder 102 may be provided within the encoder 17.

[0037] In the example of Fig. 2, the encoder 102 re-encodes the four row-wise information bits to regenerate the row-wise parity 231. The encoder 102 also re-encodes the four column-wise information bits to regenerate the column-wise parity 232.

[0038] The regenerated parity P1 is used to calculate an evaluation value used in the determination process. The determination process is a process for determining whether or not an error is contained in the read information. The determination process corresponds to a process for determining whether or not the result of the decoding process DEC1 using the outer code or the check process using the outer code, when these processes are successful, is correct. Therefore, the regeneration of the parity P1 by the encoder 102 is performed when the decoding process DEC1 or the check process is successful.

[0039] The check process is, for example, a process of checking that the read information does not contain any errors (that there are no residual errors) using the outer code. The check process is executed, for example, every time each component code of the inner code is decoded, to check whether or not any errors remain in the user data portion using the syndrome SD1 of the outer code. Even if the decoding process DEC2 is in the middle of being executed, if the check process checks that no errors remain in the user data portion, the decoding process DEC2 can be terminated as a success.

[0040] The inspection process may be any process, but is performed, for example, in the following manner. If the syndrome SD1 of the outer code is satisfied and the syndromes SD2 of the component codes of the inner code, the number of which is equal to or greater than the threshold, are satisfied, the inspection result indicating that the read information does not contain an error is output.

[0041] The calculation unit 103 calculates an evaluation value E1 (first evaluation value) used in the determination process. For example, the calculation unit 103 calculates the evaluation value E1 using the regenerated parity P1 and the parity P2 (second parity) of the inner code after executing the decoding process DEC2 using the inner code. The parity P2 of the inner code after executing the decoding process DEC2 corresponds to the parity portion (row-wise parity 231, column-wise parity 232) of the inner code stored in the read information memory 121. The method of calculating the evaluation value E1 by the calculation unit 103 will be described in detail later.

[0042] The determination unit 104 executes a determination process using the calculated evaluation value E1. For example, if the evaluation value E1 is equal to or less than a threshold value TH_A, the determination unit 104 determines that the read information does not contain an error (decoding was successful). In the determination process after the decoding process DEC1 using the outer code is successful, the evaluation value E1 being equal to or less than the threshold value TH_A corresponds to determining that there is no erroneous correction in the decoding process DEC1. In the determination process after the inspection process, the evaluation value E1 being equal to or less than the threshold value TH_A corresponds to determining that the inspection process has been completed normally.

[0043] The determination unit 104 outputs the result of the determination process as the decoding result. For example, if the determination process determines that the read information does not contain an error, the determination unit 104 outputs decoding success. If the determination process determines that the read information contains an error, the determination unit 104 outputs decoding failure. Note that not only the process by the determination unit 104 but also the process including the regeneration of parity P1 (first parity) by the encoder 102 and the calculation of evaluation value E1 by the calculation unit 103 can be interpreted as corresponding to the determination process.

[0044] Next, a description will be given of the flow of the decryption process performed by the memory system 1 of this embodiment. Fig. 4 is a flowchart showing an example of the decryption process of this embodiment.

[0045] The control unit 11 reads out the error correction code from the nonvolatile memory 20 to obtain read information (step S101). The control unit 11 transfers the read information to the read information memory 121 and stores it there.

[0046] Next, the decoder 18 executes a decoding process DEC2 using the inner code (step S102). When a product code such as that shown in Fig. 2 is used as the inner code, the decoder 18 executes the decoding process DEC2 by, for example, repeatedly decoding component codes in the row direction (dimension 1) and decoding component codes in the column direction (dimension 2). In this case, step S102 in Fig. 4 corresponds to decoding component codes for one dimension (dimension 1 or dimension 2).

[0047] When the decoder 18 finishes decoding one-dimensional component code, it executes a check process for the presence or absence of residual errors using the outer code (step S103). The decoder 18 determines whether the result of the check process (check result) indicates that there are no residual errors (step S104). If the check result indicates that there are no residual errors (step S104: Yes), the decoder 18 executes a determination process (step S105). The flow of the determination process will be described with reference to FIG. 5.

[0048] After the determination process, the decoder 18 determines whether the result of the determination process is a successful decoding (step S106). If the decoding is successful (step S106: Yes), the decoder 18 notifies an external control unit or the like of the successful decoding and the decoded word (step S112), and ends the decoding process.

[0049] If the result of the determination process is a decoding failure (step S106: No), or if it is determined in step S104 that the check result is not free of residual errors (that residual errors exist) (step S104: No), the decoder 18 determines whether the number of iterations has reached a preset specified value (step S107). If the specified value has not been reached (step S107: No), the decoder 18 increments the number of iterations by 1, returns to step S102, and repeats the process. The number of iterations is, for example, the number of times the operations of steps S102 to S106 have been repeated.

[0050] If the number of iterations reaches the specified value (step S107: Yes), the decoder 18 executes the decoding process DEC1 using the outer code (step S108). The decoder 18 determines whether the decoding by the decoding process DEC1 is successful (step S109).

[0051] If it is determined that the decoding by the decoding process DEC1 is successful (step S109: Yes), the decoder 18 executes a determination process (step S110). The flow of the determination process will be described with reference to FIG.

[0052] After the determination process, the decoder 18 determines whether the result of the determination process is a successful decoding (step S111). If the decoding is successful (step S111: Yes), the decoder 18 notifies an external control unit or the like of the successful decoding and the decoded word (step S112), and ends the decoding process.

[0053] If it is determined in step S111 or step S109 that the decoding has failed (step S111: No, step S109: No), the decoder 18 notifies an external control unit or the like of the failure of the decoding (step S113) and terminates the decoding process.

[0054] Next, the flow of the determination process in steps S105 and S110 will be described. Fig. 5 is a flowchart showing an example of the determination process of this embodiment.

[0055] The encoder 102 regenerates the parity P1 of the inner code (step S201). The calculation unit 103 calculates the evaluation value E1 using the regenerated parity P1 and the parity P2 of the inner code that is generated in the decoding process DEC2 using the inner code and stored in the read information memory 121, for example (step S202).

[0056] The determination unit 104 determines whether the evaluation value E1 is equal to or less than the threshold value TH_A (step S203). If the evaluation value E1 is equal to or less than the threshold value TH_A (step S203: Yes), the determination unit 104 outputs a decoding success as the determination result (step S204). If the evaluation value E1 is greater than the threshold value TH_A (step S203: No), the determination unit 104 outputs a decoding failure as the determination result (step S205).

[0057] Next, a detailed description will be given of a method for calculating the evaluation value E1 by the calculation unit 103. The calculation unit 103 can calculate the evaluation value E1 by, for example, the following calculation methods M1 to M3. (M1) Calculate the Hamming distance between parity P1 and parity P2 for each of the plurality of component codes. Calculate the sum of the plurality of Hamming distances for the plurality of component codes as evaluation value E1. (M2) Calculate the Hamming distance between parity P1 and parity P2 for each of the plurality of component codes. The number of component codes whose Hamming distance is greater than threshold TH_B (first threshold) (excess number counter) is calculated as evaluation value E1. (M3) Calculate the Hamming distance between parity P1 and parity P2 for each of the multiple component codes. The sum of a predetermined number of Hamming distances (L, where L is an integer equal to or greater than 1) in descending order is calculated as evaluation value E1.

[0058] Here, the value calculated by the exclusive OR (EXOR) of parity P1 and parity P2 is called a parity error vector, and the Hamming distance is called the weight of the parity error vector.

[0059] Next, an example of a determination process using the evaluation value E1 calculated by the above calculation method will be described. Figures 6 and 7 are diagrams for explaining an example of a determination process using the evaluation value E1 calculated by calculation method M1. Figure 6 shows an example of a case where decoding by the decoding process DEC1 is successful (correction).

[0060] The left part of Figure 6 shows a state in which errors remain in the user data portion (double protection portion) after decoding process DEC2 using the inner code. Note that "x" indicates the location of the remaining error. The center part of Figure 6 shows the state after decoding process DEC1 using the outer code is executed to remove the remaining errors. In the example of Figure 6, all the remaining errors in the double protection portion are removed (corrective correction) by the residual error removal.

[0061] The right side of Figure 6 shows how the evaluation value E1 is calculated using user data after residual errors have been removed, and how it is determined whether there are any miscorrections in the decoding process DEC1. During correct corrections, the parity P2 of the inner code after the decoding process DEC2 includes parities 601-605 containing errors due to channel-related errors or errors due to miscorrections in the component code decoding. Note that channel-related errors refer to errors in the user data before decoding. Meanwhile, because residual errors have been removed, the regenerated parity P1 is correct and contains no errors. The Hamming distance of component codes containing channel-related errors is, on average, less than one bit. Since the evaluation value E1 in calculation method M1 is the sum of multiple Hamming distances for multiple component codes, if the maximum number of miscorrections is three, for example, the evaluation value E1 can be limited to approximately four bits times the number of component codes containing residual errors (four bits is the sum of one channel-related bit and the maximum number of miscorrections, three).

[0062] 7 shows an example of a case where decoding by the decoding process DEC1 fails (miscorrection). In this case, as shown in the center of FIG. 7, new errors 711 and 712 are added due to the miscorrection.

[0063] The right part of FIG. 7 shows a state in which an evaluation value E1 is calculated using user data after errors have been added, and whether or not there is any miscorrection in the decoding process DEC1 is determined. In the decoding process DEC1, the parity of the inner code is not corrected, so even in the event of a miscorrection, the parity P2 of the inner code after the decoding process DEC2 is executed is the same as in FIG. 6, and is a parity that includes an error caused by the channel. On the other hand, because errors remain due to the miscorrection, the regenerated parity P1 includes incorrect parities 701 to 706. The incorrect parities 501 to 506 are a random sequence. Because it is a random sequence, on average half of the bits will differ from the correct parity.

[0064] If the parity length of a component code is, for example, 32 bits, the Hamming distance of a component code containing residual errors is approximately 16 bits on average. The evaluation value E1 in calculation method M1 is approximately the sum of the number of channel-induced errors × 1 bit and the number of component codes containing residual errors × 16 bits.

[0065] 6 and 7, when miscorrection occurs (FIG. 7), the Hamming distance of the component code containing the residual error contributes, so the evaluation value E1 takes a large value. Therefore, when the evaluation value E1 is equal to or smaller than the threshold value TH_A, the determination unit 104 determines that there is no miscorrection (decoding successful), and when the evaluation value E1 is greater than the threshold value TH_A, it determines that there is miscorrection (decoding failed).

[0066] In this way, in this embodiment, it is possible to determine whether or not an erroneous correction has occurred in the decoding by the decoding process DEC1 by using an evaluation value using the parity P1 of the regenerated inner code, thereby enabling error correction (decoding) to be performed with higher accuracy.

[0067] In calculation method M1, when calculating the Hamming distance for each component code (the contribution value for each component code to evaluation value E1), whether or not the component code contains miscorrected bits is not taken into consideration. Therefore, for example, when the number of component codes is large, the contribution values ​​not due to miscorrection, i.e., the contribution values ​​for the number of component codes containing errors due to channel errors or miscorrection in component code decoding, may accumulate and exceed threshold value TH_A. As a result, even if the decoding process DEC1 has successfully completed removal of residual errors (correct correction), it may be erroneously determined to be miscorrected. Note that when there is no error but the determination process does not correctly determine that there is no error, this is also referred to as a false positive determination.

[0068] Fig. 8 is a diagram for explaining an example of determining a false positive. As shown in the center of Fig. 8, an example will be explained in which new errors 801 and 802 have been added due to miscorrection. Parity 811 to 813 correspond to the parity of component codes that provide contribution values ​​not due to miscorrection. In Fig. 8, the number of component codes is 8 (4 in the row direction and 4 in the column direction), and the number of component codes that provide contribution values ​​not due to miscorrection is 4.

[0069] When the number of component codes is large, the number of component codes that provide contribution values ​​not due to miscorrection can be larger, for example, 80 to 500. Therefore, even if the Hamming distance of component codes containing channel-induced errors is less than 1 bit on average, the sum of contribution values ​​not due to miscorrection can be, for example, about 80 to 500.

[0070] As described above, if the parity length of the component code is 32 bits, the average contribution value of each component code due to miscorrection is about 16 bits. If the outer code is a BCH code capable of correcting 4 bits, as will be described later, the number of component codes in which a contribution value due to miscorrection occurs is about 18. Therefore, the total sum of the contribution values ​​not due to miscorrection is, for example, about 288 (= 16 × 18).

[0071] In this way, when the number of component codes is large, the sum of contribution values ​​not caused by miscorrection becomes relatively large and may exceed the threshold value TH_A for determining miscorrection. In other words, even in the case of (correct correction), a situation may arise in which it is erroneously determined to be miscorrection (false positive determination).

[0072] Here, we will explain why the number of component codes that produce contribution values ​​due to miscorrection is approximately 18. When the outer code is a BCH code that can correct 4 bits, the Hamming distance between two codewords (bit strings that can be the correct answer) is 4 + 1 + 4 = 9. Therefore, at least 9 error bits remain when a miscorrection occurs. Assuming that 9 error bits remain in both the row and column directions, contribution values ​​due to miscorrection will occur in 9 x 2 = 18 component codes.

[0073] Calculation methods M2 and M3 can be used to suppress false positive determinations such as those shown in Fig. 8. First, calculation method M2 will be described. Calculation method M2 is a method that takes into consideration whether a component code includes miscorrected bits, that is, a method that calculates evaluation value E1 only from contribution values ​​that are estimated to be caused by miscorrection.

[0074] FIG. 9 is a diagram for explaining an example of a determination process using the evaluation value E1 calculated by the calculation method M2.

[0075] In calculation method M2, the number of component codes whose Hamming distance is greater than a threshold TH_B (excess number counter) is calculated as evaluation value E1. Component codes whose Hamming distance is greater than the threshold TH_B correspond to component codes that are estimated to have a contribution value due to miscorrection. As described above, the Hamming distance of component codes containing channel-induced errors is less than 1 bit on average, while the Hamming distance of component codes due to miscorrection is about 16 bits on average (for component codes with a parity length of 32 bits). Therefore, the value of threshold TH_B may be set to a value (e.g., 9) that allows the two to be distinguished from each other. Calculation method M2 can be interpreted as a method that does not count Hamming distances smaller than the threshold TH_B.

[0076] The determining unit 104 determines that decoding has failed when the excess number counter, which is the evaluation value E1, is greater than the threshold value TH_A.

[0077] This will be explained using the example in Figure 9. The threshold value TH_B is 9, and the threshold value TH_A is 3. The numerical values ​​in Figure 9 represent the Hamming distance (contribution value) of each component code. For example, the component code in the first row contains an error in the parity, so the contribution value is 1.

[0078] During corrective correction, there is no component code whose Hamming distance is greater than the threshold TH_B=9, so the excess number counter becomes 0. Since the value of the excess number counter is smaller than the threshold TH_A=3, the determining unit 104 determines that decoding is successful.

[0079] In the case of an erroneous correction, there are six component codes whose Hamming distance is greater than the threshold value TH_B=9, and therefore the excess number counter becomes 6. Since the value of the excess number counter is greater than the threshold value TH_A=3, the determining unit 104 determines that decoding has failed.

[0080] In calculation method M2, if the threshold value TH_B is set appropriately, the contribution value of the component code including the error due to the channel is not counted, so even if the number of component codes increases, the excess number counter does not increase cumulatively, which makes it possible to suppress false positive determinations.

[0081] Next, calculation method M3 will be described. Calculation method M3 is a method for calculating evaluation value E1 from only component codes with higher magnitude of contribution values. Fig. 10 is a diagram for explaining an example of a determination process using evaluation value E1 calculated by calculation method M3.

[0082] In calculation method M3, the sum of L Hamming distances (top L contribution values) in descending order is calculated as evaluation value E1. Note that an average value may be used instead of the sum.

[0083] The determining unit 104 determines that decoding has failed when the evaluation value E1, which is the sum of the top L contribution values, is greater than the threshold value TH_A.

[0084] An example will be described using Fig. 10. Assume that L is 4 and the threshold TH_A is 30. The numerical values ​​in Fig. 10 represent the Hamming distance (contribution value) of each component code.

[0085] When corrected, the evaluation value E1, which is the sum of the top four Hamming distances, is 2+1+1+1=5. Since the evaluation value E1, 5, is smaller than the threshold value TH_A=30, the determining unit 104 determines that the decoding is successful.

[0086] When an erroneous correction occurs, the evaluation value E1, which is the sum of the top four Hamming distances, is 17+15+13+11=56. Since the evaluation value E1, 56, is greater than the threshold value TH_A=30, the determining unit 104 determines that the decoding has failed.

[0087] In calculation method M3, evaluation value E1 is calculated using the contribution values ​​of a limited number (L) of component codes. Therefore, even if the number of component codes increases, the contribution values ​​of the component codes do not accumulate, and as a result, it is possible to prevent false positive determinations.

[0088] In the above description, the determination process is executed both after the decoding process DEC1 using the outer code is successful and after the checking process using the outer code is successful (steps S105 and S110 in FIG. 4). The determination process may be executed only in one of these cases.

[0089] (Second embodiment) In the second embodiment, yet another calculation method is used for the evaluation value E1. An example of the decoder 18-2 of the second embodiment will be described below. Note that the configuration other than the decoder 18-2 is the same as that of the first embodiment.

[0090] Fig. 11 is a block diagram showing a schematic configuration example of a decoder 18-2 according to the second embodiment. As shown in Fig. 11, the decoder 18-2 includes a read information memory 121, a syndrome memory 122, a decoder 101, an encoder 102-2, a calculation unit 103-2, and a determination unit 104.

[0091] In the second embodiment, the functions of the encoder 102-2 and the calculation unit 103-2 are different from those in the first embodiment. The other configurations and functions are the same as those in the block diagram of the decoder 18 in the first embodiment shown in FIG. 3, so the same reference numerals are used and the description thereof will be omitted here.

[0092] In this embodiment, the following calculation method M4 of the evaluation value E1 is used. (M4) Calculate the Hamming distance between parity P1 and parity P2 for the component codes including the bits corrected by the outer code. Calculate the statistical value of the Hamming distance as the evaluation value E1. The statistical value is, for example, the sum or average value.

[0093] For this reason, the encoder 102-2 regenerates parity P1 for component codes that include bits corrected by the outer code. For example, when the decoder 18-2 executes the decoding process DEC1 using the outer code, the decoder 18-2 stores information indicating whether or not a component code includes bits corrected by the outer code in a memory such as the read information memory 121. The encoder 102-2 can refer to this information to determine whether or not a component code includes bits corrected by the outer code. Hereinafter, a set of component codes that include bits corrected by the outer code will be referred to as set S.

[0094] The calculation unit 103-2 calculates an evaluation value E1 for each component code included in the set S using the regenerated parity P1 and parity P2. For example, the calculation unit 103-2 calculates the Hamming distance between the parity P1 and parity P2 for each component code included in the set S, and calculates the sum of a plurality of Hamming distances for each component code included in the set S as the evaluation value E1.

[0095] The calculation method M4 of this embodiment is based on the premise that correction is performed using the outer code, and can therefore be applied to the determination process after the decoding process DEC1 using the outer code is executed. For example, in Fig. 4, the calculation of the evaluation value E1 using the calculation method M4 is applied in the determination process of step S110. Note that the flow of the decoding process other than this is the same as in the first embodiment (Fig. 4), and therefore a description thereof will be omitted.

[0096] Next, the flow of the determination process of this embodiment will be described below. Fig. 12 is a flowchart showing an example of the determination process of the second embodiment.

[0097] The decoder 18-2 sets the component code including the bit corrected by the outer code in the decoding process DEC1 executed in step S108 of FIG. 4 as the target for parity regeneration (step S301).

[0098] The encoder 102-2 regenerates the parity P1 of the inner code for each of the set component codes (step S302). The calculation unit 103-2 calculates the evaluation value E1 for each of the set component codes using the regenerated parity P1 and the parity P2 of the inner code (step S303).

[0099] Steps S304 to S306 are the same as steps S203 to S205 in the determination process (FIG. 5) of the first embodiment, and therefore a description thereof will be omitted.

[0100] 13 is a diagram illustrating an example of a determination process using an evaluation value E1 calculated by calculation method M4. Areas 1301 to 1303 represent areas including bits corrected by decoding process DEC1 using an outer code. Areas 1311 and 1312 represent areas where new errors have been added due to miscorrection in decoding process DEC1.

[0101] In calculation method M4, component codes including bits corrected by the outer code are included in the set S to be processed. This will be explained using the example of Fig. 13. The threshold value TH_A is assumed to be 30.

[0102] During correct correction, the four component codes corresponding to the first row, third row, second column, and third column are included in set S. The evaluation value E1, which is the sum of the Hamming distances for the four component codes included in set S, is 1+1+1+1=4. Because the value of evaluation value E1, 4, is smaller than threshold value TH_A=30, the determination unit 104 determines that decoding is successful.

[0103] When an erroneous correction occurs, the four component codes corresponding to the first row, fourth row, second column, and fourth column are included in set S. The evaluation value E1, which is the sum of the Hamming distances for the four component codes included in set S, is 15+11+13+17=56. Because the evaluation value E1, 56, is greater than the threshold value TH_A=30, the determination unit 104 determines that the decoding has failed.

[0104] In calculation method M3, the evaluation value E1 is calculated using the contribution values ​​of component codes including bits corrected by the outer code, in other words, a limited number of component codes. Therefore, even if the number of component codes increases, the contribution values ​​of the component codes do not accumulate, and as a result, it is possible to prevent false positives.

[0105] (Third embodiment) In the above embodiments, the inspection process is performed, for example, in the following manner. If the syndrome SD1 of the outer code is satisfied and the syndromes SD2 of the component codes of the inner code, the number of which is equal to or greater than the threshold, are satisfied, the inspection result indicating that the read information does not contain an error is output.

[0106] In this procedure, for example, if there are many component codes of the inner code for which the syndrome SD2 is not satisfied, the read information may be determined to contain an error even when the read information does not contain an error. In other words, the test process may result in a false positive.

[0107] Therefore, in the third embodiment, an example of an inspection process that can suppress false positive determinations will be described. An example of a decoder 18-3 in the third embodiment will be described below. Note that the configuration other than the decoder 18-3 is the same as in the first embodiment.

[0108] Fig. 14 is a block diagram showing a schematic configuration example of a decoder 18-3 according to the third embodiment. As shown in Fig. 11, the decoder 18-3 includes a read information memory 121, a syndrome memory 122, a decoder 101-3, an encoder 102, a calculation unit 103, and a determination unit 104.

[0109] In the third embodiment, the function of the decoder 101-3 is different from that in the first embodiment. Other configurations and functions are the same as those in the block diagram of the decoder 18 in the first embodiment shown in FIG. 3, so the same reference numerals are used and the description thereof will be omitted here.

[0110] The decoder 101-3 further has a function of calculating the reliability of correction for each of the component codes when performing the decoding process DEC2 using the inner code. The reliability is information indicating the likelihood of decoding each component code (decoding reliability).

[0111] The reliability is a metric that indicates whether the probability that a codeword is the original component codeword, calculated from, for example, a soft-decision input value, is high or low. The soft-decision input value is a received word (probability information) that is read as information on the probability that it was '0' or '1' and input to the decoder 18. For example, the reliability in a binary code can be a likelihood calculated from the soft-decision input value for the codeword. The reliability is not limited to this, and the following information, for example, can also be used. (I1) Probability that the codeword is correct (I2) Value of the distance function between the codeword and the soft decision input value (I3) Value obtained by applying a logarithmic function to the value shown in (I1) or (I2) above

[0112] The decoder 18-3 performs a check process using the outer code and an evaluation value E2 (second evaluation value) based on the calculated reliability. The evaluation value E2 is, for example, the number of component codes for which the syndrome SD2 is satisfied and the reliability is equal to or greater than a threshold TH_C (second threshold). The evaluation value E2 may be, for example, the number of component codes for which the reliability is equal to or greater than a threshold TH_C, regardless of whether the syndrome SD2 is satisfied. The evaluation value E2 may also be the sum of the reliability.

[0113] For example, the decoder 18-3 executes the check process according to the following procedure. If the syndrome SD1 of the outer code is satisfied and the evaluation value E2 is equal to or greater than the threshold value TH_D, an inspection result is output indicating that the read information does not contain an error.

[0114] Next, the flow of the inspection process of this embodiment will be described. The inspection process is applied as a process corresponding to step S103 in Fig. 4, for example. The rest of the decoding process flow is the same as in the first embodiment (Fig. 4), so the description will be omitted. Fig. 15 is a flowchart showing an example of the inspection process of this embodiment.

[0115] The decoder 18-3 calculates the number of component codes for which the syndrome SD2 of the inner code is satisfied and the reliability is equal to or greater than the threshold TH_C as an evaluation value E2 (step S401). The decoder 18-3 determines whether the syndrome of the outer code is satisfied and the number calculated in step S401 (evaluation value E2) is equal to or greater than the threshold TH_D (step S402).

[0116] If the syndrome of the outer code is sufficient and the number is equal to or greater than the threshold TH_D (step S402: Yes), the decoder 18-3 outputs a check result indicating that there is no residual error (step S403), and ends the check process.

[0117] If the syndrome of the outer code is not sufficient, or if the number is not equal to or greater than the threshold value TH_D (step S402: No), the decoder 18-3 outputs a check result indicating that there is a residual error (step S404), and ends the check process.

[0118] 16 is a diagram for explaining an example of the inspection process of this embodiment. Note that the numerical values ​​in the codes indicate the number of errors remaining in the corresponding areas. The threshold TH_C is 2, and the threshold TH_D is 5.

[0119] 16, the syndrome SD2 of the inner code is satisfied and the number of component codes whose reliability is equal to or greater than the threshold TH_C is 5. If the errors in areas 1601 and 1602 are corrected by the decoding process DEC1 using the outer code, the syndrome SD1 of the outer code becomes satisfied. Since the syndrome of the outer code is satisfied and the number 5 is equal to or greater than the threshold TH_D=5, the decoder 18-3 outputs an inspection result indicating that there are no remaining errors.

[0120] In the first and second embodiments, the inspection process is performed using only information on whether the syndrome of each component code of the inner code is satisfied, without taking reliability into consideration. Therefore, in order to prevent erroneous correction, it is necessary to set a strict threshold for the judgment. For example, assume that the inspection result indicating no residual error is output when the syndrome of the outer code is satisfied and the number of component codes satisfying the syndrome is equal to or greater than a threshold TH_E, and the inspection result indicating the presence of a residual error is output otherwise. In such a configuration, the threshold TH_E needs to be set high, which may increase the number of false positive judgments (i.e., judgments that there is a residual error even when there actually is no residual error). In this embodiment, the inspection process is performed taking reliability into consideration, so that it is possible to prevent false positive judgments by appropriately setting the threshold TH_C to be compared with the reliability.

[0121] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0122] 1. Memory System 10 Memory Controller 11 Control section 12 Data Buffers 13 Memory I / F 14 Encoding / Decoding Unit 15 Host I / F 16 Internal Bus 17 Encoder 18, 18-2, 18-3 decoder 20 Non-volatile memory 30 hosts 101, 101-3 decoder 102, 102-2 encoder 103, 103-2 Calculation section 104 Judgment section 121 Readout information memory 122 Syndrome Memory

Claims

1. a nonvolatile memory that stores a concatenated code obtained by using a first error correction code generated using data to be stored and a second error correction code generated using the first error correction code; reading read information from the nonvolatile memory; performing a second decoding process on the read information using the second error correction code; If the decoding by the second decoding process fails, a first decoding process is performed on the read information using the first error correction code; If the first decoding process or the inspection process for inspecting whether the read information contains no errors using the first error correcting code is successful, a first parity that is the parity of the second error correcting code is generated, and a first evaluation value for determining whether the read information contains an error is calculated using the generated first parity and a second parity that is the parity of the second error correcting code after the second decoding process is executed; using the first evaluation value to determine whether the read information includes an error; A memory controller; A memory system comprising:

2. the second error-correcting code is an N-dimensional error-correcting code in which at least one symbol among symbols constituting the code is protected by N component code groups (N is an integer of 2 or more), the second decoding process includes decoding M component codes (1≦i≦N, where ni is the number of component codes included in the i-th dimension component code group, and M is the sum of ni) included in the read information; The memory controller generating the first parity for each of the M component codes when it is determined by the checking process that the read information does not contain an error; calculating the first evaluation value using the generated M first parities and the second parities of the M component codes after the second decoding process is performed; 10. The memory system of claim 1.

3. The memory controller calculating a Hamming distance between the first parity and the second parity for each of the M component codes, and calculating the first evaluation value, which is the number of the component codes for which the Hamming distance is equal to or greater than a first threshold value; 3. The memory system of claim 2.

4. The memory controller calculating a Hamming distance between the first parity and the second parity for each of the M component codes, and calculating the first evaluation value, which is the sum of a predetermined number of the Hamming distances selected in descending order of value from the calculated M Hamming distances; 3. The memory system of claim 2.

5. The memory controller calculating a Hamming distance between the first parity and the second parity for each of the one or more component codes that have been subjected to correction by the first decoding process among the M component codes, and calculating the first evaluation value that is a statistical value of the calculated Hamming distances; 3. The memory system of claim 2.

6. The statistical value is a sum or an average value.

6. The memory system of claim 5.

7. the second error-correcting code is an N-dimensional error-correcting code in which at least one symbol among symbols constituting the code is protected by N component code groups (N is an integer of 2 or more), the second decoding process includes decoding M component codes (1≦i≦N, where ni is the number of component codes included in the i-th dimension component code group, and M is the sum of ni) included in the read information; The memory controller performing the checking process using the first error-correcting code and a second evaluation value based on the reliability of correction of each of the M component codes by the second decoding process; 10. The memory system of claim 1.

8. The second evaluation value is the number of component codes whose syndrome is sufficient and whose reliability is equal to or greater than a second threshold, or the number of component codes whose reliability is equal to or greater than a second threshold, or The sum of the above reliabilities That is, 8. The memory system of claim 7.

9. the second error-correcting code is an N-dimensional error-correcting code in which at least one symbol among symbols constituting the code is protected by N component code groups (N is an integer of 2 or more), the second decoding process includes decoding M component codes (1≦i≦N, where ni is the number of component codes included in the i-th dimension component code group, and M is the sum of ni) included in the read information; The memory controller performing the checking process each time M component codes are decoded; 10. The memory system of claim 1.

10. A control method by a memory controller that controls a nonvolatile memory that stores a concatenated code obtained by using a first error correction code generated using data to be stored and a second error correction code generated using the first error correction code, reading read information from the nonvolatile memory; performing a second decoding process on the read information using the second error correction code; If the decoding by the second decoding process fails, a first decoding process is performed on the read information using the first error correction code; If the first decoding process or the inspection process for inspecting whether the read information contains no errors using the first error correcting code is successful, a first parity that is the parity of the second error correcting code is generated, and a first evaluation value for determining whether the read information contains an error is calculated using the generated first parity and a second parity that is the parity of the second error correcting code after the second decoding process is executed; using the first evaluation value to determine whether the read information includes an error; A control method comprising:

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