Game machine

Abstract

To provide a game machine that is improved regarding a setting for timer interruption by a game control microcomputer and a value control microcomputer.SOLUTION: A game machine comprises a main control section 161 for controlling a game and a token number control section 171 for controlling a credit possessed by a player, microcomputers for constituting the main control section 161 and the token number control section 171 are microcomputers having the same specifications that allow interruption to occur by a first timer interruption because of expiration of a first timer circuit TM1, a second timer interruption because of expiration of a second timer circuit TM2, and the like, and the setting of the microcomputer for constituting the main control circuit 161 and the microcomputer for constituting the token number control section 171 is commonalized so as to generate a timer interruption because of expiration of the same timer circuit each.SELECTED DRAWING: Figure 46

Description

[Technical Field]

[0001] The present invention relates to a gaming machine capable of playing games. [Background technology]

[0002] This type of gaming machine is equipped with a game control microprocessor that controls the game, and the game control microprocessor makes settings for a timer interrupt when power supply begins (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-103166 Summary of the Invention [Problem to be solved by the invention]

[0004] In a gaming machine such as that described in Patent Document 1, there is room for improvement in the settings for timer interrupts by the gaming control microprocessor.

[0005] SUMMARY OF THE INVENTION An object of the present invention is to provide a gaming machine in which improvements have been made in the settings for timer interrupts by a gaming control microprocessor. [Means for solving the problem]

[0006] The gaming machine of claim 1 comprises: A gaming machine capable of playing games, a game control microcomputer that controls the game; a value control microcomputer that controls gaming values ​​owned by players; Equipped with The game control microcomputer and the value control microcomputer are both microcomputers with the same specifications that have a counting means capable of counting by thinning out the supplied clock signals, and an interrupt means capable of generating an interrupt when the count value of the counting means reaches a predetermined number, and that can identify the address of the process to be executed when an interrupt is generated based on data stored in one of a plurality of areas when an interrupt is generated by the interrupt means, When an interrupt is generated by the interrupt means, the game control microcomputer specifies an address of a process to be executed based on the data stored in a specific area among the multiple areas, When an interrupt is generated by the interrupt means, the value control microcomputer identifies an address of a process to be executed in response to the generation of the interrupt based on the data stored in the specific area among the multiple areas; The frequency of the clock signal supplied by the game control microcomputer and the value control microcomputer is the same; The time intervals at which the interrupts occur are different between the game control microcomputer and the value control microcomputer, In setting the time interval for generating the interrupt, the game control microcomputer and the value control microcomputer have different thinning rates of clock signals in the counting means, and the predetermined number value at which the count value of the counting means reaches the interrupt means is different. It is characterized by the following. According to this feature, the game control microcomputer and the value control microcomputer both have a counting means capable of counting and an interrupt means capable of generating an interrupt when the count value of the counting means reaches a predetermined number, and when using microcomputers of the same specifications that can identify the address of the processing to be executed when an interrupt occurs based on data stored in one of multiple areas when an interrupt occurs by the interrupt means, both the game control microcomputer and the value control microcomputer can identify the address of the processing to be executed when an interrupt occurs based on data stored in a specific area among the multiple areas when an interrupt occurs by the interrupt means, thereby making it possible to standardize the timer interrupt settings between the game control microcomputer and the value control microcomputer. Furthermore, in a configuration in which the time intervals for interrupt generation differ between the game control microcomputer and the value control microcomputer, by setting the time intervals for interrupt generation different values ​​for the game control microcomputer and the value control microcomputer, as well as the thinning rate of the clock signal in the counting means, and the predetermined number value that the count value of the counting means reaches to cause the interrupt means to generate an interrupt, confusion between the setting for the time intervals for interrupt generation in the game control microcomputer and the setting for the time intervals for interrupt generation in the value control microcomputer can be prevented.

[0007] The present invention may have only the invention-specifying matters set forth in the claims of the present invention, or may have the invention-specifying matters set forth in the claims of the present invention as well as configurations other than the invention-specifying matters. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 2 is a front view of the card unit and the slot machine. [Figure 2] FIG. 2 is a block diagram showing the internal configuration of the card unit and the slot machine. [Figure 3] FIG. 10 is a diagram for explaining the transition of game states. [Figure 4]10 is a diagram showing a game start command sent by the main control unit to the performance control unit when the start switch is operated. FIG. [Figure 5] This shows the game end command that the main control unit sends to the performance control unit at the third stop. [Figure 6] A diagram showing the types of commands that the main control unit sends to the medal count control unit. [Figure 7] FIG. 10 is a diagram illustrating a gaming machine installation information command. [Figure 8] FIG. 10 is a diagram illustrating the configuration of an input command. [Figure 9] FIG. 10 is a diagram showing the configuration of a settlement command. [Figure 10] FIG. 10 is a diagram showing the configuration of a payout command. [Figure 11] FIG. 10 is a diagram showing the configuration of an input pulse command. [Figure 12] FIG. 10 is a diagram showing the configuration of a dispensing pulse command. [Figure 13] A diagram showing the structure of a jackpot command. [Figure 14] A diagram showing the structure of a gaming machine fraud command. [Figure 15] FIG. 10 is a diagram illustrating the configuration of an error command. [Figure 16] A diagram showing the structure of the role ratio information 1 command. [Figure 17] A diagram showing the structure of the role ratio information 2 command. [Figure 18] A diagram showing the structure of a total payout command for reels. [Figure 19] A diagram showing the structure of a continuous reel total payout command. [Figure 20] FIG. 10 is a diagram illustrating the configuration of an over command. [Figure 21] A diagram showing the types of commands that the medal count control unit sends to the main control unit. [Figure 22] FIG. 10 is a diagram showing the configuration of an input response command. [Figure 23] FIG. 10 is a diagram showing the configuration of a settlement response command. [Figure 24] FIG. 10 is a diagram showing the configuration of a payout response command. [Figure 25] FIG. 10 is a diagram illustrating the configuration of an overflow response command. [Figure 26] A diagram showing the structure of a medal count control side information command. [Figure 27] FIG. 10 is a diagram illustrating an example of communication between a main control unit and a medal count control unit. [Figure 28] A diagram for explaining the communication of medal count control side information commands. [Figure 29] 10 is a diagram showing the flow of communication between the main control unit and the medal count control unit after the power is turned on. [Figure 30] 10A and 10B are diagrams illustrating the bet number setting operation and the settlement operation. [Figure 31] 10A and 10B are diagrams illustrating display control of the number of dispensed coins. [Figure 32] FIG. 2 is a diagram illustrating a memory area used by a main control unit. [Figure 33] FIG. 2 is a diagram showing an internal RAM area used by the main control unit. [Figure 34] 3 is a diagram illustrating the control contents of the initial setting process (main control) performed by the main control unit. FIG. [Figure 35] FIG. 10 is a diagram illustrating the control content of the external RAM initialization process performed by the main control unit. [Figure 36] 10A and 10B are diagrams illustrating control contents of setting change processing performed by a main control unit. [Figure 37] FIG. 2 is a diagram illustrating the control content of the main processing (main control) performed by the main control unit. [Figure 38] 10 is a diagram for explaining the control content of the timer interrupt processing (main control) performed by the main control unit. FIG. [Figure 39] 10 is a diagram for explaining the control contents of the initial setting process (medal number control) performed by the main control unit. [Figure 40] 10 is a diagram for explaining the control contents of the main processing (medal count control) performed by the main control unit. [Figure 41] This is a diagram explaining the control contents of the timer interrupt processing (medal number control) performed by the main control unit. [Figure 42]FIG. 10 is a block diagram showing the configuration of a microcomputer that constitutes the main control unit and the medal count control unit. [Figure 43] FIG. 2 is a diagram illustrating a configuration of a serial communication circuit. [Figure 44] 10 is a block diagram showing the connection status between the main control unit and the medal count control unit. FIG. [Figure 45] This is a diagram showing the settings of the serial communication circuit between the main control unit and the medal count control unit, and the settings of the serial communication circuit between the medal count control unit and the card unit. [Figure 46] FIG. 2 is a diagram illustrating a configuration of a timer circuit. [Figure 47] This is a diagram showing the interrupt settings and timer circuit settings in the main control unit and medal count control unit. [Figure 48] A diagram showing the setting order of the built-in registers in the main control unit and medal count control unit. [Figure 49] This is a diagram showing the control flow when the power is turned on in the main control unit and the medal count control unit. [Figure 50] 1 is a front view showing a pachinko gaming machine and a card unit. [Figure 51] FIG. 2 is a rear view showing the pachinko gaming machine. [Figure 52] FIG. 2 is a plan view showing the main parts of the pachinko gaming machine. [Figure 53] FIG. 2 is an oblique view showing the outer frame and the frame for the gaming machine. [Figure 54] 1 is a perspective view showing the lower part of the gaming machine frame. FIG. [Figure 55] A schematic front view showing the circulation path of the game balls. [Figure 56] 1 is a block diagram showing the configuration of a pachinko gaming machine and a card unit. [Figure 57] 1 is a block diagram showing the configuration of a pachinko gaming machine. [Figure 58] A diagram explaining the control contents of the game control main processing performed by the main control board. [Figure 59] This is a diagram explaining the control contents of the game control timer interrupt processing performed by the main control board. [Figure 60]FIG. 10 is a diagram showing a memory area used by the frame control board. [Figure 61] FIG. 10 is a diagram showing a ROM area used by the frame control board. [Figure 62] This is a diagram showing the configuration of the in-use area program and the out-of-use area program executed by the frame control board. [Figure 63] FIG. 2 is a diagram illustrating an outline of the control performed by the frame control board. [Figure 64] 10 is a diagram illustrating the control content of the power-on process performed by the frame control board. FIG. [Figure 65] 10A and 10B are diagrams illustrating the control content of the main loop processing performed by the frame control board. [Figure 66] 10A and 10B are diagrams illustrating the control contents of the timer interrupt control process performed by the frame control board. [Figure 67] 10A and 10B are diagrams illustrating the control content of the subtraction mechanism control process performed by the frame control board. [Figure 68] This is a diagram showing the flow of communication between the main control board and the frame control board from power-on. [Figure 69] A diagram showing the flow of communication between the main control board, frame control board, and card unit. [Figure 70] A diagram showing a list of commands sent and received between the main control board and the frame control board. [Figure 71] A diagram showing the relationship between a gaming machine information response and a launch permission signal. [Figure 72] 10A and 10B are diagrams showing the configurations of a gaming machine installation information notification and a gaming machine installation information response. [Figure 73] FIG. 10 is a diagram showing the configuration of a gaming machine information notification. [Figure 74] FIG. 10 is a diagram showing the configuration of a gaming machine information notification. [Figure 75] A diagram showing the configuration of a gaming machine information response. [Figure 76] A block diagram showing the connection status between the main control board and the frame control board. [Figure 77] This figure shows the settings of the serial communication circuit between the main control board and frame control unit board, and the settings of the serial communication circuit between the frame control board and card unit. [Figure 78] This is a diagram showing the interrupt settings and timer circuit settings on the main control board and frame control board. [Figure 79] A diagram showing the setting order of the built-in registers in the main control board and the frame board section. [Figure 80] A diagram showing the control flow when power is turned on in the main control board and frame control board. [Figure 81] A diagram showing the control flow when power is turned on in the main control board and frame control board. DETAILED DESCRIPTION OF THE INVENTION

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A gaming machine according to the present invention will be described below with reference to the following examples.

[0010] [Form 1] The gaming machine of type 1-1 is A gaming machine (slot machine 2 / pachinko gaming machine 1002) that can be used for gaming, A game control microcomputer (main control unit 161 / main control microcomputer 1160) that controls the game; A value control microcomputer (a medal count control unit 171 / a slot control microcomputer 1170) that controls the gaming value (credits / game balls) owned by the player; Equipped with The value control microcomputer (the medal count control unit 171 / frame control microcomputer 1170) can be connected to an external connection device (card unit 3 / card unit 1003) so as to be able to communicate with each other, The game control microcomputer (main control unit 161 / main control microcomputer 1160) and the value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) are both microcomputers of the same specifications, each having a first serial communication circuit (first serial communication circuit SR1) that receives data in a memory area (data register) assigned a first address (FF27h), and a second serial communication circuit (second serial communication circuit SR2) that receives data in a memory area (data register) assigned a second address (FF2Bh), The game control microcomputer (main control unit 161 / main control microcomputer 1160) communicates with the value control microcomputer (medal number control unit 171 / frame control microcomputer 1170) using the first serial communication circuit (first serial communication circuit SR1), The value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) communicates with the game control microcomputer (main control unit 161 / main control microcomputer 1160) using the second serial communication circuit (second serial communication circuit SR2), and communicates with the externally connected device (card unit 3 / card unit 1003) using the first serial communication circuit (first serial communication circuit SR1). It is characterized by the following. According to this feature, the game control microcomputer and the value control microcomputer both use microcomputers of the same specifications, each having a first serial communication circuit that receives data in a memory area assigned a first address and a second serial communication circuit that receives data in a memory area assigned a second address, and since the serial communication circuit used by the game control microcomputer when communicating with the value control microcomputer is different from the serial communication circuit used by the value control microcomputer when communicating with the game control microcomputer, even when microcomputers of the same specifications are used as the game control microcomputer and the value control microcomputer, it is possible to prevent confusion between the program executed by the game control microcomputer and the program executed by the value control microcomputer.

[0011] The gaming machine of type 1-2 is A gaming machine (slot machine 2 / pachinko gaming machine 1002) that can be used for gaming, A game control microcomputer (main control unit 161 / main control microcomputer 1160) that controls the game; A value control microcomputer (a medal count control unit 171 / a slot control microcomputer 1170) that controls the gaming value (credits / game balls) owned by the player; Equipped with The value control microcomputer (the medal count control unit 171 / frame control microcomputer 1170) can be connected to an external connection device (card unit 3 / card unit 1003) so as to be able to communicate with each other, The game control microcomputer (main control unit 161 / main control microcomputer 1160) and the value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) are both microcomputers of the same specifications, each having a first serial communication circuit (first serial communication circuit SR1) that transmits data written in a memory area (data register) to which a first address (FF27h) is assigned, and a second serial communication circuit (second serial communication circuit SR2) that transmits data written in a memory area (data register) to which a second address (FF2Bh) is assigned, The game control microcomputer (main control unit 161 / main control microcomputer 1160) communicates with the value control microcomputer (medal number control unit 171 / frame control microcomputer 1170) using the first serial communication circuit (first serial communication circuit SR1), The value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) communicates with the game control microcomputer (main control unit 161 / main control microcomputer 1160) using the second serial communication circuit (second serial communication circuit SR2), and communicates with the externally connected device (card unit 3 / card unit 1003) using the first serial communication circuit (first serial communication circuit SR1). It is characterized by the following. According to this feature, the game control microcomputer and the value control microcomputer both use microcomputers of the same specifications, each having a first serial communication circuit that transmits data written to a memory area assigned a first address and a second serial communication circuit that transmits data written to a memory area assigned a second address, and since the serial communication circuit used by the game control microcomputer when communicating with the value control microcomputer is different from the serial communication circuit used by the value control microcomputer when communicating with the game control microcomputer, even when microcomputers of the same specifications are used as the game control microcomputer and the value control microcomputer, confusion between the program executed by the game control microcomputer and the program executed by the value control microcomputer can be prevented.

[0012] The gaming machine of form 1-3 is the gaming machine according to form 1-1 or 1-2, The value control microcomputer (frame control microcomputer 1170) communicates with the externally connected device (card unit 1003) at a first speed (62,500 bps (bits per second)) using the first serial communication circuit (first serial communication circuit SR1), The game control microcomputer (main control microcomputer 1160) communicates with the value control microcomputer (frame control microcomputer 1170) at a second speed (31250 bps (bits / second)) lower than the first speed (62500 bps (bits / second)) using the first serial communication circuit (first serial communication circuit SR1). It is characterized by the following. According to this feature, the value control microcomputer communicates with the externally connected device at a first speed using a first serial communication circuit, and the game control microcomputer communicates with the value control microcomputer at a second speed lower than the first speed using the first serial communication circuit, thereby allowing communication to be carried out at a suitable speed depending on the content of the communication, and since the communication speeds of the two are different, it becomes difficult to analyze the communication, and fraud that may result from analyzing the communication can also be prevented.

[0013] The gaming machine of form 1-4 is the gaming machine according to form 1-1 or 1-2, The value control microcomputer (frame control microcomputer 1170) communicates with the externally connected device (card unit 1003) at a first speed (62,500 bps (bits / second)) using the first serial communication circuit (first serial communication circuit SR1), and communicates with the game control microcomputer (main control microcomputer 1160) at a second speed (31,250 bps (bits / second)) that is lower than the first speed using the second serial communication circuit (second serial communication circuit SR2). It is characterized by the following. According to this feature, the value control microcomputer communicates with an externally connected device at a first speed using a first serial communication circuit, and communicates with the game control microcomputer at a second speed lower than the first speed using a second serial communication circuit, thereby enabling communication to be carried out at a suitable speed depending on the content of the communication, and since the communication speeds of the two are different, it becomes difficult to analyze the communication, and fraud that may result from analyzing the communication can also be prevented.

[0014] The gaming machine of form 1-5 is the gaming machine according to form 1-1 or 1-2, The value control microcomputer (medal count control unit 171) communicates with the externally connected device (card unit 3) at a first speed (62500 bps (bits / second)) using the first serial communication circuit (first serial communication circuit SR1), The game control microcomputer (main control unit 161) communicates with the value control microcomputer (medal count control unit 171) at a second speed (187500 bps (bits / second)) that is higher than the first speed (62500 bps (bits / second)) using the first serial communication circuit (first serial communication circuit SR1). It is characterized by the following. According to this feature, the value control microcomputer communicates with the externally connected device at a first speed using a first serial communication circuit, and the game control microcomputer communicates with the value control microcomputer at a second speed that is higher than the first speed using the first serial communication circuit, thereby allowing communication to be carried out at a suitable speed depending on the content of the communication, and since the communication speeds of the two are different, it becomes difficult to analyze the communication, and fraud that may result from analyzing the communication can also be prevented.

[0015] The gaming machine of form 1-6 is the gaming machine according to form 1-1 or 1-2, The value control microcomputer (medal count control unit 171) communicates with the externally connected device (card unit 3) at a first speed (62,500 bps (bits / second)) using the first serial communication circuit (first serial communication circuit SR1), and communicates with the game control microcomputer (main control unit 161) at a second speed (187,500 bps (bits / second)) that is equal to or higher than the first speed (62,500 bps (bits / second)) using the second serial communication circuit (second serial communication circuit SR2). It is characterized by the following. According to this feature, the value control microcomputer communicates with an externally connected device at a first speed using a first serial communication circuit, and communicates with the game control microcomputer at a second speed that is higher than the first speed using a second serial communication circuit, thereby allowing communication to be carried out at a speed appropriate to the content of the communication, and since the communication speeds of the two are different, it becomes difficult to analyze the communication, and fraud that may result from analyzing the communication can also be prevented.

[0016] [Form 2] The gaming machine of type 2-1 is A gaming machine (slot machine 2 / pachinko gaming machine 1002) that can be used for gaming, A game control microcomputer (main control unit 161 / main control microcomputer 1160) that controls the game; A value control microcomputer (a medal count control unit 171 / a slot control microcomputer 1170) that controls the gaming value (credits / game balls) owned by the player; Equipped with The value control microcomputer (the medal count control unit 171 / frame control microcomputer 1170) can be connected to an external connection device (card unit 3 / card unit 1003) so as to be able to communicate with each other, The game control microcomputer (main control unit 161 / main control microcomputer 1160) and the value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) are both microcomputers of the same specifications having a first input terminal (RX0 terminal) capable of inputting a serial signal and a second input terminal (RX1 terminal) capable of inputting a serial signal, The game control microcomputer (main control unit 161 / main control microcomputer 1160) receives a serial signal from the value control microcomputer (medal number control unit 171 / frame control microcomputer 1170) at the first input terminal (RX0 terminal), The value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) receives a serial signal from the game control microcomputer (main control unit 161 / main control microcomputer 1160) at the second input terminal (RX1 terminal), and receives a serial signal from the externally connected device (card unit 3 / card unit 1003) at the first input terminal (RX0 terminal). It is characterized by the following. According to this feature, the game control microcomputer and the value control microcomputer are both microcomputers of the same specifications, having a first input terminal capable of inputting a serial signal and a second input terminal capable of inputting a serial signal, and since the input terminal through which the game control microcomputer inputs a serial signal from the value control microcomputer and the input terminal through which the value control microcomputer inputs a serial signal from the game control microcomputer are different, even when microcomputers of the same specifications are used as the game control microcomputer and the value control microcomputer, it is possible to prevent confusion between the program executed by the game control microcomputer and the program executed by the value control microcomputer.

[0017] The gaming machine of form 2-2 is the gaming machine according to form 2-1, The value control microcomputer (frame control microcomputer 1170) receives a serial signal from the externally connected device (card unit 1003) at a first speed (62500 bps (bits per second)) at the first input terminal (RX0 terminal), The game control microcomputer (main control microcomputer 1160) receives a serial signal from the value control microcomputer (frame control microcomputer 1170) at a second speed (31250 bps (bits / second)) lower than the first speed (62500 bps (bits / second)) at the first input terminal (RX0 terminal). It is characterized by the following. According to this feature, the value control microcomputer receives a serial signal from an externally connected device at a first speed at its first input terminal, and the game control microcomputer receives a serial signal from the value control microcomputer at a second speed that is lower than the first speed at its first input terminal, allowing communication to be carried out at a suitable speed depending on the content of the communication.In addition, since the communication speeds of the two are different, it becomes difficult to analyze the communication, and fraud that may occur due to analysis of the communication can also be prevented.

[0018] The gaming machine of form 2-3 is the gaming machine according to form 2-1, The value control microcomputer (frame control microcomputer 1170) receives a serial signal from the externally connected device (card unit 1003) at a first speed (62,500 bps (bits / second)) at the first input terminal (RX0 terminal), and receives a serial signal from the game control microcomputer (main control microcomputer 1160) at a second speed (31,250 bps (bits / second)) that is lower than the first speed (62,500 bps (bits / second)) at the second input terminal (RX1 terminal). It is characterized by the following. According to this feature, the value control microcomputer receives a serial signal from an externally connected device at a first speed at the first input terminal, and receives a serial signal from the game control microcomputer at a second speed that is lower than the first speed at the second input terminal, thereby enabling communication at a suitable speed depending on the content of the communication.In addition, since the communication speeds of the two are different, it becomes difficult to analyze the communication, and fraud that may result from analyzing the communication can also be prevented.

[0019] The gaming machine of form 2-4 is the gaming machine according to form 2-1, The value control microcomputer (medal count control unit 171) receives a serial signal from the external connection device (card unit 3) at a first speed (62500 bps (bits / second)) at the first input terminal (RX0 terminal), The game control microcomputer (main control unit 161) receives a serial signal from the value control microcomputer (medal count control unit 171) at the first input terminal (RX0 terminal) at a second speed (187500 bps (bits / second)) that is higher than the first speed (62500 bps (bits / second)). It is characterized by the following. According to this feature, the value control microcomputer receives a serial signal from an externally connected device at a first speed at its first input terminal, and the game control microcomputer receives a serial signal from the value control microcomputer at a second speed that is higher than the first speed at its first input terminal, allowing communication to be carried out at a suitable speed depending on the content of the communication.In addition, since the communication speeds of the two are different, it becomes difficult to analyze the communication, and fraud that may result from analyzing the communication can also be prevented.

[0020] The gaming machine of aspect 2-5 is the gaming machine according to aspect 2-1, The value control microcomputer (medal count control unit 171) receives a serial signal from the externally connected device (card unit 3) at a first speed (62,500 bps (bits / second)) at the first input terminal (RX0 terminal), and receives a serial signal from the game control microcomputer (main control unit 161) at a second speed (187,500 bps (bits / second)) that is equal to or higher than the first speed (62,500 bps (bits / second)) at the second input terminal (RX1 terminal). It is characterized by the following. According to this feature, the value control microcomputer receives a serial signal from an externally connected device at a first speed at the first input terminal, and receives a serial signal from the game control microcomputer at a second speed that is higher than the first speed at the second input terminal, thereby enabling communication at a suitable speed depending on the content of the communication.In addition, since the communication speeds of the two are different, it becomes difficult to analyze the communication, and fraud that may result from analyzing the communication can also be prevented.

[0021] [Form 3] The gaming machine of type 3-1 is A gaming machine (slot machine 2 / pachinko gaming machine 1002) that can be used for gaming, A game control microcomputer (main control unit 161 / main control microcomputer 1160) that controls the game; A value control microcomputer (a medal count control unit 171 / a slot control microcomputer 1170) that controls the gaming value (credits / game balls) owned by the player; Equipped with The value control microcomputer (the medal count control unit 171 / frame control microcomputer 1170) can be connected to an external connection device (card unit 3 / card unit 1003) so as to be able to communicate with each other, The game control microcomputer (main control unit 161 / main control microcomputer 1160) and the value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) are both microcomputers of the same specifications having a first output terminal (TX0 terminal) capable of outputting a serial signal and a second output terminal (TX1 terminal) capable of outputting a serial signal, The game control microcomputer (main control unit 161 / main control microcomputer 1160) outputs a serial signal from the first output terminal (TX0 terminal) to the value control microcomputer (medal number control unit 171 / frame control microcomputer 1170), The value control microcomputer (medal number control unit 171 / frame control microcomputer 1170) outputs a serial signal from the second output terminal (TX1 terminal) to the game control microcomputer (main control unit 161 / main control microcomputer 1160), and outputs a serial signal from the first output terminal (TX0 terminal) to the externally connected device (card unit 3 / card unit 1003). It is characterized by the following. According to this feature, the game control microcomputer and the value control microcomputer both use microcomputers of the same specifications, each having a first output terminal capable of outputting a serial signal and a second output terminal capable of outputting a serial signal, and since the output terminal through which the game control microcomputer outputs a serial signal to the value control microcomputer and the output terminal through which the value control microcomputer outputs a serial signal to the game control microcomputer are different, even when microcomputers of the same specifications are used as the game control microcomputer and the value control microcomputer, it is possible to prevent confusion between the program executed by the game control microcomputer and the program executed by the value control microcomputer.

[0022] The gaming machine of form 3-2 is the gaming machine according to form 3-1, The value control microcomputer (frame control microcomputer 1170) outputs a serial signal from the first output terminal (TX0 terminal) to the external connection device (card unit 1003) at a first speed (62500 bps (bits per second)), The game control microcomputer (main control microcomputer 1160) outputs a serial signal from the first output terminal (TX0 terminal) to the value control microcomputer (frame control microcomputer 1170) at a second speed (31250 bps (bits / second)) lower than the first speed (62500 bps (bits / second)). It is characterized by the following. According to this feature, the value control microcomputer outputs a serial signal from the first output terminal to the externally connected device at a first speed, and the game control microcomputer outputs a serial signal from the first output terminal to the value control microcomputer at a second speed that is lower than the first speed, thereby allowing communication to be carried out at a suitable speed depending on the content of the communication, and since the communication speeds of the two are different, it becomes difficult to analyze the communication, and fraud that may result from analyzing the communication can also be prevented.

[0023] The gaming machine of form 3-3 is the gaming machine according to form 3-1, The value control microcomputer (frame control microcomputer 1170) outputs a serial signal from the first output terminal (TX0 terminal) to the external connection device (card unit 1003) at a first speed (62,500 bps (bits / second)), and outputs a serial signal from the second output terminal (TX1 terminal) to the game control microcomputer (main control microcomputer 1160) at a second speed (31,250 bps (bits / second)) that is lower than the first speed (62,500 bps (bits / second)). It is characterized by the following. According to this feature, the value control microcomputer outputs a serial signal from the first output terminal to the externally connected device at a first speed, and outputs a serial signal from the second output terminal to the game control microcomputer at a second speed that is lower than the first speed, thereby allowing communication to be carried out at a suitable speed depending on the content of the communication, and since the communication speeds of the two are different, it becomes difficult to analyze the communication, and fraud that may result from analyzing the communication can also be prevented.

[0024] The gaming machine of form 3-4 is the gaming machine according to form 3-1, The value control microcomputer (medal count control unit 171) outputs a serial signal from the first output terminal (TX0 terminal) to the external connection device (card unit 3) at a first speed (62500 bps (bits / second)), The game control microcomputer (main control unit 161) outputs a serial signal from the first output terminal (TX0 terminal) to the value control microcomputer (medal count control unit 171) at a second speed (187500 bps (bits / second)) that is equal to or higher than the first speed (62500 bps (bits / second)). It is characterized by the following. According to this feature, the value control microcomputer outputs a serial signal from the first output terminal to the externally connected device at a first speed, and the game control microcomputer outputs a serial signal from the first output terminal to the value control microcomputer at a second speed that is higher than the first speed, thereby allowing communication to be carried out at a suitable speed depending on the content of the communication, and since the communication speeds of the two are different, it becomes difficult to analyze the communication, and fraud that may result from analyzing the communication can also be prevented.

[0025] The gaming machine of form 3-5 is the gaming machine according to form 3-1, The value control microcomputer (medal count control unit 171) outputs a serial signal from the first output terminal (TX0 terminal) to the external connection device (card unit 3) at a first speed (62,500 bps (bits / second)), and outputs a serial signal from the second output terminal (TX1 terminal) to the game control microcomputer (main control unit 161) at a second speed (187,500 bps (bits / second)) that is equal to or higher than the first speed (62,500 bps (bits / second)). It is characterized by the following. According to this feature, the value control microcomputer outputs a serial signal from the first output terminal to the externally connected device at a first speed, and outputs a serial signal from the second output terminal to the game control microcomputer at a second speed that is higher than the first speed, thereby allowing communication to be carried out at a suitable speed depending on the content of the communication, and since the communication speeds of the two are different, it becomes difficult to analyze the communication, and fraud that may occur due to analysis of the communication can also be prevented.

[0026] [Form 1~3] In the gaming machines of forms 1 to 3, the format of the data sent from the gaming control microcomputer (main control unit 161 / main control microcomputer 1160) to the value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) and the format of the data sent from the value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) to the gaming control microcomputer (main control unit 161 / main control microcomputer 1160) are the same (10-bit format (LSB first, no parity)). By configuring in this way, the format of the data that makes up commands can be made common between the gaming control microcomputer and the value control microcomputer.

[0027] In the gaming machines of forms 1 to 3, the format of the data sent from the value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) to the game control microcomputer (main control unit 161 / main control microcomputer 1160) and the format of the data sent from the value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) to the externally connected device (card unit 3 / card unit 1003) are the same (10-bit format (LSB first, no parity)). By configuring in this way, the format of the data constituting the commands sent by the value control microcomputer to the game control microcomputer and the externally connected device can be made common.

[0028] In the gaming machines of forms 1 to 3, the communication speed is set based on a clock signal, and the game control microcomputer (main control unit 161 / main control microcomputer 1160) and the value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) receive clock signals of the same frequency. This configuration makes it easier to set synchronized speeds.

[0029] In the gaming machines of forms 1 to 3, the communication between the game control microcomputer (main control unit 161 / main control microcomputer 1160) and the value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) is such that one sends communication data and the other sends response data. This configuration ensures reliable data transmission.

[0030] In the gaming machines of forms 1 to 3, data including multiple pieces of multi-byte numerical data (chip ID, manufacturer code, product code / main control chip ID number, main control CPU manufacturer code, main control CPU model code) can be transmitted as one command, and the multiple pieces of data that make up one command do not mix multi-byte numerical data transmitted in order from the lowest byte to the highest byte and multi-byte numerical data transmitted in order from the highest byte to the lowest byte.By configuring in this way, it is possible to standardize the management of the numerical data included in the multiple pieces of data that make up one command.

[0031] In the gaming machines of forms 1 to 3, data including multiple pieces of numerical data each consisting of multiple bytes (variable multiple-byte numerical data) can be transmitted as one command, and the multiple pieces of data that make up a specific command are all transmitted in the order of multiple-byte numerical data from the lowest byte to the highest byte. By adopting such a configuration, it is possible to standardize the management of the numerical data included in the multiple pieces of data that make up a specific command.

[0032] In gaming machines of forms 1 to 3, data including multiple pieces of multi-byte numerical data (chip ID, manufacturer code, product code / main control chip ID number, main control CPU manufacturer code, main control CPU model code) can be transmitted as one command, and the multiple pieces of data that make up a specific command are all transmitted in order from the least significant bit to the most significant bit. By configuring in this way, it is possible to standardize the management of the numerical data included in the multiple pieces of data that make up a specific command.

[0033] In the gaming machines of forms 1 to 3, data including multiple pieces of numerical data consisting of multiple bytes (chip ID, manufacturer code, product code / main control chip ID number, main control CPU manufacturer code, main control CPU model code) can be transmitted as one command, and the multiple pieces of data that make up a predetermined command are all transmitted in the order of multiple-byte numerical data from the most significant byte to the least significant byte. By adopting such a configuration, it is possible to standardize the management of the numerical data included in the multiple pieces of data that make up a predetermined command.

[0034] [Form 4] The gaming machine of type 4-1 is A gaming machine (slot machine 2 / pachinko gaming machine 1002) that can be used for gaming, A game control microcomputer (main control unit 161 / main control microcomputer 1160) that controls the game; A value control microcomputer (a medal count control unit 171 / a slot control microcomputer 1170) that controls the gaming value (credits / game balls) owned by the player; Equipped with The game control microcomputer (main control unit 161 / main control microcomputer 1160) and the value control microcomputer (medal number control unit 171 / frame control microcomputer 1170) are both based on the setting value (setting prescaler value) set in the first setting address (FF04h / FF01h) and are configured with a first counting means (second timer circuit TM2 / first timer circuit TM1) that can count by thinning out the supplied clock signal, and a second setting address (FF01h / FF04h) that is configured with a second timer circuit TM2 / first timer circuit TM1. a second counting means (first timer circuit TM1 / second timer circuit TM2) capable of counting by thinning out the clock signal supplied based on a set value (set prescaler value) set by the first counting means (second timer circuit TM2 / first timer circuit TM1), and an interrupt means capable of generating an interrupt when the count value of the first counting means (second timer circuit TM2 / first timer circuit TM1) reaches a predetermined number (set count value) or when the count value of the second counting means (first timer circuit TM1 / second timer circuit TM2) reaches a predetermined number (set count value), The game control microcomputer (main control unit 161 / main control microcomputer 1160) sets a value to the first setting address (FF04h / FF01h) and can generate an interrupt by the interrupt means using the first counting means (second timer circuit TM2 / first timer circuit TM1), The value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) sets a value to the first setting address (FF04h / FF01h) and can cause the interrupt means to generate an interrupt using the first counting means (second timer circuit TM2 / first timer circuit TM1). It is characterized by the following. According to this feature, when the game control microcomputer and the value control microcomputer both use microcomputers of the same specifications that have a first counting means capable of counting by thinning out the clock signal supplied based on a setting value set at a first setting address, a second counting means capable of counting by thinning out the clock signal supplied based on a setting value set at a second setting address, and an interrupt means capable of generating an interrupt when the counting value of the first counting means reaches a predetermined number or when the counting value of the second counting means reaches a predetermined number, the timer interrupt settings can be made common between the game control microcomputer and the value control microcomputer by setting a value at the first setting address and generating an interrupt using the interrupt means using the first counting means.

[0035] The gaming machine of type 4-2 is A gaming machine (slot machine 2 / pachinko gaming machine 1002) that can be used for gaming, A game control microcomputer (main control unit 161 / main control microcomputer 1160) that controls the game; A value control microcomputer (a medal count control unit 171 / a slot control microcomputer 1170) that controls the gaming value (credits / game balls) owned by the player; Equipped with The game control microcomputer (main control unit 161 / main control microcomputer 1160) and the value control microcomputer (medal number control unit 171 / frame control microcomputer 1170) are microcomputers of the same specifications, each having a countable first counting means (second timer circuit TM2 / first timer circuit TM1), a countable second counting means (first timer circuit TM1 / second timer circuit TM2), and interrupt means capable of generating an interrupt when the count value of the first counting means (second timer circuit TM2 / first timer circuit TM1) reaches a predetermined number (set count value) based on the set value of a first count value setting address (FF06h / FF03h), or when the count value of the second counting means (first timer circuit TM1 / second timer circuit TM2) reaches a predetermined number (set count value) based on the set value of a second count value setting address (FF03h / FF06h), The game control microcomputer (main control unit 161 / main control microcomputer 1160) sets a value to the first counting value setting address (FF06h / FF03h) and can generate an interrupt by the interrupt means using the first counting means (second timer circuit TM2 / first timer circuit TM1), The value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) sets a value to the first count value setting address (FF06h / FF03h) and can cause the interrupt means to generate an interrupt using the first counting means (second timer circuit TM2 / first timer circuit TM1). It is characterized by the following. According to this feature, when the game control microcomputer and the value control microcomputer both use microcomputers of the same specifications that have a first counting means that can count, a second counting means that can count, and an interrupt means that can generate an interrupt when the counting value of the first counting means reaches a predetermined number based on the set value of the first counting value setting address, or when the counting value of the second counting means reaches a predetermined number based on the set value of the second counting value setting address, the timer interrupt settings can be made common between the game control microcomputer and the value control microcomputer by setting a value in the first counting value setting address and using the first counting means to generate an interrupt by the interrupt means in both the game control microcomputer and the value control microcomputer.

[0036] The gaming machine of type 4-3 is A gaming machine (slot machine 2 / pachinko gaming machine 1002) that can be used for gaming, A game control microcomputer (main control unit 161 / main control microcomputer 1160) that controls the game; A value control microcomputer (a medal count control unit 171 / a slot control microcomputer 1170) that controls the gaming value (credits / game balls) owned by the player; Equipped with The game control microcomputer (main control unit 161 / main control microcomputer 1160) and the value control microcomputer (medal number control unit 171 / frame control microcomputer 1170) are each a countable first counting means (second timer circuit TM2 / first timer circuit TM1), a countable second counting means (first timer circuit TM1 / second timer circuit TM2), and a counting value of the first counting means (second timer circuit TM2 / first timer circuit TM1) that reaches a predetermined number (set count value), or and interrupt means capable of generating an interrupt when the count value of the second counting means (first timer circuit TM1 / second timer circuit TM2) reaches a predetermined number, wherein the first counting means (second timer circuit TM2 / first timer circuit TM1) starts counting when a value is set to a first start setting address (FF06h / FF03h), and the second counting means (first timer circuit TM1 / second timer circuit TM2) starts counting when a value is set to a second start setting address (FF03h / FF06h), and the microcomputers are of the same specification; The game control microcomputer (main control unit 161 / main control microcomputer 1160) can set a value to the first start setting address (FF06h / FF03h) to start counting of the first counting means (second timer circuit TM2 / first timer circuit TM1), and can cause the interrupt means to generate an interrupt using the first counting means (second timer circuit TM2 / first timer circuit TM1), The value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) sets a value to the first start setting address (FF06h / FF03h) to start counting by the first counting means (second timer circuit TM2 / first timer circuit TM1), and can cause the interrupt means to generate an interrupt using the first counting means (second timer circuit TM2 / first timer circuit TM1). It is characterized by the following. According to this feature, the game control microcomputer and the value control microcomputer both have a first counting means capable of counting, a second counting means capable of counting, and an interrupt means capable of generating an interrupt when the counting value of the first counting means reaches a predetermined number or when the counting value of the second counting means reaches a predetermined number, and the first counting means starts counting when a value is set to a first start setting address, and the second counting means starts counting when a value is set to a second start setting address.When using microcomputers with the same specifications, in both the game control microcomputer and the value control microcomputer, a value is set to the first start setting address to start counting by the first counting means, and an interrupt is generated by the interrupt means using the first counting means, thereby making it possible to standardize the timer interrupt settings between the game control microcomputer and the value control microcomputer.

[0037] The gaming machine of type 4-4 is A gaming machine (slot machine 2 / pachinko gaming machine 1002) that can be used for gaming, A game control microcomputer (main control unit 161 / main control microcomputer 1160) that controls the game; A value control microcomputer (a medal count control unit 171 / a slot control microcomputer 1170) that controls the gaming value (credits / game balls) owned by the player; Equipped with The game control microcomputer (main control unit 161 / main control microcomputer 1160) and the value control microcomputer (medal number control unit 171 / frame control microcomputer 1170) are both microcomputers with the same specifications that have counting means (second timer circuit TM2 / first timer circuit TM1) capable of counting, and interrupt means that can generate an interrupt when the count value of the counting means (second timer circuit TM2 / first timer circuit TM1) reaches a predetermined number (set count value), and that can identify the address of the processing to be executed when an interrupt occurs based on data (interrupt vector) stored in one of a plurality of areas (interrupt vector table) when an interrupt occurs by the interrupt means, When an interrupt occurs by the interrupt means, the game control microcomputer (main control unit 161 / main control microcomputer 1160) identifies the address of the process to be executed when the interrupt occurs based on the data (interrupt vector) stored in a specific area (address corresponding to timer interrupt 2 / address corresponding to timer interrupt 1) among multiple areas (interrupt vector table), The value control microcomputer (medal number control unit 171 / frame control microcomputer 1170) specifies the address of the process to be executed when an interrupt occurs based on the data (interrupt vector) stored in the specific area (address corresponding to timer interrupt 2 / address corresponding to timer interrupt 1) among multiple areas (interrupt vector table) when an interrupt occurs by the interrupt means. It is characterized by the following. According to this feature, the game control microcomputer and the value control microcomputer both have a counting means capable of counting and an interrupt means capable of generating an interrupt when the count value of the counting means reaches a predetermined number, and when using microcomputers of the same specifications that can identify the address of the processing to be executed when an interrupt occurs based on data stored in one of multiple areas when an interrupt occurs by the interrupt means, both the game control microcomputer and the value control microcomputer can identify the address of the processing to be executed when an interrupt occurs based on data stored in a specific area among the multiple areas when an interrupt occurs by the interrupt means, thereby making it possible to standardize the timer interrupt settings between the game control microcomputer and the value control microcomputer.

[0038] The gaming machine of form 4-5 is a gaming machine according to any one of forms 4-1 to 4-4, The frequency of the clock signal is the same between the game control microcomputer (main control unit 161) and the value control microcomputer (medal number control unit 171), The time intervals at which interrupts occur are different between the game control microcomputer (main control unit 161) and the value control microcomputer (medal number control unit 171), In setting the time interval for generating the interrupt, the game control microcomputer (main control unit 161) and the value control microcomputer (medal number control unit 171) have the same clock signal thinning rate (set prescaler value) in the counting means, and the value of the predetermined number (set count value) at which the interrupt means generates an interrupt when the count value of the counting means (second timer circuit TM2) reaches is different. It is characterized by the following. According to this feature, in a configuration in which the time intervals for interrupt generation differ between the game control microcomputer and the value control microcomputer, when setting the time intervals for interrupt generation, the thinning rate of the clock signal in the counting means is the same for the game control microcomputer and the value control microcomputer, and only the predetermined number value that the count value of the counting means reaches and causes the interrupt means to generate an interrupt is set to a different value, making it easier to check the setting for the time intervals for interrupt generation.

[0039] The gaming machine of form 4-5 is a gaming machine according to any one of forms 4-1 to 4-3, The clock signal frequency of the game control microcomputer (main control microcomputer 1160) and the value control microcomputer (frame control microcomputer 1170) is the same, The time intervals at which interrupts occur are different between the game control microcomputer (main control microcomputer 1160) and the value control microcomputer (frame control microcomputer 1170). In setting the time interval for generating the interrupt, the game control microcomputer (main control microcomputer 1160) and the value control microcomputer (frame control microcomputer 1170) have different thinning rates (set prescaler values) of clock signals in the counting means, and the value of the counting means (first timer circuit TM1) reaches a different value for the predetermined number (set count value) at which the interrupt means generates an interrupt. It is characterized by the following. According to this feature, in a configuration in which the time intervals for interrupt generation are different between the game control microcomputer and the value control microcomputer, when setting the time intervals for interrupt generation, the thinning rate of the clock signal in the counting means of the game control microcomputer and the value control microcomputer, as well as the predetermined number value that the counting value of the counting means reaches and causes the interrupt means to generate an interrupt, are set to different values, thereby preventing confusion between the setting regarding the time intervals for interrupt generation in the game control microcomputer and the setting regarding the time intervals for interrupt generation in the value control microcomputer.

[0040] In the gaming machine of form 4, the gaming control microcomputer (main control microcomputer 1160) and the value control microcomputer (frame control microcomputer 1170) are mounted on different boards, and clock signals of the same frequency are input to the gaming control microcomputer (main control microcomputer 1160) and the value control microcomputer (frame control microcomputer 1170) from separate clock generators (clock generation circuits SCLK1, SCLK2), and the separate clock generators (clock generation circuits SCLK1, SCLK2) are parts with the same model number and the same specifications. By using such a configuration, parts can be standardized, thereby reducing costs.

[0041] In the gaming machine of form 4, the game control microcomputer (main control unit 161) and the value control microcomputer (medal count control unit 171) are mounted on the same board (main control board 16), and clock signals are input to the game control microcomputer (main control unit 161) and the value control microcomputer (medal count control unit 171) from the same clock generator (clock generation circuit SCLK). By using such a configuration, the number of parts can be reduced, leading to cost savings.

[0042] In the gaming machine of form 4, the gaming control microcomputer (main control unit 161 / main control microcomputer 1160) and the value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) can set the priority of interrupts (priority of multiple interrupt causes), and the setting of the priority of interrupts (priority of multiple interrupt causes) is a common setting in both the gaming control microcomputer (main control unit 161 / main control microcomputer 1160) and the value control microcomputer (medal count control unit 171 / frame control microcomputer 1170). By configuring in this way, the timer interrupt setting can be made common between the gaming control microcomputer and the value control microcomputer.

[0043] In the gaming machine of form 4, the gaming control microcomputer (main control unit 161 / main control microcomputer 1160) and the value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) have multiple types of interrupt functions, and both the gaming control microcomputer (main control unit 161 / main control microcomputer 1160) and the value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) use only timer interrupts (timer interrupt 2 / timer interrupt 1) out of the multiple types of interrupt functions. By configuring in this way, interrupts are not generated unnecessarily, and processing does not become complicated.

[0044] In the gaming machine of form 4, the counting means (second timer circuit TM2 / first timer circuit TM1) starts counting when a value (set count value) is set in the start setting address (count value setting register), and while values ​​are set in multiple types of setting addresses (function setting registers) in the initial setting, the setting of the value (set count value) in the start setting address (count value setting register) is performed last. With this configuration, no interrupt occurs until other initial settings are completed.

[0045] In the gaming machine of form 4, the counting means (second timer circuit TM2 / first timer circuit TM1) starts counting when a value (set count value) is set in a start setting address (count value setting register), and after starting counting, stops counting when a value (set prescaler value) is set in a predetermined address (prescaler setting register) that sets the thinning rate of the clock signal, and while values ​​are set in multiple types of setting addresses (function setting registers) in the initial setting, after setting a value (set prescaler value) in the predetermined address (prescaler setting register), values ​​are set in other setting addresses (function setting registers), and then a value (set count value) is set in the start setting address (count value setting register).This configuration makes it possible to prevent counting from stopping unintentionally.

[0046] [Form 5] The gaming machine of type 5-1 is A gaming machine (slot machine 2 / pachinko gaming machine 1002) that can be used for gaming, A game control microcomputer (main control unit 161 / main control microcomputer 1160) that controls the game; A value control microcomputer (a medal count control unit 171 / a slot control microcomputer 1170) that controls the gaming value (credits / game balls) owned by the player; Equipped with The game control microcomputer (main control unit 161 / main control microcomputer 1160) and the value control microcomputer (medal number control unit 171 / frame control microcomputer 1170) are both microcomputers of the same specifications that have storage means (ROM, RAM, registers) that can read data from areas to which common addresses are assigned, The storage means of the game control microcomputer (main control unit 161 / main control microcomputer 1160) stores specific information (chip ID, manufacturer code, product code / main control chip ID number, main control CPU manufacturer code, main control CPU model code) at specific addresses (FE94h-FE9Bh, 3FC8h-3FCAh, 3FCBh-3FD2h), The storage means of the value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) stores the specific information (chip ID, manufacturer code, product code / frame control chip ID number, frame control CPU manufacturer code, frame control CPU model code) at the specific addresses (FE94h-FE9Bh, 3FC8h-3FCAh, 3FCBh-3FD2h), When starting game control, the game control microcomputer (main control unit 161 / main control microcomputer 1160) reads out the specific information (chip ID, manufacturer code, product code / frame control chip ID number, frame control CPU manufacturer code, frame control CPU model code) stored in the specific addresses (FE94h-FE9Bh, 3FC8h-3FCAh, 3FCBh-3FD2h), and transmits a specific information command (gaming machine installation information command / gaming machine installation information notification) including the specific information to the value control microcomputer (medal count control unit 171 / frame control microcomputer 1170). It is characterized by the following. According to this feature, the game control microcomputer and the value control microcomputer both use microcomputers of the same specifications that have storage means capable of reading data from an area assigned a common address, and the specific information contained in the specific information command is stored in the same specific address in both the game control microcomputer and the value control microcomputer, making it easy to manage the specific information.

[0047] The gaming machine of form 5-2 is the gaming machine according to form 5-1, The gaming control microcomputer (main control unit 161 / main control microcomputer 1160) transmits information regarding gaming control (insertion command, settlement command, payout command / gaming machine information notification) to the value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) on the condition that the value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) has validly received the specific information command (gaming machine installation information command / gaming machine installation information notification). It is characterized by the following. According to this feature, control can be performed while ensuring that the game control microcomputer and the value control microcomputer can communicate normally.

[0048] The gaming machine of form 5-3 is the gaming machine according to form 5-1 or 5-2, The value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) transmits information regarding value control (medal count control information command / gaming machine information response) to the game control microcomputer (main control unit 161 / main control microcomputer 1160) on the condition that the specific information command (gaming machine installation information command / gaming machine installation information notification) has been validly received from the game control microcomputer (main control unit 161 / main control microcomputer 1160). It is characterized by the following. According to this feature, control can be performed while ensuring that the game control microcomputer and the value control microcomputer can communicate normally.

[0049] The gaming machine of form 5-4 is a gaming machine according to any one of forms 5-1 to 5-3, The value control microcomputer (medal number control unit 171 / frame control microcomputer 1170) receives information about game control (insertion command, settlement command, payout command / game machine information notification) transmitted from the game control microcomputer (main control unit 161 / main control microcomputer 1160) on the condition that the specific information command (game machine installation information command / game machine installation information notification) has been effectively received from the game control microcomputer (main control unit 161 / main control microcomputer 1160). It is characterized by the following. According to this feature, control can be performed while ensuring that the game control microcomputer and the value control microcomputer can communicate normally.

[0050] The gaming machine of form 5-5 is a gaming machine according to any one of forms 5-1 to 5-4, The value control microcomputer (the medal count control unit 171 / frame control microcomputer 1170) can be connected to an external connection device (card unit 3 / card unit 1003) so as to be able to communicate with each other, The value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) transmits information (counting information) regarding the gaming value owned by the player to the externally connected device (card unit 3 / card unit 1003) on the condition that the specific information command (gaming machine installation information command / gaming machine installation information notification) has been validly received from the gaming control microcomputer (main control unit 161 / main control microcomputer 1160). It is characterized by the following. According to this feature, control can be performed while ensuring that the game control microcomputer and the value control microcomputer can communicate normally.

[0051] The gaming machine of form 5-6 is a gaming machine according to any one of forms 5-1 to 5-5, The value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) accepts the player's operation (counting operation) regarding the gaming value owned by the player on the condition that the specific information command (gaming machine installation information command / gaming machine installation information notification) has been validly received from the gaming control microcomputer (main control unit 161 / main control microcomputer 1160). It is characterized by the following. According to this feature, control can be performed while ensuring that the game control microcomputer and the value control microcomputer can communicate normally.

[0052] The gaming machine of form 5-7 is the gaming machine according to any one of forms 5-1 to 5-6, The value control microcomputer (medal number control unit 171 / frame control microcomputer 1170) performs specific notification (white lighting of counting LED 10a / white lighting of counting LED 1028c) until it effectively receives the specific information command (gaming machine installation information command / gaming machine installation information notification) from the game control microcomputer (main control unit 161 / main control microcomputer 1160). It is characterized by the following. According to this feature, it is possible to externally check whether the game control microcomputer and the value control microcomputer are in a state where they can communicate normally.

[0053] The gaming machine of form 5-8 is a gaming machine according to any one of forms 5-1 to 5-7, The value control microcomputer (the medal count control unit 171 / frame control microcomputer 1170) can be connected to an external connection device (card unit 3 / card unit 1003) so as to be able to communicate with each other, The value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) stores the specific information (chip ID, manufacturer code, product code / main control chip ID number, main control CPU manufacturer code, main control CPU model code) included in the specific information command (gaming machine installation information command / gaming machine installation information notification) received from the gaming control microcomputer (main control unit 161 / main control microcomputer 1160) in a specific area that is initialized each time control is started (power is turned on), and transmits the stored specific information (chip ID, manufacturer code, product code / main control chip ID number, main control CPU manufacturer code, main control CPU model code) to the externally connected device (card unit 3 / card unit 1003). It is characterized by the following. According to this feature, each time control is started, the externally connected device can determine whether the game control microcomputer and the value control microcomputer are in a state where they can communicate normally.

[0054] The gaming machine of form 5-9 is the gaming machine according to form 5-8, The value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) converts the specific information (chip ID, manufacturer code, product code / frame control chip ID number, frame control CPU manufacturer code, frame control CPU model code) stored in the specific addresses (FE94h to FE9Bh, 3FC8h to 3FCAh, 3FCBh to 3FD2h) of the storage means of the value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) into the specific information (chip ID, manufacturer code, product code / main control chip ID number, main control CPU manufacturer code, main control CPU model code) included in the specific information command (gaming machine installation information command / gaming machine installation information notification) in the specific area. The specific information (chip ID, manufacturer code, product code / frame control chip ID number, frame control CPU manufacturer code, frame control CPU model code) stored in the specific address (FE94h to FE9Bh, 3FC8h to 3FCAh, 3FCBh to 3FD2h) stored in the specific area and the specific information (chip ID, manufacturer code, product code / main control chip ID number, main control CPU manufacturer code, main control CPU model code) included in the specific information command (gaming machine installation information command / gaming machine installation information notification) are transmitted to the externally connected device (card unit 3 / card unit 1003). It is characterized by the following. According to this feature, both the specific information stored in the game control microcomputer and the specific information stored in the value control microcomputer can be identified on the externally connected device side.

[0055] In the gaming machine of form 5, the gaming control microcomputer (main control microcomputer 1160) performs an initial setting process when the power is turned on, and after the initial setting process is completed, performs a process for transmitting the specific information command (gaming machine installation information notification) to the value control microcomputer (frame control microcomputer 1170). With this configuration, the specific information command is not transmitted until the initial setting process is completed and gaming control becomes possible.

[0056] In the gaming machine of form 5, the gaming control microcomputer (main control microcomputer 1160) performs a first initial setting process (a process of restoring the state before the power failure based on backup data) when a first condition (when the clear switch 1071 is not in the on state) is set when the power is turned on, and a second initial setting process (a process of initializing the backup data) when a second condition (when the clear switch 1071 is in the on state) is set. When the first initial setting process is performed, after the first initial setting process (a process of restoring the state before the power failure based on backup data) is completed, a process is performed to send the specific information command (gaming machine installation information notification) to the value control microcomputer (frame control microcomputer 1170). When the second initial setting process is performed, after the second initial setting process (a process of initializing the backup data) is completed, a process is performed to send the specific information command (gaming machine installation information notification) to the value control microcomputer (frame control microcomputer 1170). With this configuration, regardless of which initial setting process is performed, the specific information command is not sent until the initial setting process is completed and gaming control is possible.

[0057] In the gaming machine of form 5, the value control microcomputer (the medal count control unit 171 / frame control microcomputer 1170) performs an initial setting process when the power is turned on, and after the initial setting process is completed, performs a process to receive the specific information command (gaming machine installation information command / gaming machine installation information notification). By configuring in this way, the specific information command will not be received until the initial setting process is completed and control becomes possible.

[0058] In the gaming machine of form 5, the value control microcomputer (the medal count control unit 171 / frame control microcomputer 1170) executes a process of initializing the specific area in the initial setting process. By adopting such a configuration, the specific information included in the specific information command can be stored in the specific area initialized in the initial setting process.

[0059] In the gaming machine of form 5, the value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) executes a process of storing, in the initial setting process, the specific information (chip ID, manufacturer code, product code / frame control chip ID number, frame control CPU manufacturer code, frame control CPU model code) stored in the specific addresses (FE94h-FE9Bh, 3FC8h-3FCAh, 3FCBh-3FD2h) of the storage means of the value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) in the specific area. By configuring in this way, the specific information stored in the specific addresses of the storage means can be stored in the specific area initialized in the initial setting process.

[0060] In the gaming machine of form 5, the specific information is a microcomputer manufacturer code, and the specific information command (gaming machine installation information command / gaming machine installation information notification) includes, in addition to the specific information, an individual number of the microcomputer and a microcomputer product code (chip ID, manufacturer code, product code / main control chip ID number, main control CPU manufacturer code, main control CPU model code). By adopting such a configuration, multiple pieces of information related to the gaming control microcomputer can be shared between the value control microcomputer side and the externally connected device side.

[0061] In the gaming machine of form 5, when the value control microcomputer (frame control microcomputer 1170) has validly received the specific information command (gaming machine installation information notification), it transmits a specific information response command (gaming machine installation information response) to the gaming control microcomputer (main control microcomputer 1160), and the gaming control microcomputer (main control microcomputer 1160) determines that it has validly received the specific information response command (gaming machine installation information response). With this configuration, the gaming control microcomputer can determine that the specific information command has been validly received on the value control microcomputer side.

[0062] In the gaming machine of form 5, the gaming control microcomputer (main control unit 161 / main control microcomputer 1160) executes processing related to gaming control on the condition that the value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) has validly received the specific information command (gaming machine installation information command / gaming machine installation information notification) (permits gaming operations such as bet number setting operation, settlement operation, and start operation, and enters a state in which the game can be started / processing related to gaming control, detection processing of switches related to gaming, signal output processing, update processing of various counters, etc. are performed, and the game can be played). With this configuration, control can be performed while ensuring that the gaming control microcomputer and value control microcomputer can communicate normally.

[0063] In the gaming machine of form 5, when the value control microcomputer (frame control microcomputer 1170) receives the specific information command (gaming machine installation information notification), it determines whether or not the information included in the previously received specific information command (gaming machine installation information notification) matches the information included in the currently received specific information command (gaming machine installation information notification). By configuring in this way, it can be confirmed that the gaming control microcomputer has not been replaced.

[0064] In the gaming machine of form 5, the gaming control microcomputer (main control unit 161) performs an initial setting process when the power is turned on, and before the initial setting process is completed, performs a process for transmitting the specific information command (gaming machine installation information command) to the value control microcomputer (medal count control unit 171). By adopting such a configuration, it is possible to quickly confirm that communication is possible on the value control microcomputer side.

[0065] In the gaming machine of form 5, the gaming control microcomputer (main control unit 161) determines whether or not a setting change operation (on state of the setting key switch 37) has been performed when the power is turned on, and when it determines that the setting change operation (on state of the setting key switch 37) has been performed, it transitions to a setting change state, and performs processing to send the specific information command (gaming machine installation information command) to the value control microcomputer (medal count control unit 171) before determining whether or not the setting change operation (on state of the setting key switch 37) has been performed. By configuring in this way, it is possible to quickly confirm that communication is possible on the value control microcomputer side.

[0066] In the gaming machine of form 5, the gaming control microcomputer (main control unit 161 / main control microcomputer 1160) and the value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) can both be set with a delay time (security time) that delays the start of control when powered on, and the gaming control microcomputer (main control unit 161 / main control microcomputer 1160) has a delay time (security time) set, while the value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) does not have a delay time (security time). By configuring in this way, it is possible to ensure that the value control microcomputer starts up before the gaming control microcomputer.

[0067] In the gaming machine of form 5, the gaming control microcomputer (main control unit 161 / main control microcomputer 1160) and the value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) can both be set to a delay time (security time) that delays the start of control when powered on, and the gaming control microcomputer (main control unit 161 / main control microcomputer 1160) has its delay time (security time) set to a first time, while the value control microcomputer (medal count control unit 171 / frame control microcomputer 1170) has its delay time (security time) set to a second time that is shorter than the first time. This configuration ensures that the value control microcomputer starts up before the gaming control microcomputer. [Example]

[0068] [Slot machine configuration] FIG. 1 is a front view of a card unit as an externally connected device and a slot machine as a gaming machine of the first embodiment.

[0069] Referring to Figure 1, a slot machine 2 is installed in each of a plurality of gaming islands (not shown) arranged in an amusement hall (hall), and a card unit (hereinafter sometimes abbreviated as CU) 3, which is an example of a gaming device, is installed in a one-to-one correspondence with the slot machine 2 at a predetermined side position of the slot machine 2. The card unit is also called a "game medal lending device."

[0070] The slot machine 2 is a slot machine in which the player does not pick up medals and insert them into an insertion slot, and medals are not paid out to the player. Therefore, the gaming value is directly added to credits (gaming points (hereinafter referred to as "gaming medals" or simply "medals") that can be used in games) according to lending operations, etc.

[0071] Unlike conventional slot machines, these machines not only lack a medal slot or payout outlet, but also do not require a medal selector, hopper, or other device for controlling inserted medals.Such slot machines, which do not require any medals at all, are called "controlled gaming machines" or "medalless slot machines."

[0072] 1 shows a slot machine 2 as viewed from the front (front) side. Inside the slot machine 2, reels 2L, 2C, and 2R (hereinafter also referred to as the left reel, center reel, and right reel) with multiple types of symbols arranged around their outer periphery are arranged side by side in a horizontal direction, and three consecutive symbols among the symbols arranged on these reels 2L, 2C, and 2R are arranged so that they can be seen through a transparent window 3W.

[0073] The reels 2L, 2C, and 2R are rotated by the reel motors 32L, 32C, and 32R provided correspondingly, respectively, as shown in Fig. 2. As a result, the symbols on the reels 2L, 2C, and 2R are displayed in a continuously changing manner in the transparent window 3W. Furthermore, by stopping the rotation of the reels 2L, 2C, and 2R, three consecutive symbols are derived and displayed in the transparent window 3W as a display result.

[0074] Reel LEDs 55 shown in Fig. 2 are provided inside the reels 2L, 2C, and 2R. The reel LEDs 55 illuminate the reels 2L, 2C, and 2R shown in Fig. 1 from behind. The reel LEDs 55 are made up of 12 LEDs corresponding to the three consecutive symbols on the reels 2L, 2C, and 2R, and can illuminate each symbol independently.

[0075] A display area of ​​a liquid crystal display 51 is located in front of each of the reels 2L, 2C, and 2R (on the player's side). The liquid crystal display 51 has a transparent area corresponding to the transparent window 3W of the display area, and each of the reels 2L, 2C, and 2R can be seen from the player's side through the transparent window 3W.

[0076] On each reel, a plurality of different types of individually identifiable symbols are arranged in a predetermined order.

[0077] The protrusion 95 protrudes toward the front side of the slot machine 2. By protruding the protrusion 95 toward the front side of the slot machine 2, an upper surface 96 is formed on the protrusion 95. The upper surface 96 of the protrusion 95 is provided with a MAXBET switch 6, a 1BET switch 20, a bet number clear switch 21, a performance switch 57, a credit indicator 11, and a game information display unit 90, and the front side of the protrusion 95 is provided with a start switch 7, stop switches 8L, 8C, and 8R, and a counting button 10. The credit indicator 11 displays the number of credits held by the player. The upper surface 96 may be a sloped surface that slopes gently from the back to the front from a position below the transparent window 3W.

[0078] The start switch 7 is a switch for starting the reels to spin after the bet number has been set. The stop switches 8L, 8C, and 8R are switches for stopping the reels while they are spinning, with 8L corresponding to the left reel, 8C corresponding to the center reel, and 8R corresponding to the right reel. The count button 10 is a switch that is operated to count the number of credits (number of game medals) and convert it into the number of medals held.

[0079] A door-open detection switch 25 shown in FIG. 2 is provided inside the front door of the slot machine 2. The door-open detection switch 25 detects whether the front door is open. Furthermore, a power supply box is provided inside the housing. A setting key switch 37 and a reset / setting switch 38 shown in FIG. 2 are provided on the front of the power supply box. The setting key switch 37 switches between a setting change state and a setting confirmation state. The reset / setting switch 38 normally functions as a reset switch for canceling an error state or a stop state, and in the setting change state functions as a setting switch for changing the set value of the winning probability (ball payout rate) of the internal lottery. A setting value display 24 shown in FIG. 2 is provided inside the front door of the slot machine 2.

[0080] In this embodiment, the first reel to stop among the three reels 2L, 2C, and 2R that have started spinning is referred to as the first stopped reel, and its stop is referred to as the first stop. Similarly, the second reel to stop is referred to as the second stopped reel, and its stop is referred to as the second stop, and the third reel to stop is referred to as the third stopped reel, and its stop is referred to as the third stop, final stop, or all reels stop.

[0081] Next, we will explain the flow of the game in the slot machine 2. When playing a game in the slot machine 2, first, a lending operation is performed in the CU 3 to secure credits (game medals). This lending operation corresponds to the two-step operation of "lending medals" and "manually inserting the loaned medals into the slot" in a conventional slot machine that uses a medal payout system.

[0082] If the MAXBET switch 6 is operated when credits are present, the maximum number of bets within the credit range is added, and the number of credits is reduced by the added amount. Once the specified number of bets is set, the pay line L becomes active, and operation of the START switch 7 becomes active, i.e., the game can be started.

[0083] Here, the winning line is a line set to determine whether the combination of symbols displayed in the transparent window 3W of each reel 2L, 2C, and 2R is a winning combination. In this embodiment, as shown in Figure 1, the winning line is the winning line L set across the symbols lined up on the bottom row of reel 2L, the middle row of reel 2C, and the bottom row of reel 2R.

[0084] When the start switch 7 is operated while the game is ready to start, the reels 2L, 2C, and 2R spin, and the symbols on each reel 2L, 2C, and 2R change continuously. When any of the stop switches 8L, 8C, and 8R is operated in this state, the rotation of the corresponding reel 2L, 2C, and 2R stops, and the display result is derived and displayed in the transparent window 3W.

[0085] A game ends when all reels 2L, 2C, and 2R come to a stop, and a win occurs when a predetermined combination of symbols on the payline L stops as a result of the display of each reel 2L, 2C, and 2R. When a win occurs, the player is awarded a number of points determined according to the win. These points are added to the player's credits.

[0086] Credits can be counted and converted into owned medals by operating the count button 10. By converting into owned medals, it becomes possible to record the owned medals on a card at the end of a game.

[0087] In this embodiment, when the count button 10 is pressed once, all of the credits currently owned by the player are counted, regardless of the time the button is pressed (whether it is pressed and held down or not). However, this is not limiting, and the counting operation may be repeatedly executed according to the time the count button 10 is pressed (for example, the counting process of 50 coins is executed every time the count button is pressed for 0.3 seconds). Furthermore, regardless of the time the button is pressed, a predetermined number (for example, 50 coins) of credits may be counted into the player's medals when the button is pressed once.

[0088] The count button 10 also has a built-in count LED 10a (see FIG. 2) that lights up in blue when the operation of the count button 10 is valid, and goes out when the operation of the count button 10 is invalid.

[0089] A credit display segment 7S and speakers 53 and 54 are provided at the top of the LCD 51. The credit display segment 7S is made up of five 7-segment displays and displays the amount of credits held by the player. By being provided at the top of the slot machine 2, the credit display segment 7S can display the amount of credits stored in the slot machine 2 to players other than the player playing with the slot machine 2 or to store clerks. The speakers 53 and 54 emit sound effects and the like that accompany the presentation.

[0090] As described above, the MAXBET switch 6 is a switch used to maximize the number of bets. That is, the MAXBET switch 6 is used to progress the game. In addition, the MAXBET switch 6 in this embodiment is also used for presentation purposes. That is, when the same operation is performed on the MAXBET switch 6, different processing is executed depending on whether the operation is a valid operation or an invalid operation. In this way, the MAXBET switch 6 is used both for progress of the game and presentation purposes.

[0091] The following describes valid and invalid operations of the MAXBET switch 6. A valid operation of the MAXBET switch 6 is an operation performed on the MAXBET switch 6 in a bet setting status in which a bet can be set. The bet setting status is, for example, a period in which a bet can be accepted, such as "a status in which one or more credits remain and a bet of less than three coins has been set" or "a status in which one or more credits remain and no bet has been set." When the MAXBET switch is operated in a status in which one or more credits remain and a bet of less than three coins has been set in the bet counter, the bet is set to the remaining credits, up to a maximum of three coins. When the MAXBET switch is operated in a status in which one or more credits remain and no bet has been set, the bet is set to the remaining credits, up to a maximum of three coins. In this way, the MAXBET switch 6 is used as a switch for progressing the game by performing a valid operation in a bet setting status to set the bet.

[0092] On the other hand, an invalid operation of the MAXBET switch 6 refers to an operation performed on the MAXBET switch 6 in a bet setting impossible situation where a bet cannot be set. The bet setting impossible situation includes "the period from the start to the end of a game." In other words, an operation on the MAXBET switch 6 is invalid while the reels are spinning and a game is being played. In this embodiment, the slot machine 2 may display an operation prompting the player to invalidate the MAXBET switch 6 while the reels are spinning. When the player invalidates the MAXBET switch 6, an effect is generated, such as an image suggesting the degree of advantage. In this way, the MAXBET switch 6 in this embodiment is used as a trigger for displaying an effect image when an invalid operation is performed in a bet setting impossible situation. In other words, the MAXBET switch 6 is used to progress the game during the period when valid operations are accepted, and is used for effect generation during the period when invalid operations are accepted.

[0093] [Card unit configuration] The configuration of the CU 3 according to this embodiment will be described with reference to Figure 1. This CU 3 accepts visitor cards (also called general cards) with prepaid functions, which are gaming storage media issued to general players who are not registered as members, and member cards, which are gaming storage media issued to member players who are registered as members of the gaming facility. Visitor cards and member cards are composed of IC cards.

[0094] CU3, which accepts these cards, has the function of converting the gaming value owned by the player (e.g., prepaid balance, number of medals held, or number of medals saved (also called "number of saved balls")) identified by the information stored on the card into the number of credits (number of gaming medals).

[0095] The front side of CU3 is provided with a bill insertion slot 302 for inserting bills, a protruding portion 305 formed to protrude forward from the front of the device, and a card insertion / ejection slot 309 for inserting a membership card or visitor card. A membership card or visitor card inserted into this card insertion / ejection slot 309 is received by a card reader / writer (not shown), and the information recorded on the card is read.

[0096] The surface of the aforementioned extension 305 facing the player is provided with a display 312, a replay button 319 for executing a replay game using the membership card ID (also simply referred to as card ID or C-ID) recorded on the membership card when the membership card is accepted and the number of medals (number of balls) identified by the membership card ID, and an IR photosensitive unit 320 for receiving infrared signals from a remote control (not shown) carried by an attendant at the amusement facility, converting the signals into electronic signals, and outputting the signals.

[0097] The display 312 can display the prepaid balance (also called the card balance or simply the balance) recorded on the inserted gaming recording medium (card), the number of medals held, the number of credits (number of gaming medals), and other various information, and its surface is made up of a transparent touch panel. It is configured so that various operations can be input by touching the various display items displayed on the display section of the display 312 with a finger.

[0098] When the owned medal button 324 is operated, part of the number of owned medals recorded on the inserted card is withdrawn and converted into the number of credits (number of game medals). When the replay button 319 is operated, if the number of owned medals acquired by the player is stored on the inserted card, part of the number of owned medals is withdrawn and converted into credits, and the player can play games on the slot machine 2 based on the converted credits.

[0099] On the other hand, if the inserted card is a membership card and does not store the number of medals held, but the medals stored in the hall management computer or the like, some of the medals are withdrawn and converted into credits, allowing play on the slot machine 2. In other words, if both the medals held and the medals held are stored in association with the inserted card, the medals held are withdrawn first. Note that a dedicated medal payout button for withdrawing the medals held may be provided in addition to the replay button 319, and the replay button 319 may be used as a dedicated button for withdrawing the medals held.

[0100] Here, the "number of credits (number of game medals)" is data that can be used to set the bet amount and can also be converted into the "number of medals in hand." The "number of credits" is generated in exchange for withdrawing the balance of a prepaid card, the number of medals in hand, or the number of medals saved.

[0101] The "number of medals in possession" is a numerical conversion of the number of credits (number of game medals) that a player has acquired as a result of playing a slot machine. This "number of medals in possession" is stored so as to be identifiable by the player's card. The number of medals in possession may also be managed by a management device for managing the number of medals in possession that is set up in the gaming facility.

[0102] "Number of saved medals (number of saved balls)" refers to the number of medals that a player has deposited in the gaming parlor. The number of medals that a player has acquired through playing is managed as the number of saved medals on the day, but is managed as the "number of saved medals" from the day after the acquisition. In other words, the number of credits (number of game medals) that a player has acquired and counted at the gaming parlor on the day is called "credit points," and the number of medals that a player has acquired and deposited in the gaming parlor on or before the day before is called the "number of saved medals." This "number of saved medals" is generally managed by a hall management computer or other management computer installed in the gaming parlor.

[0103] The direction in which each of the above data, "Balance," "Number of saved medals (number of saved balls)," "Number of medals held," and "Number of credits (number of game medals)," can be converted is shown by arrows as follows: "Balance, number of saved medals, number of medals held" → "Number of credits" → "Number of medals held" → "Number of saved medals."

[0104] In this embodiment, the medal count data is not recorded directly on the membership card, but is stored in a host server such as a hall management computer in association with the membership card number, so that the corresponding medal count can be retrieved based on the membership card number. On the other hand, the medal count is recorded directly on the card.

[0105] However, both may be stored in the upper server in association with the card number. In the case of a visitor card, the number of medals held is also recorded directly on the visitor card. However, the number of medals held may also be stored in the upper server in association with the card number. When storing the number in association with the card number in this upper server, data that can identify the time when the number was stored in the upper server may be written to the card (membership card, visitor card) and then discharged. In addition, the prepaid balance is written directly to the card (membership card, visitor card) and then discharged.

[0106] The number of medals held is stored in the card (membership card, visitor card) or in the upper server, for example, when the counting button 10 is operated to perform the counting process. However, instead of this, the number of medals held may be stored all at once when the card is returned.

[0107] Also, when a player finishes playing and returns the card from CU3, the medals stored in CU3 are temporarily stored in the hall server as saved balls, and when the player inserts the card again into the same or another CU3 on the same day that the card is returned, only the medals for that day that were temporarily stored as saved balls are stored again in that CU3, and credits are added within the range of the medals that are stored, allowing the player to play.

[0108] A bill inserted into the bill insertion slot 302 is taken in by a currency validator (not shown) and its authenticity and bill type are identified.

[0109] Further provided on the front side of CU3 are a lending button 321 and a card return button 322. The lending button 321 is a button operated to withdraw the balance recorded on the inserted card to obtain the number of credits. Specifically, by operating the lending button 321, the number of credits is added according to the balance withdrawn. The card return button 322 is an operation button operated when the player ends a game, to store in the inserted card the determined number of medals held at the end of the game (number of medals held at the time of card insertion - number of medals converted from number of medals to number of credits + number counted by the counting operation) and then discharge the card.

[0110] As explained above, according to the slot machine 2 of this embodiment, the number of medals held, as specified by the card, is converted into the number of credits (number of game medals), and the number of bets can be set using the number of credits. Therefore, it is possible to provide a new slot machine (managed game machine) that does not use medals for play, without causing confusion to players who are accustomed to conventional slot machines in which medals are loaned to them, credits are secured by inserting the medals, and the number of bets is set using the credits.

[0111] [Internal structure of the card unit and slot machine] 2 is a block diagram showing the internal configuration of the card unit and the slot machine 2. An outline of the control circuits of the card unit 3 and the slot machine 2 will be described with reference to FIG.

[0112] The CU3 is provided with a CU control board 32, which is provided with a CU control unit 323 configured with a microcomputer, etc. The CU control unit 323 is the main control function unit of the CU3, and is provided with a CPU as the control center, a ROM that stores programs and control data for the CPU to operate, a RAM that functions as a work area for the CPU, an input / output interface that maintains signal consistency with peripheral devices, etc.

[0113] The CU control unit 323 is provided with an external output terminal (not shown) for communicating with a hall management computer and a hall server that performs security management. The CU3 transmits the status of the CU3 and gaming machine status information received from the slot machine 2 to an external device such as a hall management computer (hall computer) or a hall server that performs security management via the external output terminal. The CU control unit 323 communicates with the medal count control unit 171 of the slot machine 2 via a communication control IC 325. The communication control IC 325 and the medal count control unit 171 are connected, for example, by an asynchronous serial communication port. The communication between the communication control IC 325 and the medal count control unit 171 is performed via a connection terminal board 1000.

[0114] The communication between the CU control unit 323 and the medal count control unit 171 is two-way, exchanging loan information (information regarding the operation for withdrawing the balance stored in the inserted card and using it for playing on the slot machine 2) and loan response information (information regarding the response to the loan information), while other counting information (information regarding the counting process from credit to owned medals) and gaming machine information are communicated one-way from the medal count control unit 171 to the CU control unit 323. Therefore, the slot machine 2 does not recognize whether or not the CU3 has received the counting information and gaming machine information. The CU3 is provided with a connection unit (not shown) to the slot machine 2, and the slot machine 2 is provided with a connection unit (not shown) to the CU3. These connection units are composed of, for example, connectors.

[0115] The CU control unit 323 manages and stores the medals held by the player while the player is playing. The display 312 displays an image corresponding to data such as the balance or number of medals held output from the CU control unit 323. When the player operates the touch panel provided on the surface of the display 312, the operation signal is input to the CU control unit 323. When the player operates the lending button 321, the operation signal is input to the CU control unit 323. Note that the lending button 321 is not limited to being provided in the CU 3, and may be provided in the slot machine 2 and input an operation signal to the CU control unit 323. When the player operates the card return button 322, the operation signal is input to the CU control unit 323.

[0116] The slot machine 2 is provided with a main control unit 161 that controls the progress of the game on the slot machine 2, a medal count control unit 171 that controls the credits owned by the player, a performance control unit 151 that controls the performance according to the game status, and a power supply board 101. The power supply board 101 generates power to drive the electrical components that make up the slot machine 2 and supplies it to each unit.

[0117] The power supply board 101 is supplied with AC 100V power from an external source, and this AC 100V power generates the DC voltage required to drive the electrical components that make up the slot machine 2, which is then supplied to the main control unit 161, medal count control unit 171 mounted on the main control board 16, and performance control unit 151 mounted on the performance control board 15.

[0118] The medal count control unit 171 mounted on the main control board 16 is a microcomputer equipped with a CPU 171a as the control center, a ROM 171b that stores programs and control data for the CPU 171a to operate, a RAM 171c that functions as a work area for the CPU 171a, and an input / output interface for maintaining signal consistency with peripheral devices.

[0119] A RAM clear switch 293 for erasing information stored in the RAM 171c and a door open detection switch 25 are connected to the main control board 16, and detection signals from these connected switches are input to the medal count control unit 171. In addition, a count button 10 is connected to the main control board 16, and a detection signal from the count button 10 is input to the medal count control unit 171.

[0120] The main control board 16 is connected to a credit display 11 and a role ratio monitor 89, and the display is controlled by a medal count control unit 171. In addition, the main control board 16 is connected to a counting LED 10a, and the lighting thereof is controlled by the medal count control unit 171.

[0121] The winning combination monitor 89 usually displays a numerical value indicating the performance of the slot machine (hereinafter also referred to as "winning combination information").

[0122] In addition, backup power is supplied to the main control board 16 from the power supply board 101, and the data stored in the RAM 171c of the medal count control unit 171 is retained for the period during which backup power is supplied even after a power outage.

[0123] The medal count control unit 171 displays the following on the role ratio monitor 89 in the order of (1) to (6): (1) the instructed role payout ratio to the total cumulative payout number, (2) the consecutive role payout ratio for the past 6000 games, (3) the role payout ratio for the past 6000 games, (4) the consecutive role payout ratio to the total cumulative payout number, (5) the role payout ratio to the total cumulative payout number, and (6) the role etc. status ratio to the total cumulative payout number. Hereinafter, the information shown in (1) to (6) may be referred to as the display content.

[0124] The payout ratio of special features indicates the ratio of the payout number (number of special feature payouts) in special games (RB) awarded by winning a special feature (RB) to the payout number in a specified period. The consecutive feature ratio indicates the ratio of the payout number (number of consecutive feature payouts) in special game states (BB (states in which special games occur continuously)) awarded by winning a special feature (BB) to the payout number in a specified period. The payout ratio of special features with instructions indicates the ratio of the payout number of special features to the payout number when the payout number at the time of instruction (navigation indicating a mode of stop operation advantageous to the player) is included in the payout number of special features. In other words, it is the ratio of the cumulative number of medals paid out when a navigation notification is issued and the cumulative number of medals paid out in special games to the total cumulative number of medals paid out. The feature state ratio indicates the ratio of the number of games controlled by special games to the number of games played in a specified period.

[0125] When the medal count control unit 171 switches and displays the display content in the display order (1) to (6) shown above at predetermined intervals, even if the game progresses and these values ​​can be updated to new values ​​within a period until each display has completed a cycle, the medal count control unit 171 restricts updating to new values ​​and cycles the display using the original values.

[0126] The main control unit 161 mounted on the main control board 16 is a microcomputer equipped with a CPU 161a as the control center, a ROM 161b that stores programs and control data for the CPU 161a to operate, a RAM 161c that functions as a work area for the CPU 161a, and an input / output interface for maintaining signal consistency with peripheral devices.

[0127] Reel motors 32L, 32C, and 32R are connected to the main control board 16, and are driven under the control of the main control unit 161. Also connected to the main control board 16 are a setting key switch 37, a reset / setting switch 38, and a start switch 7, and detection signals from these connected switches are input to the main control unit 161. Also connected to the main control board 16 are a game assist display 12 and a setting value display 24, and the displays are controlled by the main control unit 161.

[0128] Furthermore, the bet number clear switch 21, 1BET switch 20, stop switches 8L, 8C, 8R, door open detection switch 25, and MAXBET switch 6 are connected to the main control board 16 via a relay board 1100, and detection signals from these connected switches are input to the main control unit 161. Furthermore, 1-3BET LEDs 14-16 are connected to the main control board 16 via the relay board 1100, and the displays are controlled by the main control unit 161. If the main control unit 161 detects that the MAXBET switch 6 has been operated during the period in which an invalid operation of the MAXBET switch 6 is accepted, it transmits an operation command indicating that the MAXBET switch 6 has been operated to the performance control unit 151.

[0129] The performance control unit 151 mounted on the performance control board 15 is a microcomputer equipped with a CPU 151a as the control center, a ROM 151b that stores programs and control data for the CPU 151a to operate, a RAM 151c that functions as a work area for the CPU 151a, and an input / output interface for maintaining signal consistency with peripheral devices.

[0130] A performance switch 57 is connected to the performance control board 15, and a detection signal from the performance switch 57 is input to the performance control unit 151. In addition, performance devices such as a liquid crystal display 51, a performance effect LED 52, speakers 53 and 54, a reel LED 55, and a credit display segment 7S are connected to the performance control board 15, and these performance devices are driven under the control of the performance control unit 151.

[0131] In addition, a light intensity / volume adjustment board 111 is connected to the performance control board 15. Switches for adjusting the light intensity and volume are connected to the light intensity / volume adjustment board 111, and detection signals from these switches are input to a performance control unit 151 mounted on the performance control board 15 via the light intensity / volume adjustment board 111.

[0132] The main control unit 161 transmits various commands to the performance control unit 151. Commands transmitted from the main control unit 161 to the performance control unit 151 are transmitted in only one direction, and commands are never transmitted from the performance control unit 151 to the main control unit 161. The performance control unit 151 receives commands transmitted from the main control unit 161 and performs various controls for producing performances.

[0133] The medal count control unit 171 transmits various commands to the main control unit 161. The main control unit 161 also transmits various commands to the medal count control unit 171. In other words, communication between the medal count control unit 171 and the main control unit 161 is two-way communication.

[0134] Furthermore, the medal count control unit 171 stores credits in a predetermined area of ​​the RAM 171c. Specifically, the number of credits is stored in a credit counter. The medal count control unit 171 updates the credits stored in the predetermined area of ​​the RAM 171c in the credit addition process or credit subtraction process. The number of credits stored in the credit counter is displayed on the credit display 11.

[0135] The set bet amount is stored in a predetermined area of ​​the RAM 161c. Specifically, the set bet amount is stored as a BET counter. When the value stored in the BET counter is "3", the game can be started. Hereinafter, the value stored in the BET counter may be simply referred to as "bet amount".

[0136] As explained above, medal-less slot machines that do not require medals are provided with a medal count control unit 171. Functions related to the insertion and payout of medals in conventional slot machines are concentrated in the medal count control unit 171. Furthermore, conventional slot machines that require medals must be provided with devices related to the insertion and payout of medals, such as a medal selector or hopper, but medal-less slot machines do not require such devices.

[0137] Furthermore, by configuring a medal-less slot machine as in this embodiment, it is possible to share parts with conventional slot machines. Specifically, because the credit update function (function related to medal insertion and payout) is concentrated in the medal count control unit 171, a conventional slot machine can be configured by replacing the medal count control unit 171 of the medal-less slot machine. To configure a conventional slot machine, it is sufficient to provide the medal count control unit 171 with functions related to medal insertion and payout, and then connect devices related to medal insertion and payout, such as a medal selector and hopper, to the medal count control unit 171. This configuration ensures compatibility with conventional slot machines, and by sharing parts, it is possible to reduce costs in the design and manufacture of slot machines.

[0138] When a detection signal is input from the start switch 7, the main control unit 161 drives the reel motors 32L, 32C, and 32R to rotate, and also draws for winning combinations.

[0139] The types of winning roles are determined according to the game status, but can be broadly divided into special roles that transition to a big bonus (BB) or regular bonus (RB), small roles that result in the payout of medals, and replay roles that allow you to start the next game without having to set a bet amount.

[0140] The main control unit 161 draws winning combinations, drives the reels to spin, and then waits for the player to stop the reels. When any of the stop switches 8L, 8C, or 8R is operated, the main control unit 161 stops the rotation of the reel corresponding to that stop switch 8L, 8C, or 8R. The main control unit 161 stops the three symbols and executes a win determination process to determine whether or not a win has occurred. If a win has been determined, the player is awarded a number of credits according to the type of win. A power-on switch 102 is connected to the power supply board 101, and a detection signal from the power-on switch 102 is input.

[0141] In this embodiment, the term "game" refers to the period from when the start switch 7 is operated until the reels 2L, 2C, and 2R stop. When playing a game, the number of bets is set before the start switch 7 is operated, and medals are paid out and the game state is changed after the reels 2L, 2C, and 2R stop, so these incidental processes are also included in the "game" in a broad sense.

[0142] In addition, in this embodiment, the operation of the MAXBET switch 6 is also referred to as the MAXBET operation, the operation of the start switch 7 as the start operation, the operation of the stop switches 8L, 8C, and 8R as the stop operation, the operation of the counting button 10 as the counting operation, the operation of the lending button 321 as the lending operation, and the operation of the card return button 322 as the return operation.

[0143] The slot machine 2 is also configured to change the medal payout rate according to a setting value. Specifically, the medal payout rate is changed by using the winning probability according to the setting value in a lottery that affects the player's advantage, such as an internal lottery. The setting value has six levels, from 1 to 6, with 6 being the highest payout rate, and the payout rate decreasing as the value decreases in the order of 5, 4, 3, 2, and 1. In other words, when 6 is set as the setting value, the player has the highest advantage, and the advantage gradually decreases as the value decreases in the order of 5, 4, 3, 2, and 1.

[0144] To change the setting value, it is necessary to turn on the power of the slot machine 2 after turning on the setting key switch 37. When the power is turned on with the setting key switch 37 in the ON state, the setting value read from the RAM 161c is displayed as the display value on the setting value display 24, and the system transitions to a setting change state in which the setting value can be changed by operating the reset / set switch 38. In the setting change state, when the reset / set switch 38 is operated, the display value displayed on the setting value display 24 is updated by 1 (when the reset / set switch 38 is operated again from setting value 6, it returns to setting value 1). Then, when the start switch 7 is operated, the displayed value is confirmed as the setting value. Then, when the setting key switch 37 is turned off, the confirmed display value (setting value) is stored in the RAM 161c of the main control unit 161, and the system transitions to a state in which the game can proceed.

[0145] [state transition] 3 is a diagram for explaining the transition of the game state. As shown in FIG. 3, the states managed by the main control unit 161 include game states related to the payout rate.

[0146] The game states include non-internal, internal, and BB. Internal is a state in which the game can proceed and the medal payout rate based on a predetermined design value is guaranteed. In the slot machine 2 of this embodiment, most games are played by the player in the internal state.

[0147] On the other hand, during the non-internal period, the player does not play, or even if they do, the time they play is extremely short. During the non-internal period, if a BB is won and the BB prize is missed, the game state shifts to the internal period from the next game. In other words, during the internal period, the BB prize is carried over.

[0148] In both non-internal and internal modes, a game in which the BB can be won (hereinafter also referred to as a "BB winning game") may be played. Specifically, in non-internal modes, if the BB symbol combination can be derived in response to the operation of the stop switches 8L, 8C, and 8R in a game in which the BB is won, the BB is won. In this case, the game state is controlled to BB from the next game. In other words, in non-internal modes, the game in which the BB is won is the BB winning game.

[0149] During the internal lottery, the BB win is carried over. Here, if the BB and small wins are simultaneously won, the reels are controlled to prioritize the small win symbol combination. Furthermore, if the small win symbol combination is a combination with no misses, in a game in which the BB and small wins are simultaneously won, the small win symbol combination will always win, regardless of the operation of the stop switches 8L, 8C, and 8R, and the BB symbol combination will not win. Similarly, if the BB and replay symbol combination are simultaneously won, the replay symbol combination will always win, regardless of the operation of the stop switches 8L, 8C, and 8R, in a game in which the BB and replay symbol combination are simultaneously won, the replay symbol combination will always win, regardless of the operation of the stop switches 8L, 8C, and 8R, and the BB symbol combination will not win. Therefore, during the internal lottery, only in games that result in a loss in the internal lottery (games in which no symbol combination wins), if the BB symbol combination can be derived by operating the stop switches 8L, 8C, and 8R, the BB symbol combination will win. In this case, the game state is controlled to BB from the next game. That is, during the internal game, the game that is a loss in the internal lottery becomes a game in which the BB prize can be won.

[0150] During the BB, the BB game is played for a predetermined number of games (for example, 60G), but since the payout rate during the BB is approximately 101%, the net increase in the number of coins hardly increases. Therefore, for the player, the BB is simply a state in which a predetermined number of games (for example, 60G) is consumed. When the BB ends, the game state transitions back to the non-internal state.

[0151] The internal states include normal zones and advantageous zones. The normal zone is a state in which navigation is not performed and is a non-notification state in which navigation information cannot be notified. The advantageous zone is a state in which navigation can be performed and is a notification state in which navigation information can be notified. In this embodiment, among the advantageous zones, navigation is not performed in the normal advantageous zone, but navigation can be performed in the high probability state, AT1 state, AT2 state, and ending state. Note that navigation may also be performed in the normal advantageous zone, but in the high probability state, AT1 state, AT2 state, and ending state, the probability of performing navigation to win the main role when the push order role is won is higher than in the normal advantageous zone. Thus, navigation is performed with a higher probability in the high probability state, AT1 state, AT2 state, and ending state than in the normal advantageous zone.

[0152] In the normal zone, when the lottery for transitioning to the advantageous zone is won (winning the advantageous zone), the state is controlled to the advantageous zone. In this embodiment, since the winning of most of the roles that can be won during normal play is the condition for winning the advantageous zone, the duration of play during normal play is approximately 1G. The condition for winning the advantageous zone may also be met when any of the roles that can be won during normal play is won.

[0153] In the normal section, navigation is not performed in the game in which the push order role is won, so the net increase in the number of coins a player can win per game will be 0 or negative, taking into account the number of medals used to set the bet amount. The net increase in the number of coins per game is the number of medals paid out per game minus the number of medals used to set the bet amount per game. In this embodiment, the normal payout rate is set to 40%. Thus, normally, the payout rate is 1 or less (100% or less) or less than 1 (less than 100%).

[0154] The advantageous zone includes the normal advantageous zone, the high probability state, the AT1 state, the AT2 state, and the ending state. In the normal advantageous zone, navigation is not performed in the game in which the push order role is won, so the net increase in the number of coins that a player can win per game will be 0 or negative, taking into account the number of medals used to set the bet amount. In this embodiment, the payout rate in the normal advantageous zone is set to 40%. Thus, in the normal advantageous zone, the payout rate will be 1 or less (100% or less) or less than 1 (less than 100%).

[0155] In this embodiment, the AT1 state ends when a predetermined number of games have been played. That is, as shown in the figure, the game transitions to the normal interval. The predetermined number of games in the AT1 state can be increased by winning a specific symbol. That is, in this embodiment, winning a specific symbol increases the player's advantage.

[0156] In the normal advantageous zone, processing such as lotteries related to control to the high probability state and AT1 state is performed. In the normal advantageous zone, the main control unit 161 performs lotteries to switch to the AT1 state through point acquisition lotteries. The points updated through the point acquisition lottery are managed by the main control unit 161. The main control unit 161 has an internal point counter (not shown) for counting points. In addition, when the value of the point counter reaches a specified value, the main control unit 161 performs an AT lottery to determine whether or not to control to the AT1 state. In addition, the main control unit 161 may perform an AT lottery based on the winning of a specific symbol without using points. The high probability state is a state in which the number of points awarded is greater than in the normal advantageous zone. In other words, the high probability state is a state in which it is easier to transition to the AT1 state than in the normal advantageous zone.

[0157] Control to the AT2 state can occur when the player is in the normal or high-probability advantageous zone. The AT2 state is a so-called pseudo-bonus that allows the player to increase the net increase in coins they can win by following the navigation. A win that directly controls the player to the AT2 state from the normal or high-probability advantageous zone without going through the AT1 state is also called a "direct pseudo-bonus win." A win that controls the player to the AT2 state from the AT1 state is also called a "pseudo-bonus win." In a pseudo-bonus, navigation is performed in the game that wins the push order role, so the net increase in coins a player can win per game is positive, even when taking into account the number of medals used to set the bet amount.

[0158] In the advantageous zone, when the number of medals acquired (difference number), which will be described later, reaches a predetermined ending transition number, the game is controlled to the ending state. The number of medals acquired in the advantageous zone is the value obtained by subtracting the number of medals used by the player from the number of medals awarded to the player through winning after control to the advantageous zone has begun. In this embodiment, the number of medals acquired is counted using a difference number count value, which will be described in detail later. The ending state is a state in which it is determined that control to the advantageous zone state will continue until, for example, the total number of medals acquired in the advantageous zone reaches an upper limit number (for example, 2,400 medals).

[0159] The ending transition number is set when the game transitions from the normal zone to the advantageous zone. The ending transition number may be determined by lottery or may be set in advance. The ending transition number is managed by the main control unit 161. That is, the RAM 161c of the main control unit 161 stores the ending transition number. The ending transition number is, for example, 2300. That is, the main control unit 161 cumulatively counts the difference count value, and when the difference count value reaches the ending transition number in the counting process, the advantageous zone ends.

[0160] When the limiter condition is met in the advantageous zone, the advantageous zone is controlled to the normal zone. More specifically, when the number of medals acquired during the advantageous zone reaches 2,400, the advantageous zone ends and the zone is controlled to the normal zone. The number of medals acquired during the advantageous zone is counted by a counter stored in RAM 161c. When the number of medals acquired during the advantageous zone reaches the upper limit, it is said that the "limiter condition" is met.

[0161] In this way, the advantageous zone includes an ending state that is advantageous to the player, and the main control unit 161 controls to the ending state when it determines that the number of medals acquired is greater than 2300. This makes it easier to continue the advantageous zone when the number of medals acquired exceeds 2300.

[0162] When the game is controlled from the advantageous zone to the normal zone, the number of medals acquired during the advantageous zone that was counted in the advantageous zone, as well as the points that can be acquired during play, are also initialized. The number of medals acquired during the advantageous zone is updated not only during the advantageous zone but also during BB, but is not updated in the normal zone.

[0163] In the slot machine 2 of this embodiment, the medal payout rate changes according to a setting value. More specifically, the medal payout rate changes by changing the probability of winning a predetermined lottery, such as a point acquisition lottery, according to the setting value (for example, 1, 2, 4, 5, or 6). A staff member at the gaming facility can change this setting value by changing the setting.

[0164] In this way, the conditions for transitioning from the advantageous zone to the normal zone include limiter conditions and optional termination conditions that are established based on the progress of the game, and a condition that a setting change is made.

[0165] In addition, in the slot machine 2 of this embodiment, an upper limit on the number of games played in the normal advantageous zone is set. When the predetermined upper limit is reached in the normal advantageous zone, an AT right is granted to forcibly transition to the AT1 state regardless of the number of points reached. The upper limit on the number of games played in the normal advantageous zone is, for example, 1,280 games. This upper limit is referred to as the "ceiling." The main control unit 161 has a lottery counter in RAM 161c to determine whether the ceiling has been reached. That is, the main control unit 161 stores the number of games played in the normal advantageous zone in the lottery counter in RAM 161c. The main control unit 161 increments the value of the lottery counter each time a game is played in the normal advantageous zone. For example, if the upper limit on the number of games played in the normal advantageous zone is set to 700 games, the main control unit 161 grants an AT right when the value of the lottery counter reaches 700. The upper limit on the number of games played in the normal advantageous zone is not limited to 700 games and may be, for example, 1,280 games.

[0166] [Commands to the production control unit] FIG. 4 is a diagram showing game start commands that the main control unit 161 transmits to the performance control unit 151 when the start switch 7 is operated. When the start switch 7 is operated (start operation), the main control unit 161 executes an internal lottery process and transmits a group of commands including predetermined information to the performance control unit 151 according to the result of the internal lottery process. Hereinafter, the group of commands No. 1 to No. 13 shown in FIG. 4 will be simply referred to as "game start commands." The main control unit 161 transmits each command in the order of No. 1 to No. 13 as game start commands. Each command is assigned a serial number, which is the same as the number, as a "setting serial number." Each command stores various information managed by the main control unit 161.

[0167] For example, the command No. 2 "instruction number" stores information related to navigation. That is, the command No. 2 stores information that can identify the order in which to press the buttons in a game in which the start switch 7 is operated. Specifically, the command "instruction number" stores information that indicates the order in which to press the stop switches 8L, 8C, and 8R. When the performance control unit 151 receives the command No. 2 "instruction number," it executes a navigation performance on the LCD display 51 based on the operation procedure that can be identified from the command "instruction number." Furthermore, the performance control unit 151 outputs a sound from the speaker 53 to notify the player of the operation procedure that can be identified from the command "instruction number."

[0168] For example, the No. 3 command "Small Role Type" stores information that can identify whether the winning combination obtained by the internal lottery is a small role, a replay role, or a special role. The No. 6 command "Interval Status" stores information that can identify which of the internal states shown in FIG. 4 the game in which the start switch 7 was operated is in. Specifically, the No. 6 command "Interval Status" stores information indicating whether the currently controlled state is a normal interval or an advantageous interval, and further, whether the advantageous interval is a normal advantageous interval, a high probability state, an AT1 state, an AT2 state, or an ending state. Based on receiving the No. 6 command "Interval Status," the effect control unit 151 can identify which interval state the game in which the start switch 7 was operated is in. The No. 4 command "Ball Out Status" can also store information that can identify the game state of the game in which the start switch 7 was operated. The No. 9 command "ART Premonition G Number" stores the number of games in the AT continuous effects. The command No. 10 "Points" in the game start command stores the number of points earned in the previous game. Also, the command No. 11 "Winning Number" stores information that can identify the winning combination number of the winning combination selected by the internal lottery.

[0169] Furthermore, when the main control unit 161 transmits a game start command, it stores information indicating that medals have been bet in the command No. 12 "insert medals." If information indicating that medals have been bet in the command No. 12 "insert medals" is stored, the performance control unit 151 can determine that the game start command has been received.

[0170] FIG. 5 shows game end commands that the main control unit 161 transmits to the performance control unit 151 at the third stop. The main control unit 161 transmits a group of commands No. 1 to No. 13 to the performance control unit 151 in the order of No. 1 to No. 13 not only when the start switch 7 is operated but also at the third stop of the stop switch. Hereinafter, the group of commands No. 1 to No. 13 shown in FIG. 5 will be simply referred to as "game end commands." Note that, among the commands transmitted at the third stop, No. 11 differs from the command No. 11 transmitted when the start switch 7 is operated. No. 11 is a command that stores information related to a win. In other words, at the third stop, the main control unit 161 transmits information related to a win, not information related to a winning number.

[0171] The number of points acquired in the point acquisition lottery process at the third stop, described later, is stored in the command No. 10 "Points" in the game end command. Furthermore, when the main control unit 161 sends a game end command, it stores information indicating that the reels have stopped in the command No. 13 "Stop Reels." If information indicating that the reels have stopped is stored in the command No. 13 "Stop Reels," the performance control unit 151 can determine that it has received a game end command. That is, the performance control unit 151 determines whether the received command group is a game start command or a game end command based on the command No. 12 "Insert Medal" and the command No. 13 "Stop Reels." When sending a game start command, the main control unit 161 does not need to send the command No. 13 "Stop Reels." When sending a game end command, the main control unit 161 does not need to send the command No. 12 "Insert Medal."

[0172] [Transmission and reception between the main control unit and the medal count control unit] The following describes the manner of transmission and reception between the main control unit 161 and the medal count control unit 171. In this embodiment, communication is performed between the main control unit 161 and the medal count control unit 171 using commands. The main control unit 161 transmits a predetermined command to the medal count control unit 171 every time an event occurs. Events include pressing the start switch 7, pressing the 1BET switch 20 or the MAXBET switch 6, stopping all reels, etc.

[0173] When the predetermined command transmitted from the main control unit 161 is a command requiring a predetermined response, the medal count control unit 171 transmits a response command to the main control unit 161. For example, when the slot machine 2 is installed in an amusement facility and electrically connected, and the power is turned on, the main control unit 161 transmits a gaming machine installation information command including a main chip ID (main control chip ID) to the medal count control unit 171. Even when the power is turned on thereafter, the main control unit 161 transmits gaming machine installation information including the main chip ID (main control chip ID) to the medal count control unit 171. In other words, when the slot machine 2 is powered on, the main control unit 161 transmits to the medal count control unit 171 a gaming machine installation information command capable of identifying the main chip ID, which is unique information held by the main control unit 161.

[0174] The main control unit 161 assigns a "serial number" to the command before transmitting it. The medal count control unit 171 stores the received "serial number." By assigning a "serial number" to the command, the slot machine 2 prevents a person who attempts to fraudulently obtain medals (hereinafter referred to as a fraudulent person) from operating the slot machine 2 fraudulently. An fraudulent operation refers to, for example, an operation in which a command transmitted and received between the main control board 16 and the medal count control unit 171 is altered, or an operation in which a fraudulent person controls the main control unit 161 or the medal count control unit 171. A fraudulent person performs fraudulent operation, for example, by connecting a device that performs fraudulent operation (hereinafter referred to as a fraudulent device) to the main control unit 161 or the medal count control unit 171.

[0175] The initial value and the additional value of the "serial number" are determined by the medal count control unit 171 and the main control unit 161, respectively. The medal count control unit 171 determines the initial value and the additional value of the "serial number" based on the gaming machine installation information command received from the main control unit 161. The main chip ID included in the gaming machine installation information command includes an 8-byte chip-specific number register. Each byte included in the main chip ID stores a hexadecimal value specific to the chip. The medal count control unit 171 calculates the total value by adding the hexadecimal values ​​stored in each byte included in the main chip ID. The medal count control unit 171 converts the value indicated by the lowest two bytes of the calculated total value into a decimal number and determines the value as the initial value for the "serial number".

[0176] For example, if the total value is "189h" (the "h" indicates that "189" is a hexadecimal number), the initial value for the serial number will be the decimal representation of "89h." In other words, the initial value for the "serial number" will be "137."

[0177] Furthermore, the medal count control unit 171 divides the initial value by a predetermined number. If the predetermined number is, for example, "5," the remainder calculated as a result of the division will be one of four types: "0," "1," "2," "3," and "4." The medal count control unit 171 predetermines and stores additional values ​​corresponding to the four types of remainder. For example, the medal count control unit 171 stores "7" corresponding to "0," "11" corresponding to "1," "13" corresponding to "2," "19" corresponding to "3," and "23" corresponding to "4." After dividing the initial value by the predetermined number, the medal count control unit 171 sets the value stored corresponding to the remainder of the division result as the additional value.

[0178] For example, when the initial value "137" is divided by 5, the remainder is "2." As described above, the medal count control unit 171 stores "13" corresponding to the remainder "2" of the division. Therefore, the medal count control unit 171 determines the additional value for the serial number as "13." In this way, based on the main chip ID identified from the gaming machine installation information command, the medal count control unit 171 generates an initial value and additional value for the serial number to determine whether the command sent from the main control unit 161 is normal. The main control unit 161 also generates the initial value and additional value by performing a similar calculation. As a result, the same initial value and additional value are stored in both the main control unit 161 and the medal count control unit 171.

[0179] As described above, in this embodiment, when an event occurs, the main control unit 161 transmits a predetermined command to the medal count control unit 171. The main control unit 161 assigns a serial number to the predetermined command. For example, an example will be described in which a gaming machine installation information command is transmitted to the medal count control unit 171, and after both the main control unit 161 and the medal count control unit 171 determine the initial value and the additional value for the serial number, a predetermined event A occurs.

[0180] When a predetermined event A occurs, the main control unit 161 transmits a command A to the medal count control unit 171. At this time, the main control unit 161 assigns an initial value of a serial number to the command A that is transmitted for the first time after transmitting the gaming machine installation command. That is, the main control unit 161 assigns the serial number "137" to the command A and transmits it.

[0181] The medal count control unit 171 stores "137" as the initial value, and since the serial number assigned to the first command A received after receiving the gaming machine installation command is "137", it determines that communication is normal.

[0182] Subsequently, when a new event B occurs, the main control unit 161 transmits command B to the medal count control unit 171. At this time, the main control unit 161 transmits command B to which a value obtained by adding an additional value to the value of the previously transmitted serial number is assigned. That is, the main control unit 161 assigns "150", which is the value obtained by adding the additional value "13" to the previously transmitted "137", to command B, and transmits it. Before receiving command B, the medal count control unit 171 calculates in advance that the serial number to be assigned to the next command to be transmitted will be "150". The medal count control unit 171 determines that communication with the main control unit 161 is normal because the serial number assigned to the received command B is "150", which matches the serial number calculated in advance.

[0183] That is, each time the main control unit 161 sends a command, it assigns a serial number that is the result of adding an additional value to the value of the previously sent serial number. The medal count control unit 171 also stores an initial value and an additional value, so it can calculate in advance the value of the serial number to be assigned to the next command it receives, and can determine whether the serial number is normal each time it receives a command. If the serial number assigned to the received command does not match the calculated serial number value, the medal count control unit 171 determines that a communication abnormality has occurred between the main control unit 161 and the medal count control unit 171.

[0184] If the value obtained by adding the additional value to the value of the previously transmitted serial number exceeds 255, the main control unit 161 subtracts 255 from the serial number and transmits the result. If the main control unit 161 receives a response command from the medal count control unit 171 indicating that an error has occurred, the main control unit 161 does not add the additional value to the serial number of the command to be transmitted after the response command, but instead assigns the same serial number again and transmits it.

[0185] [Command sent from the main control unit to the medal count control unit] FIG. 6 illustrates the types of commands sent by the main control unit 161 to the medal count control unit 171. In this embodiment, the main control board 16 transmits to the medal count control unit 171, as shown in the command name column in FIG. 6, a gaming machine installation information command, a slot insertion command, a settlement command, a payout command, a slot insertion pulse command, a payout pulse command, a jackpot command, a gaming machine fraud command, a main control unit error command, a role ratio information 1 command, a role ratio information 2 command, a total payout command for bonuses, a total payout command for consecutive bonuses, and an overflow command. The number column indicates the command number preset for each command. The message length column indicates the message length, i.e., the byte length, of each command. As described below, the data format of these commands is set to 10-bit format (LSB-first, no parity), and the multiple bytes of data constituting each command are transmitted from the least significant bit to the most significant bit.

[0186] The two-way column indicates whether or not the medal count control unit 171 needs to send a response command after the main control unit 161 sends a command. For example, when the medal count control unit 171 receives a throw-in pulse command from the main control unit 161, it does not send a response command in response to the throw-in pulse command. In other words, the main control unit 161 controls the reel drums and the like without waiting to receive a response command from the medal count control unit 171.

[0187] On the other hand, when the medal count control unit 171 receives an input command, a settlement command, a payout command, or an overflow command from the main control unit 161, it transmits a response command to the main control unit 161 in response to receiving these commands. The input command, the settlement command, the payout command, and the overflow command are commands that directly affect the number of credits managed by the medal count control unit 171. Therefore, after transmitting the input command, the settlement command, the payout command, or the overflow command, the main control unit 161 performs the next control on the condition that it has received a response command from the medal count control unit 171. Below, the commands transmitted from the main control unit 161 to the medal count control unit 171 will be described using Figs. 7 to 20.

[0188] FIG. 7 is a diagram illustrating the gaming machine installation information command. As shown in FIG. 7, the gaming machine installation information command is a command having a length of 25 bytes. The first byte stores the message length of the gaming machine installation information command. The second byte stores the serial number. Since the gaming machine installation information command is a command sent after power is turned on and before the medal count control unit 171 determines the initial value and the additional value of the serial number, the serial number is fixed to the value "5Ah." The third byte stores the command number. The command number of the gaming machine installation information command is fixed to "0." The fourth byte stores the gaming machine type. As the gaming machine type, values ​​indicating the management medium (gaming balls, medals), organization classification (organization to which the user belongs), and gaming machine type (pachinko machine, slot machine, etc.) are stored. The fifth byte stores an identification code. As the identification code, values ​​indicating the CPU manufacturer and CPU type are stored. The sixth to thirteenth bytes store the chip ID. The chip ID is an 8-byte unique number assigned to each chip. From the 6th to 13th bytes, the chip ID is stored byte by byte, starting from the most significant byte. From the 14th to 16th bytes, the chip manufacturer code is stored. As the chip manufacturer code, a 3-byte code that can identify the chip manufacturer is stored. From the 14th to 16th bytes, the chip manufacturer code is stored byte by byte, starting from the most significant byte. From the 17th to 24th bytes, the product code is stored. As the product code, an 8-byte code that indicates the chip model number is stored. From the 17th to 24th bytes, the product code is stored byte by byte, starting from the most significant byte. Byte 25 stores a checksum to determine whether or not there was an error in the information sent in bytes 1 to 24.

[0189] FIG. 8 is a diagram showing the configuration of a deposit command. The deposit command is transmitted from the main control unit 161 to the medal count control unit 171 when the 1BET switch 20 is pressed or the MAXBET switch 6 is pressed. That is, the main control unit 161 transmits the deposit command to the medal count control unit 171 when it receives a bet number setting operation for setting the bet number for starting a game. Furthermore, since the deposit command is a bidirectional command, the medal count control unit 171 transmits a deposit response command in response to the deposit command to the main control unit 161 when it receives the deposit command. The deposit command is composed of 8 bytes of data. The first byte stores the message length of the deposit command. The second byte stores a serial number. The third byte stores a value indicating the command number. The command number of the deposit command is "1".

[0190] The fourth byte stores the number of medals inserted. If the 1BET switch 20 is pressed when the bet number is 0, 1, or 2, the number of medals inserted will be 1. If the MAXBET switch 6 is pressed when the bet number is 0, the number of medals inserted will be 3; if the MAXBET switch 6 is pressed when the bet number is 1, the number of medals inserted will be 2; and if the MAXBET switch 6 is pressed when the bet number is 2, the number of medals inserted will be 1. In the replay operation state, no insertion command is sent. The "replay operation state" refers to the state after a replay win has been achieved. Bytes 5 to 7 are reserved areas 1 to 3, and are always stored with "0." The eighth byte stores a checksum to determine whether or not there was an error in the information sent in bytes 1 to 7.

[0191] FIG. 9 is a diagram showing the configuration of a settlement command. The settlement command is sent from the main control unit 161 to the medal count control unit 171 when the bet number clear switch 21 is pressed. That is, the main control unit 161 sends the settlement command to the medal count control unit 171 when it receives a settlement operation to cancel the bet number for starting one game. Furthermore, since the settlement command is a bidirectional command, when the medal count control unit 171 receives the settlement command, it sends a settlement response command in response to the settlement command to the main control unit 161. The settlement command is composed of 8 bytes of data. The first byte stores the message length of the settlement command. The second byte stores the serial number. The third byte stores a value indicating the command number. The command number of the settlement command is "2".

[0192] The fourth byte stores the number of medals to be paid out. If the bet number clear switch 21 is pressed when the number of bets is one, the number of medals to be paid out will be one; if the bet number clear switch 21 is pressed when the number of bets is two, the number of medals to be paid out will be two; and if the bet number clear switch 21 is pressed when the number of bets is three, the number of medals to be paid out will be three. Bytes 5 to 7 are reserved areas 1 to 3, which are always filled with "0". Byte 8 stores a checksum to determine whether or not there was an error in the information sent in bytes 1 to 7.

[0193] FIG. 10 illustrates the configuration of a payout command. The payout command is transmitted from the main control unit 161 to the medal count control unit 171 when all reels have stopped, i.e., when the reels have reached the third stop. In other words, the main control unit 161 transmits an end command to the medal count control unit 171 when a game ends. The payout command includes the number of medals to be paid out, which is determined according to the combination of symbols derived. When medals are paid out to a player, the number of credits increases. Therefore, the payout command is a command that directly affects the number of credits managed by the medal count control unit 171. Therefore, when the medal count control unit 171 receives a payout command, it transmits a payout response command to the main control unit 161. After transmitting the payout command, the main control unit 161 performs the next control on the condition that the payout response command has been received. The next control corresponds to, for example, updating the data displayed on the game assist display device 12.

[0194] When the medal count control unit 171 receives a payout command, it transmits a payout response command in response to the payout command to the main control unit 161 and performs control in accordance with the payout command. The control in accordance with the payout command is, for example, control to add the number of medals paid out to the number of credits.

[0195] The payout command consists of 8 bytes of data. The first byte stores the message length of the payout command. The second byte stores the serial number. The third byte stores a value indicating the command number. The command number for the payout command is "3".

[0196] The fourth byte stores the number of medals to be paid out. The maximum number of medals to be paid out is 15. If a replay symbol combination is derived, or if there are no medals to be paid out, "0" is stored in the fourth byte. In other words, the payout command is a command that can specify the game value to be awarded to a player according to the result of a single game when that game ends. Bytes 5 to 7 are reserved areas 1 to 3, and "0" is always stored therein. Byte 8 stores a checksum to determine whether or not there was an error in the information sent in bytes 1 to 7.

[0197] FIG. 11 illustrates the configuration of a coin insertion pulse command. The coin insertion pulse command is transmitted from the main control unit 161 to the medal count control unit 171 when the start switch 7 is pressed. That is, the main control unit 161 transmits the coin insertion pulse command to the medal count control unit 171 when a game is started. The coin insertion pulse command is a pulse signal for transmitting the number of coins used by a player in a game to a hall computer (not shown) connected to the medal count control unit 171 in response to the start of the game. After receiving the coin insertion pulse command, the medal count control unit 171 transmits the coin insertion pulse signal to the hall computer (not shown). This allows the hall computer to store the number of coins inserted into the slot machine 2. The coin insertion pulse command is transmitted even when the start switch 7 is pressed during replay operation. The coin insertion pulse command does not directly affect the number of credits managed by the medal count control unit 171. Therefore, when the coin insertion pulse command is received, the medal count control unit 171 performs control in accordance with the coin insertion pulse command without transmitting a response command to the main control unit 161. Control according to the input pulse command corresponds to, for example, a process of controlling to a state of waiting for the game to end, a preparation process for receiving a payout command, etc. After transmitting the input pulse command, the main control unit 161 performs the next control without waiting for a response from the medal count control unit 171. The next control is, for example, a control to drive the reels.

[0198] The input pulse command consists of 5 bytes of data. The first byte stores the message length of the input pulse command. The second byte stores the serial number. The third byte stores a value indicating the command number. The command number of the input pulse command is "4".

[0199] The fourth byte stores the number of input pulses (1 to 3) to be sent to the hall computer. Even in the replay mode, the specified number of input pulses is sent. Bytes 5 to 7 are reserved areas 1 to 3, which are always set to "0". Byte 8 stores a checksum to determine whether there was an error in the information sent in bytes 1 to 7.

[0200] FIG. 12 shows the configuration of a payout pulse command. The payout pulse command is transmitted from the main control unit 161 to the medal count control unit 171 when all reels have stopped, i.e., when the third stop occurs. The payout pulse command is a pulse signal for transmitting the number of medals awarded to a player in response to a winning combination to a hall computer (not shown) connected to the medal count control unit 171. After receiving the payout pulse command, the medal count control unit 171 transmits a payout pulse signal to the hall computer (not shown). This allows the hall computer to store the number of medals paid out in the slot machine 2. The payout pulse command is transmitted to the medal count control unit 171 even when the slot machine is in a replay operation state. After transmitting the payout pulse command, the main control unit 161 performs the next control operation without waiting for a response from the medal count control unit 171.

[0201] The payout pulse command consists of 5 bytes of data. The first byte stores the message length of the payout pulse command. The second byte stores the serial number. The third byte stores a value indicating the command number. The command number for the payout pulse command is "5".

[0202] The fourth byte stores the number of payout pulses to be sent to the hall computer. The maximum number of payout pulses is 15. If a replay symbol combination is derived, or if there are no payout medals, "0" is stored in the fourth byte. Bytes 5 to 7 are reserved areas 1 to 3, which are always set to "0". Byte 8 stores a checksum to determine whether there was an error in the information sent in bytes 1 to 7.

[0203] 13 is a diagram showing the configuration of a jackpot command. The jackpot command is sent from the main control unit 161 to the medal count control unit 171 when the reels start to spin. The jackpot command is also sent from the main control unit 161 to the medal count control unit 171 when the power is turned on in a hot start state. This allows the slot machine 2 to restore the hall computer signal without having to back up the hall computer signal.

[0204] The jackpot command consists of 8 bytes of data. The first byte stores the message length of the jackpot command. The second byte stores the serial number. The third byte stores a value indicating the command number. The command number for the jackpot command is "6".

[0205] The fourth byte stores the hall computer signal. The hall computer signal is a signal used to notify the hall computer of jackpot information for the slot machine 2. The type of jackpot, such as RB, BB, or AT, is stored here. Bytes 5 to 7 are reserved areas 1 to 3, which are always set to "0." Byte 8 stores a checksum to determine whether or not there was an error in the information sent in bytes 1 to 7.

[0206] 14 is a diagram showing the configuration of a gaming machine improper command. The gaming machine improper command is transmitted from the main control unit 161 to the medal count control unit 171 at the start and end of setting change and setting confirmation.

[0207] The gaming machine fraud command consists of 8 bytes of data. The first byte stores the message length of the gaming machine fraud command. The second byte stores the serial number. The third byte stores a value indicating the command number. The command number for the gaming machine fraud command is "7".

[0208] The fourth byte stores fraud information 1. Fraud information 1 is information sent to the hall computer when settings are changed or confirmed, and information that notifies the hall computer of whether or not fraud was detected. The fifth byte stores fraud information 2. The sixth byte stores fraud information 3. Fraud information 2 and 3 are unused, and are always stored as "0". The seventh byte is a reserved area, and is always stored as "0". The eighth byte stores a checksum to determine whether or not there was an error in the information sent in bytes 1 to 7.

[0209] 15 is a diagram showing the configuration of an error command. The error command is a command that indicates the type of error that has occurred in the main control unit 161. The main control board error command is sent from the main control unit 161 to the medal count control unit 171 when an error occurs in the main control unit 161 and when the error that has occurred is resolved.

[0210] An error command consists of 8 bytes of data. The first byte stores the message length of the error command. The second byte stores the serial number. The third byte stores a value indicating the command number. The command number for an error command is "8".

[0211] The fourth byte stores error information. This error information notifies the hall computer of a number indicating the type of error that has occurred in the main control unit 161. Bytes 5 to 7 are reserved areas 1 to 3, which are always filled with "0". Byte 8 stores a checksum to determine whether or not an error has occurred in the information sent in bytes 1 to 7.

[0212] 16 is a diagram showing the configuration of the role ratio information 1 command. The role ratio information 1 command is a command for the medal count control unit 171 to update the gaming machine performance information and role ratio monitor information. The role ratio information 1 command is sent from the main control unit 161 to the medal count control unit 171 when all reels have stopped, that is, when the third stop has occurred.

[0213] The Role Ratio Information 1 command consists of 8 bytes of data. The first byte stores the message length of the Role Ratio Information 1 command. The second byte stores the serial number. The third byte stores a value indicating the command number. The command number for the Role Ratio Information 1 command is "10".

[0214] The fourth byte stores replay operation information. As the replay operation information, a value indicating whether or not replay has been activated (0: replay not activated, 1: replay activated) is stored. The fifth byte stores feature ratio information. As feature ratio information, the feature payout ratio for the past 6,000 games is stored. The sixth byte stores consecutive feature ratio information. As consecutive feature ratio information, the consecutive feature payout ratio for the past 6,000 games is stored. The seventh byte stores advantageous zone information. As advantageous zone information, the advantageous zone ratio for the past 6,000 games is stored. For feature ratio information, consecutive feature ratio information, and advantageous zone information, 255 is stored until 6,000 games are reached, and after 6,000 games are reached, the calculated ratio is stored. The eighth byte stores a checksum to determine whether or not there was an error in the information sent in bytes 1 to 7.

[0215] 17 is a diagram showing the configuration of the role ratio information 2 command. The role ratio information 2 command is a command for the medal count control unit 171 to update the gaming machine performance information and role ratio monitor information. The role ratio information 2 command is sent to the medal count control unit 171 after the role ratio information 1 command is sent.

[0216] The Role Ratio Information 2 command consists of 8 bytes of data. The first byte stores the message length of the Role Ratio Information 2 command. The second byte stores the serial number. The third byte stores a value indicating the command number. The command number for the Role Ratio Information 2 command is "11".

[0217] The fourth byte stores instruction-included feature ratio information. As instruction-included feature ratio information, the instruction-included feature payout ratio for the past 6000 games is stored. The fifth byte stores feature status information. As feature status information, the feature status ratio for the past 6000 games is stored. For instruction-included feature ratio information and feature status information, 255 is stored until 6000 games are played, and after 6000 games are played, the calculated ratio is stored. Bytes 6 to 7 are spare areas 1 to 2, and are always stored with "0". Byte 8 stores a checksum to determine whether or not there was an error in the information sent in bytes 1 to 7.

[0218] 18 is a diagram showing the configuration of the total payout command for bonus items. The total payout command for bonus items is a command for the medal count control unit 171 to update the gaming machine performance information and the bonus item ratio monitor information. The total payout command for bonus items is sent to the medal count control unit 171 after the bonus item ratio information 2 command is sent.

[0219] The total payout command for reels consists of 8 bytes of data. The first byte stores the message length of the total payout command for reels. The second byte stores the serial number. The third byte stores a value indicating the command number. The command number for the total payout command for reels is "12".

[0220] The total number of coins paid out from the reels is stored in bytes 4 to 6. In this case, the total number of coins paid out from the reels is stored in bytes 4 to 6, one byte at a time, from the lower byte to the higher byte. The seventh byte is a reserved area, and is always stored as "0". The eighth byte stores a checksum to determine whether there was an error in the information sent in bytes 1 to 7.

[0221] 19 is a diagram showing the configuration of the continuous feature total payout command. The continuous feature total payout command is a command for the medal count control unit 171 to update the gaming machine performance information and the feature ratio monitor information. The continuous feature total payout command is sent to the medal count control unit 171 after the feature total payout command is sent.

[0222] The continuous reel payout total command consists of 8 bytes of data. The first byte stores the message length of the continuous reel payout total command. The second byte stores the serial number. The third byte stores a value indicating the command number. The command number for the continuous reel payout total command is "13".

[0223] The total number of consecutive payouts is stored in bytes 4 to 6. In this case, the total number of consecutive payouts is stored in bytes 4 to 6, one byte at a time, from the lower byte to the upper byte. The seventh byte is a reserved area, and is always stored as "0". The eighth byte stores a checksum to determine whether there was an error in the information sent in bytes 1 to 7.

[0224] FIG. 20 is a diagram showing the configuration of an overflow command. The overflow command is a command for notifying an inquiry about a credit overflow on the medal count control unit 171 side. The overflow command is a command that directly affects the number of credits managed by the medal count control unit 171. Therefore, when the medal count control unit 171 receives an overflow command, it transmits an overflow response command to the main control unit 161. Furthermore, after transmitting the overflow command, the main control unit 161 performs the following control on the condition that the overflow response command has been received.

[0225] An overflow command consists of 8 bytes of data. The first byte stores the message length of the overflow command. The second byte stores a serial number. The third byte stores a value indicating the command number. The command number for an overflow command is "14".

[0226] Bytes 4 to 7 are reserved areas 1 to 4, which are always set to "0." Byte 8 stores a checksum to determine whether an error occurred in the information sent in bytes 1 to 7.

[0227] [Command sent from medal count control unit to main control unit] 21 is a diagram showing a list of commands sent from the medal count control unit 171 to the main control unit 161. The medal count control unit 171 sends two types of commands to the main control unit 161.

[0228] The response commands (insertion response command, settlement response command, payout response command, overflow response command) are commands for responding to commands received from the main control unit 161. For example, when the medal count control unit 171 receives a payout command, it sends a payout response command because the payout command affects the number of credits. In other words, response commands are bidirectional commands, responding in response to their reception. Response commands can be assigned command numbers 1 to 3, or 14. The message length of a response command is 8 bytes. As will be described later, the data format of these commands is set to 10-bit format (LSB first, no parity), and the multiple bytes of data that make up the command are all transmitted from the least significant bit to the most significant bit.

[0229] The medal count control side information command is a command for transmitting system information including connection information between the medal count control unit 171 and CU3. The medal count control unit 171 transmits the medal count control side information command to the main control unit 161 every 0.5 seconds. The specified period for transmitting the medal count control side information command does not have to be 0.5 seconds, and may be another period. The main control unit 161 does not respond even when it receives a medal count control side information command. Therefore, the medal count control side information command is a command that is continuously transmitted unidirectionally from the medal count control unit 171 to the main control unit 161, and is not bidirectional. The command number of the medal count control side information command is "81h", and the message length is 8 bytes.

[0230] 22 is a diagram showing the configuration of an insertion response command. The insertion response command is a command for responding to an insertion command received from the main control unit 161. When the medal count control unit 171 receives an insertion command, the medal count control unit 171 transmits an insertion response command because the insertion command affects the number of credits. In other words, the insertion response command is a bidirectional command that responds in response to its reception.

[0231] The submission response command consists of 8 bytes of data. The first byte contains the message length of the submission response command. The second byte contains a value indicating the command number. The command number of the submission response command is "1", the same as the received submission command to which the response is made.

[0232] The third byte stores the processing result. If the input command is "received OK", 0 is stored as the processing result, and if the number of game medals is insufficient, 1 is stored. "Received OK" indicates that the received command received by the medal count control unit 171 is normal. Bytes 4 to 7 are reserved areas 1 to 4, and "0" is always stored. Byte 8 stores a checksum to determine whether or not there was an error in the information sent in bytes 1 to 7.

[0233] Fig. 23 is a diagram showing the configuration of a settlement response command. The settlement response command is a command for responding to a settlement command received from the main control unit 161. When the medal count control unit 171 receives a settlement command, the medal count control unit 171 transmits a settlement response command because the settlement command affects the number of credits. In other words, the settlement response command is a bidirectional command, as it responds in response to receiving it.

[0234] The settlement response command consists of 8 bytes of data. The first byte contains the message length of the settlement response command. The second byte contains a value indicating the command number. The command number of the settlement response command is "2", the same as the received settlement command that is the subject of the response.

[0235] The third byte stores the processing result. As a processing result, 0 is stored, indicating that the settlement command was "received OK." Bytes 4 to 7 are reserved areas 1 to 4, which are always filled with "0." Byte 8 stores a checksum to determine whether there was an error in the information sent in bytes 1 to 7.

[0236] 24 is a diagram showing the configuration of a payout response command. The payout response command is a command for responding to a payout command received from the main control unit 161. When the medal count control unit 171 receives a payout command, the medal count control unit 171 transmits a payout response command because the payout command affects the number of credits. In other words, the payout response command is a bidirectional command that responds in response to receiving the command.

[0237] The payout response command consists of 8 bytes of data. The first byte contains the message length of the payout response command. The second byte contains a value indicating the command number. The command number of the payout response command is "3", the same as the received payout command that is the subject of the response.

[0238] The third byte stores the processing result. As a processing result, 0 is stored, indicating that the withdrawal command was "received OK." Bytes 4 to 7 are reserved areas 1 to 4, which are always stored with "0." Byte 8 stores a checksum to determine whether there was an error in the information sent in bytes 1 to 7.

[0239] 25 is a diagram showing the configuration of an overflow response command. The overflow response command is a command for responding to an overflow command received from the main control unit 161. When the medal count control unit 171 receives an overflow command, the medal count control unit 171 transmits an overflow response command because the overflow command affects the number of credits. In other words, the overflow response command is a bidirectional command that responds in response to receiving it.

[0240] The overflow response command consists of 8 bytes of data. The first byte stores the message length of the overflow response command. The second byte stores a value indicating the command number. The command number of the overflow response command is "14", the same as the received overflow command to which it is being responded.

[0241] The third byte stores the processing result. If the overflow command is "Receive OK", 0 is stored as the processing result, and if the number of credit medals overflows, 4 is stored. Bytes 4 to 7 are reserved areas 1 to 4, which are always stored with "0". Byte 8 stores a checksum to determine whether or not there was an error in the information sent in bytes 1 to 7.

[0242] 26 is a diagram showing the configuration of the medal count control-side information command. As described above, the medal count control-side information command is transmitted from the medal count control unit 171 to the main control unit 161 every 0.5 seconds.

[0243] The medal count control side information command consists of 8 bytes of data. The first byte stores the message length of the medal count control side information command. The second byte stores the command number. The command number of the medal count control side information command is "81h." The third and fourth bytes store the number of game medals (0 to 16383) stored as credits. At this time, the number of game medals is stored in one byte from the third byte to the fourth byte, from the lower byte to the higher byte. The fifth to seventh bytes store medal count control side information 1 to 3 indicating the system status of the medal count control unit 171. The system status of the medal count control unit 171 includes information on whether the count button has been pressed and whether CU3 and the medal count control unit 171 are normally connected. The eighth byte stores a checksum to determine whether an error has occurred in the information sent in the first to seventh bytes.

[0244] [Communication between the main control unit and medal count control unit] Fig. 27 is a diagram showing an example of communication between the main control unit 161 and the medal count control unit 171. Serial communication is used for communication between the main control unit 161 and the medal count control unit 171. As shown in Fig. 27, the main control unit 161 transmits a deposit command when a bet number setting operation is performed. The bet number setting operation includes pressing the 1BET switch 20 or the MAXBET switch 6.

[0245] When the medal count control unit 171 receives a command from the main control unit 161, it measures the elapsed time using a counter. If reception of the command is not completed before 10 ms has elapsed since the command was received from the main control unit 161, the medal count control unit 171 determines that a timeout error has occurred in the communication between the main control unit 161 and the medal count control unit 171. In the example of FIG. 27, the reception of the insertion command is completed before 10 ms has elapsed since the medal count control unit 171 received the command, so a timeout error does not occur.

[0246] The medal count control unit 171 transmits a medal insertion response command in response to receiving the insertion command. When the main control unit 161 receives a command from the medal count control unit 171, it measures the elapsed time using a counter. If reception of the command from the medal count control unit 171 is not completed before 2.24 ms has elapsed since the command was received, the main control unit 161 determines that a timeout error has occurred in the communication between the main control unit 161 and the medal count control unit 171. In the example of FIG. 27, reception of the insertion response command is completed before 2.24 ms has elapsed since the main control unit 161 received it, so a timeout error does not occur.

[0247] In addition, when the main control unit 161 sends a command that requires a response command from the medal count control unit 171, such as an insertion command, it uses a counter to measure the elapsed time from the time the bet number setting operation that triggered the sending of the insertion command was performed.

[0248] If the reception of the insertion response command from the medal count control unit 171 is not completed within 40 ms from the occurrence of an event such as a bet number setting operation, the main control unit 161 determines that a timeout error has occurred in the communication between the main control unit 161 and the medal number control unit 171. In the example of Fig. 27, the reception of the insertion response command is completed within 40 ms from the occurrence of the bet number setting operation, so a timeout error does not occur.

[0249] After receiving the insertion response command in response to the insertion command, the main control unit 161 starts control corresponding to the bet number setting operation.

[0250] Next, the start switch 7 of the slot machine 2 is pressed by the player. In response to the start switch 7 being pressed, the main control unit 161 transmits an insertion pulse command to the medal count control unit 171. As described above, the insertion pulse command is a command that does not require a response command from the medal count control unit 171. Therefore, the medal count control unit 171 does not transmit a response command.

[0251] Finally, when the player performs a third stop operation, all the reels stop. Based on the fact that all the reels have stopped, the main control unit 161 transmits a payout command to the medal count control unit 171. In this example, even though the payout command requires a payout response command, the medal count control unit 171 does not transmit the payout response command. Therefore, the main control unit 161 does not receive the payout response command until 40 ms has elapsed since all the reels stopped, and determines that a timeout error has occurred.

[0252] Fig. 28 is a diagram for explaining communication of medal count control side information commands. As shown in Fig. 28, after receiving a gaming machine installation information command from the main control unit 161 when the power is turned on, the medal count control unit 171 transmits a medal count control side information command to the main control unit 161 every 500 ms. If a period of more than 2.24 ms has passed from the start of reception of the medal count control side information command until reception is completed, the main control unit 161 determines that a timeout error has occurred.

[0253] 29 is a diagram showing the flow of communication between the main control unit 161 and the medal count control unit 171 after the power is turned on. When the power-on switch 102 is pressed and the power is turned on to the main control unit 161, the main control unit 161 transmits a gaming machine installation information command. Thereafter, when a bet number setting operation is performed, the main control unit 161 transmits a deposit command. Since the deposit command is a command that requires a response command, the medal count control unit 171 transmits a deposit response command to the main control unit 161 based on receiving the deposit command.

[0254] Next, the main control unit 161 transmits a settlement command to the medal count control unit 171 based on the fact that a settlement operation has been performed. The settlement operation is an operation indicating that the bet number clear switch 21 has been pressed. This causes a process to be executed to return the number of bets to the number of credits. Since the settlement command is a command that requires a settlement response command, the medal count control unit 171 transmits the settlement response command to the main control unit 161 based on the fact that the settlement command has been received.

[0255] In FIG. 29, the bet number setting operation is performed again, and communication based on the bet number setting operation is performed. Subsequently, when the start switch 7 is pressed, the main control unit 161 transmits an insertion pulse command to the medal count control unit 171. After transmitting the insertion pulse command, the main control unit 161 performs control to progress the game, such as control to drive the reels, without waiting for a response from the medal count control unit 171. When the medal count control unit 171 receives the insertion pulse command from the main control unit 161, it controls the game to wait for the end of the game as control in response to the insertion pulse command. Since the insertion pulse command is a command that does not require a response command, the medal count control unit 171 does not transmit a response command.

[0256] Based on the fact that all reels have stopped, the main control unit 161 transmits to the medal count control unit 171 in this order: role ratio information 1 command, role ratio information 2 command, total role payout command, and continuous role total payout command. The role ratio information 1 command, role ratio information 2 command, total role payout command, and continuous role total payout command are commands that do not require a response command, so the medal count control unit 171 does not transmit a response command. When the medal count control unit 171 receives the payout pulse command, role ratio information 1 command, role ratio information 2 command, total role payout command, and continuous role total payout command from the main control unit 161, it performs control in response to these commands, such as control to send a payout pulse signal to the hall computer and control to update gaming machine performance information and role ratio monitor information.

[0257] Next, it transmits a payout command to the medal count control unit 171. The medal count control unit 171 performs control to add credits based on the receipt of the payout command, and transmits a payout response command to the main control unit 161. Furthermore, the main control unit 161 transmits a payout pulse command to the medal count control unit 171. The medal count control unit 171 performs control in response to the payout pulse command, such as transmitting a payout pulse signal to the hall computer. Since the payout pulse command is a command that does not require a response command, the medal count control unit 171 does not transmit a response command.

[0258] In this way, when the main control unit 161 transmits an input pulse command, a payout pulse command, a role ratio information 1 command, a role ratio information 2 command, a total payout command for consecutive roles, or a total payout command for consecutive roles that do not affect the number of credits, the main control unit 161 then executes the next control without waiting for a response from the medal count control unit 171, whereas when the main control unit 161 transmits an input command, a settlement command, or a payout command that affects the number of credits, the main control unit 161 then executes the next control on the condition that it has received the response command transmitted from the medal count control unit 171.

[0259] [About bet setting and settlement operations] 30 is a diagram illustrating the bet number setting operation and the settlement operation. As described above, the main control unit 161 transmits an insertion command to the medal count control unit 171 based on the bet number setting operation being performed by pressing the 1BET switch 20 or the MAXBET switch 6. In addition, the main control unit 161 transmits a settlement command to the medal count control unit 171 based on the settlement operation being performed by pressing the bet number clear switch 21.

[0260] As shown in FIG. 30, the main control unit 161 transmits a deposit command to the medal count control unit 171 based on the bet number setting operation. The deposit command is a command including the number of deposited medals. The medal count control unit 171 reads the number of deposited medals included in the received deposit command and performs the bet number setting process. Specifically, the medal count control unit 171 subtracts the number of deposited medals from the number of credits managed by the medal count control unit 171 and adds the number of deposited medals to the bet number. For example, if the number of bets before the bet number setting process is executed is 0 and a valid operation of the MAXBET switch 6 is performed to set the bet number, the medal count control unit 171 subtracts 3 from the number of credits and adds 3 to the bet number. Based on receiving the deposit command, the medal count control unit 171 transmits a deposit response command to the main control unit 161.

[0261] Next, the main control unit 161 transmits a settlement command to the medal count control unit 171 based on the settlement operation being performed. The settlement command is a command that includes the number of settled medals. The medal count control unit 171 reads the number of settled medals included in the received settlement command and performs bet number cancellation processing. Specifically, it subtracts the number of settled medals from the number of bets managed by the medal count control unit 171 and adds the number of settled medals to the number of credits. For example, if the number of bets before the bet number cancellation processing was performed was three and the bet number clear switch 21 was pressed, the medal count control unit 171 subtracts three from the number of bets and adds three to the number of credits. Based on receiving the settlement command, the medal count control unit 171 transmits a settlement response command to the main control unit 161.

[0262] [Display of payout quantity] FIG. 31 is a diagram illustrating the display control of the number of payout coins. After all reels have stopped, the main control unit 161 transmits a payout command to the medal count control unit 171. The payout command shown in FIG. 31 is a command involving at least one payout medal. The medal count control unit 171 transmits a payout response command based on the receipt of the payout command. The medal count control unit 171 also performs operations such as adding credits based on the number of payout medals indicated by the payout command. After receiving the payout response command, the main control unit 161 displays the number of payout coins on the gaming support display 12. That is, after transmitting the payout command, the main control unit 161 causes the gaming support display 12 to display the number of payout coins on the condition that the payout response command has been received. This allows the main control unit 161 to display the number of payout coins on the gaming support display 12 while checking the status of the medal count control unit 171.

[0263] [About in-capacity and out-of-capacity programs] The main control unit 161 of the slot machine 2 of this embodiment executes an in-capacity program and an out-of-capacity program. The in-capacity program is a program that contains instructions related to the progress of a game, such as an internal lottery process. The out-of-capacity program is a program that contains instructions not directly related to the progress of a game, such as error detection. Malfunctions can occur when data is unintentionally mixed between the in-capacity program and the out-of-capacity program. For example, if an instruction from the in-capacity program rewrites data in the out-of-capacity RAM area even though it should, this can result in a program malfunction. To prevent such malfunctions, the main control unit 161 distinguishes between the in-capacity program and the out-of-capacity program, executes the program, and progresses the game.

[0264] The following describes the areas where out-of-capacity programs and in-capacity programs are stored. Fig. 32 is a memory map of the memory area used by the main control unit 161. As shown in Fig. 32, the memory area used by the main control unit 161 includes a memory area allocated to ROM 161b and a memory area allocated to RAM 161c.

[0265] The memory area of ​​the ROM 161b consists of a program / data area where programs and fixed data are stored, an unused area where access is prohibited, and other areas. The other areas include a ROM comment area where any data such as the program title and version can be set, a vector table area where the upper addresses of the subroutines of the CALLV instruction and the start address of the timer interrupt process (main control) are set, a HW parameter area where parameters for setting the internal functions of the main control unit 161 in terms of hardware are set, and the unused area where access is prohibited.

[0266] The memory area of ​​the RAM 161c consists of a usable area that can be used as a work area and other areas. The other areas include an internal function register area that stores registers for controlling the various functions installed in the main control unit 161. The various functions installed in the main control unit 161 include, for example, the functions of the serial communication circuit described below. In other words, the internal function register area of ​​the RAM 161c includes a storage area for setting the functions of the serial communication circuit.

[0267] The program / data area in ROM161b includes an in-capacity program area in which in-capacity programs directly related to the progress of the game are stored, an in-capacity data area in which in-capacity data used by the in-capacity programs is stored, an out-of-capacity program area in which out-of-capacity programs not directly related to the progress of the game are stored, an out-of-capacity data area in which out-of-capacity data used by the out-of-capacity programs is stored, and an unused area.

[0268] The progression of a game refers to the progression of a series of processes that make up the game, and in the case of a slot machine, this refers to the progression of the stages of setting the number of bets and allowing the game to begin, starting the game and spinning the reels, stopping the reels and deriving the display result, and awarding value such as medals based on the display result.

[0269] In the above, the term "before and after" refers to the relationship between the address values ​​assigned to the storage areas, with a smaller address being the front and a larger address being the back. Therefore, a storage area allocated behind a certain storage area corresponds to a storage area with a larger address value than that storage area, and a storage area allocated ahead of that storage area corresponds to a storage area with a smaller address value than that storage area.

[0270] RAM 161c includes an internal RAM area used by internal programs as a work area, an external RAM area used by external programs as a work area, and an unused area where control data is never stored and is always filled with 0s. The internal RAM area also includes an internal stack area where internal programs save data, and the external RAM area also includes an external stack area where external programs save data. A temporary stack area is allocated to a 4-byte area from the last address of the internal RAM area toward the first address, and a payout management temporary stack area is allocated to a further 4-byte area toward the first address. The internal stack area is allocated further toward the first address of the payout management stack area, and data is saved toward the address toward the first address. Data is saved to the external stack area from the last address of the internal RAM area toward the first address.

[0271] As shown in Figure 33, the internal RAM area is composed of areas A to F, an unused area, an internal stack area, and a payout management temporary stack area and temporary stack area used only in the initial setting process (main control) described below. Area A is allocated to store setting values ​​and the status of the setting key switch 37. Area B is allocated to store output buffers for reel motors 32L, 32C, 32R, etc., door commands, advantageous zone signal buffers, AT status, external signal flags, etc. Area C is allocated to store timer counters, LED output buffers, control data for reel motors 32L, 32C, 32R, external signal data, etc. Area D is allocated to store game status, RT status, replay medal counter, counter during BB, etc. Area E is allocated to store stopped reel information (stop order, etc.), win flags, instruction numbers, advantageous zone end flags, reel effects, reel motor status, number of inserted medals, random numbers, reel status, reel control data, etc. Area F is allocated with a payout-related area in which data related to control with the medal count control unit 171 is stored.

[0272] Here, as shown in Figure 33, the area from area A to the payout management temporary stack area is called the area to be initialized entirely, the area from area B to the unused area just before the stack area is called the area to be initialized at the start of a setting change, the area from area C to area E is called the area to be initialized at the end of a setting change, areas D and E are called the area to be initialized at the end of a BB, and area E is called the area to be initialized at the end of each game. The area to be initialized entirely is an area that is initialized when a RAM abnormality error occurs. The area to be initialized at the start of a setting change is an area that is initialized when a setting change begins. The area to be initialized at the end of a setting change is an area that is initialized when a setting change is completed. The area to be initialized at the end of a BB is an area that is initialized at the end of a BB. The area to be initialized at the end of each game is an area that is initialized every time a game is completed.

[0273] In the following, the internal program area, internal data area, and internal RAM area may be collectively referred to as the internal area, and the external program area, external data area, and external RAM area may be collectively referred to as the external area.

[0274] [Initial setting process (main control)] FIG. 34 is a diagram illustrating the initial setting process (main control) performed by the main control unit 161.

[0275] When power supply to the slot machine 2 is started, the main control unit 161 starts up in a state where timer interrupts are set to be prohibited due to the occurrence of a reset, and performs various processes according to the programs stored in the ROM 161b of the main control unit 161. After starting up, first, all output ports are initialized, and initial setting processing (main control) included in the in-capacity program is performed.

[0276] The initial setting process (main control) starts with timer interrupts disabled. As shown in FIG. 34, the initial setting process (main control) first refers to a predetermined area of ​​the input port (Sa1) and determines whether the power interruption detection signal output from the power interruption detection circuit is ON (Sa2). If the power interruption detection signal is ON, the process waits until the power interruption detection signal turns OFF. After that, once the power supply voltage of the slot machine 2 returns to normal and the power interruption detection signal turns OFF, the internal register setting process is performed (Sa3). In the internal register setting process, values ​​indicating the hardware function settings are set.

[0277] Next, the address of the temporary stack area is set in the stack pointer (Sa4), RAM access permission is set (Sa5), and external RAM area initialization processing is called (Sa6). In other words, processing in Sa6 is processing to call an external RAM area program from an internal RAM area program. For this reason, the words "(external RAM)" are added to the end of the processing name. Hereinafter, such processing to call an external RAM area program from an internal RAM area program will be simply referred to as "external RAM area call processing."

[0278] Furthermore, when Sa6 calls the external RAM initialization process, the registers are saved, and at this time, the registers are saved to the temporary stack area set in the stack pointer in Sa5.

[0279] In the external RAM initialization process of Sa6, as shown in Figure 35, first, RAM parity, which is the exclusive OR of the data stored in all areas of RAM161c, is calculated (Sb1), and it is determined whether the RAM parity is 0 (Sb2).

[0280] If power outage processing is performed normally when power is cut off, parity adjustment data is set so that the RAM parity in all areas of RAM161c is 0, and if the RAM parity is not 0 in Sb2, it is determined that an abnormality has occurred in the data stored in RAM161c.

[0281] Furthermore, in Sa6, when the external RAM initialization process is called, the register values ​​are saved in the temporary stack area of ​​RAM 161c, but after the external RAM initialization process is completed and the registers are restored, the temporary stack area is no longer used, the values ​​in the temporary stack area are maintained as they are, and when the external RAM initialization process is called in the initial setting process (main control) the next time the power is turned on, the same register values ​​are stored in the temporary stack area again. In other words, since the same data is always stored in the temporary stack area when no abnormality occurs in the data in RAM 161c, it is possible to correctly determine whether or not an abnormality has occurred in the data stored in RAM 161c even when a determination is made based on the RAM parity of the entire area of ​​RAM 161c, including the values ​​in the temporary stack area.

[0282] If it is determined in Sb2 that the RAM parity is 0, the destructive diagnostic data is acquired (Sb3). The destructive diagnostic data is 1 byte of data that is set in the RAM 161c during power outage processing, and is data in which multiple bits are 1.

[0283] After the destructive diagnosis data is acquired in Sb3, the destructive diagnosis data set in the RAM 161c is cleared (Sb4), and it is determined whether the destructive diagnosis data acquired in Sb3 is 0 (Sb5).

[0284] If the power outage processing is performed normally when the power is cut off, as mentioned above, destructive diagnostic data in which multiple bits are 1 is set in RAM 161c.If the destructive diagnostic data is 0 in Sb5, it is possible that all data has been initialized even if the RAM parity is 0.In such a case, it is determined that an abnormality has occurred in the data stored in RAM 161c.

[0285] If the RAM parity is 0 in Sb2 and the destruction diagnosis data is not 0 in Sb5, that is, if it is determined that the data in the RAM 161c is not abnormal, the process returns to the initial setting process (main control) in FIG.

[0286] On the other hand, if the RAM parity is not 0 in Sb2, or if the data for destruction diagnosis is 0 in Sb5, i.e., if it is determined that the data in RAM 161c is abnormal, the entire area of ​​the extra-RAM area of ​​RAM 161c is initialized (Sb6) without returning to the initial setting process (main control), i.e., the internal program, and a RAM destruction diagnosis flag indicating that the data in RAM 161c has been destroyed is set in a predetermined area of ​​the extra-RAM area (Sb7), and then the initial setting process (main control) of Figure 34 is returned to.

[0287] After the external RAM initialization process in Sa6 is completed, it is determined whether the RAM corruption diagnostic flag is set (Sa7). If it is determined that the RAM corruption diagnostic flag is not set, i.e., if it is determined that the data in RAM 161c is not abnormal, the process proceeds to Sa9. If it is determined that the RAM corruption diagnostic flag is set, i.e., if it is determined that the data in RAM 161c is abnormal, the process initializes all initialization areas of the internal RAM area (Sa8) and proceeds to Sa9. The entire initialization area initialized in Sa8 does not include the temporary stack area and the temporary stack area for payout management, and the data in the temporary stack area and the temporary stack area for payout management is maintained. In particular, by maintaining the data in the temporary stack area, it is possible to ensure that the RAM parity will be 0 after the registers are saved to the temporary stack area the next time the power is turned on.

[0288] In Sa9, the address of the temporary payout management stack area is set in the stack pointer, and the payout management area initialization process that initializes the payout management area is called and executed (Sa10).

[0289] In addition, when Sa10 calls the payout management area initialization process, the registers are saved to the payout management temporary stack area set in the stack pointer in Sa9.However, after the payout management area initialization process is completed and the registers are restored, the payout management temporary stack area is no longer used and the value of the payout management temporary stack area is maintained as is.Therefore, even if the judgment is based on the RAM parity of the entire area of ​​RAM161c, including the value of the payout management temporary stack area, it is possible to correctly determine whether or not an abnormality has occurred in the data stored in RAM161c.

[0290] After the payout management area initialization process in Sa10 is completed, the address of the in-capacity stack area is set in the stack pointer (Sa11), and a gaming machine installation information command is sent to the medal count control unit 171 (Sa12).

[0291] Next, it is determined whether the setting key switch 37 is in the ON state (Sa13), and if it is determined that the setting key switch 37 is in the ON state, i.e., if the power is turned on with the setting key switch 37 in the ON state, the setting change processing shown in Figure 36 is performed.

[0292] If it is determined in Sa13 that the setting key switch 37 is not in the ON state, it is determined whether or not the RAM destruction diagnostic flag is set (Sa14). If it is determined that the RAM destruction diagnostic flag is not set, that is, if it is determined that the data in RAM 161c is not abnormal, it is determined whether or not the reset / setting switch 38 is in the ON state (Sa15). If it is determined that the reset / setting switch 38 is in the ON state, that is, even if the setting key switch 37 is in the OFF state but the power is turned on with the reset / setting switch 38 in the ON state and the data in RAM 161c is not abnormal, the setting change processing shown in Figure 36 is performed.

[0293] As shown in Figure 36, in the setting change process, the area initialized at the start of the setting change in RAM 161c, i.e., the area of ​​the internal RAM area excluding area A where the buffer of the setting value / setting key switch 37 is stored, the internal stack area, the payout management temporary stack area, and the temporary stack area, is initialized (Sc1).

[0294] Next, the external RAM clearing process is called (Sc2). The external RAM clearing process is the external program call process described above. The external RAM clearing process initializes the external RAM area excluding the external stack area.

[0295] After the extraneous RAM clearing process of Sc2 is completed, a setting change start command indicating that the setting change state has started is sent to the performance control unit 151 (Sc3), and it is determined whether the setting key switch 37 is in the ON state (Sc4).

[0296] If it is determined in Sc4 that the setting key switch is not in the ON state, i.e., the setting key switch 37 is in the OFF state, but the power is turned on with the reset / setting switch 38 in the ON state, and the process proceeds to setting change processing, it is determined whether or not a RAM clear permission flag is set in the RAM 161c (Sc5). The RAM clear permission flag is set in the RAM 61c first after the RAM 161c is initialized in the main processing (main control) described below, and indicates that the state before power failure was during the main processing (main control), i.e., a state other than during the initial setting processing (main control), setting change processing, or error processing due to a RAM abnormality.

[0297] If it is determined in Sc5 that the RAM clear permission flag is not set, the timer interrupt is set to permission (Sc6), a RAM abnormality error code indicating that there is an abnormality in the RAM 161c is set in a predetermined register (Sc7), and the process proceeds to error processing, which will be described later.

[0298] If it is determined in Sc5 that the RAM clear permission flag is set, the process proceeds to Sc20, where a setting change end command indicating the end of the setting change process is sent to the performance control unit 151, a timer interrupt process (main control) is waited for once (Sc21), the size of the area in RAM 161c to be initialized when the setting change is completed (the area initialized when the setting change is completed) is set (Sc22), and the process proceeds to main process (main control). In this case, that is, when the setting key switch 37 is OFF, but the power is turned on with the reset / setting switch 38 ON, and the process proceeds to setting change process, if the RAM clear permission flag is set, the internal RAM area excluding area A where the setting value and setting key switch buffer are stored, the internal stack area, the payout management temporary stack area, and the temporary stack area, and the external RAM area excluding the external stack area are initialized, but no new setting values ​​are set, and the system transitions to a playable state with the setting values ​​before the power outage maintained.

[0299] If it is determined in Sc4 that the setting key switch is in the ON state, i.e., the power is turned on with the setting key switch 37 in the ON state and the process proceeds to setting change processing, the setting value is obtained from RAM 161c into the A register (Sc8) and 1 is subtracted from the setting value in the A register (Sc9). At this time, the value obtained from RAM 161c minus 1 is set in the A register. Also, if RAM 161c is cleared due to a RAM abnormality and 0 is stored as the setting value, 0 is set in the A register.

[0300] Next, the setting value of the A register is incremented by 1 (Sc10), and it is determined whether the setting value after the increment exceeds 6 (Sc11). If the setting value after the increment does not exceed 6, proceed to Sc13; if the setting value after the increment exceeds 6, correct the setting value after the increment to 1 (Sc12), and proceed to Sc13.

[0301] In Sc13, the value of the output buffer of the set value display 24 is updated to the updated set value (Sc13), and one interrupt wait process is performed (Sc14). As a result, the timer interrupt is set to enabled, the timer interrupt process (main control) is executed once, and the updated set value is displayed on the set value display 24.

[0302] Thereafter, the process waits until operation of the reset / setting switch 38 or the start switch 7 is detected (Sc15, Sc16), and if operation of the reset / setting switch 38 is detected in Sc15, the process returns to Sc10, and the processing of Sc10 to Sc14 is performed, thereby incrementing and updating the set value by 1 (if the set value after the increment exceeds 6, it is updated to 1), and the process waits again until operation of the reset / setting switch 38 or the start switch 7 is detected (Sc15, Sc16).

[0303] When the start switch 7 is detected in Sc16, the process waits until the setting key switch 37 is detected as OFF (Sc17). When the setting key switch 37 is detected as OFF, the setting value of the A register is confirmed and stored in RAM 161c (Sc18), the value of the output buffer of the setting value display 24 is cleared (Sc19), a setting change end command indicating the end of the setting change process is sent to the performance control unit 151 (Sc20), and a one-time interrupt wait process is performed (Sc21). This executes the timer interrupt process (main control) once, clearing the setting value of the setting value display 24. Next, the process sets the size of the area in RAM 161c that will be initialized when the setting change is completed (the setting change completion initialization area) (Sc22), and then proceeds to main processing (main control). As described below, in the main processing (main control), the area of ​​the specified size up to the final address to be initialized is first initialized. After the setting change process is completed, the process proceeds to main processing (main control), where the setting change completion initialization area in the internal RAM area is initialized.

[0304] Returning to Figure 34, if Sa15 determines that the reset / setting switch 38 is not in the ON state, the stack pointer is restored to the state stored in RAM 161c at the time of power outage (Sa16), a restoration command indicating that the main control unit 161 has restored is sent to the performance control unit 151 (Sa17), and the port input processing is performed twice in succession (Sa18, Sa19).

[0305] The port input process is a process for updating input status data (input data indicating the current input status of the various switches, decision data indicating that the current and previous input data are the same, and edge data indicating that the decision data has changed from the previous time) relating to the input status of the detection signals of the various switches input to the parallel input port. In a predetermined area of ​​the RAM area within the RAM 161c, port input buffers 0 to 2 for storing the input status data of the various switches are provided, and the input status data of the various switches updated by the port input process is stored in a predetermined bit of the port input buffer that is predetermined for each type.

[0306] The detected states (ON state or OFF state) of various switches are stored as input data in predetermined bits of the port input buffer. Furthermore, the detected states (ON state or OFF state) of the previous and current port input processes are compared. If the current and previous input data are the same, the determined data is updated to indicate the detected state of the current input data. On the other hand, if the current and previous input data are different, the previous determined data is maintained. Furthermore, the current and previous determined data are compared. If the determined data changes from an OFF state to an ON state, ON edge data indicating that the determined data has changed from an OFF state to an ON state is stored in predetermined bits of the port input buffers 0 to 2. If the determined data changes from an ON state to an OFF state, OFF edge data indicating that the determined data has changed from an ON state to an OFF state is stored in predetermined bits of the port input buffers 0 to 2. The input data, determined data, and edge data of various switches stored in the port input buffers can be referenced by both internal and external programs.

[0307] Furthermore, by performing the port input process twice consecutively in the initial setting process (main control), when the port input process is subsequently performed, input state data relating to the input states of the detection signals of the various switches is created based on the input states of the various switches after the initial setting process (main control) was performed, i.e., the input states of the various switches after the power supply to the slot machine 2 is resumed. This prevents unintended input situations from being identified. Furthermore, the port input process may be configured to create finalized data based on input data acquired through three or more port input processes (e.g., input data from the current, previous, and previous-previous inputs). In such a configuration, by performing the port input process in the initial setting process (main control) consecutively one less than the number of port input processes required to create finalized data, input state data can be created when the port input process is performed after the initial setting process (main control) is performed, based on the input states of the various switches after the initial setting process (main control).

[0308] After the port input processing is performed in Sa18 and Sa19, all registers are restored to the state before power outage stored in RAM 161c (Sa20), the timer interrupt is set to enabled (Sa21), the initial setting processing (main control) is terminated and transition is made to the timer interrupt processing (main control), and then the processing in the main processing (main control) that was being executed before the power supply to the slot machine 2 was stopped is returned to.

[0309] On the other hand, if it is determined in Sa14 that the RAM destruction diagnostic flag is set, i.e., if it is determined that the data in RAM161c is abnormal, the process proceeds to Sa22, the timer interrupt is set to enabled, a RAM abnormality error code indicating that there is an abnormality in RAM161c is set in a specified register (Sa23), and error processing is started.

[0310] Error processing is a process that controls the game to an error state in which game progress is disabled. An error command that can identify an error code set in a specified register is sent to the performance control unit 151, and the error code is set in a specified area of ​​the RAM 161c as an error flag that can be referenced by other processes (e.g., the sensor monitoring process described below). The error code is also controlled to be displayed on the game support display 12. Thereafter, the error state is controlled until it is determined that the error state release condition corresponding to the error code set in the specified register has been met, rendering game progress disabled. When a RAM abnormality error code is set in a specified register and the game enters an error state, turning on the power switch with the setting key switch 37 turned on switches the game to a setting change state, initializes the data in the RAM 161c, and sets new setting values, thereby disabling the error state. On the other hand, if the power switch is turned on without turning on the setting key switch 37, an abnormality in the RAM 161c is detected again, and the game enters an error state again.

[0311] [Main processing (main control)] FIG. 37 is a diagram explaining the control content of the main processing (main control) performed by the main control unit 161. The main processing (main control) is repeatedly executed for each unit of play (one game). One cycle of the main processing (main control) corresponds to one unit of play. The main processing (main control) is included in the in-capacity program and includes multiple processes. As explained above, in the main processing (main control) shown in FIG. 37, the process name of the process corresponding to the out-of-capacity program call process has the words "(out-of-capacity)" added to the end.

[0312] As shown in FIG. 37, in the main processing (main control), first, an area of ​​a specified size up to the final address to be initialized in the internal RAM area is initialized (Sd1). The final address to be initialized is the final address of area E in the internal RAM area, and an area of ​​the specified size up to the final address of area E is initialized. When transitioning from the setting change processing, the size of the area to be initialized at the end of the setting change is specified, so the area of ​​the internal RAM area to be initialized at the end of the setting change is initialized. Furthermore, at the end of a BB, the size of the area to be initialized at the end of the BB is specified, so the area of ​​the internal area to be initialized at the end of the BB is initialized. Furthermore, at the end of one game, the size of the area to be initialized at the end of one game is specified, so the area of ​​the internal area to be initialized at the end of one game is initialized.

[0313] Next, the RAM clear permission flag is set to ON (Sd2), and a game end command transmission process is performed to transmit a game end command that can identify that one game has ended to the performance control unit 151 (Sd3). The main control unit 161 transmits the game end command based on the fact that the game has ended due to the operation of the stop switches 8L, 8C, and 8R in the previous game, to notify the performance control unit 151 of the end of the game.

[0314] Next, the RT information output process included in the out-of-capacity program is executed (Sb4). In the RT information output process, a test signal is transmitted so that RT information indicating the RT status of the slot machine 2 can be confirmed by a test device installed outside the slot machine. Then, a multiple interrupt wait process is executed (Sd5). The multiple interrupt wait process is executed to ensure the output time of the information output in the RT information output process. That is, the main control unit 161 executes the multiple interrupt wait process to delay the progress of the game for a predetermined period of time. The multiple interrupt wait process is also referred to as a delay process. As a result, the main control unit 161 generates a test signal when the previous game ends, and then waits for a predetermined period of time. This ensures that an external device, such as a test board, reliably receives the test signal, and prevents information discrepancies from occurring between the external device and the main control unit 161.

[0315] Thereafter, a game start waiting process (Sd6) is performed, which will be described later, to perform processing from the end of control of the previous game to the start of the next game. In the game start waiting process, acceptance of bet number settings is started, processing to set the bet number in accordance with the bet number setting operation is performed, and processing to start the next game is performed when operation of the start switch 7 is detected with the specified number of bets set. Furthermore, in the game start waiting process, in accordance with the bet number setting operation, a medal insertion command is sent to the medal number control unit 171, the bet number is set upon reception of a medal insertion response command, a medal settlement command is sent to the medal number control unit 171 in accordance with the settlement operation, and the bet number is canceled upon reception of the settlement response command.

[0316] After the waiting process for the start of the game, an internal lottery process is performed to determine whether or not a win is allowed to occur (internal lottery) (Sd7). In the internal lottery process, an internal lottery is performed to determine whether or not a win is allowed to occur (i.e., whether or not a display result is allowed to be derived) based on a preset setting value (1 to 6) in the slot machine 2 and a random number value for the internal lottery obtained simultaneously with the start of the game by detecting the start switch 7.

[0317] Next, the main control unit 161 performs a ball output control pre-processing for controlling ball output at the start of a game (Sd8). The ball output control pre-processing is a pre-processing for controlling ball output within an advantageous zone.

[0318] Then, after the AT lottery and the like are executed, a presentation control process (Sd9) and a test signal generation process (Sd10) are performed, and an input pulse command is sent to the medal count control unit 171 (Sd11). In the presentation control process, a presentation flag that the main control unit 161 refers to when controlling presentation is set. The test signal generation process corresponds to an out-of-capacity program call process. In the test signal generation process, a test signal is sent so that information indicating the control status of the slot machine 2 can be confirmed by a test device installed outside the slot machine. The information indicating the control status of the slot machine 2 includes the lottery result of the internal lottery process in Sd7.

[0319] Next, the control state command group transmission process (Sd12) and freeze control execution process (Sd13) are performed. In the control state command group transmission process, a control state command group including multiple commands capable of identifying various control states at the start of a game is transmitted to the performance control unit 151. That is, the main control unit 161 outputs information related to the results of the internal lottery and information related to the game state to the performance control unit 151. In the freeze control execution process, the main control unit 161 checks whether or not there is a request for freeze control, which delays game progress until a predetermined termination condition is met. If there is a request, the type of freeze control and the timing to execute the freeze control are set in a predetermined area of ​​RAM 161c, and the freeze control is executed based on the type of freeze control and the execution timing of the freeze control set in RAM 161c. Specifically, if freeze control is set, the freeze control is executed to delay game control for a predetermined period of time.

[0320] Furthermore, when the type of freeze control that involves an effect using reels 2L, 2C, and 2R (hereinafter referred to as reel effect) is set as the type of freeze control, an acceleration pattern for effect (for example, an acceleration pattern that rotates the reels in a direction different from the rotation of the reels in play, an acceleration pattern that starts rotation in the same direction as the rotation of the reels in play at a speed slower than the rotation of the reels in play, an acceleration pattern that vibrates the reels, etc.) is set in a predetermined area of ​​RAM 161c as an excitation pattern for exciting reel motors 32L, 32C, and 32R, and control is performed so that the reel effect is performed during the period when freeze control is being performed.

[0321] Thereafter, the main control unit 161 executes a process of waiting for multiple interrupts (Sd14). The process of waiting for multiple interrupts is executed to ensure the output time of the information output in the test signal generation process. That is, the main control unit 161 executes the process of waiting for multiple interrupts in order to delay the progress of the game for a predetermined period of time.

[0322] After performing the interrupt multiple waiting process in Sd14, the CPU 110 refers to a timer for managing one game time set in a predetermined area of ​​RAM161c to measure the elapsed time from the start of reel rotation in the previous game (Sd15), and determines based on the timer for managing one game time whether the specified time for one game (4.1 seconds in this embodiment) has elapsed from the start of reel rotation in the previous game (Sd16).

[0323] Then, if it is determined that the prescribed time for one game has not elapsed, it waits until the prescribed time for one game has elapsed based on the timer for managing one game time, and after the prescribed time for one game has elapsed based on the timer for managing one game time, it sets a predetermined value (in this embodiment, a value corresponding to 4.1 seconds) in the timer for managing one game time, newly starts measuring the elapsed time from the start of reel rotation (Sd17), and performs a reel rotation start command transmission process to transmit to the performance control unit 151 a reel rotation start command that can specify that rotation control of reels 2L, 2C, and 2R will be started (Sd18). On the other hand, if it is determined in Sd15 that the prescribed time for one game has elapsed, it immediately performs the processes of Sd17 to Sd18. After a predetermined value is set in Sd17, the timer for managing one game's time is decremented every predetermined time, and becomes 0 when the specified time for one game (4.1 seconds in this embodiment) has elapsed from the start of reel rotation in the game. Therefore, it is possible to determine whether the specified time for one game has elapsed based on whether the timer for managing one game's time is 0 or not.

[0324] After the reel rotation start command sending process is performed in Sd18, a jackpot command is sent to the medal count control unit 171 (Sd19), a normal acceleration pattern that controls the rotation of the reels at a predetermined speed for gaming is set in a predetermined area of ​​RAM 161c as the excitation pattern when exciting and controlling the reel motors 32L, 32C, and 32R (Sd20), and a reel rotation start process is performed to start the rotation of the reels by exciting and controlling the reel motors 32L, 32C, and 32R based on the excitation pattern set in RAM 161c (Sd21).

[0325] Next, the navigation notification process is performed (Sd22). In the navigation notification process, the AT is controlled, and if the notification target role is won in the internal lottery, the game auxiliary display 12 is controlled to display a navigation number that can identify a stop mode that is advantageous to the player according to the notification target role, while if the AT is not controlled, the game auxiliary display 12 is controlled not to display the navigation number.

[0326] Next, a reel stop initial setting process (Sd23) is performed to set various information required for reel stop control according to the RT state and the result of the internal lottery. Then, a freeze control execution control process (Sd24) is performed, and if freeze control is set to be performed at that timing, the set type of freeze control is performed.

[0327] After the freeze control process in Sd24, the reel stop control process (Sd25) is performed to control the reels to stop. In the reel stop control process, it is determined whether the reels under rotation control are rotating at a predetermined constant speed. If any reels are not rotating at a constant speed, a reel error is detected, and an excitation pattern is set for the corresponding reel to accelerate to a constant speed, thereby controlling all reels under rotation control to rotate at a constant speed. On the other hand, if all reels under rotation control are rotating at a constant speed, the process enables acceptance of a stop operation for the reels under rotation control and waits for a stop operation via the stop switch. Then, when a valid stop operation is detected for a reel for which a stop operation is enabled (ON edge data is detected for a stop switch for which a stop operation is enabled), the process performs reel stop control to stop the reel for which a valid stop operation has been performed at a predetermined stop position based on information set in the reel stop initial setting process. This reel stop control is repeatedly performed for the reels under rotation control until all reels have stopped rotating, and the reel stop process is completed.

[0328] After the reel stop process is completed, the freeze control process is performed (Sd26), and if it is set that freeze control is to be performed at that timing, the set type of freeze control is performed.

[0329] After that, the RT state check process (Sd27) and the winning determination process (Sd28) are performed. In the RT state check process, it is determined whether or not a combination of RT transition symbols that accompanies a transition to the RT state has stopped on the reels, and if a combination of RT transition symbols has stopped, the current RT state set in a predetermined area of ​​RAM 161c is updated to the RT state corresponding to the combination of RT transition symbols. In the winning determination process, it is determined whether or not an illegal winning has occurred based on the internal lottery result and the symbol combination stopped on reels 2L, 2C, and 2R.

[0330] Then, after the winning determination process in Sd28, data processing for the role ratio monitor is performed (Sd29), and role ratio information transmission processing is performed (Sd30). In the role ratio monitor data processing, data required for updating the gaming machine performance information and role ratio monitor information is calculated. In the role ratio information transmission processing, a role ratio information 1 command, a role ratio information 2 command, a role total payout command, and a consecutive role total payout command are transmitted to the medal count control unit 171 based on the data calculated in the role ratio monitor data processing.

[0331] Next, a stop-play determination process corresponding to the out-of-capacity program call process is performed (Sd31). In the stop-play determination process, it is determined whether the increase in the number of medals awarded to the player has exceeded an upper limit after the number of medals awarded to the player has started to increase. For example, a net increase counter that counts only the + range, i.e., a counter that subtracts the number of medals inserted and adds the number of medals paid out, and corrects the updated value to 0 if it falls below 0, is provided, and it is determined whether the value of the net increase counter has exceeded an upper limit. Then, if it is determined that the increase in the number of medals awarded to the player has exceeded an upper limit after the number of medals awarded to the player has started to increase, a stop-play flag is set in the out-of-capacity RAM area.

[0332] After the stoppage determination process is completed, an error check process is performed (Sd32), and post-processing for ball output control is performed (Sd33) to control ball output at the end of the game. Post-processing for ball output control is post-processing for controlling ball output within the advantageous zone.

[0333] Thereafter, a medal payout process is performed (Sd34). In the medal payout process, a payout command specifying the number of medals to be paid out is sent to the medal count control unit 171, and upon receiving a payout response command, the game control unit 171 controls the game assist display 12 to display the number of medals to be paid out.

[0334] After the medal payout process, the replay LED is controlled to the OFF state (light off state) (Sd35), the replay in progress flag indicating that a replay is in progress is cleared (Sd36), a payout pulse command is sent to the medal count control unit 171 (Sd37), freeze control execution process is performed (Sd38), and if freeze control is set to be performed at that timing, the set type of freeze control is performed.

[0335] Then, a game end setting process is performed (Sd39), which determines whether the replay symbol combination has stopped on reels 2L, 2C, and 2R. If the replay symbol combination has stopped, the process sets the number of bets to be made for a replay in the next game (in this embodiment, the replay symbol counter set in a predetermined area of ​​RAM 161c is set to 3 as the number of replay symbols), sets a replay flag in a predetermined area of ​​RAM 161c, and controls the replay LED to the ON state (lit state). In the game end setting process, it is determined whether the number of medals won during the advantageous zone has reached 2,400. If the number of medals won during the advantageous zone has reached 2,400, the advantageous zone is ended and the control returns to the normal zone.

[0336] Then, the size of the area of ​​RAM 161c to be initialized at the end of the game is set (Sd40). As a result, the area to be initialized at the end of one game is initialized in Sd2 of the next game.

[0337] Next, it is determined whether or not a stop flag is set in the external RAM area (Sd41). If it is determined in Sd40 that the stop flag is not set, the process returns to Sd1. As a result, the main control unit 161 returns to the process of Sd1 and repeats the process from Sd1 again. When the main process (main control) is completed, the process related to the control of one unit of game is completed, and the main process (main control) is repeatedly executed for each unit of game.

[0338] On the other hand, if it is determined in Sd41 that the play stop flag is set, i.e., if it is determined in Sd31 that the number of medals awarded to the player has increased and the increase in the number of medals awarded has exceeded the upper limit, a play stop error code is set (Sd42), and then error processing is initiated, rendering the game unable to proceed. In error processing resulting from the setting of the play stop error code, turning on the power switch with the setting key switch 37 turned on shifts the system to a setting change state, initializes the data in RAM 161c, and sets new settings. Alternatively, turning on the power switch with the setting key switch 37 turned off but the reset / setting switch 38 turned on shifts the system to a setting change state, initializes the data in RAM 161c, and clears the error state. On the other hand, turning on the power switch without turning on the setting key switch 37 or the reset / setting switch 38 re-enters the error state.

[0339] [Timer interrupt processing (main control)] The control content of the timer interrupt processing (main control) performed by the main control unit 161 of this embodiment will be described with reference to Fig. 38. The timer interrupt processing (main control) is a subroutine included in the in-capacity program, and is executed by interrupting the main processing (main control) every 0.56 ms.

[0340] 38, in the timer interrupt process (main control), first, all the front registers and back registers are exchanged (Se1), and then it is determined whether or not a voltage drop signal has been input (Se2). If a voltage drop signal has been input, the value of the voltage drop status counter stored in RAM 161c is updated (Se3), and it is determined whether or not the voltage drop status counter has reached a predetermined upper limit (4 in this embodiment) (Se4). If the voltage drop status counter has reached the upper limit, power cut-off process (main control) is performed (Se5).

[0341] In the power cutoff process (main control), all front registers are exchanged with back registers, and the values ​​of all registers provided in the main control unit 161 are saved. Then, after initializing the output port, destruction diagnosis data is set in a predetermined area of ​​RAM 161c, and the parity adjustment data set in a predetermined area of ​​RAM 161c is cleared. Then, new parity adjustment data for RAM 161c is calculated so that the exclusive OR of all storage areas of RAM 161c becomes 0, and the parity adjustment data is set in a predetermined area of ​​RAM 161c, access to RAM 161c is prohibited, and loop processing begins.

[0342] In the loop processing, the system waits while monitoring the output status of the voltage drop signal. In this state, if the voltage drop signal is no longer input, it determines that the voltage has recovered and starts the program from the initial setting processing (main control). On the other hand, if the voltage drops while the voltage drop signal is still being input, the system will internally stop operating.

[0343] If it is determined in step Se2 of the timer interrupt processing (main control) that a voltage drop signal has not been input, and if it is determined in step Se4 that the voltage drop status counter has not reached its upper limit value, the process proceeds to step Se6, where the detection status of various switches is input from the input port, and port input processing is performed to generate input data, determination data, and edge data (ON edge data and OFF edge data).

[0344] Then, a time monitoring update process included in the out-of-capacity program is performed (Se7). The time monitoring update process sequentially performs a test signal output process that outputs a test signal generated in relation to the game result, a timer update process that updates various timers used by the out-of-capacity program, and the like.

[0345] Next, the watchdog timer (WDT) register is cleared (Se8). A medal count control transmission process (Se9), a response information reception process (Se10), and a medal count control side information reception process (Se11) are performed. The medal count control transmission process controls the transmission of commands from the main control unit 161 to the medal count control unit 171. The response information reception process is a process that confirms the reception of an insertion response command, a settlement response command, a payout response command, and an overflow response command from the medal count control unit 171. The medal count control side information reception process is a process that confirms the reception of a medal count control side information command from the medal count control unit 171, and identifies the state of the medal count control unit 171 side.

[0346] Next, the value of the branch counter in the RAM 161c is updated (Se12). In the process of updating the branch counter, if the branch counter is between 0 and 2, 1 is added, and if the branch counter is 3, the branch counter is initialized and returned to 0, thereby updating the value within the range of 0 to 3. In other words, the value of the branch counter loops in the order of 0 → 1 → 2 → 3 → 0... each time the timer interrupt process (main) is executed.

[0347] After updating the branch counter in step Se12, it is determined whether the branch counter is 3 (Se13), and if the branch counter is 3, a counter update process (Se14) is performed to update various timers set in RAM 161c, and an LED dynamic display process (Se15) is performed to dynamically light up various indicators such as LEDs.

[0348] If it is determined in step Se13 that the branching counter is not 3, and after the LED dynamic display process is performed in step Se15, a reel control process is performed (Se16) to control the rotation and stopping of the reels by setting the excitation pattern of each reel motor 32L, 32C, 32R according to the progress of the game, etc.

[0349] After the reel control process, a drive signal according to the excitation pattern set by the reel control process is output to each reel motor 32L, 32C, 32R, thereby causing each reel motor 32L, 32C, 32R to rotate and stop in a predetermined control manner, and a port output update process (Se18) is performed in sequence to update the state of the output port. After that, all front and back registers are exchanged (Se19), the timer interrupt process (main control) is terminated, and the process returns to the main process (main control) that was in effect when the timer interrupt process (main control) was started.

[0350] [Memory area of ​​medal count control unit] The medal count control unit 171 of the slot machine 2 of this embodiment executes an in-capacity program and an out-of-capacity program, similar to the main control unit 161. The in-capacity program of the medal count control unit 171 is a program in which commands related to the progress of the game, such as adding and subtracting credits, are written. The out-of-capacity program of the medal count control unit 171 is a program in which commands not directly related to the progress of the game, such as error detection and output control of external signals, are written.

[0351] Like the main control unit 161, the memory area of ​​the medal count control unit 171 also includes a memory area allocated to ROM 171b and a memory area allocated to RAM 171c. The memory area of ​​ROM 171b includes a program / data area in which programs and fixed data are stored, and a ROM comment area in which arbitrary data such as the program title and version can be set. The memory area of ​​RAM 171c includes a usable area that can be used as a work area, and an internal function register area in which a group of registers for controlling each function installed in the medal count control unit 171 is stored.

[0352] The program / data area in ROM171b includes an in-capacity program area in which in-capacity programs directly related to the progress of the game are stored, an in-capacity data area in which in-capacity data used by the in-capacity programs is stored, an out-of-capacity program area in which out-of-capacity programs not directly related to the progress of the game are stored, and an out-of-capacity data area in which out-of-capacity data used by the out-of-capacity programs is stored.

[0353] The RAM 171c includes an internal RAM area used by internal programs as a work area and an external RAM area used by external programs as a work area. The internal RAM area includes an internal stack area where the internal programs save data, and the external RAM area includes an external stack area where the external programs save data.

[0354] [Initial setting process (medal count control)] FIG. 39 is a diagram for explaining the initial setting process (medal count control) performed by the medal count control unit 171 of the medal count control unit 171.

[0355] When power supply to the slot machine 2 is started, the medal count control unit 171 starts up in a state where timer interrupts are set to be prohibited due to the occurrence of a reset, and performs various processes according to the programs stored in the ROM 171b provided in the medal count control unit 171. After starting up, first, all output ports are initialized, and initial setting processing (medal count control) included in the in-capacity program is performed.

[0356] The initial setting process (medal count control) starts with timer interrupts disabled. As shown in Figure 39, the initial setting process (medal count control) first sets the stack pointer to the internal stack area (Sf1), then references a specified area of ​​the input port to determine whether the power interruption detection signal output from the power interruption detection circuit is ON (Sf2). If the power interruption detection signal is ON, the process waits until the power interruption detection signal turns OFF. After that, once the power supply voltage of the slot machine 2 returns to normal and the power interruption detection signal turns OFF, RAM access permission is set (Sf3), and an interrupt vector (the area storing the start address of the timer interruption process (medal count control)) is set (Sf4).

[0357] Next, a parity check is performed on the internal RAM area and the external RAM area in RAM 171c (Sf5), and it is determined whether the parity is normal (Sf6). If it is determined that the parity is normal, it is further determined whether the power outage detection flag is set (Sf7). If the power outage processing is performed normally at the time of power outage, the power outage detection flag is set in RAM 171c. If the power outage detection flag is not set in Sf7, even if the parity is normal, all data may have been initialized. In such a case, it is determined that an abnormality has occurred in the data stored in RAM 171c.

[0358] If the parity is determined to be normal in step Sf6 and if it is determined that the power outage detection flag is set in step Sf7, the process proceeds to step Sf10. If it is determined that the parity is not normal in step Sf6, that is, if an abnormality has occurred in the data in RAM 171c, or if the power outage detection flag is not set in step Sf7, that is, if the power outage processing has not been performed normally, the area of ​​the internal RAM area excluding the internal stack area is initialized (Sf8), and the external RAM clear processing is called to initialize the area of ​​the external RAM area excluding the external stack area (Sf9), and the process proceeds to step Sf10.

[0359] In step Sf10, an internal register setting process is performed, in which values ​​indicating the hardware function settings are set.

[0360] Next, it is determined whether the RAM clear switch 293 is in the ON state (Sf11), and if the RAM clear switch 293 is not in the ON state, the process proceeds to step Sf13, and if the RAM clear switch 293 is in the ON state, the area in RAM 171c where the number of credits is stored is cleared to 0, and the process proceeds to step Sf13.

[0361] In step Sf13, the area of ​​the RAM area within RAM171c that is to be uniformly initialized at startup is initialized (Sf13), and the startup initialization process (outside the capacity) is called to initialize the area of ​​the RAM area outside the capacity of RAM171c that is to be uniformly initialized at startup (Sf14).

[0362] Next, the data required at startup is set in RAM 171c, the state of the main control unit 161 corresponding to the external signal is set (Sf16), the number of credits to be displayed on the credit display 11 is set in the display buffer (Sf17), and the process proceeds to the main processing (medal number control).

[0363] [Main processing (medal count control)] FIG. 40 is a diagram for explaining the control contents of the main processing (control of the number of medals) performed by the main control unit 161.

[0364] As shown in Figure 40, in the main processing (medal count control), first, interrupts are set to permitted (Sg1), and the process waits until the timer interrupt processing (medal count control) is executed (Sg2). Whether the timer interrupt processing (medal count control) has been executed is confirmed by checking whether the interrupt flag set in the timer interrupt processing (medal count control) is set in RAM 171c.

[0365] When execution of the timer interrupt processing (medal count control) is confirmed in step Sg2, the interrupt flag is cleared (Sg3), the interrupt is set to prohibited (Sg4), power-off processing (Sg5), main board communication processing (Sg6), gaming machine fraud information processing (Sg7), counting processing (Sg8), CU communication processing (Sg9), medal count control side information setting processing (Sg10), counting LED processing (Sg12), credit count display setting processing (Sg13), error processing (Sg14), and external signal output processing (out of capacity) (Sg15) are executed in sequence, and the process returns to step Sg1 and loops.

[0366] In the power failure processing in step Sg5, it is determined whether a power failure has been detected based on the power failure detection signal, and if it is determined that a power failure has been detected, adjustment data is set so that the parity of the internal RAM area and the external RAM area is 0, and a power failure detection flag is set.

[0367] In the main board communication process in step Sg6, processing is performed according to the command received from the main control unit 161. For example, when a deposit command, a settlement command, or a payout command is received from the main control unit 161, the number of credits is updated and a process is performed to send a deposit response command, a settlement response command, and a payout response command to the main control unit 161. When a deposit pulse command or a payout pulse command is received from the main control unit 161, the process is performed to set the number of deposit pulses for external output and the number of payout pulses for external output. When a jackpot command is received from the main control unit 161, the process is performed to update the jackpot signal for external output. When a role ratio information 1 command, a role ratio information 2 command, a total payout command for bonus items, or a total payout command for consecutive bonus items is received from the main control unit 161, the process is performed to update the gaming machine performance information and the role ratio monitor information. When an overflow command is received from the main control unit 161, the process is performed to check the number of credits and send an overflow response command to the main control unit 161.

[0368] In the gaming machine fraud information processing in step Sg7, when a gaming machine fraud command is received from the main control unit 161, processing is performed to update the state of the main control unit 161 corresponding to the external signal.

[0369] In the counting process in step Sg8, when an operation of the counting button 10 is detected, the credit number is converted into the medal number.

[0370] In the CU communication process in step Sg9, processing according to the command received from the CU control unit 323 is performed, and processing for transmitting necessary information (counting information and gaming machine information) to the CU control unit 323 is also performed.

[0371] In the medal count control side information setting process in step Sg10, a process for updating the control state on the medal count control unit 171 side is performed.

[0372] In the medal count control side information transmission process in step Sg11, a process of transmitting a medal count control side information command to the main control unit 161 is performed.

[0373] The credit number display setting process in step Sg12 is a process for setting the display buffer of the credit display 11.

[0374] In the error processing in step Sg13, if an error is detected, processing is performed to control the system to an error state.

[0375] In the test signal output process (outside capacity) in step Sg14, a process for outputting a test signal is performed.

[0376] [About timer interrupt processing (medal count control)] The control content of the timer interruption processing (medal count control) performed by the medal count control unit 171 of this embodiment will be described with reference to Fig. 41. The timer interruption processing (medal count control) is a subroutine included in the in-capacity program, and is executed by interrupting the main processing (medal count control) every 1 ms.

[0377] As shown in Figure 41, in the timer interrupt process (medal count control), first, the register values ​​are saved to the stack (Sh1), and then an interrupt flag indicating that the timer interrupt process (medal count control) has been performed is set in the RAM 171c (Sh2). Next, the interrupt counter is updated (Sh3). The interrupt counter is a counter for specifying the 2 ms processing timing and the 4 ms processing timing, and is updated by 1 within the range of 0 to 3 each time the timer interrupt process (medal count control) is executed.

[0378] Next, the main board communication timer is updated (Sh4). The main board communication timer is a counter that determines the timing for clearing the number of commands received from the main control unit 161, etc. It is determined whether the main board communication timer value is 0 (Sh5), and if the main board communication timer value is 0, the number of main control commands received and the flag indicating there are unanalyzed commands are cleared (Sh6, 7).

[0379] Next, the CU communication timer is updated (Sh8). The CU communication timer is a counter that specifies the timing for clearing the CU reception flag and the like from the CU control unit 323. It is determined whether the CU communication timer value is 0 (Sh9), and if the CU communication timer value is 0, the CU reception flag and reception pointer are cleared (Sh10).

[0380] Next, output processing is performed to update the state of the output port (Sh11), and it is determined whether or not it is 2 ms processing time (Sh12).

[0381] If it is determined in step Sh12 that it is time for 2 ms processing, the following steps are performed in sequence: 1-byte timer processing (Sh13) to update the 1-byte timer value, port input processing (Sh14) to obtain the status of the input port, switch detection processing (Sh15) to obtain the detection status of the switch, and 2 ms processing (out of capacity) (Sh16) performed every 2 ms.

[0382] Next, it is determined whether or not the processing timing is 4 ms (Sh17).

[0383] If it is determined in step Sh17 that it is time for 4 ms processing, the following steps are performed in sequence: 2-byte timer processing (Sh18) to update the 2-byte timer value, and 4 ms processing (outside capacity) (Sh16) performed every 4 ms.

[0384] Next, the registers that were saved to the stack are restored (Sh20), the interrupt is set to enabled (Sh21), and the process returns to the main processing (medal count control) that was in effect when the timer interrupt processing (medal count control) was started.

[0385] [Microcomputer configuration] In this embodiment, the microcomputers that constitute the main control unit 161 and the medal count control unit 171 are the same product (same product number) from the same manufacturer, that is, microcomputers with the same specifications.

[0386] The microcomputer that constitutes the main control unit 161 and the medal count control unit 171 includes a CPU, ROM, and RAM, which are connected via an internal bus, as shown in Fig. 42. It also includes a clock circuit CLK that inputs a system clock supplied from a control clock circuit mounted on a board on which this microcomputer is mounted, first to third timer circuits TC1 to TC3 as timer circuits, first and second serial communication circuits SR1 and SR2 that are capable of sending and receiving data as serial communication circuits, and third to fifth serial communication circuits SR3 to SR5 that are only capable of sending data, all of which are connected via an internal bus.

[0387] [Serial communication circuit configuration] Of the serial communication circuits provided in the microcomputers that constitute the main control unit 161 and the medal count control unit 171, the first and second serial communication circuits SR1 and SR2 that are capable of transmitting and receiving data are provided with a data register, a transmission register, a transmission unit, a reception register, and a reception unit, as shown in Fig. 43(A). The data register is used for both transmission data and reception data. The third to fifth serial communication circuits SR3 to SR5 that are only capable of transmitting data are provided with a data register, a transmission register, and a transmission unit.

[0388] When transmitting data, the transmission data is written to the data register. The transmission data written to the data register is stored in the transmission register. The transmission data stored in the transmission register is transferred to the transmission unit in the order in which it was stored, converted into a serial signal, and transmitted from the corresponding output terminal. On the other hand, when receiving data, the serial signal received from the corresponding input terminal is converted into reception data by the reception unit and stored in the reception register. The reception data stored in the reception register is transferred to the data register, and it becomes possible to read the reception data from the data register.

[0389] 43(A), the serial communication circuit transmits and receives data based on communication settings (transmission enabled / disabled, reception enabled / disabled, data format (10-bit format / 11-bit format, parity enabled / disabled, LSB first / MSB first)) that are based on the setting values ​​of the function setting register. Also, the baud rate can be set based on the setting values ​​of the function setting register, and the data transmission speed and reception speed can be changed.

[0390] As shown in FIG. 43(B), data register addresses, output terminals, input terminals, baud rate setting addresses, and communication setting addresses corresponding to the first to fifth serial communication circuits SR1 to SR5 are defined.

[0391] The address of the data register of the first serial communication circuit SR1, i.e., the area where the transmitted data and received data are stored, is FF27h, the output terminal is TX0, the input terminal is RX0, the address of the area where the baud rate settings are set is FE0Ah in the lower byte and FE0Bh in the upper byte, and the address of the area where the communication settings are set is FE0Ch.

[0392] The address of the data register of the second serial communication circuit SR2 is FF2Bh, the output terminal is TX1, the input terminal is RX1, the address of the area for setting the baud rate setting is FE0Eh in the lower byte and FE0Fh in the upper byte, and the address of the area for setting the communication setting is FE10h.

[0393] The address of the data register of the third serial communication circuit SR3 is FF2Eh, the output terminal is TX2, the address of the area for setting the baud rate setting is FE12h in the lower byte and FE13h in the upper byte, and the address of the area for setting the communication setting is FE14h.

[0394] The address of the data register of the fourth serial communication circuit SR4 is FF30h, the output terminal is TX3, the address of the area for setting the baud rate setting is FE15h in the lower byte and FE16h in the upper byte, and the address of the area for setting the communication setting is FE17h.

[0395] The address of the data register of the fifth serial communication circuit SR5 is FF32h, the output terminal is TX4, the address of the area for setting the baud rate setting is FE18h in the lower byte and FE19h in the upper byte, and the address of the area for setting the communication setting is FE1Ah.

[0396] [Connection between the main control unit, medal count control unit, and CU control unit] 44, both the main control unit 161 and the medal count control unit 171 are mounted on the main control board 16, and two-way communication is performed between the first serial communication circuit SR1 of the main control unit 161 and the second serial communication circuit SR2 of the medal count control unit 171, and one-way communication is performed from the medal count control unit 171 to the main control unit 161 between the second serial communication circuit SR2 of the main control unit 161 and the third serial communication circuit SR3 of the medal count control unit 171. For this reason, the output terminal TX0 and input terminal RX0 corresponding to the first serial communication circuit SR1 of the main control unit 161 are connected to the input terminal RX1 and output terminal TX1 corresponding to the second serial communication circuit SR2 of the medal count control unit 171, respectively, and the input terminal RX1 corresponding to the second serial communication circuit SR2 of the main control unit 161 is connected to the output terminal TX2 corresponding to the third serial communication circuit SR3 of the medal count control unit 171.

[0397] In addition, two-way communication is performed between the first serial communication circuit SR1 of the medal count control unit 171 and the CU control unit 323 of the CU control board 32, and the output terminal TX0 and input terminal RX0 corresponding to the first serial communication circuit SR1 of the medal count control unit 171 are connected to the input terminal and output terminal of the CU control unit 323, respectively.

[0398] In addition, since the third serial communication circuit SR3 of the main control unit 161 is used for one-way communication to the performance control unit 151 of the performance control board 15, the output terminal TX2 corresponding to the third serial communication circuit SR3 of the main control unit 161 is connected to the input terminal of the performance control unit 151.

[0399] In addition, a common 30 MHz system clock generated by a clock generation circuit SCLK mounted on the main control board 16 is input to the main control unit 161 and the medal count control unit 171, and a 15 MHz clock signal obtained by dividing this clock signal by two is used as the system clock of the main control unit 161 for sending and receiving data in the first to fifth serial communication circuits SR1 to SR5 of the main control unit 161 and for timer counting by the first to third timer circuits TM1 to TM3 described later, and as the system clock of the medal count control unit 171 for sending and receiving data in the first to fifth serial communication circuits SR1 to SR5 of the medal count control unit 171 and for timer counting by the first to third timer circuits TM1 to TM3 described later.

[0400] In the two-way communication between the main control unit 161 and the medal count control unit 171, all commands from the main control unit 161 are sent to the medal count control unit 171, and commands other than medal count control commands from the medal count control unit 171 are sent to the main control unit 161.

[0401] As shown in Figure 45(A), in the two-way communication between the main control unit 161 and the medal count control unit 171, the main control unit 161 uses the first serial communication circuit SR1, the data register used is FF27h, and the output and input terminals used are TX0 and RX0, while the medal count control unit 171 uses the second serial communication circuit SR2, the data register used is FF2Bh, and the output and input terminals used are TX1 and RX1. The main control unit 161 and the medal count control unit 171 use different serial communication circuits, data register addresses, and output and input terminals. On the other hand, the baud rate setting and communication settings are the same, with both baud rate settings being 187,500 bps (bits per second), and both communication settings being send enabled, receive enabled, and 10-bit format (LSB first, no parity).

[0402] In the one-way communication between the main control unit 161 and the medal count control unit 171, a medal count control command is sent from the medal count control unit 171 to the main control unit 161.

[0403] As shown in Figure 45 (B), in one-way communication between the main control unit 161 and the medal count control unit 171, the main control unit 161 side uses the second serial communication circuit SR2, the data register used is FF2Bh, and the input terminal used is RX1, while the medal count control unit 171 side uses the third serial communication circuit SR3, the data register used is FF2Eh, and the output terminal used is TX2. In addition, the baud rate setting is the same for both, with the baud rate setting being 93750 bps (bits per second), and the data format of the communication setting is the same for both, with the 10-bit format (LSB first, no parity).

[0404] In the two-way communication between the medal count control unit 171 and the CU control unit 323, all commands from the medal count control unit 171 are sent to the CU control unit 323, and all commands from the CU control unit 323 are sent to the medal count control unit 171.

[0405] As shown in Figure 45 (C), in the two-way communication between the medal count control unit 171 and the CU control unit 323, the medal count control unit 171 side uses the first serial communication circuit SR1, the data register used is FF27h, the output terminal and input terminal used are TX0 and RX0, the baud rate setting is 62,500 bps (bits per second), and the communication settings are send allowed, receive allowed, 10-bit format (LSB first, no parity).

[0406] In this embodiment, the communication speed between the main control unit 161 and the medal count control unit 171 is 187,500 bps (bits / second) and 93,750 bps (bits / second), and the communication speed between the medal count control unit 171 and the CU control unit 323 is 62,500 bps (bits / second), and communication between the main control unit 161 and the medal count control unit 171 is performed at a faster communication speed than communication between the medal count control unit 171 and the CU control unit 323.

[0407] In this embodiment, the communication between the main control unit 161 and the medal count control unit 171 is performed at a faster communication speed than the communication between the medal count control unit 171 and the CU control unit 323, but the communication between the main control unit 161 and the medal count control unit 171 may be performed at the same communication speed as the communication between the medal count control unit 171 and the CU control unit 323, or the communication between the main control unit 161 and the medal count control unit 171 may be performed at a slower communication speed than the communication between the medal count control unit 171 and the CU control unit 323.

[0408] In addition, the communication speed for two-way communication between the main control unit 161 and the medal count control unit 171 is 187,500 bps (bits / second), and the communication speed for one-way communication between the main control unit 161 and the medal count control unit 171 is 93,750 bps (bits / second), so that two-way communication between the main control unit 161 and the medal count control unit 171 is performed at a faster communication speed than in the case of one-way communication.

[0409] In this embodiment, the two-way communication between the main control unit 161 and the medal count control unit 171 is performed at a faster communication speed than in the case of one-way communication, but the two-way communication between the main control unit 161 and the medal count control unit 171 may be performed at the same communication speed as in the case of one-way communication, or the two-way communication between the main control unit 161 and the medal count control unit 171 may be performed at a slower communication speed than in the case of one-way communication.

[0410] [About the timer circuit configuration] The first to third timer circuits TM1 to TM3 provided in the microcomputer that constitutes the main control unit 161 and the medal count control unit 171 include a prescaler setting register, a count value setting register, a prescaler, and a timer counter, as shown in Figure 46 (A).

[0411] The prescaler setting register is a function setting register that sets the thinning rate for thinning out the number of clocks output from the system clock to the timer counter, and the count value setting register is a function setting register that sets the value at which the timer counter times out. The prescaler setting register functions as a trigger to stop counting by the timer counter by setting a set prescaler value, and the count value setting register functions as a trigger to start counting by the timer counter by setting a set count value.

[0412] The prescaler supplies a clock signal to the timer counter, which is an externally supplied system clock that has been thinned out at a thinning rate according to the set prescaler value. The timer counter then counts (counts) the clock signal input from the prescaler, and when the count value reaches the set count value, it sets a timeout flag to notify a timeout. The set prescaler value and set count value are changeable, and the time from the start of counting until a timeout is notified can be set according to the set prescaler value and set count value. Furthermore, if a timeout occurs, the count (counting) starts again from 0, and a timeout is notified when the count value reaches the set count value, so it is possible to notify a timeout every time the set time according to the set prescaler value and set count value has elapsed.

[0413] As shown in Figure 46(B), the addresses of the prescaler setting register and count value setting register corresponding to the first to third timer circuits TM1 to TM3 are determined, and it is possible to set the time until a timeout is notified, and the start and stop of measurement for each of the first to third timer circuits TM1 to TM3.

[0414] The address of the prescaler setting register of the first timer circuit TM1 is FF01h, and the counter value setting address is FF03h. The address of the prescaler setting register of the second timer circuit TM2 is FF04h, and the counter value setting address is FF06h. The address of the prescaler setting register of the third timer circuit TM3 is FF07h, and the counter value setting address is FF09h.

[0415] [About interrupt settings in the main control unit and medal count control unit] The microcomputer that constitutes the main control unit 161 and the medal count control unit 171 can generate interrupts in response to the occurrence of multiple interrupt factors. The multiple interrupt factors include a first timer interrupt due to time-up of the first timer circuit TM1, a second timer interrupt due to time-up of the second timer circuit TM2, a third timer interrupt due to time-up of the third timer circuit TM3, an RX0 interrupt due to reception by the first serial communication circuit SR1, an RX1 interrupt due to reception by the second serial communication circuit SR2, and an XINT interrupt due to a signal input to the XINT terminal. The priority of the multiple interrupt factors and the enable / disable of the multiple interrupt factors can be set. The priority of the multiple interrupt factors can be set by setting a setting value in the program management area in ROM, and the enable / disable of the multiple interrupt factors can be set by setting a setting value in the interrupt mask setting register.

[0416] In addition, the microcomputer constituting the main control unit 161 and the medal count control unit 171 is equipped with an interrupt vector table having multiple areas in which the starting address (interrupt vector) of the processing to be executed in accordance with each of multiple interrupt factors can be set.

[0417] 47(A), in this embodiment, the setting of the priority of the interrupt factors of the main control unit 161 and the setting of the priority of the interrupt factors of the medal count control unit 171 are common, and in both cases the priorities are set in the order of RX0 interrupt, RX1 interrupt, first timer interrupt, second timer interrupt, third timer interrupt, and XINT interrupt. Also, the setting of whether to enable / disable the interrupt factors of the main control unit 161 and the setting of whether to enable / disable the interrupt factors of the medal count control unit 171 are common, and in both cases only the second timer interrupt is set to be enabled, and the other interrupt factors are set to be disabled.

[0418] Furthermore, in both the main control unit 161 and the medal count control unit 171, because only the second timer interrupt is enabled, an interrupt vector is set in the address area corresponding to the second timer interrupt in the interrupt vector table in both cases. In the interrupt vector table of the main control unit 161, the leading address of the timer interrupt processing (main control) is set as an interrupt vector in the address area corresponding to the second timer interrupt, and when the second timer interrupt occurs, the timer interrupt processing (main control) is executed. On the other hand, in the interrupt vector table of the medal count control unit 171, the leading address of the timer interrupt processing (medal count control) is set as an interrupt vector in the address area corresponding to the second timer interrupt, and when the second timer interrupt occurs, the timer interrupt processing (medal count control) is executed.

[0419] 47(B), the system clock frequencies used by the second timer circuit TM2 used as an interrupt factor for the main control unit 161 and the medal count control unit 171 are both 15 MHz. This system clock is generated by the same clock generation circuit SCLK mounted on the main control board 16 as described above, and is a clock signal obtained by dividing the 30 MHz clock signal input to the main control unit 161 and the medal count control unit 171 by two. The set prescaler value set for the second timer circuit TM2 of the main control unit 161 is 150, the set count value is 56, and the timeout period is set to 0.56 ms. On the other hand, the set prescaler value set for the second timer circuit TM2 of the medal count control unit 171 is 150, the set count value is 100, and the timeout period is set to 1 ms. In this way, the same second timer circuit TM2 is used as an interrupt factor for the main control unit 161 and the medal count control unit 171, and different timeout periods are set by setting the same set prescaler value and changing the set count value.

[0420] [Regarding the setting order of the built-in registers in the main control unit and medal count control unit] Figure 48(A) is a diagram showing the order in which the main control unit 161 sets the built-in register (function setting register) during the initial setting process performed when the power is turned on, and Figure 48(B) is a diagram showing the order in which the medal count control unit 171 sets the built-in register (function setting register) during the initial setting process performed when the power is turned on.

[0421] 48(A), when the main control unit 161 sets the built-in registers in the initial setting process, it first sets a set prescaler value in the prescaler setting register of the second timer circuit TM2, sets a set counter value in the count value setting register of the second timer circuit TM2 to start counting by the timer counter of the second timer circuit TM2, and sets the interrupt mask register to enable / disable the interrupt cause. Thereafter, it sets the baud rate setting register and communication setting register of the first serial communication circuit SR1, the baud rate setting register and communication setting register of the second serial communication circuit SR2, and the baud rate setting register and communication setting register of the third serial communication circuit SR3 in that order, and then sets the other function setting registers.

[0422] 48(B), when setting the built-in register in the initial setting process, the medal count control unit 171 first sets the set prescaler value in the prescaler setting register of the second timer circuit TM2, and sets the interrupt mask register to enable / disable the interrupt cause. After that, it sets the baud rate setting register and communication setting register of the first serial communication circuit SR1, the baud rate setting register and communication setting register of the second serial communication circuit SR2, and the baud rate setting register and communication setting register of the third serial communication circuit SR3 in that order, and then sets the set counter value in the count value setting register of the second timer circuit TM2 to start counting by the timer counter of the second timer circuit TM2.

[0423] [Control of the main control unit and medal count control unit when powered on] The microcomputers constituting the main control unit 161 and the medal count control unit 171 can set a security time in the program management area of ​​the ROM to delay the time until the user program starts after startup. In this embodiment, as shown in Fig. 49, the main control unit 161 sets a security time, while the medal count control unit 171 does not set a security time (sets it to 0), and the medal count control unit 171 starts the user program before the main control unit 161.

[0424] 49, after the main control unit 161 is started by powering on and the security time has elapsed, it starts a user program and performs initial setting processing. In the initial setting processing of the main control unit 161, before determining whether the setting key switch 37 is ON, that is, before determining whether to initialize the data in the RAM 161c and transition to a setting change state in which the setting value can be changed, the main control unit 161 reads out the gaming machine type, identification code, chip ID, manufacturer code, and product code to create a gaming machine installation information command, and sends the gaming machine installation information command including this information to the medal count control unit 171. The chip ID is 8 bytes of data stored in the CID register (FE94h to FE9Bh) of the main control unit 161, the manufacturer code is 3 bytes of data stored in 3FC8h to 3FCAh of ROM 161b of the main control unit 161, and the product code is 8 bytes of data stored in 3FCBh to 3FD2h of ROM 161b of the main control unit 161. The chip ID, manufacturer code, and product code are read from these address areas to create a gaming machine installation information command.

[0425] On the other hand, since the security time is not set for the medal count control unit 171 when the power is turned on, the medal count control unit 171 starts a user program and performs initial setting processing earlier than the main control unit 161. In the initial setting processing of the medal count control unit 171, a startup initialization area of ​​the RAM 171c is initialized. The startup initialization area includes a specific area of ​​the RAM 171c in which installation information (main control) and installation information (medal count control), which will be described later and are stored in the gaming machine installation information transmitted to the CU control unit 323, are stored. The installation information (main control) and installation information (medal count control) are initialized by initializing the startup initialization area. In addition, in the initial setting processing of the medal count control unit 171, the chip ID, manufacturer code, and product code of the medal count control unit 171 are read and stored as installation information (medal count control) in a specific area of ​​the RAM 171c. The memory area of ​​the medal count control unit 171 is shared with the memory area of ​​the main control unit 161, and the same addresses are assigned to them. The chip ID of the medal count control unit 171 is 8-byte data stored in the CID register (FE94h to FE9Bh) just like the main control unit 161, the manufacturer code of the medal count control unit 171 is 3-byte data stored at 3FC8h to 3FCAh in ROM 161b of the medal count control unit 171, and the product code of the medal count control unit 171 is 8-byte data stored at 3FCBh to 3FD2h in ROM 161b of the medal count control unit 171, and the chip ID, manufacturer code, and product code of the medal count control unit 171 are read from these address areas and stored in a specific area of ​​RAM 171c. In other words, the chip ID, manufacturer code, and product code of the medal count control unit 171 are read from the same address area as the addresses where the chip ID, manufacturer code, and product code of the main control unit 161 are stored, and stored in a specific area of ​​RAM 171c. After the initial setting process is completed, the medal count control unit 171 transitions to the main process, thereby lighting up the count LED 10a in white and informing that the counting operation is invalid.

[0426] Thereafter, the medal count control unit 171 waits until it receives a gaming machine installation information command from the main control unit 161. In this state, even if it receives a command other than the gaming machine installation information command from the main control unit 161, it discards the received command. Then, upon receiving the gaming machine installation information command from the main control unit 161, the medal count control unit 171 stores the gaming machine type, identification code, chip ID, manufacturer code, and product code of the main control unit 161 included in the gaming machine installation information command as installation information (main control) in a specific area of ​​the RAM 171c. The installation information (main control) is stored in an area in the specific area starting from the address next to the last address of the storage area for the installation information (medal count control). In other words, the installation information (medal count control) and the installation information (main control) are set in consecutive address areas. Then, the medal count control unit 171 reads out the installation information (main control) and installation information (medal count control) stored in the specific area to create gaming machine installation information, and transmits the gaming machine installation information including the installation information (main control) and installation information (medal count control) to the CU control unit 323, while also enabling reception of lending information from the CU control unit 323, and transmission of lending response information, counting information (information related to the counting process from credits to held medals), and gaming machine information to the CU control unit 323. In this way, the CU control unit 323 that has received the gaming machine installation information enables the lending operation.

[0427] Furthermore, after transmitting the gaming machine installation information to the CU control unit 323, the medal count control unit 171 validates the counting operation and stops the white lighting of the counting LED 10a to notify that the counting operation has been validated. Furthermore, upon receiving the gaming machine installation information command, the medal count control unit 171 thereafter creates a medal count control information command every 500 ms and transmits it to the main control unit 161.

[0428] After completing the initial setting process, the main control unit 161 waits in a state where it prohibits the transmission of gaming operations such as bet number setting operations, settlement operations, and start operations, as well as input commands, settlement commands, and payout commands to the medal number control unit 171 until it receives a medal number control side information command.The medal number control unit 171 then receives a medal number control side information command that is sent in response to receiving the gaming machine installation information command, and thereby permits the transmission of gaming operations such as bet number setting operations, settlement operations, and start operations, as well as input commands, settlement commands, and payout commands to the medal number control unit 171, thereby making it possible to start the game.

[0429] [Action Effect 1-1] The slot machine 2 of this embodiment includes a main control unit 161 that controls games, and a medal count control unit 171 that controls credits owned by a player, and the medal count control unit 171 is connectable to be able to communicate with the CU control unit 323 of the card unit 3, which is an externally connected device. The main control unit 161 and the medal count control unit 171 are both microcomputers of the same specifications that have a first serial communication circuit SR1 that receives data to a data register assigned with FF27h, and a second serial communication circuit SR2 that receives data to a data register assigned with FF2Bh. The main control unit 161 communicates with the medal count control unit 171 using the first serial communication circuit SR1, and the medal count control unit 171 communicates with the main control unit 161 using the second serial communication circuit SR2, and communicates with the CU control unit 323 of the card unit 3 using the first serial communication circuit SR1. With this configuration, the main control unit 161 and the medal count control unit 171 In this way, microcomputers of the same specifications are used, both of which have a first serial communication circuit SR1 that receives data to a data register assigned to FF27h and a second serial communication circuit SR2 that receives data to a data register assigned to FF2Bh, and the serial communication circuit used by the main control unit 161 when communicating with the medal count control unit 171 is different from the serial communication circuit used by the medal count control unit 171 when communicating with the main control unit 161.Therefore, even when microcomputers of the same specifications are used as the main control unit 161 and the medal count control unit 171, confusion between the program executed by the main control unit 161 and the program executed by the medal count control unit 171 can be prevented.

[0430] The slot machine 2 of this embodiment includes a main control unit 161 that controls games, and a medal count control unit 171 that controls credits owned by a player. The medal count control unit 171 is communicably connectable with a CU control unit 323 of the card unit 3, which is an externally connected device. The main control unit 161 and the medal count control unit 171 are both microcomputers with the same specifications, each having a first serial communication circuit SR1 that transmits data written to a data register assigned with FF27h, and a second serial communication circuit SR2 that transmits data written to a data register assigned with FF2Bh. The main control unit 161 communicates with the medal count control unit 171 using the first serial communication circuit SR1, and the medal count control unit 171 communicates with the main control unit 161 using the second serial communication circuit SR2, and communicates with the CU control unit 323 of the card unit 3, which is an externally connected device, using the first serial communication circuit SR1. With this configuration, the main control unit 161 and the medal count control unit 171 can communicate with each other. 71, microcomputers of the same specifications are used, both of which have a first serial commu...

Claims

[Claim 1] A gaming machine capable of playing games, a game control microcomputer that controls the game; a value control microcomputer that controls gaming values ​​owned by players; Equipped with The game control microcomputer and the value control microcomputer are both microcomputers with the same specifications that have a counting means capable of counting by thinning out the supplied clock signals, and an interrupt means capable of generating an interrupt when the count value of the counting means reaches a predetermined number, and that can identify the address of the process to be executed when an interrupt is generated based on data stored in one of a plurality of areas when an interrupt is generated by the interrupt means, The game control microcomputer specifies an address of a process to be executed when an interrupt occurs based on data stored in a specific area among the multiple areas when an interrupt occurs by the interrupt means; When an interrupt is generated by the interrupt means, the value control microcomputer identifies an address of a process to be executed in response to the generation of the interrupt based on the data stored in the specific area among the multiple areas; The frequency of the clock signal supplied by the game control microcomputer and the value control microcomputer is the same; The time intervals at which the interrupts occur are different between the game control microcomputer and the value control microcomputer, A gaming machine in which, in setting the time interval for generating the interrupt, the thinning rate of the clock signal in the counting means differs between the game control microcomputer and the value control microcomputer, and the value of the predetermined number at which the count value of the counting means reaches and the interrupt means generates an interrupt differs.

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