Power supply circuit

Abstract

To provide a power supply circuit capable of appropriately suppressing inrush current and improving power factor.SOLUTION: A power supply circuit (1) includes a PFC transistor (9), an inrush resistance element (3) connected between a second input line (L2) and a second output terminal (T4), an inrush control transistor (4) connected in parallel with the inrush resistance element, and a PFC control circuit (30) that detects the voltage across the inrush control transistor when it is in the ON state and controls the PFC transistor (9) on the basis of the detected voltage.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a power supply circuit. [Background technology]

[0002] Patent Document 1 discloses an inrush current suppression circuit, which switches a changeover switching element connected in parallel to a first resistor in accordance with a terminal voltage detected by a voltage detection circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-122158 Summary of the Invention [Problem to be solved by the invention]

[0004] Incidentally, power supply circuits that convert AC to DC and supply it require power factor correction (PFC) in addition to suppressing inrush current. To detect the inductor current for power factor correction, it is conceivable to add a resistive element to the current path and detect the voltage across the resistive element. However, adding this resistive element naturally increases losses, which is not desirable.

[0005] An object of one embodiment of the present invention is to provide a power supply circuit that can appropriately suppress inrush current and improve the power factor. [Means for solving the problem]

[0006] A power supply circuit according to a first aspect of the present invention comprises a first positive output terminal and a second negative output terminal, a first positive input wiring and a second negative input wiring, a coil having one end connected to the first input wiring, a power factor correction transistor connected between the other end of the coil and the second output terminal, an inrush resistance element connected between the second input wiring and the second output terminal, an inrush resistance transistor connected in parallel to the inrush resistance element, and a power factor correction control circuit that detects the voltage across both ends of the inrush control transistor in an on state and controls the power factor correction transistor based on the detected voltage.

[0007] According to the above configuration, the on-resistance of the inrush control transistor for suppressing the inrush current can be used to control the power factor correction transistor for power factor correction. Therefore, a resistive element for measuring the inductor current for power factor correction can be omitted. Therefore, loss can be reduced by the amount of the resistive element for measuring the inductor current. Therefore, inrush current suppression and power factor correction can be performed appropriately.

[0008] A power supply circuit according to a second aspect of the present invention may be configured in the above-mentioned first aspect such that the inrush resistance element is a thermistor.

[0009] According to the above configuration, the inrush current can be appropriately suppressed by using a thermistor whose resistance changes depending on heat generation (temperature). Because the resistance of a thermistor changes, it is not suitable for measuring current for power factor correction. However, the above power supply circuit can detect the inductor current by utilizing the on-resistance of the inrush control transistor connected in parallel to the thermistor.

[0010] A power supply circuit according to a third aspect of the present invention may be configured in the first aspect above, wherein the inrush control transistor is an n-type field effect transistor.

[0011] According to the above configuration, the loss can be reduced by the small on-resistance of the n-type field effect transistor, and the on-resistance can also be used to control power factor correction.

[0012] A power supply circuit according to a fourth aspect of the present invention may be configured in the first aspect described above, further comprising a reverse current prevention transistor connected between the other end of the coil and the first output terminal, and a forced shutoff circuit that detects the voltage across the inrush current control transistor in an on state and forcibly maintains the reverse current prevention transistor in an off state while the detected voltage is below a threshold.

[0013] According to the above configuration, the on-resistance of the inrush control transistor 4 is used to determine whether the condition is close to a condition where backflow may occur, and if so, the backflow prevention transistor is forcibly turned off, thereby reducing loss in the power supply circuit and preventing backflow.

[0014] A power supply circuit according to a fifth aspect of the present invention may be configured in accordance with the first aspect above, further comprising an inrush control circuit that switches the inrush control transistor to an on state after a period has elapsed since the input voltage was applied.

[0015] A power supply circuit according to a sixth aspect of the present invention may be configured such that, in the fifth aspect described above, the inrush control circuit turns the inrush control transistor on, then turns the inrush control transistor off, and then turns the inrush control transistor on.

[0016] According to the above configuration, by providing a plurality of ON-state periods sandwiched between OFF-state periods, it is possible to reduce the peak of the inrush current.

[0017] A power supply circuit according to a seventh aspect of the present invention may be configured in the above-mentioned fifth aspect such that the inrush control circuit alternates between an on period during which the inrush control transistor is turned on and an off period during which the inrush control transistor is turned off, gradually increasing the proportion of the on period in one on / off cycle.

[0018] According to the above configuration, the peak of the inrush current when the inrush control transistor is turned on can be reduced, and the output voltage can be raised to a stable state more quickly.

[0019] A power supply circuit according to an eighth aspect of the present invention may be configured in accordance with the seventh aspect above, wherein the inrush control circuit gradually increases the length of the on-period.

[0020] A ninth aspect of the present invention relates to the power supply circuit of the seventh aspect, and may be configured such that the inrush control circuit gradually reduces the length of the off period.

[0021] A power supply circuit according to aspect 10 of the present invention may be configured in the above-mentioned aspect 8 such that the inrush control circuit includes a reference generation circuit that generates a reference voltage having a voltage waveform that repeatedly increases and decreases, a detection circuit that detects the output voltage between the first output terminal and the second output terminal, and a control signal generation circuit that generates a control signal for controlling the inrush control transistor by comparing the reference voltage with a first voltage corresponding to the output voltage.

[0022] According to the above configuration, by comparing the gradually increasing output voltage with the reference voltage having a voltage waveform that repeatedly increases and decreases, it is possible to easily generate a control signal in which the proportion of the on-period gradually increases.

[0023] A power supply circuit according to an eleventh aspect of the present invention may be configured in the tenth aspect above, wherein the voltage waveform of the reference voltage is a triangular wave, a sawtooth wave, or a sine wave.

[0024] A power supply circuit according to a twelfth aspect of the present invention may be configured in accordance with the tenth aspect above, such that the control signal generating circuit sets the period during which the first voltage exceeds the reference voltage as the on period.

[0025] A power supply circuit according to aspect 13 of the present invention may be configured such that, in aspect 10 above, the detection circuit includes a subtraction circuit that outputs, as a detection result of the output voltage, a second voltage corresponding to the difference between the potential of the first output terminal and the potential of the second output terminal when the potential of the second input wiring is used as a reference.

[0026] According to the above configuration, even if the second input wiring is grounded, it is possible to output the detection result of the output voltage with respect to the ground. [Effects of the Invention]

[0027] According to one aspect of the present invention, it is possible to appropriately suppress inrush current and improve the power factor. [Brief explanation of the drawings]

[0028] [Figure 1] 1 is a circuit diagram showing a configuration of a power supply circuit according to an embodiment of the present invention; [Figure 2] FIG. 10 is a diagram showing the output voltage, control signal, and input current during a certain period immediately after the input of AC input voltage. [Figure 3] 1 is a circuit diagram showing a configuration of a power supply circuit according to an embodiment of the present invention; [Figure 4] 3A and 3B are diagrams illustrating an example of an output voltage, a reference voltage, and a control signal. [Figure 5] 1 is a circuit diagram showing a configuration of a power supply circuit according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0029] [Embodiment 1] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to one aspect of the present invention (hereinafter also referred to as "the present embodiment") will be described below with reference to the drawings.

[0030] §1 Application Examples 1 is a circuit diagram showing the configuration of a power supply circuit 1 according to this embodiment. The power supply circuit 1 receives AC voltage from an input side, converts the AC voltage to DC, and outputs the DC voltage from an output side to a load 90. The power supply circuit 1 includes a first input terminal T1, a second input terminal T2, a first positive-side output terminal T3, a second negative-side output terminal T4, a rectifier circuit 2, a first positive-side input wiring L1, a second negative-side input wiring L2, an inrush resistance element 3, an inrush control transistor 4, and a PFC transistor 9. The inrush resistance element 3 is connected between the second negative-side input wiring L2 and the second negative-side output terminal T4. The inrush control transistor 4 is connected in parallel with the inrush resistance element 3. The inrush resistance element 3 and the inrush control transistor 4 are used to suppress inrush current.

[0031] In order to control the PFC transistor 9 for power factor correction, the inductor current needs to be sensed.

[0032] The power supply circuit 1 of this embodiment does not have a resistor element for measuring current, but instead utilizes the on-resistance of the inrush control transistor 4, which is provided to suppress inrush current. The power supply circuit 1 detects the voltage across both ends of the inrush control transistor 4 in the on state and controls power factor correction based on that voltage. This reduces loss due to the resistor element for measuring current.

[0033] §2 Configuration example The configuration of the power supply circuit 1 will be described in more detail with reference to Fig. 1. The power supply circuit 1 includes a first input terminal T1, a second input terminal T2, a first positive output terminal T3, a second negative output terminal T4, a rectifier circuit 2, a first positive input wiring L1, a second negative input wiring L2, an inrush resistance element 3, an inrush control transistor 4, a smoothing capacitor 5, a coil 6, a first diode 7, a second diode 8, a PFC transistor 9, an inrush control circuit 10, and a PFC control circuit 30.

[0034] The first input terminal T1 and the second input terminal T2 are terminals to which an AC input voltage is input. The rectifier circuit 2 rectifies the AC to DC. Here, the rectifier circuit 2 is a bridge circuit including a plurality of diodes, but is not limited to this and may be a circuit including a plurality of switching elements. The rectifier circuit 2 has a first AC terminal 2a connected to the first input terminal T1, a second AC terminal 2b connected to the second input terminal T2, a positive terminal 2c, and a negative terminal 2d. The rectifier circuit 2 outputs a DC (pulsating) input voltage V1 from the positive terminal 2c and the negative terminal 2d.

[0035] The first input wiring L1 is a wiring connected to the positive terminal 2c of the rectifier circuit 2. The second input wiring L2 is a wiring connected to the negative terminal 2d of the rectifier circuit 2. The voltage between the first input wiring L1 and the second input wiring L2 is a DC (pulsating) input voltage V1. The second input wiring L2 is grounded.

[0036] One end of the inrush resistance element 3 is connected to the second negative input wiring L2, and the other end of the inrush resistance element 3 is connected to the second output terminal T4. The inrush resistance element 3 may be, for example, a thermistor whose resistance decreases as the temperature increases. The thermistor's resistance value changes significantly in response to temperature changes, making it suitable as an element for suppressing inrush current.

[0037] The inrush control transistor 4 is connected in parallel to the inrush resistance element 3. The inrush control transistor 4 is, for example, an n-type field effect transistor. The n-type field effect transistor has a small on-resistance, which reduces loss. Because the n-type field effect transistor is controlled by a positive gate voltage, it is more convenient to provide the inrush control transistor 4 on the low side (between the negative terminal 2d and the second output terminal T4) rather than on the high side (between the positive terminal 2c and the first output terminal T3). The on-resistance of the inrush control transistor 4 (resistance value in the on state) is much smaller than the resistance value of the inrush resistance element 3 (small enough to be negligible in the on state).

[0038] The smoothing capacitor 5 is connected between the first output terminal T3 and the second output terminal T4.

[0039] The coil 6 is connected to the first positive input wiring L1. The anode of the first diode 7 is connected to the coil 6, and the cathode is connected to the first output terminal T3. The second diode 8 is connected in parallel to the coil 6 and the first diode 7. The cathode of the second diode 8 is connected to the first output terminal T3.

[0040] One end of the PFC transistor 9 (power factor correction transistor) is connected to the node between the coil 6 and the first diode 7, and the other end of the PFC transistor 9 is connected to the second output terminal T4. The coil 6, the first diode 7, the second diode 8, and the PFC transistor 9 form a boost circuit. The PFC transistor 9 is driven by the PFC control circuit 30 and improves the power factor of the power supply circuit 1. The PFC transistor 9 is, for example, an n-type field effect transistor.

[0041] The PFC control circuit 30 (power factor correction control circuit) detects the voltage across the inrush control transistor 4 and controls the PFC transistor 9 based on the detected voltage. The PFC control circuit 30 obtains the GND potential of the grounded second input line L2 from the GND terminal. The PFC control circuit 30 obtains the potential of the second output terminal T4 from the IS terminal. The PFC control circuit 30 obtains the potential of the first input line L1 from the Vin terminal. The PFC control circuit 30 obtains the potential of the first output terminal T3 from the FB terminal. The PFC control circuit 30 outputs a signal for controlling the on / off of the PFC transistor 9 from the OUT terminal to the control terminal of the PFC transistor 9.

[0042] The first output terminal T3 is a positive output terminal. The second output terminal T4 is a negative output terminal. The voltage between the first output terminal T3 and the second output terminal T4 is a smoothed DC output voltage V2. The first output terminal T3 and the second output terminal T4 output the output voltage V2 to the load 90.

[0043] After an AC input voltage is applied to the power supply circuit 1, the output voltage V2 gradually increases. During the period immediately after this application, the peak value of the potential of the first input wiring L1 > the potential of the first output terminal T3 > the potential of the second output terminal T4 > the potential of the second input wiring L2 (ground) is satisfied. Because a current flows through the inrush resistance element 3, the potential of the second output terminal T4, which is the negative side of the output, becomes higher than the potential of the second input wiring L2, which is ground.

[0044] The inrush control circuit 10 determines the output voltage V2. The inrush control circuit 10 controls the inrush control transistor 4 based on the output voltage V2. The inrush control circuit 10 obtains the GND potential of the grounded second input wiring L2 from the GND terminal. The inrush control circuit 10 obtains the potential of the first output terminal T3 from the VT3 terminal. The inrush control circuit 10 obtains the potential of the second output terminal T4 from the VT4 terminal. The inrush control circuit 10 outputs a signal for controlling the on / off of the inrush control transistor 4 from the OUT terminal to the control terminal of the inrush control transistor 4.

[0045] (Example of operation of inrush control circuit 10) After an AC input voltage is applied to the power supply circuit 1, the inrush control circuit 10 waits a period of time before switching on the inrush control transistor 4. For example, if the output voltage V2 is equal to or less than a first threshold, the inrush control circuit 10 switches off the inrush control transistor 4. If the output voltage V2 is greater than the first threshold, the inrush control circuit 10 switches on the inrush control transistor 4. Immediately after the input voltage is applied, the output voltage V2 is equal to or less than the first threshold, so the inrush control transistor 4 is off. The current flows through the inrush resistance element 3, suppressing the inrush current. The output voltage V2 between the first output terminal T3 and the second output terminal T4 gradually increases and approaches the input voltage V1. When the output voltage V2 exceeds the first threshold, the inrush control circuit 10 switches on the inrush control transistor 4. After that, the current flows through the inrush control transistor 4, reducing loss. This suppresses the inrush current and stabilizes the power supply. A more detailed description of the operation of the inrush control circuit 10 will be provided later.

[0046] (Example of operation of the PFC control circuit 30) The PFC control circuit 30 controls the PFC transistor 9 to perform power factor correction based on the input voltage V1, the output voltage V2, and the current flowing through the inrush control transistor 4. In a stable state after the inrush control transistor 4 is switched on, the PFC control circuit 30 detects the voltage across the inrush control transistor 4. A current equal to the current (inductor current) flowing through the coil 6 flows through the inrush control transistor 4. The inrush control transistor 4 in the on state has a specific resistance value (on-resistance). Therefore, the voltage across the inrush control transistor 4 corresponds to the inductor current. The PFC control circuit 30 can detect the current flowing through the inrush control transistor 4 by detecting the voltage across the inrush control transistor 4 in the on state. The PFC control circuit 30 controls the PFC transistor 9 based on the detected voltage across the inrush control transistor 4 (i.e., based on the current flowing through the inrush control transistor 4). For example, the PFC control circuit 30 determines the timing to turn on the PFC transistor 9 based on the current flowing through the inrush control transistor 4.

[0047] In the power supply circuit 1, in order to perform power factor correction control, the PFC control circuit 30 detects the voltage across the inrush control transistor 4, which is provided to suppress inrush current. This allows the PFC control circuit 30 to detect the inductor current. This makes it possible to omit a resistive element for measuring the inductor current. As a result, the power supply circuit 1 can reduce losses by the amount of the resistive element for measuring the inductor current.

[0048] (Detailed operation example of the inrush control circuit 10) 2 is a diagram showing the output voltage V2, control signal St, and input current IL during a certain period immediately after the application of an AC input voltage. The horizontal axis represents time. The control signal St is a control signal output from the inrush control circuit 10 to the control terminal of the inrush control transistor 4. The input current IL is a current input from the rectifier circuit 2, i.e., an inductor current. When the control signal St is H (High), the inrush control transistor 4 is turned on, and when the control signal St is L (Low), the inrush control transistor 4 is turned off.

[0049] The inrush control circuit 10 turns on the inrush control transistor 4, turns off the inrush control transistor 4, and then turns on the inrush control transistor 4. For example, the inrush control circuit 10 repeats an on period during which the inrush control transistor 4 is turned on and an off period during which the inrush control transistor 4 is turned off.

[0050] 2, after an AC input voltage is applied, the output voltage V2 rises and exceeds the first threshold Vth at time t1. Once the output voltage V2 exceeds the first threshold Vth, the inrush control circuit 10 operates by repeating an on-period and an off-period. The on-period is from time t1 to t2, the off-period is from time t2 to t3, the on-period is from time t3 to t4, and so on. When the inrush control transistor 4 is turned on, the input current IL increases rapidly.

[0051] If no OFF period is provided, the input current IL increases suddenly after the inrush control transistor 4 is turned on, and flows as an inrush current with a high peak.

[0052] In the inrush control circuit 10 of this embodiment, the increased input current IL is reduced by providing an off period. Because the input current IL increases intermittently during the discontinuous on periods, the peak of the input current IL can be kept low. During this period, the output voltage V2 increases in accordance with the flowing input current IL and eventually reaches a stable state. After time t13, the inrush control circuit 10 continues to maintain the inrush control transistor 4 in the on state.

[0053] Here, the inrush control circuit 10 gradually increases the proportion of the on-period in one on / off cycle. For example, the on-period (t12-t11) in one cycle from time t11 to t13 is longer than the on-period (t2-t1) in one cycle from time t1 to t3. In the first on-period, the rate of increase of the input current IL is high. On the other hand, in later on-periods, the rate of increase of the input current IL is slower than in earlier on-periods. Therefore, even if the consecutive on-periods are made longer, the peak of the input current IL can be suppressed. By making the on-period longer, the output voltage V2 can be raised to a stable state more quickly.

[0054] The inrush control circuit 10 may gradually increase the proportion of the on period in one cycle by gradually increasing the length of the on period. The inrush control circuit 10 may gradually increase the proportion of the on period in one cycle by gradually decreasing the length of the off period. Alternatively, the inrush control circuit 10 may gradually increase the proportion of the on period in one cycle by gradually increasing the length of the on period and gradually decreasing the length of the off period.

[0055] [Embodiment 2] Other embodiments of the present invention will be described below. For ease of explanation, the same reference numerals will be used to designate components having the same functions as those described in the above embodiment, and the description thereof will not be repeated.

[0056] (Configuration of power supply circuit 1a) 3 is a circuit diagram showing the configuration of a power supply circuit 1a of this embodiment. The power supply circuit 1a differs from embodiment 1 in that it includes an inrush control circuit 10a instead of the inrush control circuit 10. The inrush control circuit 10a is configured with an analog circuit. The inrush control circuit 10a includes a detection circuit 11, a reference generation circuit 12, a control signal generation circuit 13, a first buffer circuit 16, a second buffer circuit 17, and resistance elements R1 to R4.

[0057] The resistor element R1 and the resistor element R2 are connected in series between the first output terminal T3 and the second input wiring L2, and form a first voltage dividing circuit.

[0058] The input terminal of the first buffer circuit 16 is connected to the node between the resistor element R1 and the resistor element R2.

[0059] The resistor element R3 and the resistor element R4 are connected in series between the second output terminal T4 and the second input wiring L2, and form a second voltage dividing circuit.

[0060] The input terminal of the second buffer circuit 17 is connected to the node between the resistor element R3 and the resistor element R4.

[0061] The detection circuit 11 includes a first operational amplifier 11a and resistors R11 to R14 that form a subtraction circuit. The non-inverting input terminal of the first operational amplifier 11a is connected to the output terminal of the first buffer circuit 16 via a resistor R13. The non-inverting input terminal of the first operational amplifier 11a is connected to the second input wiring L2 via a resistor R14. The inverting input terminal of the first operational amplifier 11a is connected to the output terminal of the second buffer circuit 17 via a resistor R11. The inverting input terminal of the first operational amplifier 11a is connected to the output terminal of the first operational amplifier 11a via a resistor R12. The output of the first operational amplifier 11a is the output of the detection circuit 11.

[0062] The reference generation circuit 12 generates a reference voltage having a voltage waveform that repeatedly increases and decreases. The reference voltage may have, for example, a periodically changing voltage waveform. The voltage waveform of the reference voltage may be, for example, a triangular wave, a sawtooth wave, or a sine wave. The frequency of the reference voltage may be higher than the frequency of the AC input voltage input to the power supply circuit 1a. The reference generation circuit 12 outputs the reference voltage to the control signal generation circuit 13. The reference generation circuit 12 generates a reference voltage based on ground (the potential of the second input wiring L2).

[0063] The control signal generating circuit 13 includes a first comparator 13a. A non-inverting input terminal of the first comparator 13a is connected to the output terminal of the first operational amplifier 11a. An inverting input terminal of the first comparator 13a is connected to the output terminal of the reference generating circuit 12. An output terminal of the first comparator 13a is connected to the control terminal (gate) of the inrush control transistor 4.

[0064] (Operation of inrush control circuit 10a) A first voltage divided by a predetermined voltage division ratio, which corresponds to the difference between the potential of the first output terminal T3 and the potential of the second input line L2, is input to the first buffer circuit 16. The first buffer circuit 16 outputs the input first voltage.

[0065] A second voltage divided by a predetermined voltage division ratio, which corresponds to the difference between the potential of the second output terminal T4 and the potential of the second input line L2, is input to the second buffer circuit 17. The second buffer circuit 17 outputs the input second voltage.

[0066] The detection circuit 11 outputs the difference between the first voltage and the second voltage as a third voltage. If the resistance values ​​of the resistive elements R11 to R14 are r11 to r14, respectively, and r11=r13 and r12=r14, then the following relationship holds. Third voltage = (r12 / r11) (first voltage - second voltage) The first voltage and the second voltage are both voltages relative to ground (the potential of the second input wiring L2). Therefore, the third voltage obtained as the subtraction result by the detection circuit 11 is also a voltage relative to ground (the potential of the second input wiring L2). Therefore, the third voltage obtained as the subtraction result by the detection circuit 11 is a value corresponding to the output voltage V2. In this way, the detection circuit 11 detects the output voltage V2.

[0067] The control signal generating circuit 13 compares a third voltage corresponding to the output voltage V2 with a reference voltage to generate a control signal St for controlling the inrush control transistor 4. If the third voltage is greater than the reference voltage, the control signal generating circuit 13 turns on the inrush control transistor 4. If the third voltage is equal to or less than the reference voltage, the control signal generating circuit 13 turns off the inrush control transistor 4.

[0068] If a subtraction circuit were to simply subtract the potentials of the first output terminal T3 and the second output terminal T4 as inputs to obtain V2, the output (V2) of the subtraction circuit would be a voltage based on the potential of the second output terminal T4. When viewed from the ground (the potential of the second input wiring L2), the potential of this output would change due to fluctuations in the potential of the second output terminal T4. Therefore, this output cannot be used to properly compare V2 with the reference voltage.

[0069] In this embodiment, the detection circuit 11 receives as input the potentials of the first output terminal T3 and the second output terminal T4 relative to the potential (ground) of the second input wiring L2. That is, the detection circuit 11 receives as input the voltage difference between the potential of the first output terminal T3 and the potential (ground) of the second input wiring L2, and the voltage difference between the potential of the second output terminal T4 and the potential (ground) of the second input wiring L2. The detection circuit 11 then generates a third voltage corresponding to the difference (V2) between these potentials. As a result, the third voltage becomes a voltage corresponding to the output voltage V2 relative to the potential (ground) of the second input wiring L2.

[0070] In this way, the inrush control circuit 10a obtains all voltages used in the calculations as voltages based on the potential of the second input wiring L2, thereby enabling appropriate evaluation of the comparison between the output voltage V2, which has a different negative potential, and the reference voltage, which is the output of the reference generation circuit 12. Furthermore, because the inrush control circuit 10a realizes these calculations using analog circuits, the circuit configuration can be made compact.

[0071] 4 is a diagram showing an example of an output voltage V2, a reference voltage, and a control signal St. The vertical axis represents voltage (V). The horizontal axis represents time (ms). The dashed line represents the output voltage V2. The dotted-dash line represents the reference voltage. The solid line represents the control signal St.

[0072] The reference voltage has a triangular waveform. The output voltage V2 increases over time and eventually intersects with the triangular reference voltage. While the output voltage V2 exceeds the reference voltage, the control signal generation circuit 13 outputs a high-level control signal St to the control terminal of the inrush control transistor 4. Thus, the control signal generation circuit 13 defines the period during which the output voltage V2 exceeds the reference voltage as the on-period of the inrush control transistor 4. As the output voltage V2 increases, the length of consecutive on-periods increases and the length of consecutive off-periods decreases. Once the output voltage V2 exceeds the peak of the reference voltage, the control signal generation circuit 13 continues to maintain the inrush control transistor 4 in the on-state. In this way, by comparing the output voltage V2 with a reference voltage having a waveform that repeatedly increases and decreases, a control signal St with a gradually increasing on-period ratio can be generated. For example, the reference voltage may have a sawtooth waveform, a sine wave, or the like.

[0073] (Variation) The voltage divider circuit can be omitted. For example, the resistor elements R1 and R3 may be omitted, and the paths of the resistor elements R2 and R4 may be cut off. The same result can be obtained if the resistor element R14 of the detection circuit 11 is connected to the second input wiring L2.

[0074] The first buffer circuit 16 and the second buffer circuit 17 can be omitted. However, it is preferable to provide the first buffer circuit 16 and the second buffer circuit 17 so that the impedance of the subsequent stage does not affect the impedance of the input stage.

[0075] [Embodiment 3] Other embodiments of the present invention will be described below. For ease of explanation, the same reference numerals will be used to designate components having the same functions as those described in the above embodiment, and the description thereof will not be repeated.

[0076] (Configuration of power supply circuit 1b) 5 is a circuit diagram showing the configuration of a power supply circuit 1b according to this embodiment. The power supply circuit 1b includes a first input terminal T1, a second input terminal T2, a first positive output terminal T3, a second negative output terminal T4, a rectifier circuit 20, a first positive input wiring L1, a second negative input wiring L2, an inrush current resistance element 3, an inrush current control transistor 4, a smoothing capacitor 5, a coil 6, a reverse current prevention transistor 7a, a PFC transistor 9, an inrush current control circuit 10b, a PFC control circuit 30b, a forced shutdown circuit 40, a first delay circuit 42, an inverting circuit 43, a second delay circuit 44, a first signal generating circuit 45, and a second signal generating circuit 46. In the power supply circuit 1b, the second output terminal T4 is grounded, not the second input wiring L2.

[0077] The power supply circuit 1b includes a rectifier circuit 20 instead of the rectifier circuit 2 of the power supply circuit 1. In order to reduce loss, the rectifier circuit 20 includes four transistors 21 to 24 in the current path instead of four diodes. Here, the four transistors 21 to 24 are n-type field effect transistors. The rectifier circuit 20 includes two photocouplers 25 and 26. The photocouplers 25 and 26 control the transistor 21 and the transistor 23, respectively. The rectifier circuit 20 operates in the same manner as the rectifier circuit 2, and performs full-wave rectification in synchronization with the AC input voltage. Since the rectifier circuit 20 is well known, detailed description of its operation will be omitted.

[0078] The power supply circuit 1b includes a backflow prevention transistor 7a instead of the first diode 7 of the power supply circuit 1. The backflow prevention transistor 7a is connected between the coil 6 and the first output terminal T3.

[0079] The inrush control circuit 10b controls the inrush control transistor 4 in accordance with the output voltage V2. The control method is the same as in the above-described embodiment, except for the position of the ground.

[0080] The PFC control circuit 30b detects the voltage across the inrush control transistor 4 and controls the PFC transistor 9 based on the detected voltage. The control method of the PFC control circuit 30b is the same as that of the above-described embodiment. The PFC control circuit 30b outputs a PFC signal from an OUT terminal that controls the on / off of the PFC transistor 9.

[0081] The first delay circuit 42 delays the PFC signal output from the PFC control circuit 30b by a predetermined period and outputs the delayed PFC signal to the first signal generation circuit 45. The first signal generation circuit 45 turns the PFC transistor 9 on or off based on the PFC signal.

[0082] The inverting circuit 43 inverts the PFC signal output from the PFC control circuit 30b and outputs the inverted PFC signal to a second delay circuit 44. The second delay circuit 44 delays the PFC signal inverted by the inverting circuit 43 by a predetermined period and outputs the delayed PFC signal to a second signal generating circuit 46. The second signal generating circuit 46 turns the backflow prevention transistor 7a on or off based on the inverted PFC signal.

[0083] The forcing shutoff circuit 40 includes a second comparator 41. The forcing shutoff circuit 40 detects the voltage across the inrush control transistor 4. The potential (ground) of the second output terminal T4 is input to the non-inverting input terminal of the second comparator 41. A potential obtained by increasing the potential of the second input wiring L2 by a second threshold is input to the inverting input terminal of the second comparator 41. If the voltage across the inrush control transistor 4 (>0) is greater than the second threshold (>0), the second comparator 41 outputs an H signal to the second signal generating circuit 46. If the voltage across the inrush control transistor 4 is equal to or less than the second threshold, the second comparator 41 outputs an L signal to the second signal generating circuit 46.

[0084] (Backflow prevention operation of power supply circuit 1b) A state in which the inrush control transistor 4 remains continuously on after the AC input voltage is applied will be described. The PFC control circuit 30b controls the PFC transistor 9 and the backflow prevention transistor 7a so that the on / off states of the PFC transistor 9 and the backflow prevention transistor 7a are reversed. In PFC control, basically, when the PFC transistor 9 is on, the backflow prevention transistor 7a is off, and when the PFC transistor 9 is off, the backflow prevention transistor 7a is on.

[0085] However, if the backflow prevention transistor 7a is turned on when the input current IL is 0, there is a possibility that a current will flow backward through the backflow prevention transistor 7a and the rectifier circuit 20 in the power supply circuit 1b.

[0086] Therefore, the forcing shutoff circuit 40 forcibly keeps the backflow prevention transistor 7a in the OFF state when the input current IL is smaller than a predetermined value. Specifically, the second comparator 41 outputs an L signal to the second signal generating circuit 46 when the voltage across the inrush control transistor 4 is equal to or lower than a second threshold. The voltage across the inrush control transistor 4 corresponds to the input current IL flowing through the inrush control transistor 4.

[0087] The second signal generating circuit 46 turns on the backflow prevention transistor 7a when the signal from the forcing shutoff circuit 40 is H and the inverted PFC signal from the second delay circuit 44 is H. The second signal generating circuit 46 turns off the backflow prevention transistor 7a when the signal from the forcing shutoff circuit 40 is L or the inverted PFC signal from the second delay circuit 44 is L. In other words, when the voltage across the inrush control transistor 4 is equal to or lower than the second threshold, which is close to the condition where backflow may occur, the forcing shutoff circuit 40 forcibly maintains the backflow prevention transistor 7a in the off state. This makes it possible to prevent backflow in the power supply circuit 1b.

[0088] 〔summary〕 A power supply circuit according to a first aspect of the present invention comprises a first positive output terminal and a second negative output terminal, a first positive input wiring and a second negative input wiring, a coil having one end connected to the first input wiring, a power factor correction transistor connected between the other end of the coil and the second output terminal, an inrush resistance element connected between the second input wiring and the second output terminal, an inrush resistance transistor connected in parallel to the inrush resistance element, and a power factor correction control circuit that detects the voltage across both ends of the inrush control transistor in an on state and controls the power factor correction transistor based on the detected voltage.

[0089] A power supply circuit according to a second aspect of the present invention may be configured in the above-mentioned first aspect such that the inrush resistance element is a thermistor.

[0090] A power supply circuit according to a third aspect of the present invention may be configured in the first or second aspect above, wherein the inrush control transistor is an n-type field effect transistor.

[0091] A power supply circuit according to a fourth aspect of the present invention may be configured in accordance with any of the first to third aspects above, further comprising a reverse current prevention transistor connected between the other end of the coil and the first output terminal, and a forced shutoff circuit that detects a voltage across the inrush current control transistor in an on state and forcibly maintains the reverse current prevention transistor in an off state while the detected voltage is below a threshold.

[0092] A power supply circuit according to a fifth aspect of the present invention may be configured in any of the first to fourth aspects above, further comprising an inrush control circuit that switches the inrush control transistor to an on state after a period of time has elapsed since the input voltage was applied.

[0093] A power supply circuit according to a sixth aspect of the present invention may be configured such that, in the fifth aspect described above, the inrush control circuit turns the inrush control transistor on, then turns the inrush control transistor off, and then turns the inrush control transistor on.

[0094] A power supply circuit according to a seventh aspect of the present invention may be configured in the fifth or sixth aspect above, such that the inrush control circuit alternates between an on period during which the inrush control transistor is turned on and an off period during which the inrush control transistor is turned off, gradually increasing the proportion of the on period in one on / off cycle.

[0095] A power supply circuit according to an eighth aspect of the present invention may be configured in accordance with the seventh aspect above, wherein the inrush control circuit gradually increases the length of the on-period.

[0096] A ninth aspect of the present invention relates to the power supply circuit of the seventh or eighth aspect, and may be configured such that the inrush control circuit gradually reduces the length of the off period.

[0097] A power supply circuit according to aspect 10 of the present invention may be configured in the above-mentioned aspect 8 or 9 such that the inrush control circuit comprises a reference generation circuit that generates a reference voltage having a voltage waveform that repeatedly increases and decreases, a detection circuit that detects the output voltage between the first output terminal and the second output terminal, and a control signal generation circuit that generates a control signal for controlling the inrush control transistor by comparing the reference voltage with a first voltage corresponding to the output voltage.

[0098] A power supply circuit according to an eleventh aspect of the present invention may be configured in the tenth aspect above, wherein the voltage waveform of the reference voltage is a triangular wave, a sawtooth wave, or a sine wave.

[0099] A power supply circuit according to a twelfth aspect of the present invention may be configured in accordance with the tenth or eleventh aspect above, wherein the control signal generating circuit defines a period during which the first voltage exceeds the reference voltage as the on period.

[0100] A power supply circuit according to aspect 13 of the present invention may be configured such that, in aspects 10 to 12 above, the detection circuit includes a subtraction circuit that outputs, as a detection result of the output voltage, a second voltage corresponding to the difference between the potential of the first output terminal and the potential of the second output terminal when the potential of the second input wiring is used as a reference.

[0101] The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present invention. [Explanation of symbols]

[0102] 1, 1a, 1b power circuit 2, 20 rectifier circuit 3 Inrush resistance element 4 Inrush control transistor 5 smoothing capacitors 6 coils 7a Backflow prevention transistor 9 PFC transistor (power factor correction transistor) 10, 10a, 10b Inrush control circuit 11 Detection circuit 12 Reference generation circuit 13 Control signal generation circuit 16 First buffer circuit 17 Second buffer circuit 30, 30b PFC control circuit (power factor correction control circuit) 40 Forced shutdown circuit 42 First delay circuit 43 Inverter Circuit 44 Second delay circuit 45 1st signal generation circuit 46 Second signal generation circuit 90 load L1 First input wiring L2 Second input wiring T1 First input terminal T2 Second input terminal T3 1st output terminal T4 Second output terminal V1 input voltage V2 Output voltage

Claims

1. a first positive output terminal and a second negative output terminal; a first input wiring on the positive side and a second input wiring on the negative side; a coil having one end connected to the first input wiring; a power factor correction transistor connected between the other end of the coil and the second output terminal; an inrush resistance element connected between the second input wiring and the second output terminal; an inrush control transistor connected in parallel to the inrush resistance element; a power factor correction control circuit that detects a voltage across both ends of the inrush control transistor in an on state and controls the power factor correction transistor based on the detected voltage.

2. 2. The power supply circuit according to claim 1, wherein the inrush resistance element is a thermistor.

3. 2. The power supply circuit of claim 1, wherein the inrush control transistor is an n-type field effect transistor.

4. a backflow prevention transistor connected between the other end of the coil and the first output terminal; 2. The power supply circuit according to claim 1, further comprising: a forced cutoff circuit that detects a voltage across both ends of the inrush current control transistor in an on state, and forcibly maintains the backflow prevention transistor in an off state while the detected voltage is less than a threshold.

5. 2. The power supply circuit according to claim 1, further comprising an inrush control circuit that switches said inrush control transistor to an on state after a period of time has elapsed since an input voltage was applied.

6. 6. The power supply circuit according to claim 5, wherein said inrush control circuit turns said inrush control transistor on, then turns said inrush control transistor off, and then turns said inrush control transistor on.

7. 6. The power supply circuit according to claim 5, wherein the inrush control circuit alternates between an on period during which the inrush control transistor is turned on and an off period during which the inrush control transistor is turned off, and gradually increases a proportion of the on period in one on / off cycle.

8. The power supply circuit of claim 7 , wherein the inrush control circuitry gradually increases the length of the on-period.

9. The power supply circuit of claim 7 , wherein the inrush control circuit gradually decreases the length of the off period.

10. The inrush control circuit includes: a reference generating circuit for generating a reference voltage having a voltage waveform that repeatedly increases and decreases; a detection circuit for detecting an output voltage between the first output terminal and the second output terminal; 9. The power supply circuit according to claim 8, further comprising: a control signal generation circuit that generates a control signal for controlling said inrush control transistor by comparing said reference voltage with a first voltage corresponding to said output voltage.

11. The power supply circuit according to claim 10 , wherein the voltage waveform of the reference voltage is a triangular wave, a sawtooth wave, or a sine wave.

12. The power supply circuit according to claim 10 , wherein the control signal generating circuit determines the ON period to be a period during which the first voltage exceeds the reference voltage.

13. The detection circuit 11. The power supply circuit according to claim 10, further comprising a subtraction circuit that outputs, as a detection result of the output voltage, a second voltage corresponding to a difference between a potential of the first output terminal and a potential of the second output terminal when a potential of the second input wiring is used as a reference.

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