Separation of three-dimensional NAND selection gate

Abstract

To provide a three-dimensional NAND device including a drain side selection gate cut part, and a manufacturing method for the three-dimensional NAND device.SOLUTION: In an electronic device, a memory string including at least one drain side selection gate (SGD) transistor 192 and at least one memory transistor 194 in a vertical hole extending through a memory stack on a substrate is disposed. The memory stack includes a first layer 110 forming a non-substituted word line and a substituted insulator alternately. A filling slit extends through the memory stack, and in the memory stack adjacent to the filling slit, at least two drain side selection gate (SGD) isolation regions 196 exist. In several sets of uppermost parts of the alternate layers in the memory stack, a drain side selection gate (SGD) cut part is patterned. A sacrifice layer of the memory stack is removed through a cut opening part, and the opening part is filled with an insulator layer material 190.SELECTED DRAWING: Figure 16C

Description

[Technical Field]

[0001]

[0001] Embodiments of the present disclosure relate to the field of electronic devices and methods and apparatus for fabricating electronic devices. More particularly, embodiments of the present disclosure provide a three-dimensional NAND select transistor and method for forming. [Background technology]

[0002]

[0002] Semiconductor technology is advancing rapidly, and device dimensions are shrinking as technology advances to enable faster processing and storage per unit space. In NAND devices, the string current must be high enough to provide enough current to distinguish between ON and OFF cells. This string current depends on carrier mobility, which is improved by increasing the grain size of the silicon channel.

[0003] Current 3D NAND devices, which have a memory stack containing alternating layers of oxide and nitride materials, have multiple memory holes between two slits. To access each cell via word lines and bit lines, the memory holes between the slits must be divided by a drain select gate (SGD) cut. For example, Toshiba's 96L-stacked 3D NAND, which has eight memory holes and one dummy hole, separates the holes into two groups using a single SGD cut. To reduce the array size of 3D NAND, the number of holes (nHole) between the slits must be increased. Increasing nHole beyond eight requires two or more SGD cuts using the same technology. Holes at the same bit line level must be separately accessible using a combination of bit line (BL) and word line (WL). In other words, holes under the same bit line are independently selected by the drain select gate (SGD) and bit line. Therefore, the SGD between the slits must be separated by an SGD cut. When the number of holes between slits (nHole) is small (e.g., ≥ 8), one SGD cut separates the drain-side select gates (SGDs). However, when the number of holes between slits (nHole) is large (e.g., ≥ 12), an additional SGD cut is required every four holes.

[0004]

[0004] Therefore, there is a need in the art for a 3D NAND device with a drain-side select gate (SGD) cut and a method for fabricating a 3D NAND device. Summary of the Invention

[0005]

[0005] One or more embodiments of the present disclosure are directed to a semiconductor memory device. In one or more embodiments, the semiconductor memory device includes a memory string including at least one drain-side select gate (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate, the memory stack including alternating non-replaced word lines and replacement insulators, a filled slit extending through the memory stack, and at least two drain-side select gate (SGD) isolation regions of the memory stack adjacent to the filled slit.

[0006]

[0006] Additional embodiments of the present disclosure are directed to methods of forming semiconductor devices. In one or more embodiments, a method of forming a semiconductor device having three-dimensional vertical memory strings including drain-side select gate (SGD) transistors and memory transistors includes forming first openings in a memory stack including alternating first and second layers over a substrate, recessing the second layer through the first openings to form first recessed regions, forming drain-side select gate (SGD) isolation in the first openings and the first recessed regions, forming memory string structures through the memory stack, forming slits extending from a top surface of the memory stack to the substrate, removing the second layer to form second openings, and filling the second openings and slits with an insulating material.

[0007]

[0007] A further embodiment of the present disclosure is directed to a non-transitory computer-readable medium. In one or more embodiments, the non-transitory computer-readable medium includes instructions, when executed by a controller of a processing chamber, that cause the processing chamber to perform the following steps: form a first opening in a memory stack including alternating first and second layers on a substrate; recess the second layer through the first opening to form a first recessed region; form drain-side select gate (SGD) isolation in the first opening and the first recessed region; form a memory string structure through the memory stack; form a slit extending from a top surface of the memory stack to the substrate; remove the second layer to form a second opening; and fill the second opening and the slit with an insulating material.

[0008]

[0008] In order that the features of the present disclosure as described above may be understood in detail, the present disclosure summarized above will now be more particularly described with reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings merely illustrate exemplary embodiments of the present disclosure and therefore should not be considered as limiting the scope of the present disclosure, which may also admit of other equally effective embodiments. The embodiments described herein are presented by way of example and not by way of limitation to the figures of the accompanying drawings, in which like references indicate similar elements. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a process flow diagram of a method for forming a memory device according to embodiments described herein. [Figure 2] 1 is a cross-sectional view of an electronic device including a memory stack according to one or more embodiments. [Figure 3] 1A and 1B are cross-sectional views of an electronic device after forming a staircase pattern of a memory stack according to one or more embodiments. [Figure 4] 1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 5]1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 6] 1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 7] 1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 8] 1A is a cross-sectional view of an electronic device according to one or more embodiments, and FIG. 1B is an enlarged view of region 170 according to one or more embodiments. [Figure 9] 1A is a cross-sectional view of an electronic device according to one or more embodiments, and FIG. 1B is an enlarged view of region 170 according to one or more embodiments. [Figure 10] 1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 11] 1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 12] 1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 13A] 1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 13B] FIG. 10 is an enlarged view of region 183 according to one or more embodiments. [Figure 14A] 1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 14B] FIG. 10 is an enlarged view of region 183 according to one or more embodiments. [Figure 15] 1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 16A] 1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 16B] FIG. 10 is an enlarged view of region 183 according to one or more embodiments. [Figure 16C] FIG. 1 is an enlarged view of region 191 according to one or more embodiments. [Figure 17] 1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 18]FIG. 1 illustrates a cluster tool according to one or more embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0010]

[0033] Before describing several example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0011]

[0034] As used herein and in the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to refer to any gas species capable of reacting with the substrate surface.

[0012]

[0035] In the following description, numerous specific details are set forth, such as particular materials, chemicals, dimensions of elements, etc., to provide a thorough understanding of one or more embodiments of the present disclosure. However, it will be apparent to one skilled in the art that one or more embodiments of the present disclosure may be practiced without these specific details. In other instances, semiconductor manufacturing processes, techniques, materials, equipment, etc. have not been described in great detail to avoid unnecessarily obscuring this description. Those skilled in the art will be able, with the included description, to implement the appropriate functionality without undue experimentation.

[0013]

[0036] While certain exemplary embodiments of the present disclosure have been described and illustrated in the accompanying drawings, it is to be understood that the above embodiments are merely illustrative and do not limit the present disclosure, and that the disclosure is not limited to the specific constructions and arrangements shown and described, as such may be modified by those skilled in the art.

[0014]

[0037] Existing 3D NAND devices based on memory stacks of alternating layers of oxide and nitride materials cannot use current integration schemes, such as forming drain-side select gate (SGD) cuts before word line replacement, when multiple SGD cuts are present. In the current integration scheme, SGDs formed before replacement block word line replacement between SGD cuts. To reduce the array size of 3D NAND, the number of memory strings (e.g., holes) between slits (nHole) must be increased. Furthermore, holes under the same bit line level must be separately accessible by a combination of bit line (BL) and word line (WL). That is, holes under the same bit line are independently selected by the drain-side select gate (SGD) and bit line (WL). Therefore, SGDs between slits must be separated by SGD cuts. When the number of holes between slits (nHole) is small (e.g., ≥ 8), a single SGD cut separates the drain-side select gates (SGDs). However, when the number of holes between slits (nHole) is large (e.g., ≧12), an additional SGD cut is required for every four holes. Therefore, one or more embodiments provide a method for fabricating a 3D NAND structure and drain-side select gate cut using a non-replacement gate integration scheme.

[0015]

[0038] One or more embodiments provide a memory string including at least one drain-side select gate (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate. In one or more embodiments, the memory stack includes alternating non-replacement word lines and replacement insulators. A fill slit extends through the memory stack, and at least two drain-side select gate (SGD) isolation regions are present in the memory stack adjacent to the fill slit. Drain-side select gate (SGD) cuts are patterned in the top sets of alternating layers of the memory stack. A sacrificial layer of the memory stack is removed through the cut openings, and an insulator layer is used to fill the openings.

[0016]

[0039] The device and fabrication method of one or more embodiments advantageously enables drain-side select gate isolation regardless of the number of holes (memory strings) between the slits, resulting in increased bit density per area and therefore reduced manufacturing costs for 3D NAND devices.

[0017]

[0040] In one or more embodiments, metal deposition and other processes may be performed in an isolated environment (e.g., a cluster processing tool). Accordingly, some embodiments of the present disclosure provide an integrated tool system with associated process modules for performing the methods.

[0018]

[0041] FIG. 1 is a flow diagram illustrating an exemplary method 10 for forming a memory device. Those skilled in the art will recognize that method 10 can include any or all of the illustrated processes. Furthermore, the order of individual steps may vary in some respects. Method 10 can begin with any of the listed processes without departing from this disclosure. Referring to FIG. 1 , in step 15, a memory stack is formed. In step 20, word line steps are formed in the memory stack. In step 25, select gates are etched / cut to create the memory stack steps. In step 30, a second layer, such as a metal, metal nitride, conductive metal compound, or semiconductor material, can be recessed through the select gate cuts. In step 35, the select gate cuts are filled with a dielectric material. In step 40, memory is patterned. In step 45, a transistor layer is deposited in the memory holes. In step 50, bit line pads are formed. In step 55, the memory steps are patterned into slits. In step 60, slit spacers are deposited. In step 65, the common source line sacrificial layer is removed. In step 70, the common source line contact area is etched. In step 75, polysilicon is deposited in the common source line contact area. In step 80, the mold is removed. In step 85, the slits are filled with a dielectric material, and in step 90, back-end of line (BEOL) contacts are formed.

[0019]

[0042] 2-17 illustrate a portion of a memory device 100 according to the process flow illustrated in method 10 of FIG.

[0020]

[0043] Figure 2 illustrates an initial or starting memory stack for an electronic device 100 according to one or more embodiments of the present disclosure. In some embodiments, the electronic device 100 shown in Figure 2 is layered on a bare substrate 102, as shown. The electronic device of Figure 2 comprises the substrate 102, a common source line 103, and a memory stack 130.

[0021]

[0044] The substrate 102 can be any suitable material known to those skilled in the art. As used herein and in the appended claims, the term "substrate" refers to a surface, or a portion of a surface, upon which a process acts. Those skilled in the art will also understand that a reference to a substrate may refer to only a portion of the substrate, unless the context clearly indicates otherwise. Furthermore, a reference to deposition on a substrate can refer to both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0022]

[0045] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which a film treatment is performed in a manufacturing process. For example, substrate surfaces on which treatment may be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes that polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In the present disclosure, in addition to film treatments directly on the surface of the substrate itself, any of the disclosed film treatment steps may also be performed on underlying layers formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlying layers as the context indicates. Thus, for example, when a film / layer or partial film / layer is deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0023]

[0046] In one or more embodiments, the common source line 103 is on the substrate 102. The common source line 103 may also be referred to as a semiconductor layer. The common source line 103 may be formed by any suitable technique known to those skilled in the art and may be made of any suitable material, including, but not limited to, polysilicon (poly-Si). In some embodiments, the common source line 103 includes several different conductive or semiconductor materials. For example, in one or more embodiments, as shown in FIG. 2 , the common source line 103 includes a polysilicon layer 104 on the substrate 102, a sacrificial layer 106 on the polysilicon layer, a second polysilicon layer 104 on the sacrificial layer 106, and an oxide layer 108 on the second polysilicon layer 104.

[0024]

[0047] In one or more embodiments, the sacrificial layer 106 may be formed on the polysilicon layer 104 and may be made of any suitable material. In some embodiments, the sacrificial layer 106 is removed and replaced in a later process. In some embodiments, the sacrificial layer 106 is not removed but remains in the memory device 100. In this case, the term "sacrificial" has an expanded meaning to include a permanent layer, which may also be referred to as a conductive layer. In the illustrated embodiment, the sacrificial layer 106 is removed in step 65, as described further below. In one or more embodiments, the sacrificial layer 106 comprises a material that can be selectively removed relative to the adjacent polysilicon layer 104. In one or more embodiments, the sacrificial layer comprises a nitride material, such as silicon nitride (SiN), or an oxide material, such as silicon oxide (SiOx).

[0025]

[0048] In one or more embodiments, the memory stack 130 is formed in the oxide layer 108 above the common source line 103. The memory stack 130 in the illustrated embodiment includes a plurality of alternating first layers 110 and second layers 112. In some embodiments, the memory stack 130 may be referred to as an "XM" stack, where "X" is a sacrificial non-insulating layer and "M" is a metal. In embodiments described herein, "M" refers to the first layer 110 and "X" refers to the second layer 112. In one or more embodiments, the second layer 112 includes a material that is etch-selective to the first layer 110 such that the second layer 112 can be removed without substantially affecting the first layer 110.

[0026]

[0049] In one or more embodiments, the "M" layer or first layer 110 comprises a metal or a semiconductor. In one or more embodiments, the metal of first layer 110 is selected from one or more of tungsten (W), molybdenum (Mo), tantalum (Ta), ruthenium (Ru), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), rhenium (Re), titanium (Ti), silicon (Si), silicon germanium (SiGe), and germanium (Ge).

[0027]

[0050] In one or more embodiments, the "X" layer or second layer 112 comprises one or more of a metal, a metal nitride, a conductive metal compound, a dielectric material, and a semiconductor material. In one or more embodiments, the metal of the second layer 112 is selected from one or more of tungsten (W), molybdenum (Mo), tantalum (Ta), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), rhenium (Re), or titanium (Ti). In one or more embodiments, the metal nitride of the second layer 112 is selected from one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), and zirconium nitride (ZrN). In one or more embodiments, the conductive metal compound of the second layer 112 is selected from one or more of tungsten oxide (WOx), ruthenium oxide (RuOx), and iridium oxide (IrOx). In one or more embodiments, the dielectric material of the second layer 112 is selected from one or more of silicon nitride (SiN), silicon oxide (SiO2), and tungsten oxide (WO3). In one or more embodiments, the semiconductor material of the second layer 112 is selected from one or more of silicon (Si), silicon germanium (SiGe), and germanium (Ge).

[0028]

[0051] In one or more embodiments, the dielectric material may include any suitable dielectric material known to those skilled in the art. As used herein, the term "dielectric material" refers to an electrical insulator that can be polarized in an electric field. In some embodiments, the dielectric material includes one or more of an oxide, a carbon-doped oxide, porous silicon dioxide (SiO), silicon dioxide (SiO), silicon nitride (SiN), silicon dioxide / silicon nitride, a carbide, an oxycarbide, a nitride, an oxynitride, an oxycarbonitride, a polymer, a phosphosilicate glass, a fluorosilicate (SiOF) glass, or an organosilicate glass (SiOCH).

[0029]

[0052] In one or more embodiments, the first layer 110 and the second layer 112 are deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD). The individual alternating layers may be formed to any suitable thickness. In some embodiments, the thickness of each second layer 112 is approximately equal. In one or more embodiments, each second layer 112 has the thickness of the first second layer. In some embodiments, the thickness of each first layer 110 is approximately equal. As used in this context, approximately equal thicknesses are within + / - 5% of each other. In one or more embodiments, the first layer 110 has a thickness in the range of about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm. In one or more embodiments, the second layer 112 has a thickness in the range of about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm.

[0030]

[0053] 3, in step 20 of method 10, staircase structure 131 is fabricated. Mask layer 120 is deposited on top of memory stack 130. Mask layer 120 may comprise any suitable material known to those skilled in the art. In one or more embodiments, mask layer 120 comprises nitride.

[0031]

[0054] In one or more embodiments, the staircase structure 131 exposes a top surface 134 of the "X" layer or second layer 112. The top surface 134 may be used to provide a space in which word line contacts are formed, as described below. A suitable fill material 136 may be deposited to occupy the space outside the staircase structure 131. The suitable fill material 136 may be any material that prevents electrical shorting between adjacent word lines, as will be understood by those skilled in the art. In the staircase structure 131, each word line has a smaller width (viewed from left to right in the figure) than the word line below it. The use of relative terms such as "top" and "bottom" should not be construed as limiting the scope of the present disclosure to physical orientation in space.

[0032]

[0055] Referring to FIG. 4 , in step 25, the select gate is etched / cut into the memory stack to form a first opening 150. In some embodiments, this may be referred to as patterning a drain-side select gate cut (SGD). The first opening 150 extends from the top surface of the mask layer 120 to the top surface of one of the “M” layers or first layers 110. The etching / patterning may be performed by any suitable means known to those skilled in the art. In one or more embodiments, forming the first opening comprises a drain-side select gate (SGD) isolation etch.

[0033]

[0056] 5, in step 30, the "X" layer or second layer 112 is recessed to form recessed openings 152 through the first openings 150. In one or more embodiments, the first openings have a pitch ranging from about 20 nm to about 60 nm, and the second layer is recessed by about 100 nm to about 300 nm, which is about twice the pitch of the memory holes.

[0034]

[0057] 6, in step 35, drain-side select gate (SGD) isolation is formed in first opening 150 and recessed region 152. In one or more embodiments, forming the drain-side select gate (SGD) isolation includes depositing an oxide material 154 in first opening 150 and recessed region 152. Oxide material 154 can be deposited by any suitable method known to those skilled in the art. In one or more embodiments, oxide material 154 is deposited by atomic layer deposition (ALD). In one or more embodiments, oxide material 154 is silicon oxide (SiO x ) or silicon oxynitride (SiON).

[0035]

[0058] 7-9B illustrate the formation of a memory string through the memory stack 130. Referring to FIG. 7, in step 40, a memory hole channel 160 is opened / patterned through the memory stack 130. In some embodiments, opening the memory hole channel 160 includes etching through the mask layer 120, the memory stack 130, the common source line 103, and down to the substrate 102. The memory hole channel 160 has sidewalls that extend through the memory stack 130, exposing the surface 111 of the second layer 112 and the surface 109 of the first layer 110.

[0036]

[0059] The sacrificial layer 106 has an exposed surface 123 as a sidewall of a memory hole channel 160. The memory hole channel 160 extends a distance into the substrate 102 such that the sidewall surfaces 123 and a bottom 114 of the memory hole channel 160 are formed in the substrate 102. The bottom 114 of the memory hole channel 160 can be formed anywhere within the thickness of the substrate 102. In some embodiments, the memory hole channel 160 extends into the substrate 102 a thickness in the range of about 10% to about 90%, or about 20% to about 80%, or about 30% to about 70%, or about 40% to about 60% of the thickness of the substrate 102. In some embodiments, the memory hole channel 160 extends into the substrate 102 a distance of 10%, 20%, 30%, 40%, 50%, 60%, 70%, or 80% or more of the thickness of the substrate 102.

[0037]

[0060] 8A illustrates step 45 in which a transistor layer 172 is formed in the memory hole channel 160. The transistor layer 172 can be formed by any suitable technique known to those skilled in the art. In some embodiments, the transistor layer is formed by a conformal deposition process. In some embodiments, the transistor layer is formed by one or more of atomic layer deposition or chemical vapor deposition.

[0038]

[0061] In one or more embodiments, the deposition of the transistor layer 172 is substantially conformal. As used herein, a "substantially conformal" layer refers to a layer that is about the same thickness throughout (e.g., at the top, middle, and bottom of the sidewalls and at the bottom of the memory hole channel 160). A substantially conformal layer varies in thickness by no more than about 5%, no more than 2%, no more than 1%, or no more than 0.5%.

[0039]

[0062] 8B, which is an expanded view of region 170 of FIG. 8A, in one or more embodiments, transistor layer 172 includes aluminum oxide layer 172a, blocking oxide layer 172b, nitride trapping layer 172c, tunnel oxide layer 172d, and channel material 172e of memory hole channel 160. In one or more embodiments, channel material 172e includes polysilicon. In one or more embodiments, aluminum oxide layer 172a is deposited on the sidewalls of memory hole channel 160.

[0040]

[0063] The transistor layer 172 can have any suitable thickness depending, for example, on the dimensions of the memory hole channel 160. In some embodiments, the transistor layer 172 has a thickness in the range of about 0.5 nm to about 50 nm, or in the range of about 0.75 nm to about 35 nm, or in the range of about 1 nm to about 20 nm.

[0041]

[0064] In one or more embodiments, the transistor layer 172 includes one or more of a drain-side select gate (SGD) transistor or a memory transistor, and the transistor layer 172 includes one or more transistor layers independently selected from aluminum oxide (AlO), a blocking oxide, a trapping material, a tunnel oxide, and a channel material.

[0042]

[0065] 9A-9B illustrate step 50 of method 10 in which bit line pads 142 are formed in mask layer 120. Bit line pads 142 may be any suitable material known to those skilled in the art, including, but not limited to, polysilicon.

[0043]

[0066] 9A and 9B, an interlevel dielectric layer 140 is deposited on top of the mask layer 120 and the bit line pads 142. The interlevel dielectric (ILD) layer 140 may be deposited by any suitable technique known to those skilled in the art. The interlevel dielectric layer 140 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the interlevel dielectric layer 140 is a low-k dielectric, including, but not limited to, materials such as silicon dioxide, silicon oxide, carbon-doped oxide ("CDO"), e.g., carbon-doped silicon dioxide, porous silicon dioxide (SiO), silicon nitride (SiN), or any combination thereof. While the term "silicon oxide" may be used to describe the interlevel dielectric layer 140, those skilled in the art will recognize that the present disclosure is not limited to a particular stoichiometry. For example, the terms "silicon oxide" and "silicon dioxide" may both be used to describe a material having silicon atoms and oxygen atoms in any suitable stoichiometric ratio. The same is true for other materials described in this disclosure, such as silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, and the like.

[0044]

[0067] Referring to FIG. 10, in step 55 of method 10, the memory stack 130 is patterned in a slit shape to form a slit pattern opening 180 extending from the top surface of the interlayer dielectric layer 140 to the sacrificial layer 106 of the common source line 103.

[0045]

[0068] 11 illustrates step 60 in which spacer material 182 is deposited in slit pattern openings 180 and then etched back so that spacer material 182 forms on the sidewalls of slit pattern openings 180 but not on the bottom surface 181 of slit pattern openings 180. Spacer material 182 may include any suitable material known to those skilled in the art. In one or more embodiments, spacer material 182 includes polysilicon.

[0046]

[0069] 12, a diagram illustrating step 65 of method 10 is shown in which sacrificial layer 106 of common source line 103 is removed to form opening 184. Sacrificial layer 106 can be removed by any suitable technique known to those skilled in the art, including, but not limited to, selective etching, hot phosphoric acid, etc.

[0047]

[0070] 13A and 13B, which are enlarged views of region 183 in FIG. 13A, illustrate step 70 of method 10, exposing channel material 172e to form common source line contact region 179. Channel material 172e is exposed by removing aluminum oxide (AlO) layer 172a, blocking oxide layer 172b, trapping layer 172c, and tunnel oxide layer 172d in common source line contact region 179. In one or more embodiments, forming the memory string structure includes patterning memory holes extending from the top surface of the memory stack to the bottom surface of the substrate and depositing transistor layers in the memory holes, the transistor layers including one or more of the aluminum oxide (AlO) layer, blocking oxide layer, trapping layer, tunnel oxide layer, and channel layer. Bit line pads are formed on the top surfaces of the memory holes.

[0048]

[0071] 14A and 14B, which is an enlarged view of region 183 of FIG. 14A, illustrate step 75 of method 10 in which spacer material 182 is removed from slit pattern openings 180 and openings 184 created by the removal of sacrificial layer 106 are filled with polysilicon layer 186. Spacer material 182 may be removed by any suitable means known to those skilled in the art. In one or more embodiments, spacer material 182 is removed by an isotropic etching process (e.g., a wet etch using tetramethylammonium hydroxide (TMAH), etc.). Polysilicon layer 186 may be doped or undoped.

[0049]

[0072] 15 illustrates step 80 of method 10, in which the "X" layer or second layer 112 is removed. The second layer 112 may be removed by any suitable means known to those skilled in the art. In one or more embodiments, the second layer 112 is removed by a selective etch, such as a selective wet etch or a selective dry etch. Removal of the second layer 112 forms an opening 188.

[0050]

[0073] 16A and 16B, which is an enlarged view of region 183 of FIG. 16A, in step 85 of method 10, opening 188 is filled with an insulator material 190. Insulator material 190 may include any suitable material known to those skilled in the art. In one or more embodiments, insulator material 190 is silicon oxide (SiO x ), silicon nitride (SiN), and silicon oxynitride (SiO x N y ) is selected from one or more of:

[0051]

[0074] Figure 16C is an expanded view showing region 191 of Figure 16A. Referring to Figure 16C, in one or more embodiments, at least one drain side select gate (SGD) transistor 192 and at least one memory transistor 194 are present in a vertical hole extending through a memory stack on a substrate. In one or more embodiments, at least two select drain side select gate (SGD) isolation regions 196 are present in the memory stack adjacent to the filled slit 190.

[0052]

[0075] 17 illustrates step 90 of method 10, in which word line (W / L) contacts are formed. Word line contacts 225 extend through memory stack 130 a sufficient distance to terminate at one of the word lines. In one or more embodiments, word line contacts 225 may comprise any suitable material known to those skilled in the art. In one or more embodiments, word line contacts 225 comprise one or more of a metal, a metal silicide, polysilicon, amorphous silicon, or epitaxial silicon. In one or more embodiments, word line contacts 225 are doped with either an N-type dopant or a P-type dopant to reduce contact resistance. In one or more embodiments, the metal of the word line contact 225 is selected from one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt).

[0053]

[0076] In one or more embodiments, a semiconductor memory device includes a memory string including at least one drain-side select gate (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate, the memory stack including alternating non-replaced word lines and replacement insulators, a filled slit extending through the memory stack, and at least two drain-side select gate (SGD) isolation regions of the memory stack adjacent to the filled slit.

[0054]

[0077] In another embodiment, a method for forming a semiconductor device is provided. The semiconductor device has a three-dimensional vertical memory string including drain-side select gate (SGD) transistors and memory transistors. In one or more embodiments, the method for forming the semiconductor device includes forming a first opening in a memory stack including alternating first and second layers over a substrate, recessing the second layer through the first opening to form a first recessed region, forming drain-side select gate (SGD) isolation in the first opening and the first recessed region, forming a memory string structure through the memory stack, forming a slit extending from a top surface of the memory stack to the substrate, removing the second layer to form a second opening, and filling the second opening and the slit with an insulating material.

[0055]

[0078] An additional embodiment of the present disclosure is directed to a processing tool 900 for forming the described memory devices and methods, as shown in FIG.

[0056]

[0079] The cluster tool 900 includes at least one central transfer station 921, 931 having multiple sides. Robots 925, 935 are positioned within the central transfer stations 921, 931 and configured to move the robot blade and wafer to each of the multiple sides.

[0057]

[0080] The cluster tool 900 includes multiple processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918, also referred to as process stations, connected to a central transfer station. The various processing chambers provide distinct processing regions isolated from adjacent process stations. The processing chambers may be any suitable chamber, including, but not limited to, a pre-clean chamber, a buffer chamber, a transfer space(s), a wafer orienter / degassing chamber, a cryo-cooling chamber, a deposition chamber, an annealing chamber, an etching chamber, a selective oxidation chamber, an oxide layer thinning chamber, or a word line deposition chamber. The specific arrangement of process chambers and components may vary depending on the cluster tool and should not be construed as limiting the scope of the present disclosure.

[0058]

[0081] In some embodiments, the cluster tool 900 includes a drain side select gate (SGD) patterning chamber. The drain side select gate (SGD) patterning chamber in some embodiments includes one or more selective etch chambers.

[0059]

[0082] 18, a factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a loading chamber 954 and an unloading chamber 956 at the front 951 of the factory interface 950. Although the loading chamber 954 is shown on the left and the unloading chamber 956 is shown on the right, one skilled in the art will understand that this represents just one possible configuration.

[0060]

[0083] The size and shape of the loading chamber 954 and unloading chamber 956 can vary depending on, for example, the substrates being processed in the cluster tool 900. In the illustrated embodiment, the loading chamber 954 and unloading chamber 956 are sized to hold a wafer cassette having multiple wafers positioned within the cassette.

[0061]

[0084] The robot 952 resides within the factory interface 950 and can move between a loading chamber 954 and an unloading chamber 956. The robot 952 can transfer wafers from a cassette in the loading chamber 954 through the factory interface 950 to a load lock chamber 960. The robot 952 can also transfer wafers from the load lock chamber 962 through the factory interface 950 to a cassette in the unloading chamber 956. As will be appreciated by those skilled in the art, the factory interface 950 can include multiple robots 952. For example, the factory interface 950 can include a first robot that transfers wafers between the loading chamber 954 and the load lock chamber 960 and a second robot that transfers wafers between the load lock chamber 962 and the unloading chamber 956.

[0062]

[0085] The illustrated cluster tool 900 includes a first section 920 and a second section 930. The first section 920 is connected to a factory interface 950 through load lock chambers 960 and 962. The first section 920 includes a first transfer chamber 921 having at least one robot 925 positioned therein. The robot 925 is also referred to as a robotic wafer transfer mechanism. The first transfer chamber 921 is centrally located relative to the load lock chambers 960 and 962, the process chambers 902, 904, 916, and 918, and the buffer chambers 922 and 924. In some embodiments, the robot 925 is a multi-arm robot capable of independently moving multiple wafers at a time. In some embodiments, the first transfer chamber 921 includes multiple robotic wafer transfer mechanisms. The robot 925 in the first transfer chamber 921 is configured to move wafers between chambers surrounding the first transfer chamber 921. Individual wafers are carried on a wafer transfer blade located at the distal end of the first robotic mechanism.

[0063]

[0086] After processing the wafer in the first section 920, the wafer may proceed through a pass-through chamber to the second section 930. For example, chambers 922, 924 may be unidirectional or bidirectional pass-through chambers. The pass-through chambers 922, 924 may be used, for example, to cryo-cool the wafer before processing in the second section 930 or to allow for cooling or post-processing of the wafer before returning to the first section 920.

[0064]

[0087] A system controller 990 is in communication with the first robot 925, the second robot 935, the first plurality of processing chambers 902, 904, 916, 918, and the second plurality of processing chambers 906, 908, 910, 912, 914. The system controller 990 may be any suitable component capable of controlling the processing chambers and robots. For example, the system controller 990 may be a computer including a central processing unit, memory, appropriate circuitry, and storage.

[0065]

[0088] The processes may generally be stored in the memory of the system controller 990 as software routines that, when executed by a processor, cause the process chamber to perform the processes of the present disclosure. The software routines may also be stored and / or executed by a second processor (not shown) located remotely from the hardware being controlled by the processor. Some or all of the methods of the present disclosure may be performed in hardware. Thus, the processes may be implemented in software and executed in hardware using a computer system, for example, as an application-specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. The software routines, when executed by a processor, transform a general-purpose computer into a special-purpose computer (controller) that controls chamber operation to perform the processes.

[0066]

[0089] In one or more embodiments, the processing tool includes a central transfer station including a robot configured to move wafers; a plurality of process stations, each process station connected to the central transfer station to provide a processing region separate from the processing regions of adjacent process stations, the plurality of process stations including drain side select gate (SGD) patterning chambers; and a controller connected to the central transfer station and the plurality of process stations, the controller configured to operate the robot to move wafers between the process stations and to control the process performed at each process station.

[0067]

[0090] One or more embodiments provide a non-transitory computer-readable medium comprising instructions, when executed by a controller of a processing chamber, that cause the processing chamber to perform the following steps: form a first opening in a memory stack including alternating first and second layers on a substrate; recess the second layer through the first opening to form a first recessed region; form drain-side select gate (SGD) isolation in the first opening and in the first recessed region; form a memory string structure through the memory stack; form a slit extending from a top surface of the memory stack to the substrate; remove the second layer to form a second opening; and fill the second opening and the slit with an insulating material.

[0068]

[0091] The use of the terms "a," "an," and "the" and similar referents in the context of describing the materials and methods described herein (particularly in the context of the claims below) should be construed to cover both the singular and the plural unless otherwise stated herein or clearly contradicted by context. The recitation of ranges of values ​​herein is merely intended to serve as a shorthand method of referring individually to each individual value falling within the range, unless otherwise stated herein, and each individual value is incorporated herein as if the value were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise stated herein or clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., "etc.") provided herein is intended merely to better clarify the materials and methods and does not impose a limitation on the scope unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0069]

[0092] References throughout this specification to "one embodiment," "a particular embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of phrases such as "in one or more embodiments," "a particular embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment of the present disclosure. Furthermore, particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0070]

[0093] Although the disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made in the disclosed method and apparatus without departing from the spirit and scope of the disclosure. Therefore, it is intended that the disclosure cover modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. 1. A semiconductor memory device, comprising: a memory string including at least one drain-side select gate (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate, the memory stack including alternating non-replacement word lines and replacement insulators; a fill slit extending through the memory stack; at least two drain-side select gate (SGD) isolation regions of the memory stack adjacent to the filled slit; A semiconductor memory device comprising:

2. 10. The semiconductor memory device of claim 1, wherein the non-replaced word lines comprise one or more of tungsten (W), molybdenum (Mo), tantalum (Ta), ruthenium (Ru), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), rhenium (Re), titanium (Ti), silicon (Si), silicon germanium (SiGe), and germanium (Ge).

3. The semiconductor memory device of claim 1 , wherein the non-replaced word lines comprise one or more of a metal, a metal nitride, a conductive metal compound, and a semiconductor material.

4. 4. The semiconductor memory device of claim 3, wherein the metal is selected from one or more of tungsten (W), molybdenum (Mo), tantalum (Ta), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), rhenium (Re), or titanium (Ti).

5. 4. The semiconductor memory device of claim 3, wherein the metal nitride is selected from one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), and zirconium nitride (ZrN).

6. 4. The semiconductor memory device of claim 3, wherein the conductive metal compound is selected from one or more of tungsten oxide (WOx), ruthenium oxide (RuOx), and iridium oxide (IrOx).

7. The semiconductor memory device of claim 3 , wherein the semiconductor material is selected from one or more of silicon (Si), silicon germanium (SiGe), and germanium (Ge).

8. 10. The semiconductor memory device of claim 1, wherein the drain-side select gate (SGD) transistor and the memory transistor independently comprise one or more transistor layers selected from aluminum oxide (AlO), a blocking oxide, a trapping material, a tunnel oxide, and a channel material.

9. The semiconductor memory device of claim 1 , wherein the filled slits comprise an insulator material selected from one or more of silicon oxide, silicon nitride, and silicon oxynitride.

10. 2. The semiconductor memory device of claim 1, wherein the substrate is a common source line, the common source line including a sacrificial layer, an oxide layer, and a polysilicon layer.

11. 1. A method for forming a semiconductor device having a three-dimensional vertical memory string including a drain-side select gate (SGD) transistor and a memory transistor, comprising: forming a first opening in a memory stack including alternating first and second layers over a substrate; recessing the second layer through the first opening to form a first recessed region; forming a drain-side select gate (SGD) isolation in the first opening and the first recessed region; forming a memory string structure through the memory stack; forming a slit extending from a top surface of the memory stack to the substrate; removing the second layer to form a second opening; filling the second opening and the slit with an insulating material; A method comprising:

12. 12. The method of claim 11, wherein forming the first opening comprises a drain-side select gate (SGD) isolation etch.

13. 12. The method of claim 11, wherein forming the drain-side select gate (SGD) isolation comprises depositing an oxide material in the first opening and the first recessed region.

14. forming the memory string structure patterning a memory hole extending from a top surface of the memory stack to a bottom surface of the substrate; depositing a transistor layer in the memory hole, the transistor layer including one or more of an aluminum oxide (AlO) layer, a blocking oxide layer, a trapping layer, a tunnel oxide layer, and a channel layer; forming a bit line pad on an upper surface of the memory hole; The method of claim 11 , comprising:

15. 15. The method of claim 14, wherein the first openings have a pitch in a range of about 20 nm to about 60 nm, and the second layer is recessed by about 100 nm to about 300 nm, which is about twice the pitch of the memory holes.

16. The method of claim 14 further comprising depositing a spacer material in the slit.

17. 17. The method of claim 16, wherein the substrate is a common source line, the common source line including a sacrificial layer, an oxide layer, and a polysilicon layer, the method further comprising removing the sacrificial layer from the common source line to form a common source opening.

18. The method of claim 17 , further comprising exposing a channel layer through the common source opening.

19. The method of claim 11 further comprising forming a word line contact.

20. 1. A non-transitory computer-readable medium that, when executed by a controller of a processing chamber, causes the processing chamber to: forming a first opening in a memory stack comprising alternating first and second layers over a substrate; recessing the second layer through the first opening to form a first recessed region; forming a drain-side select gate (SGD) isolation in the first opening and the first recessed region; forming a memory string structure through the memory stack; forming a slit extending from a top surface of the memory stack to a substrate; removing the second layer to form a second opening; filling the second opening and the slit with an insulating material; A non-transitory computer-readable medium containing instructions for causing a

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