Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device capable of reducing chip height and a manufacturing method thereof.SOLUTION: A primary electrode 3 is formed on a substrate 1. An insulating layer 5 is formed on the substrate 1 and the primary electrode 3. The insulating layer 5 has an opening 6. A secondary electrode 7 is formed on the insulating layer 5 and faces the primary electrode 3 via the insulating layer 5, and is magnetically or capacitively coupled. Wiring 8 is bonded to the primary electrode 3 exposed from the insulating layer 5 in the opening 6. At least one step 9 is formed on the sidewall of the opening 6.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] In a semiconductor device, a primary electrode and a secondary electrode are magnetically or capacitively coupled to face each other via an insulating layer as a coil or a transformer. An opening is formed in the insulating layer, and wiring such as a wire is bonded to the primary electrode exposed from the insulating layer in the opening (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2022 / 065007 Summary of the Invention [Problem to be solved by the invention]

[0004] Conventionally, openings are formed by a single etching process, and the sidewalls of the openings are nearly vertical, with no steps formed. This means that wiring must be bonded at an angle close to perpendicular to the semiconductor substrate to avoid contact with the sidewalls of the openings. This creates the problem of increased chip height.

[0005] The present disclosure has been made to solve the above-mentioned problems, and its object is to provide a semiconductor device and a manufacturing method thereof that can reduce the chip height. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure comprises a substrate, a primary electrode formed on the substrate, an insulating layer formed on the substrate and the primary electrode and having an opening, a secondary electrode formed on the insulating layer and magnetically or capacitively coupled to the primary electrode opposite the insulating layer, and wiring bonded to the primary electrode exposed from the insulating layer at the opening, and is characterized in that at least one step is formed on the side wall of the opening.

[0007] The method for manufacturing a semiconductor device according to the present disclosure includes the steps of forming a primary electrode on a substrate, forming an insulating layer on the substrate and the primary electrode, forming a secondary electrode on the insulating layer so as to face the primary electrode via the insulating layer and be magnetically or capacitively coupled to it, forming an opening in the insulating layer by etching to expose a portion of the primary electrode, and bonding wiring to the primary electrode exposed from the insulating layer in the opening, and is characterized in that at least one step is formed on the sidewall of the opening by performing the etching multiple times. [Effects of the Invention]

[0008] In the present disclosure, at least one step is formed on the sidewall of the opening. This effectively makes the angle of the sidewall of the opening gentler. This increases the distance between the wiring and the upper edge of the opening, eliminating restrictions on the wiring pull-out angle. This eliminates the need to bond the wiring perpendicular to the primary electrode in the opening, allowing for a larger wiring curvature. As a result, the chip height can be reduced. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a plan view showing a primary electrode. [Figure 3] FIG. 10 is a plan view showing a modified example of the primary electrode. [Figure 4]2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 5] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 6] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 7] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 8] 10A to 10C are cross-sectional views showing an example of a step for forming an opening having a step. [Figure 9] 10A to 10C are cross-sectional views showing an example of a step for forming an opening having a step. [Figure 10] 10A to 10C are cross-sectional views showing another example of the step of forming an opening having a step. [Figure 11] 10A to 10C are cross-sectional views showing another example of the step of forming an opening having a step. [Figure 12] FIG. 10 is a cross-sectional view showing a modified example of an opening having a step. [Figure 13] FIG. 10 is a cross-sectional view showing a modified example of an opening having a step. [Figure 14] FIG. 10 is a cross-sectional view showing a modified example of the semiconductor device according to the first embodiment. [Figure 15] FIG. 10 is a cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 16] 10A to 10C are cross-sectional views showing a manufacturing process of a semiconductor device according to a second embodiment. [Figure 17] FIG. 10 is a cross-sectional view showing a semiconductor device according to a third embodiment. [Figure 18] 10A to 10C are cross-sectional views showing a manufacturing process of a semiconductor device according to a third embodiment. [Figure 19] FIG. 10 is a cross-sectional view showing a semiconductor device according to a fourth embodiment. [Figure 20] 10A to 10C are cross-sectional views showing a manufacturing process of a semiconductor device according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] A semiconductor device and a manufacturing method thereof according to an embodiment will be described with reference to the drawings. The same or corresponding components are designated by the same reference numerals, and repeated description may be omitted.

[0011] Embodiment 1 FIG. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. This semiconductor device is a high-voltage semiconductor device. Substrate 1 is a semiconductor substrate made of Si, SiC, GaN, or the like, or an insulating substrate made of glass, ceramics, or the like. An insulating layer 2 is formed on substrate 1. Insulating layer 2 is an oxide film or nitride film formed by a general semiconductor process.

[0012] A primary electrode 3 connected to a first potential is formed on the insulating layer 2. If the substrate 1 is an insulating substrate, the insulating layer 2 is not necessarily required. However, in actual processes, the insulating layer 2 is often formed to improve adhesion with the primary electrode 3 or to address concerns about chemical reactions such as gas emission during pattern formation of the primary electrode 3. If the substrate 1 is made of a semiconductor material, the primary electrode 3 may be connected to a diffusion layer or wiring of the substrate 1 by a contact 4 that penetrates the insulating layer 2.

[0013] An insulating layer 5 is formed on the substrate 1 and the primary electrode 3. The insulating layer 5 has an opening 6. A portion of the primary electrode 3 is exposed from the insulating layer 5 at the bottom of the opening 6. A secondary electrode 7 is formed on the insulating layer 5 and faces the primary electrode 3 via the insulating layer 5, being magnetically or capacitively coupled. The insulating layer 5 maintains a desired dielectric strength between the primary electrode 3 and the secondary electrode 7. The thickness of the insulating layer 5 is adjusted according to the voltage applied between the primary electrode 3 and the secondary electrode 7. The insulating layer 5 is made of a material such as an oxide film, a nitride film, or polyimide.

[0014] Wiring 8 such as aluminum wire is bonded to primary electrode 3 exposed from insulating layer 5 in opening 6. At least one step 9 is formed on the side wall of opening 6.

[0015] 2 is a plan view showing the primary electrode. The primary electrode 3 has a spiral shape, as does the secondary electrode 7. In this case, the primary electrode 3 and the secondary electrode 7 are magnetically coupled to transmit signals.

[0016] 3 is a plan view showing a modified example of the primary electrode. The primary electrode 3 has a flat plate shape, as does the secondary electrode 7. In this case, the primary electrode 3 and the secondary electrode 7 are capacitively coupled to transmit signals.

[0017] As described above, the opposing portions of the primary electrode 3 and the secondary electrode 7 have the same shape. This improves the coupling coefficient between the primary electrode 3 and the secondary electrode 7. However, it is also possible to make the diameter of the secondary electrode 7 smaller than that of the primary electrode 3 to increase the creeping distance to the primary electrode 3 exposed at the opening 6. This improves the creeping discharge withstand voltage.

[0018] Next, a method for manufacturing the semiconductor device according to the first embodiment will be described. Figures 4 to 7 are cross-sectional views showing the manufacturing process of the semiconductor device according to the first embodiment. First, as shown in Figure 4, an insulating layer 2 is formed on a substrate 1, and a primary electrode 3 is formed on the insulating layer 2. Next, an insulating layer 5 is formed on the insulating layer 2 and the primary electrode 3.

[0019] Next, as shown in FIG. 5, a secondary electrode 7 is formed on the insulating layer 5. Next, as shown in FIG. 6, an opening 6 is formed in the insulating layer 5 by etching to expose a portion of the primary electrode 3. At this time, etching is performed in multiple steps to form at least one step 9 on the side wall of the opening 6. As an alternative manufacturing method, after the step of FIG. 4, the opening 6 may be formed by etching as shown in FIG. 7, and then the secondary electrode 7 may be formed. Finally, a wire 8 is bonded to the primary electrode 3 exposed from the insulating layer 5 in the opening 6.

[0020] 8 and 9 are cross-sectional views illustrating an example of a process for forming an opening having a step. First, as shown in FIG. 8, a photosensitive positive resist 10A is applied to the insulating layer 5, and the portions to be etched are exposed. Next, the exposed portions 10a are removed by development, and the insulating layer 5 is partially etched using the resist 10A, leaving the unexposed portions 10b, as a mask to form the recess 6a. Next, as shown in FIG. 9, a photosensitive positive resist 10B is applied to the insulating layer 5, and the portions to be etched are exposed. In this process, the exposed portions 10a of the resist 10B are made smaller than the exposed portions 10a of the resist 10A. Next, the exposed portions 10a are removed by development, and the insulating layer 5 is etched using the resist 10B, leaving the unexposed portions 10b, as a mask until a portion of the primary electrode 3 is exposed. This process forms an opening 6 having a step 9. The steeper the sidewall angle of the step 9, the longer the creepage distance. Therefore, anisotropic etching such as dry etching is desirable.

[0021] 10 and 11 are cross-sectional views illustrating another example of a process for forming an opening having a step. First, as shown in FIG. 10, a photosensitive negative resist 10C is applied to the insulating layer 5, and the portions that will not be etched later are exposed to light. Next, the unexposed portions 10b are removed by development, and the insulating layer 5 is partially etched using the resist 10C, leaving the exposed portions 10a, as a mask to form a recess 6a. Next, as shown in FIG. 11, a photosensitive negative resist 10D is applied to the insulating layer 5, and the portions that will not be etched later are exposed to light. In this process, the exposed portions 10a of the resist 10D are made larger than the exposed portions 10a of the resist 10C. Next, the unexposed portions 10b are removed by development, and the insulating layer 5 is etched using the resist 10D, leaving the exposed portions 10a, as a mask, until a portion of the primary electrode 3 is exposed. This allows the opening 6 having a step 9 to be formed.

[0022] When using a photosensitive resist for etching, the difficulty of development increases if there are recesses 6a in the exposed areas. Therefore, it is necessary to adjust the size of the exposed areas 10a of the second resist relative to the recesses 6a, as described above.

[0023] 12 and 13 are cross-sectional views showing modified examples of an opening having a step. When the height of the lower sidewall of the step 9 is made greater than the height of the upper sidewall of the step 9 as in Fig. 12, the distance between the wiring 8 and the upper end of the opening 6 is reduced, so care must be taken to prevent discharge. When the height of the lower sidewall of the step 9 is made smaller than the height of the upper sidewall of the step 9 as in Fig. 13, the distance between the upper surface of the insulating layer 5 and the primary electrode 3 is reduced, so care must be taken to prevent short circuits.

[0024] As described above, in this embodiment, the wiring 8 is bonded to the primary electrode 3 exposed from the insulating layer 5 in the opening 6. There is a possibility of discharge occurring between the wiring 8 and the secondary electrode 7 through the surface of the insulating layer 5. Therefore, the wiring 8 needs to be formed sufficiently away from the upper end of the opening 6. Therefore, at least one step 9 is formed on the side wall of the opening 6. This effectively reduces the angle of the side wall of the opening 6. Therefore, the distance between the wiring 8 and the upper end of the opening 6 is increased, and the extraction angle of the wiring 8 is not limited. This eliminates the need to bond the wiring 8 perpendicularly to the primary electrode 3 in the opening 6, allowing the wiring 8 to have a large curvature. As a result, the chip height can be reduced.

[0025] Furthermore, even in the case of a conventional opening with vertical side walls, the curvature of the wiring 8 can be made larger by widening the opening width. However, this increases the exposed area of ​​the primary electrode 3, shortening the creeping distance between the primary electrode 3 and the secondary electrode 7, resulting in a decrease in the creeping discharge voltage. In contrast, in this embodiment, the width of the bottom of the opening 6 can be made smaller, preventing a decrease in the creeping discharge voltage.

[0026] In the present invention, the sidewall of the opening 6 is vertical except for the step 9. However, tapering the sidewall increases the processing time. In particular, to make the taper angle gentler, the ratio of the etching rate in the horizontal direction to the etching rate in the vertical direction must be increased, which increases the processing time.

[0027] The wiring 8 is a wire that has a curvature within the opening 6 without coming into contact with the sidewall of the opening 6. However, since signals are transmitted between the magnetically or capacitively coupled primary electrode 3 and secondary electrode 7, it is preferable that the wiring 8 has low resistance so that a current or charge can easily flow. Therefore, a bus bar can also be used as the wiring 8.

[0028] 14 is a cross-sectional view showing a modified example of the semiconductor device according to the first embodiment. A surface protective layer 11 is formed on the secondary electrode 7. Covering the secondary electrode 7 with the surface protective layer 11 prevents the secondary electrode 7 from coming into contact with unspecified fluids, thereby suppressing corrosion of the secondary electrode 7. Furthermore, when the semiconductor device is molded with resin, for example, the surface protective layer 11 can suppress damage to the secondary electrode 7 caused by fillers contained in the resin. The surface protective layer 11 can also be applied to the second or third embodiment described below.

[0029] Embodiment 2 15 is a cross-sectional view showing a semiconductor device according to embodiment 2. In this embodiment, opening 6 has an arc-shaped cross section at the topmost stage above step 9.

[0030] Generally, the secondary electrode 7 is formed by photolithography using a liquid such as resist and etching. After the opening 6 is formed, the arc at the top of the opening 6 acts as a slope when, for example, spin-coating resist. This makes it easier for the liquid to climb over the top edge of the opening 6, facilitating the application of the liquid such as resist. Note that the same effect can be obtained when further liquid is applied to the cross-sectional shape of FIG. 15. Other configurations and effects are the same as those of the first embodiment.

[0031] Next, a method for manufacturing a semiconductor device according to the second embodiment will be described. FIG. 16 is a cross-sectional view showing a manufacturing process of a semiconductor device according to the second embodiment. As in the first embodiment, the opening 6 may be formed after the secondary electrode 7 is formed, or the secondary electrode 7 may be formed after the opening 6 is formed. If the opening 6 is formed first by etching, the structure shown in FIG. 16 will be obtained. The step 9 is formed by dividing the etching for forming the opening 6 into multiple steps. In order to make the top step of the opening 6 arc-shaped, isotropic etching such as wet etching is used in the first or final etching for forming the opening 6.

[0032] Embodiment 3 FIG. 17 is a cross-sectional view showing a semiconductor device according to a third embodiment. In this embodiment, opening 6 has an arc-shaped cross-section at the lowest level below step 9. Rounding the bottom corners of opening 6 can prevent liquid such as resist spin-coated after opening 6 is formed from accumulating at the bottom corners of opening 6. Note that a similar effect can be obtained when further liquid is applied to the cross-sectional shape of FIG. 17. Other configurations and effects are the same as those of the first embodiment.

[0033] Next, a method for manufacturing a semiconductor device according to the third embodiment will be described. FIG. 18 is a cross-sectional view showing a manufacturing process of a semiconductor device according to the third embodiment. As in the first embodiment, the opening 6 may be formed after the secondary electrode 7 is formed, or the secondary electrode 7 may be formed after the opening 6 is formed. If the opening 6 is formed first by etching, the structure shown in FIG. 18 will be obtained. The step 9 is formed by dividing the etching for forming the opening 6 into multiple steps. In order to make the bottom step of the opening 6 arc-shaped, isotropic etching such as wet etching is used in the first or final etching for forming the opening 6.

[0034] Embodiment 4 19 is a cross-sectional view showing a semiconductor device according to a fourth embodiment. In this embodiment, the opening 6 has an arc-shaped cross section at the top of the opening 6 above the step 9, and also has an arc-shaped cross section at the bottom of the opening 6 below the step 9. This makes it possible to obtain the effects of both the second and third embodiments. The same effect can also be obtained when a liquid is further applied to the cross-sectional shape of FIG. 19. The other configurations and effects are the same as those of the first embodiment.

[0035] Next, a method for manufacturing a semiconductor device according to the fourth embodiment will be described. FIG. 20 is a cross-sectional view showing a manufacturing process of a semiconductor device according to the fourth embodiment. As in the first embodiment, the opening 6 may be formed after the secondary electrode 7 is formed, or the secondary electrode 7 may be formed after the opening 6 is formed. If the opening 6 is formed first by etching, the structure shown in FIG. 20 will be obtained. The step 9 is formed by dividing the etching for forming the opening 6 into multiple steps. In the etching step for forming the opening 6, where it is desired to form an arc-shaped cross section, isotropic etching such as wet etching is used.

[0036] The substrate 1 is not limited to those made of silicon, but may also be made of a wide-bandgap semiconductor having a wider bandgap than silicon. Examples of wide-bandgap semiconductors include silicon carbide, gallium nitride-based materials, and diamond. Semiconductor devices made of such wide-bandgap semiconductors have high voltage resistance and allowable current density, allowing for miniaturization. By using such miniaturized semiconductor devices, semiconductor modules incorporating such semiconductor devices can also be miniaturized and highly integrated. Furthermore, the high heat resistance of the semiconductor device allows for miniaturization of the heat dissipation fins of the heat sink, enabling water-cooled parts to be replaced by air-cooled parts, further miniaturizing the semiconductor module. Furthermore, the low power loss and high efficiency of the semiconductor device allow for high efficiency of the semiconductor module.

[0037] Although the preferred embodiments have been described above in detail, the present disclosure is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. Various aspects of the present disclosure are summarized below as appendices.

[0038] (Appendix 1) A substrate; a primary electrode formed on the substrate; an insulating layer formed on the substrate and the primary electrode and having an opening; a secondary electrode formed on the insulating layer and magnetically or capacitively coupled to the primary electrode while facing the insulating layer; a wiring bonded to the primary electrode exposed from the insulating layer at the opening, The semiconductor device is characterized in that at least one step is formed on the sidewall of the opening. (Appendix 2) 2. The semiconductor device according to claim 1, wherein the width of the opening increases stepwise from the lower surface of the insulating layer toward the upper surface of the insulating layer. (Appendix 3) 3. The semiconductor device according to claim 1, wherein the wiring is a wire or bus bar that has a curvature within the opening without contacting a sidewall of the opening. (Appendix 4) 4. The semiconductor device according to claim 1, wherein the cross section of the uppermost part of the opening is arc-shaped. (Appendix 5) 5. The semiconductor device according to any one of claims 1 to 4, wherein the cross section of the lowermost part of the opening has an arc shape. (Appendix 6) 6. The semiconductor device according to any one of claims 1 to 5, further comprising a surface protection layer formed on the secondary electrode. (Appendix 7) 7. The semiconductor device according to any one of claims 1 to 6, wherein the substrate is made of a wide band gap semiconductor. (Appendix 8) forming a primary electrode on a substrate; forming an insulating layer on the substrate and the primary electrode; forming a secondary electrode on the insulating layer, the secondary electrode being magnetically or capacitively coupled to the primary electrode and facing the insulating layer; forming an opening in the insulating layer by etching to expose a portion of the primary electrode; and bonding a wire to the primary electrode exposed from the insulating layer at the opening. A method for manufacturing a semiconductor device, wherein the etching is performed in multiple steps to form at least one step on the sidewall of the opening. (Appendix 9) 9. The method for manufacturing a semiconductor device according to claim 8, wherein the cross-sectional shape of the uppermost part of the opening is made arc-shaped by isotropic etching. (Appendix 10) 10. The method for manufacturing a semiconductor device according to claim 8 or 9, wherein the cross-sectional shape of the lowermost part of the opening is made to be arc-shaped by isotropic etching. [Explanation of symbols]

[0039] 1 substrate, 3 primary electrode, 5 insulating layer, 6 opening, 7 secondary electrode, 8 wiring, 9 step, 11 surface protection layer

Claims

1. A substrate; a primary electrode formed on the substrate; an insulating layer formed on the substrate and the primary electrode and having an opening; a secondary electrode formed on the insulating layer and magnetically or capacitively coupled to the primary electrode while facing the insulating layer; a wiring bonded to the primary electrode exposed from the insulating layer at the opening, The semiconductor device is characterized in that at least one step is formed on the side wall of the opening.

2. 2. The semiconductor device according to claim 1, wherein the width of the opening increases stepwise from the lower surface of the insulating layer toward the upper surface of the insulating layer.

3. 3. The semiconductor device according to claim 1, wherein the wiring is a wire or a bus bar having a curvature within the opening without contacting a sidewall of the opening.

4. 3. The semiconductor device according to claim 1, wherein the cross section of the uppermost part of the opening is arc-shaped.

5. 3. The semiconductor device according to claim 1, wherein the cross section of the lowermost part of the opening is arc-shaped.

6. 3. The semiconductor device according to claim 1, further comprising a surface protection layer formed on the secondary electrode.

7. 3. The semiconductor device according to claim 1, wherein the substrate is made of a wide bandgap semiconductor.

8. forming a primary electrode on a substrate; forming an insulating layer on the substrate and the primary electrode; forming a secondary electrode on the insulating layer, the secondary electrode being magnetically or capacitively coupled to the primary electrode and facing the insulating layer; forming an opening in the insulating layer by etching to expose a portion of the primary electrode; and bonding a wire to the primary electrode exposed from the insulating layer at the opening. A method for manufacturing a semiconductor device, wherein the etching is performed in a plurality of steps to form at least one step on the sidewall of the opening.

9. 9. The method for manufacturing a semiconductor device according to claim 8, wherein the cross section of the uppermost part of the opening is formed into an arc shape by isotropic etching.

10. 10. The method for manufacturing a semiconductor device according to claim 8, wherein the cross section of the lowermost part of the opening is formed into an arc shape by isotropic etching.

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