Multilayer ceramic capacitor

Abstract

To provide a multilayer ceramic capacitor that can suppress the occurrence of interfacial peeling while suppressing the decrease in capacitance, even in a multilayer ceramic capacitor with high voltage resistance specifications.SOLUTION: In a multilayer ceramic capacitor 1, multiple internal electrode layers include a first internal electrode layer 31, a second internal electrode layer 32, and an intermediate electrode layer 33, and the coverage of the intermediate electrode layer 33 is higher than the coverage of the first internal electrode layer 31 and the coverage of the second internal electrode layer 32.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor. [Background technology]

[0002] Conventionally, multilayer ceramic capacitors that can withstand high voltages have been known to have a structure in which a plurality of capacitor sections are connected in series, that is, a multilayer ceramic capacitor with a series structure (see Patent Document 1).

[0003] Series-structure multilayer ceramic capacitors form a series-connected capacitance, which improves voltage resistance but tends to reduce capacitance. Therefore, measures such as increasing the number of stacked internal electrode layers and dielectric layers are taken to maintain capacitance. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-209495 Summary of the Invention [Problem to be solved by the invention]

[0005] However, increasing the number of stacked internal electrode layers and dielectric layers increases the internal stress caused by the difference in shrinkage between the dielectric layers and the internal electrode layers, which may result in peeling at the interface between the internal electrode layers and the dielectric layers.

[0006] An object of the present invention is to provide a multilayer ceramic capacitor that can suppress the occurrence of interfacial peeling while suppressing a decrease in capacitance, even in a multilayer ceramic capacitor with high voltage resistance specifications. [Means for solving the problem]

[0007] The multilayer ceramic capacitor of the present invention comprises a laminate including a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, the laminate including a first main surface and a second main surface opposing each other in a lamination direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the lamination direction and the width direction, a first external electrode disposed on the first end surface, and a second external electrode disposed on the second end surface, the plurality of internal electrode layers including a first internal electrode layer, a second internal electrode layer, and an intermediate electrode layer, the first internal electrode layer having a first lead portion, one end of which is led out to the first end surface and connected to the first external electrode, the second internal electrode layer has a second extension portion, one end of which is extended to the second end face and connected to the second external electrode, and a second extension portion, which is connected to the second extension portion and faces the internal electrode layer arranged adjacent to the second internal electrode layer in the stacking direction; the intermediate electrode layer is not connected to either the first external electrode or the second external electrode, and is an internal electrode layer that forms a series-connected capacitor element together with the first internal electrode layer and the second internal electrode layer, and the coverage of the intermediate electrode layer is higher than the coverage of the first internal electrode layer and the coverage of the second internal electrode layer. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can suppress the occurrence of interfacial peeling while suppressing a decrease in capacitance, even in a multilayer ceramic capacitor with high voltage resistance specifications. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is an external perspective view of a double-structure multilayer ceramic capacitor according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1, illustrating the schematic configuration of a double-structure laminate according to the first embodiment. [Figure 3]FIG. 3 is a cross-sectional view taken along the line III-III in FIG. 2. [Figure 4A] FIG. 3 is a cross-sectional view taken along line IVA-IVA in FIG. 2, along a first internal electrode layer and a second internal electrode layer. [Figure 4B] 4 is a cross-sectional view taken along line IVB-IVB of FIG. 2, taken along the intermediate electrode layer. [Figure 5] 3 is a schematic cross-sectional view illustrating a configuration in which the coverage of intermediate electrode layers is increased in the internal electrode layers of the multilayer ceramic capacitor according to the first embodiment. FIG. [Figure 6] 10 is a schematic cross-sectional view illustrating a configuration in which the coverage of intermediate electrode layers is increased in the internal electrode layers of the multilayer ceramic capacitor according to the second embodiment. FIG. [Figure 7] 10 is a schematic cross-sectional view illustrating a configuration in which the coverage of intermediate electrode layers is increased in internal electrode layers of a multilayer ceramic capacitor according to a third embodiment. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the multilayer ceramic capacitor of the present invention will be described, but the present invention is not limited to these.

[0011] First Embodiment A multilayer ceramic capacitor 1 as a double-structure multilayer ceramic electronic component according to a first embodiment of the present disclosure will be described with reference to the drawings. The multilayer ceramic capacitor 1 according to this embodiment has a small rate of change in capacitance due to temperature change and is a temperature-compensating capacitor used for matching filters and high-frequency circuits. However, the multilayer ceramic capacitor 1 according to the present disclosure is not limited to this. FIG. 1 is an external perspective view of the double-structure multilayer ceramic capacitor 1 according to the first embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 and is a diagram illustrating a schematic configuration of a double-structure laminate according to the first embodiment. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. FIG. 4A is a cross-sectional view taken along line IVA-IVA in FIG. 2 and is a cross-sectional view taken along the first internal electrode layer and the second internal electrode layer. FIG. 4B is a cross-sectional view taken along line IVB-IVB in FIG. 2 and is a cross-sectional view taken along the intermediate electrode layer.

[0012] The drawings may be simplified and schematic for the purpose of explaining the invention, and the dimensional ratios of the depicted components or between the components may not match those described in the specification. Furthermore, components described in the specification may be omitted from the drawings, or the number of components may be omitted. For example, the number of internal electrode layers shown in Figures 2 and 3 is seven for the sake of convenience, but this does not represent the actual number of internal electrode layers 30. The same applies to Figures 5 to 7. Terms used in the present invention that specify shapes and geometric conditions, as well as their degrees of similarity, such as "parallel," "orthogonal," and "identical," as well as values ​​of length and angle, are not limited to their strict meanings but are interpreted to encompass a range within which similar functions can be expected.

[0013] 1, the multilayer ceramic capacitor 1 according to the embodiment has a substantially rectangular parallelepiped shape. The multilayer ceramic capacitor 1 includes a laminate 10 having a substantially rectangular parallelepiped shape and a pair of external electrodes 40 disposed at both ends of the laminate 10 while being spaced apart from each other.

[0014] In FIG. 1, arrow T indicates the stacking direction of the multilayer ceramic capacitor 1 and the laminate 10. This stacking direction T also corresponds to the thickness direction and height direction of the multilayer ceramic capacitor 1 and the laminate 10. In FIG. 1, arrow L indicates the length direction of the multilayer ceramic capacitor 1 and the laminate 10, which is perpendicular to the stacking direction T. In FIG. 1, arrow W indicates the width direction of the multilayer ceramic capacitor 1 and the laminate 10, which is perpendicular to the stacking direction T and the length direction L. A pair of external electrodes 40 are respectively disposed at one end and the other end of the length direction L of the laminate 10.

[0015] 1 to 4B show an XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The stacking direction T of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, the cross section shown in FIG. 2 is also referred to as an LT cross section. The cross section shown in FIG. 3 is also referred to as a WT cross section. The cross sections shown in FIGS. 4A and 4B are also referred to as LW cross sections.

[0016] As shown in Figures 1 to 4B, the laminate 10 includes a first main surface TS1 and a second main surface TS2 facing in the stacking direction T, a first end surface LS1 and a second end surface LS2 facing in a length direction L perpendicular to the stacking direction T, and a first side surface WS1 and a second side surface WS2 facing in a width direction W perpendicular to the stacking direction T and the length direction L.

[0017] As shown in FIG. 1, the laminate 10 has a substantially rectangular parallelepiped shape. The dimension of the laminate 10 in the length direction L is not necessarily longer than the dimension in the width direction W. The corners and ridges of the laminate 10 are preferably rounded. A corner is a portion where three surfaces of the laminate intersect, and a ridge is a portion where two surfaces of the laminate intersect. Incidentally, unevenness may be formed on part or all of the surfaces constituting the laminate 10.

[0018] The dimensions of the laminate 10 are not particularly limited, but if the dimension of the laminate 10 in the length direction L is defined as the L dimension, then the L dimension is preferably 0.2 mm or more and 10 mm or less. If the dimension of the laminate 10 in the stacking direction T is defined as the T dimension, then the T dimension is preferably 0.1 mm or more and 10 mm or less. If the dimension of the laminate 10 in the width direction W is defined as the W dimension, then the W dimension is preferably 0.1 mm or more and 10 mm or less.

[0019] As shown in Figures 2 and 3, the laminate 10 has an inner layer portion 11, and a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13 arranged to sandwich the inner layer portion 11 in the stacking direction T.

[0020] The inner layer portion 11 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 alternately stacked in the stacking direction T. The inner layer portion 11 includes the internal electrode layer 30 located closest to the first principal surface TS1 to the internal electrode layer 30 located closest to the second principal surface TS2 in the stacking direction T. In the inner layer portion 11, the plurality of internal electrode layers 30 are arranged opposite each other with the dielectric layer 20 interposed therebetween. The inner layer portion 11 is a portion that generates electrostatic capacitance and essentially functions as a capacitor.

[0021] The multiple dielectric layers 20 are made of a dielectric material. As described above, the multilayer ceramic capacitor 1 according to this embodiment is a temperature-compensated capacitor, and the dielectric material is a CaZrO3-based (hereinafter sometimes abbreviated as CZ-based) or Ca(Sr,Zr)O3-based (hereinafter sometimes abbreviated as CSZ-based) dielectric material. CZ-based and CSZ-based dielectric materials contain perovskite compounds containing at least Ca and Zr. CZ-based dielectric materials are materials based on CaZrO3, as well as CaZrO3 solid solutions in which part of Ca, part of Zr, or part of Ca and Zr is replaced with an appropriate element. The dielectric material contains at least one of Ca (calcium), Zr (zirconium), and Ti (titanium). As an example, the dielectric layer 20 contains a perovskite-type compound containing Ca and Zr and optionally Sr and Ti. Specifically, the dielectric layer 20 contains CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), BaZrO3 (proton-conducting metal oxide), titanium oxide (TiO2), etc. Normally, multilayer ceramic capacitor 1 generates oxygen vacancies when fired in a reducing atmosphere. However, CaZrO3, in particular, has a wide band gap that can suppress the generation of oxygen vacancies. As a result, high reliability can be achieved. Furthermore, the dielectric material may contain these main components plus secondary components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds.

[0022] The dielectric layer 20 of this embodiment uses a material containing at least one of Ca (calcium), Zr (zirconium), and Ti (titanium), and therefore has a relative dielectric constant of approximately 20 to 300 and a smaller capacitance than high-dielectric-constant materials. Furthermore, the dielectric layer 20 of this embodiment has the characteristic that the relative dielectric constant changes almost linearly with temperature, providing excellent heat resistance and high-frequency characteristics. Furthermore, the dielectric layer 20 of this embodiment exhibits negligible change in capacitance value over time, resulting in small capacitor loss and excellent stability even at high temperatures, high power, and high frequencies. Additionally, the dielectric layer 20 exhibits small changes in its dielectric constant over time and with application of voltage. The dielectric material is not limited to this, and may be a high-dielectric-constant ceramic such as a BaTiO3 (BT)-based material.

[0023] The thickness of the dielectric layer 20 is preferably 0.2 μm or more and 10 μm or less. In particular, the thickness of the dielectric layer 20 is preferably 3 μm or more and 10 μm or less. The number of laminated dielectric layers 20 is preferably 15 to 1200. Note that this number of dielectric layers 20 is the total number of the dielectric layers 20 in the inner layer portion 11 and the number of the dielectric layers 20 in each of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0024] The multiple internal electrode layers 30 include multiple first internal electrode layers 31, multiple second internal electrode layers 32, and intermediate electrode layers 33. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged adjacent to each other while being spaced apart in the length direction L, and the first internal electrode layers 31 and the second internal electrode layers 32 and the intermediate electrode layers 33 are arranged alternately in the stacking direction T with the dielectric layer 20 sandwiched therebetween.

[0025] The first internal electrode layer 31 is extended to the first end face LS1 and connected to a first external electrode 40A (described later). The second internal electrode layer 32 is extended to the second end face LS2 and connected to a second external electrode 40B (described later). The intermediate electrode layer 33 is not extended to either the first end face LS1 or the second end face LS2, and is not connected to either the first external electrode 40A or the second external electrode 40B (described later). The first internal electrode layer 31, the intermediate electrode layer 33, and the second internal electrode layer 32 included in the multiple internal electrode layers 30 form a series-connected capacitor element. Note that, hereinafter, when it is not necessary to distinguish between the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33, the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 may be collectively referred to as the internal electrode layer 30.

[0026] As shown in FIGS. 2 and 4A , the first internal electrode layer 31 has a first opposing portion EA and a first lead portion D1. The first opposing portion EA is a region facing the intermediate electrode layer 33 arranged adjacent to the first internal electrode layer 31 in the stacking direction T with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10. The first internal electrode layer 31 has a first opposing portion EA connected to the first lead portion D1 and facing the internal electrode layer 30 arranged adjacent to the first internal electrode layer 31 in the stacking direction T. The first lead portion D1 is a portion extending from the first opposing portion EA to the first end face LS1 and exposed at the first end face LS1. The first internal electrode layer 31 has a first lead portion D1, one end of which is extended to the first end face LS1 and connected to the first external electrode 40A.

[0027] As shown in FIGS. 2 and 4A, the second internal electrode layer 32 has a second opposing portion EB and a second lead portion D2. The second opposing portion EB is a region facing the intermediate electrode layer 33 arranged adjacent to the second internal electrode layer 32 in the stacking direction T with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10. The second internal electrode layer 32 has a second opposing portion EB connected to the second lead portion D2 and facing the internal electrode layer 30 arranged adjacent to the second internal electrode layer 32 in the stacking direction T. The second lead portion D2 is a portion drawn from the second opposing portion EB to the second end face LS2 and is exposed at the second end face LS2. The second internal electrode layer 32 has a second lead portion D2, one end of which is drawn to the second end face LS2 and connected to the second external electrode 40B.

[0028] 2 and 4B, the intermediate electrode layer 33 has a first electrode layer side facing portion ECA, a second electrode layer side facing portion ECB, and a connecting portion E0. The first electrode layer side facing portion ECA is a region facing the first internal electrode layer 31 arranged adjacent to the first internal electrode layer 31 in the stacking direction T with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10. The second electrode layer side facing portion ECB is a region facing the second internal electrode layer 32 arranged adjacent to the first internal electrode layer 31 in the stacking direction T with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10. The connecting portion E0 is a portion that connects the first electrode layer side facing portion ECA and the second electrode layer side facing portion ECB, and is located between the first electrode layer side facing portion ECA and the second electrode layer side facing portion ECB.

[0029] In the multilayer ceramic capacitor 1 according to this embodiment, the end of the intermediate electrode layer 33 on the first end face LS1 side is disposed away from the first end face LS1. In the multilayer ceramic capacitor 1 according to this embodiment, the end of the intermediate electrode layer 33 on the first end face LS1 side is disposed closer to the first end face LS1 than the end 40AE of the first external electrode 40A. However, this is not limiting, and the end of the intermediate electrode layer 33 on the first end face LS1 side may be disposed closer to the second end face LS2 than the end 40AE of the first external electrode 40A.

[0030] An end portion of the intermediate electrode layer 33 on the second end face LS2 side is disposed spaced apart from the second end face LS2. In the multilayer ceramic capacitor 1 according to this embodiment, the end portion of the intermediate electrode layer 33 on the second end face LS2 side is disposed closer to the second end face LS2 than the end portion 40BE of the second external electrode 40B. However, this is not limiting, and the end portion of the intermediate electrode layer 33 on the second end face LS2 side may be disposed closer to the first end face LS1 than the end portion 40BE of the second external electrode 40B.

[0031] 2, in the multilayer ceramic capacitor 1 according to the first embodiment, the first internal electrode layer 31 and the second internal electrode layer 32 are arranged adjacent to each other in the length direction L. In the multilayer ceramic capacitor 1 according to the first embodiment, the first internal electrode layer 31 and the second internal electrode layer 32 are stacked alternately with the intermediate electrode layer 33 interposed between them, with the dielectric layer 20 interposed therebetween.

[0032] In this embodiment, the first opposing portion EA and the first electrode layer side opposing portion ECA face each other via the dielectric layer 20, thereby forming a capacitance CAP1 (first capacitor portion CAP1). The second opposing portion EB and the second electrode layer side opposing portion ECB of the intermediate electrode layer 33 including the first electrode layer side opposing portion ECA face each other via the dielectric layer 20, thereby forming a capacitance CAP2 (second capacitor portion CAP2). The coupling portion E0 connects the capacitances CAP1 and CAP2 in series. The multilayer ceramic capacitor 1 of this embodiment is a multilayer ceramic capacitor 1 of a so-called double series structure in which two capacitor portions connected in series are formed.

[0033] The shapes of the first opposing portion EA, the second opposing portion EB, the first electrode layer side opposing portion ECA, and the second electrode layer side opposing portion ECB are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle. The shapes of the first lead portion D1 and the second lead portion D2 are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle. The shape of the connecting portion E0 is not particularly limited, but is preferably rectangular.

[0034] The width direction W dimension of the first opposing portion EA and the width direction W dimension of the first lead portion D1 may be the same dimension, or one of the dimensions may be smaller. The width direction W dimension of the second opposing portion EB and the width direction W dimension of the second lead portion D2 may be the same dimension, or one of the dimensions may be smaller. The width direction W dimension of the first electrode layer side opposing portion ECA and the second electrode layer side opposing portion ECB and the width direction W dimension of the connecting portion E0 may be the same dimension, or one of the dimensions may be smaller.

[0035] The first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 are made of an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 may be made of, for example, an Ag-Pd alloy.

[0036] The thickness of each of the first internal electrode layers 31, the second internal electrode layers 32, and the intermediate electrode layers 33 is preferably, for example, 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layers 31, the second internal electrode layers 32, and the intermediate electrode layers 33 is preferably 15 or more and 1000 or less.

[0037] As shown in FIGS. 2 and 3 , the first main surface side outer layer portion 12 is located on the first main surface TS1 side of the laminate 10. The first main surface side outer layer portion 12 is an assembly of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. On the other hand, the second main surface side outer layer portion 13 is located on the second main surface TS2 side of the laminate 10. The second main surface side outer layer portion 13 is an assembly of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13 may both be the same as the dielectric layers 20 used in the internal layer portion 11.

[0038] The laminate 10 has a series capacitor-forming portion 11E. The series capacitor-forming portion 11E includes a portion where the first opposing portion EA of the first internal electrode layer 31 faces the first-electrode-layer-side opposing portion ECA of the intermediate electrode layer 33 (portion forming capacitance CAP1), a portion where the second opposing portion EB of the second internal electrode layer 32 faces the second-electrode-layer-side opposing portion ECB of the intermediate electrode layer 33 (portion forming capacitance CAP2), and a portion connecting the capacitances CAP1 and CAP2 in series. The series capacitor-forming portion 11E is configured as a part of the inner layer portion 11. FIGS. 4A and 4B show the width direction W and length direction L of the series capacitor-forming portion 11E. The portion of the series capacitor-forming portion 11E where the capacitance CAP1 is formed (first capacitor portion CAP1) and the portion where the capacitance CAP2 is formed (second capacitor portion CAP2) are also referred to as effective capacitor portions.

[0039] The laminate 10 has side surface-side outer layer portions. The side surface-side outer layer portions include a first side surface-side outer layer portion WG1 and a second side surface-side outer layer portion WG2. The first side surface-side outer layer portion WG1 is a portion including the dielectric layer 20 located between the series capacitor-forming portion 11E and the first side surface WS1. The second side surface-side outer layer portion WG2 is a portion including the dielectric layer 20 located between the series capacitor-forming portion 11E and the second side surface WS2. FIGS. 3, 4A, and 4B show the ranges in the width direction W of the first side surface-side outer layer portion WG1 and the second side surface-side outer layer portion WG2. The side surface-side outer layer portions are also referred to as W gaps or side gaps.

[0040] The laminate 10 has an end surface side outer layer portion. The end surface side outer layer portion has a first end surface side outer layer portion LG1 and a second end surface side outer layer portion LG2. The first end surface side outer layer portion LG1 is a portion located between the series capacitor forming portion 11E and the first end surface LS1 and including the dielectric layers 20 and the first lead portion D1. That is, the first end surface side outer layer portion LG1 is an assembly of the portions of the multiple dielectric layers 20 on the first end surface LS1 side and the multiple first lead portions D1. The second end surface side outer layer portion LG2 is a portion located between the series capacitor forming portion 11E and the second end surface LS2 and including the dielectric layers 20 and the second lead portion D2. That is, the second end surface side outer layer portion LG2 is an assembly of the portions of the multiple dielectric layers 20 on the second end surface LS2 side and the multiple second lead portions D2. 2, 4A, and 4B show the range of the first end-side outer layer portion LG1 and the second end-side outer layer portion LG2 in the length direction L. The end-side outer layer portions are also called L gaps or end gaps.

[0041] The series capacitor-forming portion 11E of the laminate 10 has a series connection region. The series connection region is a portion that includes the dielectric layer 20 and the coupling portion E0 and is located between the portion that forms the capacitance CAP1 and the portion that forms the capacitance CAP2. That is, the series connection region is an assembly of the central portions of the multiple dielectric layers 20 in the length direction L and the multiple coupling portions E0. The series connection region is also referred to as a middle gap.

[0042] As shown in Figures 1 and 2, the external electrode 40 has a first external electrode 40A arranged on the first end face LS1 side of the laminate 10, and a second external electrode 40B arranged on the second end face LS2 side of the laminate 10.

[0043] The first external electrode 40A and the second external electrode 40B have the same basic configuration. The first external electrode 40A and the second external electrode 40B have shapes that are approximately plane-symmetric with respect to a WT cross section at the center of the longitudinal direction L of the multilayer ceramic capacitor 1. Therefore, in the following, when it is not necessary to distinguish between the first external electrode 40A and the second external electrode 40B, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the external electrodes 40.

[0044] The first external electrode 40A is disposed on the first end face LS1. The first external electrode 40A is in contact with the first lead portions D1 of each of the first internal electrode layers 31 exposed at the first end face LS1. This electrically connects the first external electrode 40A to the first internal electrode layers 31. The first external electrode 40A may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the first external electrode 40A is formed to extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0045] The second external electrode 40B is disposed on the second end face LS2. The second external electrode 40B is in contact with the second lead portions D2 of each of the second internal electrode layers 32 exposed at the second end face LS2. This electrically connects the second external electrode 40B to the second internal electrode layers 32. The second external electrode 40B may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second external electrode 40B is formed to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0046] As described above, in the laminate 10, the capacitance CAP1 (first capacitor portion CAP1) is formed by the first opposing portion EA of the first internal electrode layer 31 and the first electrode layer side opposing portion ECA of the intermediate electrode layer 33 facing each other via the dielectric layer 20. The capacitance CAP2 (second capacitor portion CAP2) is formed by the second opposing portion EB of the second internal electrode layer 32 and the second electrode layer side opposing portion ECB of the intermediate electrode layer 33 facing each other via the dielectric layer 20.

[0047] The coupling portion E0 connects the capacitances CAP1 and CAP2 in series, so that the characteristics of a capacitor due to the series connection capacitance are exhibited between the first outer electrode 40A connected to the first internal electrode layer 31 and the second outer electrode 40B connected to the second internal electrode layer 32.

[0048] 2, the first external electrode 40A has a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A. The second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B.

[0049] The first base electrode layer 50A is disposed on the first end face LS1. The first base electrode layer 50A is connected to the first lead portions D1 of each of the first internal electrode layers 31 exposed at the first end face LS1. In this embodiment, the first base electrode layer 50A is formed to extend from the first end face LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0050] The second base electrode layer 50B is disposed on the second end face LS2. The second base electrode layer 50B is in contact with the second lead portions D2 of each of the second internal electrode layers 32 exposed at the second end face LS2. In this embodiment, the second base electrode layer 50B is formed to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0051] The first base electrode layer 50A and the second base electrode layer 50B include at least one selected from a baked layer, a thin film layer, and the like.

[0052] The first base electrode layer 50A and the second base electrode layer 50B of this embodiment are baked layers. The baked layers preferably contain a metal component and either a glass component or a ceramic component, or both. The metal component includes at least one selected from, for example, Cu, Ni, Ag, Pd, an Ag-Pd alloy, and Au. The glass component includes at least one selected from, for example, B, Si, Ba, Mg, Al, and Li. The ceramic component may be the same ceramic material as that of the dielectric layer 20, or a different ceramic material. The ceramic component may include at least one selected from, for example, CaZrO3 (calcium zirconate), CaTiO (calcium titanate), SrTiO3 (strontium titanate), BaZrO3 (proton-conducting metal oxide), and titanium oxide (TiO2).

[0053] The baked layer is formed by, for example, applying a conductive paste containing glass and metal to the laminate 10 and baking it. The baked layer can be formed by co-firing a pre-fired laminate chip, which is the material for the laminate 10 having multiple internal electrode layers and dielectric layers, with a conductive paste applied to the laminate chip. Alternatively, the baked layer can be formed by first firing the laminate chip to obtain the laminate 10, and then applying a conductive paste to the laminate 10 and baking it. In the above configuration, the baked layer is preferably formed by baking a material to which a ceramic material is added instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. The baked layer may be multiple layers.

[0054] The thickness of the first base electrode layer 50A located on the first end face LS1 in the longitudinal direction L is preferably, for example, approximately 3 μm or more and 200 μm or less at the center of the first base electrode layer 50A in the stacking direction T and width direction W.

[0055] The thickness of the second base electrode layer 50B located on the second end face LS2 in the longitudinal direction L is preferably, for example, approximately 3 μm or more and 200 μm or less at the center of the second base electrode layer 50B in the stacking direction T and width direction W.

[0056] When the first base electrode layer 50A is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the first base electrode layer 50A provided on this portion, corresponding to the stacking direction T, is preferably, for example, approximately 3 μm or more and 25 μm or less at the center of the first base electrode layer 50A provided on this portion in the length direction L and width direction W.

[0057] When the first base electrode layer 50A is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, the thickness of the first base electrode layer 50A provided on this portion in the width direction W is preferably, for example, approximately 3 μm or more and 25 μm or less at the center of the first base electrode layer 50A provided on this portion in the length direction L and stacking direction T.

[0058] When the second base electrode layer 50B is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the second base electrode layer 50B provided on this portion in the stacking direction T is preferably, for example, approximately 3 μm or more and 25 μm or less at the center in the length direction L and width direction W of the second base electrode layer 50B provided on this portion.

[0059] When the second base electrode layer 50B is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, the thickness corresponding to the width direction W of the second base electrode layer 50B provided on this portion is preferably, for example, approximately 3 μm or more and 25 μm or less at the center of the length direction L and stacking direction T of the second base electrode layer 50B provided on this portion.

[0060] In this embodiment, the first base electrode layer 50A and the second base electrode layer 50B may be thin film layers, which are layers on which metal particles are deposited.

[0061] When the first base electrode layer 50A and the second base electrode layer 50B are formed as thin film layers, they are preferably formed by a thin film formation method such as sputtering or vapor deposition. Here, a sputtered electrode formed by sputtering will be described.

[0062] In this embodiment, the first base electrode layer 50A may be composed of a first thin film layer formed by a sputtered electrode. The second base electrode layer 50B may be composed of a second thin film layer formed by a sputtered electrode. When forming the base electrode layer by a sputtered electrode, it is preferable to form the sputtered electrode directly on a portion of at least one of the first main surface TS1 and the second main surface TS2 of the laminate 10. The first thin film layer formed by the sputtered electrode is disposed on a portion of the first main surface TS1 on the side of the first side surface WS1. The second thin film layer formed by the sputtered electrode is disposed on a portion of the first main surface TS1 on the side of the second side surface WS2.

[0063] The thin film layer formed by the sputtered electrode preferably contains at least one metal selected from the group consisting of Mg, Al, Ti, W, Cr, Cu, Ni, Ag, Co, Mo, and V. This increases the adhesive strength of the external electrode 40 to the laminate 10. The thin film layer may be a single layer or may be formed of multiple layers. For example, it may be formed of a two-layer structure consisting of a layer of Ni-Cr alloy and a layer of Ni-Cu alloy.

[0064] The first plating layer 60A is disposed so as to cover the first base electrode layer 50A.

[0065] The second plating layer 60B is disposed so as to cover the second base electrode layer 50B.

[0066] The first plating layer 60A and the second plating layer 60B may contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag-Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may each be formed of multiple layers. The first plating layer 60A and the second plating layer 60B preferably have a two-layer structure in which a Sn plating layer is formed on a Ni plating layer.

[0067] In this embodiment, the first plating layer 60A has a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0068] In this embodiment, the second plating layer 60B has a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0069] The Ni plating layer prevents the first base electrode layer 50A and the second base electrode layer 50B from being eroded by solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1, thereby facilitating mounting of the multilayer ceramic capacitor 1. The thickness of each of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B, and the second Sn plating layer 62B is preferably 2 μm or more and 10 μm or less.

[0070] The external electrode 40 of this embodiment may have, for example, a conductive resin layer containing conductive particles and a thermosetting resin. The conductive resin layer may be disposed so as to cover the baked layer. When the conductive resin layer is disposed so as to cover the baked layer, the conductive resin layer is disposed between the baked layer and the plating layer (first plating layer 60A, second plating layer 60B). The conductive resin layer may completely cover the baked layer or may cover only a portion of the baked layer.

[0071] The conductive resin layer containing a thermosetting resin is more flexible than a conductive layer made of, for example, a plating film or a fired conductive paste. Therefore, even if the multilayer ceramic capacitor 1 is subjected to a physical shock or a shock due to a thermal cycle, the conductive resin layer functions as a buffer layer. Therefore, the conductive resin layer suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0072] The metal constituting the conductive particles may be Ag, Cu, Ni, Sn, Bi, or an alloy containing any of these. The conductive particles preferably contain Ag. The conductive particles may be, for example, Ag metal powder. Ag has the lowest resistivity among metals, making it suitable as an electrode material. Furthermore, Ag is a noble metal, so it is resistant to oxidation and has high weather resistance. Therefore, Ag metal powder is suitable as the conductive particles.

[0073] The conductive particles may also be metal powders whose surfaces are coated with Ag. When using metal powders whose surfaces are coated with Ag, the metal powder is preferably Cu, Ni, Sn, Bi, or an alloy powder thereof. In order to maintain the properties of Ag while making the base metal inexpensive, it is preferable to use Ag-coated metal powders.

[0074] Furthermore, the conductive particles may be Cu or Ni that has been subjected to an anti-oxidation treatment. Furthermore, the conductive particles may be metal powder whose surface is coated with Sn, Ni, or Cu. When using metal powder whose surface is coated with Sn, Ni, or Cu, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof.

[0075] The shape of the conductive particles is not particularly limited. The conductive particles may be spherical, flat, or other shapes, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0076] The conductive particles contained in the conductive resin layer mainly play a role in ensuring the electrical conductivity of the conductive resin layer. Specifically, the contact between the conductive particles forms an electrical path within the conductive resin layer.

[0077] The resin constituting the conductive resin layer may include at least one selected from various known thermosetting resins, such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Furthermore, the resin of the conductive resin layer preferably includes a curing agent in addition to the thermosetting resin. When an epoxy resin is used as the base resin, the curing agent for the epoxy resin may be any of various known compounds, such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.

[0078] The conductive resin layer may be formed of a plurality of layers. The thickness of the thickest part of the conductive resin layer is preferably 10 μm or more and 150 μm or less.

[0079] Note that the first plating layer 60A and the second plating layer 60B may be disposed directly on the laminate 10 without providing the first base electrode layer 50A and the second base electrode layer 50B. That is, the multilayer ceramic capacitor 1 may include plating layers that are directly and electrically connected to the first internal electrode layer 31 and the second internal electrode layer 32. In such a case, a catalyst may be disposed on the surface of the laminate 10 as a pretreatment, and then the plating layers may be formed.

[0080] Even in this case, the plating layer preferably comprises multiple layers. The lower plating layer and the upper plating layer each preferably contain at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing these metals. The lower plating layer is more preferably formed using Ni, which has solder barrier properties. The upper plating layer is more preferably formed using Sn or Au, which have good solder wettability. For example, when the first internal electrode layer 31 and the second internal electrode layer 32 are formed using Ni, the lower plating layer is preferably formed using Cu, which has good bonding properties with Ni. The upper plating layer may be formed as needed, and the external electrode 40 may be composed of only the lower plating layer. Furthermore, the upper plating layer may be the outermost layer, or another plating layer may be formed on the surface of the upper plating layer.

[0081] The thickness of each plating layer, which is disposed without a base electrode layer, is preferably 2 μm or more and 10 μm or less. The plating layer preferably does not contain glass. The metal content per unit volume of the plating layer is preferably 99% by volume or more.

[0082] Note that when the plating layer is formed directly on the laminate 10, the thickness of the base electrode layer can be reduced. Therefore, the dimension of the multilayer ceramic capacitor 1 in the stacking direction T can be reduced by the amount of the reduced thickness of the base electrode layer, thereby making it possible to reduce the height of the multilayer ceramic capacitor 1. Alternatively, the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 can be increased by the amount of the reduced thickness of the base electrode layer, thereby improving the thickness of the element body. In this way, by forming the plating layer directly on the laminate 10, the degree of freedom in designing the multilayer ceramic capacitor can be improved.

[0083] The above is the basic configuration of the multilayer ceramic capacitor 1 according to the embodiment. If the lengthwise dimension of the multilayer ceramic capacitor 1 including the laminate 10 and the external electrodes 40 is defined as L, then the L dimension is preferably 0.2 mm or more and 10 mm or less. If the lengthwise dimension of the multilayer ceramic capacitor 1 is defined as T, then the T dimension is preferably 0.1 mm or more and 10 mm or less. If the widthwise dimension of the multilayer ceramic capacitor 1 is defined as W, then the W dimension is preferably 0.1 mm or more and 10 mm or less.

[0084] Hereinafter, this embodiment will be described in detail with reference to Figures 1 to 5. Figure 5 is a schematic cross-sectional view for explaining a configuration in which the coverage of the intermediate electrode layer 33 is increased in the internal electrode layer 30 of the multilayer ceramic capacitor 1 according to the first embodiment.

[0085] In the multilayer ceramic capacitor 1 according to this embodiment, the coverage of the intermediate electrode layer 33 is higher than the coverage of the first internal electrode layer 31 and the coverage of the second internal electrode layer 32. The internal electrode layer 30 includes, in addition to the metal material, hollow portions where no metal material is present, and the ratio of the metal material to the internal electrode layer 30 will be described as the coverage. Coverage is also referred to as the coverage rate of the internal electrode layer 30 relative to the dielectric layer 20. The hollow portions where no metal material is present may contain a ceramic component such as a dielectric or a glass component such as silica. Alternatively, the hollow portions where no metal material is present may be voids.

[0086] For example, in the multilayer ceramic capacitor 1 according to this embodiment, the coverage of the first internal electrode layers 31 and the coverage of the second internal electrode layers 32 are preferably less than 85%, and more preferably 60% to 80%. The coverage of the intermediate electrode layers 33 is preferably 90% or more, and more preferably 95% or more. The coverage of the intermediate electrode layers 33 is preferably 10 percentage points or more higher, and more preferably 15 percentage points or more higher than the coverage of the first internal electrode layers 31 and the coverage of the second internal electrode layers 32.

[0087] In the multilayer ceramic capacitor 1 according to this embodiment, the first internal electrode layers 31 and the second internal electrode layers 32 have a larger proportion of hollow portions where no metal is present than the intermediate electrode layers 33. In other words, the proportion of metal material in the first internal electrode layers 31 and the second internal electrode layers 32 is smaller than the proportion of metal material in the intermediate electrode layers 33.

[0088] Ceramic columnar structures that connect the two dielectric layers 20 sandwiching both sides of the internal electrode layer 30 are likely to be formed in the cavity portion of the internal electrode layer 30. For this reason, the lower the coverage, the more columnar structures there are in the cavity portion, and the more columnar structures there are, the more firmly the two dielectric layers 20 are connected. In this case, the internal electrode layer 30 sandwiched between the two dielectric layers 20 is firmly sandwiched by the two dielectric layers 20, so interfacial peeling between the two dielectric layers 20 and the internal electrode layer 30 sandwiched between the two dielectric layers 20 is suppressed. Here, particular care must be taken to prevent interfacial peeling from occurring in the first lead portion D1 and the second lead portion D2 (lead electrode portions), which are the starting points for penetration of moisture and plating solution.

[0089] Therefore, in this embodiment, the coverage of the first internal electrode layer 31 and the second internal electrode layer 32 including the lead electrode portion is reduced to improve the interfacial adhesion between the internal electrode layer 30 and the dielectric layer 20, while the coverage of the intermediate electrode layer 33 is increased to increase the capacitance. That is, the high-voltage, double-structure multilayer ceramic capacitor according to this embodiment can suppress the occurrence of interfacial peeling while suppressing a decrease in capacitance.

[0090] Here, the coverage relationship between the first internal electrode layer 31, the second internal electrode layer 32 and the intermediate electrode layer 33 will be described in more detail.

[0091] As described above, in the multilayer ceramic capacitor 1 according to this embodiment, the coverage of the intermediate electrode layer 33 is higher than the coverage of the first internal electrode layer 31 and the coverage of the second internal electrode layer 32. For example, it is preferable that the coverage of the first opposing portion EA of the first internal electrode layer 31 and the coverage of the first lead portion D1 are both lower than the coverage of the first electrode layer side opposing portion ECA of the intermediate electrode layer 33. It is preferable that the coverage of the second opposing portion EB of the second internal electrode layer 32 and the coverage of the second lead portion D2 are both lower than the coverage of the second electrode layer side opposing portion ECB of the intermediate electrode layer 33. For example, the coverage of the first opposing portion EA and the first lead portion D1 may be substantially the same, but lower than the coverage of the first electrode layer side opposing portion ECA. Furthermore, the coverage of the second opposing portion EB and the second lead portion D2 may be substantially the same, but may be lower than the coverage of the second electrode layer side opposing portion ECB. This prevents the manufacturing process for forming the first internal electrode layer 31 and the second internal electrode layer 32 from becoming complicated. The coverage of the first opposing portion EA may be higher than the coverage of the first lead portion D1. The coverage of the second opposing portion EB may be higher than the coverage of the second lead portion D2. This prevents the occurrence of interfacial peeling and increases the capacitance. The coverage of the first opposing portion EA may be higher than the coverage of the first lead portion D1 and lower than the coverage of the first electrode layer side opposing portion ECA. The coverage of the second facing portion EB may be higher than the coverage of the second lead portion D2 and lower than the coverage of the second electrode layer side facing portion ECB.

[0092] The coverage of the first electrode layer side facing portion ECA of the intermediate electrode layer 33 is higher than the coverage of the first facing portion EA of the first internal electrode layer 31. The coverage of the second electrode layer side facing portion ECB of the intermediate electrode layer 33 is higher than the coverage of the second facing portion EB of the second internal electrode layer 32. In this way, by increasing the coverage of at least one of the pair of facing portions that form the capacitor forming portion, it is possible to suppress a decrease in capacitance.

[0093] The coverage of the first electrode layer side facing portion ECA of the intermediate electrode layer 33 is higher than the coverage of the first lead portion D1 of the first internal electrode layer 31. The coverage of the second electrode layer side facing portion ECB of the intermediate electrode layer 33 is higher than the coverage of the first lead portion D2 of the second internal electrode layer 32. This makes it possible to suppress the occurrence of interfacial peeling while suppressing a decrease in capacitance.

[0094] The coverage of the connecting portion E0 of the intermediate electrode layer 33 is higher than the coverage of the first opposing portion EA of the first internal electrode layer 31 and the coverage of the second opposing portion EB of the second internal electrode layer 32. The coverage of the connecting portion E0 of the intermediate electrode layer 33 is higher than the coverage of the first lead portion D1 of the first internal electrode layer 31 and the coverage of the second lead portion D2 of the second internal electrode layer 32. This allows for more stable electrical series connection of multiple capacitor-forming portions. Furthermore, this configuration makes it easier to form the intermediate electrode layer 33 with a consistent coverage and thickness, thereby preventing the manufacturing process from becoming complicated. The coverages of the first electrode layer side opposing portion ECA of the intermediate electrode layer 33, the connecting portion E0 of the intermediate electrode layer 33, and the second electrode layer side opposing portion ECB of the intermediate electrode layer 33 may be substantially the same.

[0095] <Coverage measurement method> A description will be given of a method for measuring coverage as the coverage rate of the internal electrode layers 30 relative to the dielectric layers 20. Note that the measurement of coverage in this measurement method is also called measurement of line coverage.

[0096] First, the multilayer ceramic capacitor 1 is polished from the first side surface WS1 or the second side surface WS2 to expose the LT cross section where the series capacitor forming portion 11E of the laminate 10 is exposed. If necessary, the exposed LT cross section at the observation position is etched to remove the internal electrode layers 30 that have been stretched by polishing. Measurement points M1 to M5 (described below) in the center of the width direction W of the exposed LT cross section are observed using an SEM (scanning electron microscope).

[0097] Measurement points are set in the L gap, the capacitor effective portion, and the intermediate gap. In this embodiment, measurement points M1 to M5 are set in the first end face side outer layer portion LG1 and the second end face side outer layer portion LG2 as the L gap, the first capacitor portion CAP1 and the second capacitor portion CAP2 as the capacitor effective portion, and the intermediate gap including the connecting portion E0. Measurement points M1 to M5 are set at the center in the stacking direction T of the exposed LT cross section.

[0098] The measurement point M1 is set in a region including the lead portion D1 of the first internal electrode layer 31. Specifically, the measurement point M1 is set at the center in the length direction L of the lead portion D1.

[0099] The measurement point M2 is set in a region including the first opposing portion EA of the first internal electrode layer 31 in the first capacitor portion CAP1 and the first electrode layer side opposing portion ECA of the intermediate electrode layer 33. Specifically, the measurement point M2 is set at the center in the length direction L of the first opposing portion EA and the first electrode layer side opposing portion ECA that form the first capacitor portion CAP1.

[0100] The measurement point M3 is set in a region in the intermediate gap that includes the connecting portion E0 of the intermediate electrode layer 33. Specifically, the measurement point M3 is set at the center in the length direction L of the connecting portion E0.

[0101] The measurement point M4 is set in a region including the second opposing portion EB of the second internal electrode layer 32 in the second capacitor portion CAP2 and the second electrode layer side opposing portion ECB of the intermediate electrode layer 33. Specifically, the measurement point M4 is set at the center in the length direction L of the second opposing portion EB and the second electrode layer side opposing portion ECB that form the second capacitor portion CAP2.

[0102] The measurement point M5 is set in a region in the second end face side outer layer portion LG2 including the lead portion D2 of the second internal electrode layer 32. Specifically, the measurement point M5 is set at the center in the length direction L of the lead portion D2.

[0103] In the case of a multilayer ceramic capacitor having three or more rows as shown in the embodiments described later, the measurement points are preferably set in regions according to the structure, and are preferably set in the L gap, the capacitor effective portion, and the intermediate gap, as in the present embodiment.

[0104] The line coverage of the exposed LT cross section is measured using an optical microscope. The line coverage is measured at the measurement points M1 to M5. The magnification for observing each measurement point is 1000x.

[0105] The internal electrode layer 30 has regions where conductive components are present and regions where conductive components are not present, such as hollow portions. The line coverage is calculated as the ratio of the length in the length direction L of the region occupied by the conductive components that actually constitute the internal electrode layer 30 to the length in the length direction L of the internal electrode layer 30 in an optical microscope image without considering the presence or absence of conductive components, i.e., the ratio of the length in the length direction L of the internal electrode layer 30 excluding the region where conductive components are not present to the length in the length direction L of the internal electrode layer 30 without considering the presence or absence of conductive components. Then, the coverages of the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 present at each measurement point are measured, and an average value is calculated for each of the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33. The average values ​​are used as the coverages of the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 in this embodiment.

[0106] For example, when measuring the coverage of the first internal electrode layer 31, the coverage of the first internal electrode layer 31 is measured at measurement point M1 and measurement point M2, and the average value is defined as the coverage of the first internal electrode layer 31 in this embodiment. When measuring the coverage of the second internal electrode layer 32, the coverage of the second internal electrode layer 32 is measured at measurement point M4 and measurement point M5, and the average value is defined as the coverage of the second internal electrode layer 32 in this embodiment. When measuring the coverage of the intermediate electrode layer 33, the coverage of the intermediate electrode layer 33 is measured at measurement point M2, measurement point M3, and measurement point M4, and the average value is defined as the coverage of the intermediate electrode layer 33 in this embodiment.

[0107] <Manufacturing method> Next, a method for manufacturing the multilayer ceramic capacitor 1 of this embodiment will be described. The method for manufacturing the multilayer ceramic capacitor 1 of this embodiment is not limited as long as it satisfies the above-mentioned requirements. However, a suitable manufacturing method includes the following steps. Each step will be described in detail below.

[0108] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and the solvent may be known.

[0109] A conductive paste for the internal electrode layer 30 is printed in a predetermined pattern on a dielectric sheet by, for example, screen printing or gravure printing. As a result, a dielectric sheet on which the pattern of the first internal electrode layer 31 and the pattern of the second internal electrode layer 32 are formed, and a dielectric sheet on which the pattern of the intermediate electrode layer 33 is formed are prepared, respectively. The coverage of the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 is adjusted by stacking dielectric sheets with different coating thicknesses. For example, the coating thickness of the conductive paste for the intermediate electrode layer 33, which requires higher coverage, is made thicker than the coating thickness of the conductive paste for the first internal electrode layer 31 and the second internal electrode layer 32. Note that the printing method is not limited to screen printing or the like.

[0110] The conductive paste for the intermediate electrode layer 33 may be applied with a substantially constant coating thickness so that the intermediate electrode layer 33 has a substantially constant thickness and substantially constant coverage overall. The conductive paste for the first internal electrode layer 31 may be applied with a substantially constant coating thickness so that the first internal electrode layer 31 has a substantially constant thickness and substantially constant coverage overall. The conductive paste for the second internal electrode layer 32 may be applied with a substantially constant coating thickness so that the second internal electrode layer 32 has a substantially constant thickness and substantially constant coverage overall. This prevents the manufacturing process from becoming complicated. The conductive paste for the first internal electrode layer 31 and the conductive paste for the second internal electrode layer 32 may be applied with a substantially constant coating thickness so that the coverages of the first internal electrode layer 31 and the second internal electrode layer 32 are substantially the same. This prevents the manufacturing process from becoming complicated. However, this is not limited to this.

[0111] The laminated sheets are pressed in the height direction by means of a hydrostatic press or the like to produce a laminated block.

[0112] The laminated block is cut to a predetermined size to obtain laminated chips, and at this time, corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0113] The laminated chip is fired to produce the laminate 10. The firing temperature depends on the materials of the dielectric layers 20 and the internal electrode layers 30, but is preferably 900°C or higher and 1400°C or lower.

[0114] A conductive paste that will become a base electrode layer is applied to both end surfaces of the laminate 10 .

[0115] In this embodiment, the base electrode layer is a baked layer. A conductive paste containing a glass component and a metal is applied to the laminate 10 by a method such as dipping. A baking process is then performed to form the base electrode layer. The baking temperature at this time is preferably 700°C or higher and 900°C or lower.

[0116] When the unfired laminated chip and the conductive paste applied to the laminated chip are simultaneously fired, the fired layer is preferably formed by firing a material containing a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as that of the dielectric layer 20 as the added ceramic material. In this case, the conductive paste is applied to the unfired laminated chip, and the laminated chip and the conductive paste applied to the laminated chip are simultaneously fired to form the laminate 10 with the fired layer.

[0117] Thereafter, a plating layer is formed on the surface of the base electrode layer. In this embodiment, a first plating layer 60A is formed on the surface of the first base electrode layer 50A. Furthermore, a second plating layer 60B is formed on the surface of the second base electrode layer 50B. In this embodiment, a Ni plating layer and an Sn plating layer are formed as the plating layers. Either electrolytic plating or electroless plating may be used for the plating process.

[0118] However, electroless plating has the disadvantage of requiring pretreatment with a catalyst to improve plating deposition speed, which makes the process more complicated. Therefore, electrolytic plating is usually preferred. The Ni plating layer and Sn plating layer are formed sequentially, for example, by barrel plating.

[0119] When a conductive resin layer is provided as the base electrode layer, the conductive resin layer may be disposed so as to cover the baked layer. When providing the conductive resin layer, a conductive resin paste containing a thermosetting resin and a metal component is applied onto the baked layer, and then heat-treated at a temperature of 250 to 550°C or higher. This causes the thermosetting resin to thermally harden, forming a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent the resin from scattering and the various metal components from oxidizing, the oxygen concentration is preferably 100 ppm or less.

[0120] Through these manufacturing steps, the multilayer ceramic capacitor 1 is manufactured.

[0121] The present invention is not limited to the multilayer ceramic capacitor 1 having a double structure, but can be widely used in multilayer ceramic capacitors having a series structure.

[0122] <Second embodiment> The multilayer ceramic capacitor 1 according to the second embodiment is a multilayer ceramic capacitor with a triplet structure. The multilayer ceramic capacitor 1 according to the second embodiment will be described below with reference to FIG. 6. In the following description, detailed description of the same configuration as in the first embodiment may be omitted. FIG. 6 is a schematic cross-sectional view illustrating a configuration in which the coverage of the intermediate electrode layers 33 is increased in the internal electrode layers 30 of the multilayer ceramic capacitor 1 according to the second embodiment. The manufacturing method of the second embodiment is the same as that of the first embodiment, and description thereof will be omitted.

[0123] The multilayer ceramic capacitor 1 of this embodiment differs from the first embodiment in the form of the internal electrode layers 30 inside the laminate 10. Specifically, while the multilayer ceramic capacitor 1 according to the first embodiment has a double structure, the multilayer ceramic capacitor 1 according to the second embodiment has a triple structure internal electrode layers 30, and the form of the internal electrode layers 30 inside the laminate 10 differs from that of the first embodiment.

[0124] The multiple internal electrode layers 30 include multiple first internal electrode layers 31 as multiple first internal conductor layers, multiple second internal electrode layers 32 as multiple second internal conductor layers, and an intermediate electrode layer 33.

[0125] As shown in FIG. 6, the intermediate electrode layer 33 according to the second embodiment includes a first intermediate electrode layer 331 and a second intermediate electrode layer 332.

[0126] The first intermediate electrode layer 331 has a first electrode layer side facing portion EC1A, a first intermediate electrode layer facing portion EC1B, and a first connecting portion E10. The first electrode layer side facing portion EC1A is a region facing the first internal electrode layer 31 arranged adjacent to it in the stacking direction T, and is located inside the laminate 10. The first intermediate electrode layer facing portion EC1B is a region facing the second intermediate electrode layer 332 arranged adjacent to it in the stacking direction T, and is located inside the laminate 10. The first connecting portion E10 is a portion connecting the first electrode layer side facing portion EC1A and the first intermediate electrode layer facing portion EC1B, and is located between the first electrode layer side facing portion EC1A and the first intermediate electrode layer facing portion EC1B.

[0127] The second intermediate electrode layer 332 has a second electrode layer side facing portion EC2A, a second intermediate electrode layer facing portion EC2B, and a second connecting portion E20. The second electrode layer side facing portion EC2A faces the second internal electrode layer 32 arranged adjacent to it in the stacking direction T. The second intermediate electrode layer facing portion EC2B faces the first intermediate electrode layer 331 arranged adjacent to it in the stacking direction T. The second connecting portion E20 connects the second electrode layer side facing portion EC2A and the second intermediate electrode layer facing portion EC2B, and is arranged between the second electrode layer side facing portion EC2A and the second intermediate electrode layer facing portion EC2B.

[0128] 6, in the multilayer ceramic capacitor 1 according to the second embodiment, the first internal electrode layer 31 and the second intermediate electrode layer 332 are arranged adjacent to each other in the length direction L. In the multilayer ceramic capacitor 1 according to the second embodiment, the second internal electrode layer 32 and the first intermediate electrode layer 331 are arranged adjacent to each other in the length direction L.

[0129] In the multilayer ceramic capacitor 1 according to the second embodiment, the first internal electrode layer 31 and the second intermediate electrode layer 332, and the second internal electrode layer 32 and the first intermediate electrode layer 331 are stacked alternately with the dielectric layer 20 interposed therebetween.

[0130] In this embodiment, the first opposing portion EA and the first electrode layer side opposing portion EC1A face each other via the dielectric layer 20, thereby forming a capacitance CAP1 (first capacitor portion CAP1). The second opposing portion EB and the second electrode layer side opposing portion EC2A face each other via the dielectric layer, thereby forming a capacitance CAP2 (second capacitor portion CAP2). The first intermediate electrode layer opposing portion EC1B and the second intermediate electrode layer opposing portion EC2B face each other via the dielectric layer 20, thereby forming a capacitance CAP3 (third capacitor portion CAP3). The first connecting portion E10 connects the capacitance CAP1 and the capacitance CAP3 in series. The second connecting portion E20 connects the capacitance CAP2 and the capacitance CAP3 in series. The multilayer ceramic capacitor 1 of this embodiment is a multilayer ceramic capacitor 1 with a so-called triplet series structure in which three capacitor portions are connected in series.

[0131] The laminate 10 has a series capacitor-forming portion 11E. The series capacitor-forming portion 11E includes a portion that forms capacitance CAP1, a portion that forms capacitance CAP2, a portion that forms capacitance CAP3, a portion that connects capacitances CAP1 and CAP3 in series, and a portion that connects capacitances CAP2 and CAP3 in series. The series capacitor-forming portion 11E is configured as a part of the inner layer portion 11. Of the series capacitor-forming portion 11E, the portion that forms capacitance CAP1 (first capacitor portion CAP1), the portion that forms capacitance CAP2 (second capacitor portion CAP2), and the portion that forms capacitance CAP3 (third capacitor portion CAP3) are also referred to as effective capacitor portions.

[0132] The series capacitor forming portion 11E of the laminate 10 has a first series connection region and a second series connection region. The first series connection region is a portion including the dielectric layer 20 and the first coupling portion E10, located between the portion forming the capacitance CAP1 and the portion forming the capacitance CAP3. The second series connection region is a portion including the dielectric layer 20 and the second coupling portion E20, located between the portion forming the capacitance CAP2 and the portion forming the capacitance CAP3. That is, the first series connection region is a collection of portions of the multiple dielectric layers 20 that overlap with the first coupling portion E10 when viewed from the stacking direction T, and the multiple first coupling portions E10. The second series connection region is a collection of portions of the multiple dielectric layers 20 that overlap with the second coupling portion E20 when viewed from the stacking direction T, and the multiple second coupling portions E20.

[0133] As shown in FIG. 6, the external electrode 40 has a first external electrode 40A arranged on the first end face LS1 side of the laminate 10, and a second external electrode 40B arranged on the second end face LS2 side of the laminate 10.

[0134] The first connecting portion E10 connects the capacitances CAP1 and CAP3 in series. The second connecting portion E20 connects the capacitances CAP2 and CAP3 in series. Therefore, the characteristics of a capacitor due to the series connection capacitance are exhibited between the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32.

[0135] In the multilayer ceramic capacitor 1 according to the second embodiment, the coverage of the intermediate electrode layers 33 is also higher than that of the first internal electrode layers 31 and the second internal electrode layers 32. More specifically, the coverage of the first internal electrode layers 331 and the second internal electrode layers 332 is higher than that of the first internal electrode layers 31 and the second internal electrode layers 32. For example, in the multilayer ceramic capacitor 1 according to the second embodiment, the coverage of the first internal electrode layers 31 and the coverage of the second internal electrode layers 32 are preferably less than 85%, and more preferably 60% to 80%. The coverage of the first intermediate electrode layers 331 and the second intermediate electrode layers 332 are preferably 90% or higher, and more preferably 95% or higher. The coverage of the intermediate electrode layer 33 is preferably 10 percentage points or more higher than the coverage of the first internal electrode layer 31 and the coverage of the second internal electrode layer 32, and more preferably 15 percentage points or more higher.

[0136] In the multilayer ceramic capacitor 1 according to this embodiment, the first intermediate electrode layer facing portion EC1B of the first intermediate electrode layer 331 and the second intermediate electrode layer facing portion EC2B of the second intermediate electrode layer 332 are both higher than the coverage of the first internal electrode layer 31 and the coverage of the second internal electrode layer 32. Furthermore, the first intermediate electrode layer facing portion EC1B of the first intermediate electrode layer 331 and the second intermediate electrode layer facing portion EC2B of the second intermediate electrode layer 332 face each other to form a third capacitor portion CAP3. Therefore, the coverage of the internal electrode layers constituting the third capacitor portion CAP3 is higher than the coverage of the first internal electrode layer 31 and the coverage of the second internal electrode layer 32.

[0137] As a result, in the high-voltage multilayer ceramic capacitor having a triple structure according to the second embodiment, the capacitance can be increased while preventing the occurrence of interfacial peeling.

[0138] <Third embodiment> 1 to 4B, the multilayer ceramic capacitor 1 may be a multilayer ceramic capacitor having a four-layer structure as shown in FIG.

[0139] The multilayer ceramic capacitor 1 according to the third embodiment will be described below with reference to FIG. 7. In the following description, detailed description of the same configurations as those of the first and second embodiments will be omitted. The method for manufacturing the multilayer ceramic capacitor according to the third embodiment is similar to that of the multilayer ceramic capacitor according to the first embodiment, and description thereof will be omitted. FIG. 7 is a schematic cross-sectional view illustrating a configuration in which the coverage of the intermediate electrode layers 33 is increased in the internal electrode layers 30 of the multilayer ceramic capacitor 1 according to the third embodiment.

[0140] The multilayer ceramic capacitor 1 of this embodiment differs from the first embodiment in the configuration of the internal electrode layers 30 inside the laminate 10 and the external electrodes 40. Specifically, while the multilayer ceramic capacitor 1 according to the first embodiment has a double structure for the internal electrode layers 30, the multilayer ceramic capacitor 1 according to the third embodiment has a quadruple structure for the internal electrode layers 30 inside the laminate 10, and the configuration of the internal electrode layers 30 inside the laminate 10 differs from that of the first embodiment.

[0141] The multiple internal electrode layers 30 include multiple first internal electrode layers 31 as multiple first internal conductor layers, multiple second internal electrode layers 32 as multiple second internal conductor layers, and an intermediate electrode layer 33.

[0142] As shown in FIG. 7, the intermediate electrode layer 33 includes a first intermediate electrode layer 331 , a second intermediate electrode layer 332 , and a third intermediate electrode layer 333 .

[0143] The first intermediate electrode layer 331 has a first electrode layer side opposing portion EC1A opposing the first internal electrode layer 31 arranged adjacent to it in the stacking direction T, a first intermediate electrode layer opposing portion EC1B opposing the third intermediate electrode layer 333 arranged adjacent to it in the stacking direction T, and a first connecting portion E10.

[0144] The second intermediate electrode layer 332 has a second electrode layer side opposing portion EC2A that faces the second internal electrode layer 32 arranged adjacent to it in the stacking direction T, a second intermediate electrode layer opposing portion EC2B that faces the third intermediate electrode layer 333 arranged adjacent to it in the stacking direction T, and a second connecting portion E20.

[0145] The third intermediate electrode layer 333 has a third intermediate electrode layer opposing portion EC3A opposing the first intermediate electrode layer 331 arranged adjacent to it in the stacking direction T, a fourth intermediate electrode layer opposing portion EC3B opposing the second intermediate electrode layer 332 arranged adjacent to it in the stacking direction T, and a third connecting portion E30.

[0146] 7, in the multilayer ceramic capacitor 1 according to the third embodiment, the first internal electrode layer 31, the third intermediate electrode layer 333, and the second internal electrode layer 32 are arranged adjacent to each other in the length direction L. In the multilayer ceramic capacitor 1 according to the third embodiment, the first intermediate electrode layer 331 and the second intermediate electrode layer 332 are arranged adjacent to each other in the length direction L.

[0147] In the multilayer ceramic capacitor 1 of the third embodiment, the first internal electrode layer 31, the third intermediate electrode layer 333 and the second internal electrode layer 32, and the first intermediate electrode layer 331 and the second intermediate electrode layer 332 are stacked alternately with the dielectric layer 20 interposed therebetween.

[0148] In this embodiment, the first opposing portion EA and the first electrode layer side opposing portion EC1A face each other via the dielectric layer 20, thereby forming a capacitance CAP1 (first capacitor portion CAP1). The second opposing portion EB and the second electrode layer side opposing portion EC2A face each other via the dielectric layer 20, thereby forming a capacitance CAP2 (second capacitor portion CAP2). The first intermediate electrode layer opposing portion EC1B and the third intermediate electrode layer opposing portion EC3A face each other via the dielectric layer 20, thereby forming a capacitance CAP3 (third capacitor portion CAP3). The second intermediate electrode layer opposing portion EC2B and the fourth intermediate electrode layer opposing portion EC3B face each other via the dielectric layer 20, thereby forming a capacitance CAP4 (fourth capacitor portion CAP4). The first connecting portion E10 connects the capacitance CAP1 and the capacitance CAP3 in series. The second connecting portion E20 connects the capacitance CAP2 and the capacitance CAP4 in series. The third coupling portion E30 connects the capacitance CAP3 and the capacitance CAP4 in series. The multilayer ceramic capacitor 1 of this embodiment is a multilayer ceramic capacitor 1 having a so-called four-series structure in which four capacitor units are connected in series.

[0149] The laminate 10 has a series capacitor-forming portion 11E. The series capacitor-forming portion 11E includes a portion forming capacitance CAP1, a portion forming capacitance CAP2, a portion forming capacitance CAP3, a portion forming capacitance CAP4, a portion connecting capacitances CAP1 and CAP3 in series, a portion connecting capacitances CAP2 and CAP4 in series, and a portion connecting capacitances CAP3 and CAP4 in series. The series capacitor-forming portion 11E is configured as a part of the inner layer portion 11. Of the series capacitor-forming portion 11E, the portion forming capacitance CAP1 (first capacitor portion CAP1), the portion forming capacitance CAP2 (second capacitor portion CAP2), the portion forming capacitance CAP3 (third capacitor portion CAP3), and the portion forming capacitance CAP4 (fourth capacitor portion CAP4) are also referred to as effective capacitor portions.

[0150] The series capacitor forming portion 11E of the laminate 10 has a first series connection region, a second series connection region, and a third series connection region. The first series connection region is a portion including the dielectric layer 20 and the first coupling portion E10, located between the portion forming the capacitance CAP1 and the portion forming the capacitance CAP3. The second series connection region is a portion including the dielectric layer 20 and the second coupling portion E20, located between the portion forming the capacitance CAP2 and the portion forming the capacitance CAP4. The third series connection region is a portion including the dielectric layer 20 and the third coupling portion E30, located between the portion forming the capacitance CAP3 and the portion forming the capacitance CAP4. In other words, the first series connection region is an assembly of the portions of the multiple dielectric layers 20 that overlap with the first coupling portion E10 when viewed from the stacking direction T, and multiple first coupling portions E10. The second series connection region is an assembly of the plurality of second coupling portions E20 and portions of the plurality of dielectric layers 20 that overlap with the second coupling portion E20 when viewed from the stacking direction T. The third series connection region is an assembly of the plurality of third coupling portions E30 and portions of the plurality of dielectric layers 20 that overlap with the third coupling portion E30 when viewed from the stacking direction T.

[0151] As shown in FIG. 7, the external electrode 40 has a first external electrode 40A arranged on the first end face LS1 side of the laminate 10, and a second external electrode 40B arranged on the second end face LS2 side of the laminate 10.

[0152] The first connecting portion E10 connects the capacitances CAP1 and CAP3 in series. The second connecting portion E20 connects the capacitances CAP2 and CAP4 in series. The third connecting portion E30 connects the capacitances CAP3 and CAP4 in series. Therefore, the characteristics of a capacitor due to the series connection capacitance are exhibited between the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32.

[0153] In the multilayer ceramic capacitor 1 according to the third embodiment, the coverage of the intermediate electrode layer 33 is also higher than the coverage of the first internal electrode layer 31 and the second internal electrode layer 32. More specifically, the coverage of the first intermediate electrode layer 331, the second intermediate electrode layer 332, and the third intermediate electrode layer 333 is higher than the coverage of the first internal electrode layer 31 and the second internal electrode layer 32.

[0154] For example, in the multilayer ceramic capacitor 1 according to the third embodiment, the coverage of the first internal electrode layer 31 and the coverage of the second internal electrode layer 32 are preferably less than 85%, and more preferably 60% to 80%. The coverage of the first intermediate electrode layer 331, the second intermediate electrode layer 332, and the third intermediate electrode layer 333 are preferably 90% or more, and more preferably 95% or more. The coverage of the intermediate electrode layer 33 is preferably 10 percentage points or more higher than the coverage of the first internal electrode layer 31 and the coverage of the second internal electrode layer 32, and more preferably 15 percentage points or more higher.

[0155] In the multilayer ceramic capacitor 1 according to this embodiment, the first intermediate electrode layer facing portion EC1B of the first intermediate electrode layer 331, the second intermediate electrode layer facing portion EC2B of the second intermediate electrode layer 332, and the third intermediate electrode layer facing portion EC3A and fourth intermediate electrode layer facing portion EC3B of the third intermediate electrode layer 333 are all higher than the coverage of the first internal electrode layer 31 and the coverage of the second internal electrode layer 32. Furthermore, the third intermediate electrode layer facing portion EC3A of the third intermediate electrode layer 333 faces the first intermediate electrode layer facing portion EC1B of the first intermediate electrode layer 331 to form a third capacitor portion CAP3. The fourth intermediate electrode layer facing portion EC3B of the third intermediate electrode layer 333 faces the second intermediate electrode layer facing portion EC2B of the second intermediate electrode layer 332 to form a fourth capacitor portion CAP4. Therefore, the coverage of the internal electrode layers constituting the third capacitor portion CAP3 and the fourth capacitor portion CAP4 is higher than the coverage of the first internal electrode layer 31 and the coverage of the second internal electrode layer 32.

[0156] As a result, in the high-voltage multilayer ceramic capacitor having a four-layer structure according to the third embodiment, the capacitance can be increased while preventing the occurrence of interfacial peeling.

[0157] <Experimental Example> Next, an experimental example performed on the multilayer ceramic capacitor 1 according to the first embodiment, which is representative of the multilayer ceramic capacitor 1 according to the present disclosure, will be described. According to the manufacturing method described in the first embodiment, samples were manufactured in lots, with manufacturing conditions adjusted so that the coverage of each internal electrode layer was different, as samples for Experimental Examples 1 to 3 and Comparative Examples 1 to 3. The samples within each lot were manufactured under the same manufacturing conditions. For each example and comparative example, n=5 samples for coverage measurement, n=10 samples for peel test, and n=10 samples for capacitance test were taken from the same lot and prepared. The coverage measurements and each test were evaluated using the average value of the measurement results. Specific coverages and evaluation results for each example and comparative example are listed in Table 1 below.

[0158] First, a multilayer ceramic capacitor having the following specifications was fabricated as an example sample according to the manufacturing method described in the first embodiment.

[0159] (sample) -Size of multilayer ceramic capacitor: 3.4mm(L) x 2.7mm(W) x 2.7mm(T) Rated voltage: 1000V Dielectric layer: CaZrO3 (thickness of dielectric layer: 3.96 μm) Internal electrode layer: Ni (internal electrode layer coverage: see Table 1) Laminate structure: 2-layer structure

[0160] (Coverage measurement) The coverage was measured by the above-mentioned measurement method.

[0161] (peel test) Using an ultrasonic flaw detector, 20 kHz ultrasonic waves were irradiated onto the sample, and cracks and delaminations inside the chip were detected from the difference between the incident wave and the reflected wave. Here, the time until peeling occurs at the interface between the dielectric layer and the internal electrode layer and the time until peeling occurs across the entire interface were evaluated by the following method. The chip is polished to expose the internal electrode layer. The exposed surface of the internal electrode layer is cleaned with a mixed solution mainly containing ethanol. The stacked chip is held with tweezers and the tweezers are fixed to a stand. The negative power cord of the DC power supply is connected to the top of the tweezers. The position of the stand is then adjusted and part of the stacked chip held with the tweezers is immersed in the sodium hydroxide solution in the petri dish. Immerse one end of the Pt wire connected to the positive power cord of the DC power supply in the sodium hydroxide solution in the petri dish. Apply a voltage of 5V to the power cord using a DC power supply, and use an ultrasonic flaw detector to check for cracks every minute. The time from when a voltage of 5V starts to be applied until the first interfacial peeling is confirmed is defined as the interfacial peeling occurrence time. The time from when a voltage of 5V starts to be applied until the complete interfacial peeling is confirmed is defined as the total interfacial peeling time.

[0162] The evaluation criteria for the peel test were as follows: ◯ (pass) when the time required for peeling the entire interface was 40 minutes or more, and × (fail) when the time required for peeling the entire interface was less than 40 minutes.

[0163] (Capacitance test) The capacitance was measured using a C meter under the conditions of a frequency of 120 Hz and an applied voltage of 0.5 Vrms. In Table 1, the capacitance of Comparative Example 1 was used as the reference, and the acceptable range was within ±5% of the capacitance of Comparative Example 1. If the capacitance was within the acceptable range, it was marked as "pass" (◯), and if the capacitance was outside the acceptable range, it was marked as "fail" (×).

[0164] Table 1 shows the measurement results and evaluation results of Examples 1 to 3 and Comparative Examples 1 to 3.

[0165] [Table 1]

[0166] In Table 1, the measurement results include the coverage of the first internal electrode layer and the second internal electrode layer, the coverage of the intermediate electrode layer, the time to interface peeling, and the time to complete interface peeling. In Table 1, the evaluation results include the interface peeling failure judgment, capacitance judgment, and overall judgment.

[0167] In Table 1, the overall judgment is based on the results of the interface peeling defect judgment and the capacitance judgment. For example, if the results of the interface peeling defect judgment and the capacitance judgment are pass (◯), the overall judgment is pass (◯). If the results of either the interface peeling defect judgment or the capacitance judgment are fail (×), the overall judgment is fail (×).

[0168] In Examples 1 to 3, the interface peeling defect judgment and the capacitance judgment were passed, and the overall judgment was passed. Here, in Examples 1 to 3, the coverage of the first internal electrode layer and the second internal electrode layer was higher than the coverage of the intermediate electrode layer.

[0169] In Comparative Examples 1 to 3, the interface peeling defect judgment or the capacitance judgment was failed, resulting in a fail overall judgment. More specifically, in Comparative Examples 1 and 2, the capacitance judgment was passed but the interface peeling defect judgment was failed, resulting in a fail overall judgment. In Comparative Example 3, the interface peeling defect judgment was passed but the capacitance judgment was failed, resulting in a fail overall judgment.

[0170] In this way, the effects of the present disclosure are expected by making the coverage of the intermediate electrode layer 33 higher than the coverage of the first internal electrode layer 31 and the second internal electrode layer 32. For example, by relatively increasing the coverage of the intermediate electrode layer 33 compared to when the coverage of the intermediate electrode layer 33 is the same as the coverage of the first internal electrode layer 31 and the second internal electrode layer 32, it is expected that the effect of suppressing interfacial peeling will be achieved while improving capacitance. Also, by relatively decreasing the coverage of the first internal electrode layer 31 and the second internal electrode layer 32 compared to when the coverage of the first internal electrode layer 31 and the second internal electrode layer 32 is the same, it is expected that the effect of suppressing interfacial peeling will be achieved while suppressing a decrease in capacitance.

[0171] The coverage of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably less than 85%, more preferably 60% to 80%. The coverage of the intermediate electrode layer is preferably 90% or more, more preferably 95% or more. The coverage of the intermediate electrode layer 33 is preferably 10 percentage points or more higher than the coverage of the first internal electrode layer 31 and the second internal electrode layer 32, more preferably 15 percentage points or more higher.

[0172] The multilayer ceramic capacitor 1 according to the embodiment described above has the following advantages. There are cases where a high withstand voltage is required for the multilayer ceramic capacitor 1. As a multilayer ceramic capacitor 1 that achieves a high withstand voltage, a multilayer ceramic capacitor 1 having a structure in which a plurality of capacitor parts are connected in series, that is, a so-called series structure, is known.

[0173] In the series-structure multilayer ceramic capacitor 1, the formation of series-connected capacitance improves the withstand voltage, but reduces the capacitance accordingly. In order to increase the capacitance, it is necessary to increase the number of laminated internal electrode layers 30, but increasing the number of laminated layers increases the internal stress within the laminate 10, making interfacial peeling more likely to occur.

[0174] More specifically, in the structure of the multilayer ceramic capacitor 1, there is an internal stress caused by the difference in the linear expansion coefficient between the internal electrode layers 30 and the dielectric layers 20, and peeling may occur particularly at the interface between the internal electrode layers 30 and the dielectric layers 20. Furthermore, it is known that the internal stress increases as the number of stacked elements, i.e., the amount of internal electrode layers 30, increases, which becomes an obstacle when increasing the number of layers.

[0175] In particular, multilayer ceramic capacitors 1 in the medium to high voltage range may have a series structure to distribute the voltage applied to one capacitor section (the section that forms the capacitance). However, in order to reduce the voltage applied to one capacitor section while maintaining the capacitance, it is necessary to increase the number of layers in the series according to the number of layers. As a result of increasing the number of layers, the internal stress increases, increasing the risk of interfacial peeling.

[0176] Particular care must be taken to prevent interface peeling at the extraction electrode portion, which is the starting point for the penetration of moisture and plating solution.

[0177] Therefore, by making the coverage of the intermediate electrode layer 33 higher than the coverage of the first internal electrode layer 31 and the coverage of the second internal electrode layer 32, in other words, by making the coverage of the first internal electrode layer 31 and the coverage of the second internal electrode layer 32 lower than the coverage of the intermediate electrode layer 33, it is possible to suppress the occurrence of interfacial peeling while suppressing a decrease in capacitance even in a multilayer ceramic capacitor 1 with high voltage resistance specifications.

[0178] The multilayer ceramic capacitor 1 according to the above-described embodiment includes a laminate 10 including a plurality of laminated dielectric layers 20 and a plurality of laminated internal electrode layers 30, and including a first main surface TS1 and a second main surface TS2 facing in a stacking direction T, a first side surface WS1 and a second side surface WS2 facing in a width direction W perpendicular to the stacking direction T, and a first end face LS1 and a second end face LS2 facing in a length direction L perpendicular to the stacking direction T and the width direction W, a first external electrode 40A arranged on the first end face LS1, and a second external electrode 40B arranged on the second end face LS2, and the plurality of internal electrode layers 30 include a first internal electrode layer 31, a second internal electrode layer 32, and an intermediate electrode layer 33, and one end of the first internal electrode layer 31 is drawn to the first end face LS1 and is connected to the first external electrode 40A. the second internal electrode layer 32 has a second lead portion D2, one end of which is led to the second end face LS2 and connected to the second external electrode 40B, and a second opposing portion EB, which is connected to the second lead portion D2 and faces the internal electrode layer 30 arranged adjacent to the second internal electrode layer 32 in the stacking direction T; the intermediate electrode layer 33 is not connected to either the first external electrode 40A or the second external electrode 40B, and is an internal electrode layer 30 that forms a series-connected capacitor element together with the first internal electrode layer 31 and the second internal electrode layer 32, and the coverage of the intermediate electrode layer 33 is higher than the coverage of the first internal electrode layer 31 and the coverage of the second internal electrode layer 32.

[0179] As a result, even in the multilayer ceramic capacitor 1 with high breakdown voltage specifications, it is possible to suppress the occurrence of interfacial peeling while suppressing a decrease in capacitance.

[0180] In the multilayer ceramic capacitor 1 according to the above embodiment, the coverage of the first internal electrode layers 31 and the coverage of the second internal electrode layers 32 are 60% or more and 80% or less.

[0181] As a result, even in the multilayer ceramic capacitor 1 with high breakdown voltage specifications, it is possible to more effectively prevent the occurrence of interfacial peeling while suppressing a decrease in capacitance.

[0182] In the multilayer ceramic capacitor 1 according to the above embodiment, the coverage of the intermediate electrode layer 33 is 90% or more.

[0183] As a result, even in the multilayer ceramic capacitor 1 with high breakdown voltage specifications, it is possible to increase the capacitance while suppressing the occurrence of interfacial peeling.

[0184] In the multilayer ceramic capacitor 1 according to the above embodiment, the coverage of the intermediate electrode layer 33 is higher than the coverage of the first internal electrode layer 31 and the coverage of the second internal electrode layer 32 by 10 percentage points or more.

[0185] This makes it possible to more effectively prevent the occurrence of interfacial peeling while suppressing a decrease in capacitance even in the multilayer ceramic capacitor 1 with high withstand voltage specifications.

[0186] In the multilayer ceramic capacitor 1 of the second embodiment, the intermediate electrode layer 33 includes a first intermediate electrode layer 331 and a second intermediate electrode layer 332, and the first intermediate electrode layer 331 has a first electrode layer side opposing portion EC1A opposing the first internal electrode layer 31 arranged adjacent to it in the stacking direction T, and a first intermediate electrode layer opposing portion EC1B opposing the second intermediate electrode layer 332 arranged adjacent to it in the stacking direction T, and the second intermediate electrode layer 332 has a second electrode layer side opposing portion EC2A opposing the second internal electrode layer 32 arranged adjacent to it in the stacking direction T, and a second intermediate electrode layer opposing portion EC2B opposing the first intermediate electrode layer 331 arranged adjacent to it in the stacking direction T.

[0187] Even in such a triple-structure multilayer ceramic capacitor 1 with high voltage resistance, it is possible to suppress the occurrence of interfacial peeling while suppressing a decrease in capacitance.

[0188] In the multilayer ceramic capacitor 1 according to the third embodiment, the intermediate electrode layer 33 includes a first intermediate electrode layer 331, a second intermediate electrode layer 332, and a third intermediate electrode layer 333. The first intermediate electrode layer 331 has a first electrode layer side opposing portion EC1A opposing the first internal electrode layer 31 arranged adjacently in the stacking direction T, and a first intermediate electrode layer side opposing portion EC1B opposing the third intermediate electrode layer 333 arranged adjacently in the stacking direction T. The second intermediate electrode layer 333 has a second electrode layer side opposing portion EC2A opposing the second internal electrode layer 32 arranged adjacent to it in the stacking direction T, and a second intermediate electrode layer opposing portion EC2B opposing the third intermediate electrode layer 333 arranged adjacent to it in the stacking direction T, and the third intermediate electrode layer 333 has a third intermediate electrode layer opposing portion EC3A opposing the first intermediate electrode layer 331 arranged adjacent to it in the stacking direction T, and a fourth intermediate electrode layer opposing portion EC3B opposing the second intermediate electrode layer 332 arranged adjacent to it in the stacking direction T.

[0189] Even in such a high-voltage-resistant, four-layer structure multilayer ceramic capacitor 1, it is possible to suppress the occurrence of interfacial peeling while suppressing a decrease in capacitance.

[0190] In the multilayer ceramic capacitor 1 according to this embodiment, the dielectric layers 20 contain a perovskite compound containing at least Ca and Zr.

[0191] As a result, even in the multilayer ceramic capacitor 1 with high voltage resistance specifications, it is possible to improve the heat resistance and high frequency characteristics, suppress the decrease in capacitance, and prevent the occurrence of interfacial peeling.

[0192] The present invention is not limited to the configurations of the above-described embodiments, and can be appropriately modified and applied within the scope of the present invention. Note that the present invention also includes a combination of two or more of the individual desirable configurations described in the above-described embodiments.

[0193] In addition, various modifications and variations are possible, such as those described below. <1> a laminate including a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, the laminate including a first main surface and a second main surface opposing each other in a lamination direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the lamination direction and the width direction; a first external electrode disposed on the first end surface; a second external electrode disposed on the second end surface, the plurality of internal electrode layers include a first internal electrode layer, a second internal electrode layer, and an intermediate electrode layer, the first internal electrode layer has a first lead portion, one end of which is led out to the first end face and connected to the first external electrode, and a first opposing portion, which is connected to the first lead portion and faces the internal electrode layer disposed adjacent to it in the stacking direction; the second internal electrode layer has a second lead portion, one end of which is led out to the second end face and connected to the second external electrode, and a second opposing portion, which is connected to the second lead portion and faces the internal electrode layer disposed adjacent to it in the stacking direction, the intermediate electrode layer is an internal electrode layer that is not connected to either the first external electrode or the second external electrode, and forms a series-connected capacitor element together with the first internal electrode layer and the second internal electrode layer; A multilayer ceramic capacitor, wherein the intermediate electrode layers have a higher coverage than the first internal electrode layers and the second internal electrode layers.

[0194] <2> a coverage of the first internal electrode layer and a coverage of the second internal electrode layer are 60% or more and 80% or less; <1> The multilayer ceramic capacitor according to claim 1.

[0195] <3> The coverage of the intermediate electrode layer is 90% or more. <1> or <2> The multilayer ceramic capacitor according to claim 1.

[0196] <4> the coverage of the intermediate electrode layer is 10 percentage points or more higher than the coverage of the first internal electrode layer and the coverage of the second internal electrode layer; <1> ~ <3> 10. The multilayer ceramic capacitor according to claim 9, wherein

[0197] <5> the intermediate electrode layer includes a first intermediate electrode layer and a second intermediate electrode layer; the first intermediate electrode layer has a first electrode layer side opposing portion opposing the first internal electrode layer arranged adjacent to the first intermediate electrode layer in the stacking direction, and a first intermediate electrode layer opposing portion opposing the second intermediate electrode layer arranged adjacent to the first intermediate electrode layer in the stacking direction, the second intermediate electrode layer has a second electrode layer side opposing portion opposing the second internal electrode layer arranged adjacent to the second intermediate electrode layer in the stacking direction, and a second intermediate electrode layer opposing portion opposing the first intermediate electrode layer arranged adjacent to the second intermediate electrode layer in the stacking direction. <1> ~ <4> 10. The multilayer ceramic capacitor according to claim 9, wherein

[0198] <6> the intermediate electrode layers include a first intermediate electrode layer, a second intermediate electrode layer, and a third intermediate electrode layer; the first intermediate electrode layer has a first electrode layer side opposing portion opposing the first internal electrode layer arranged adjacent to the first intermediate electrode layer in the stacking direction, and a first intermediate electrode layer opposing portion opposing the third intermediate electrode layer arranged adjacent to the first intermediate electrode layer in the stacking direction, the second intermediate electrode layer has a second electrode layer side opposing portion opposing the second internal electrode layer arranged adjacent to the second internal electrode layer in the stacking direction, and a second intermediate electrode layer opposing portion opposing the third intermediate electrode layer arranged adjacent to the second internal electrode layer in the stacking direction, the third intermediate electrode layer has a third intermediate electrode layer facing portion facing the first intermediate electrode layer arranged adjacent to the first intermediate electrode layer in the stacking direction, and a fourth intermediate electrode layer facing portion facing the second intermediate electrode layer arranged adjacent to the first intermediate electrode layer in the stacking direction; <1> (4) The multilayer ceramic capacitor according to any one of (1) to (4). [Explanation of symbols]

[0199] 1. Multilayer ceramic capacitors 10 Laminate 20 dielectric layer 30 Internal electrode layer 31 First internal electrode layer 32 Second internal electrode layer 33 Intermediate electrode layer 40A First outer electrode 40B Second external electrode D1 First drawer D2 Second drawer EA First opposing part EB Second opposing part L lengthwise LS1 First end face LS2 Second end face T Stacking direction TS1 First principal surface TS2 Second principal surface W width direction WS1 First Aspect WS2 Second Aspect

Claims

1. a laminate including a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, the laminate including a first main surface and a second main surface opposing each other in a lamination direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the lamination direction and the width direction; a first external electrode disposed on the first end surface; a second external electrode disposed on the second end surface, the plurality of internal electrode layers include a first internal electrode layer, a second internal electrode layer, and an intermediate electrode layer, the first internal electrode layer has a first lead portion, one end of which is led out to the first end face and connected to the first external electrode, and a first opposing portion, which is connected to the first lead portion and opposed to the internal electrode layer disposed adjacent to it in the stacking direction, the second internal electrode layer has a second lead portion, one end of which is led out to the second end face and connected to the second external electrode, and a second opposing portion, which is connected to the second lead portion and opposed to the internal electrode layer disposed adjacent to it in the stacking direction, the intermediate electrode layer is an internal electrode layer that is not connected to either the first external electrode or the second external electrode, and forms a series-connected capacitor element together with the first internal electrode layer and the second internal electrode layer, A multilayer ceramic capacitor, wherein the coverage of the intermediate electrode layers is higher than the coverage of the first internal electrode layers and the coverage of the second internal electrode layers.

2. 2. The multilayer ceramic capacitor according to claim 1, wherein the coverage of the first internal electrode layers and the coverage of the second internal electrode layers are 60% or more and 80% or less.

3. 3. The multilayer ceramic capacitor according to claim 1, wherein the coverage of the intermediate electrode layer is 90% or more.

4. 3. The multilayer ceramic capacitor according to claim 1, wherein the coverage of the intermediate electrode layers is 10 percentage points or more higher than the coverage of the first internal electrode layers and the coverage of the second internal electrode layers.

5. the intermediate electrode layer includes a first intermediate electrode layer and a second intermediate electrode layer; the first intermediate electrode layer has a first electrode layer side opposing portion opposing the first internal electrode layer arranged adjacent to the first intermediate electrode layer in the stacking direction, and a first intermediate electrode layer opposing portion opposing the second intermediate electrode layer arranged adjacent to the first intermediate electrode layer in the stacking direction, 3. The multilayer ceramic capacitor according to claim 1, wherein the second intermediate electrode layer has a second electrode layer side opposing portion opposing the second internal electrode layer arranged adjacent to the second intermediate electrode layer in the stacking direction, and a second intermediate electrode layer opposing portion opposing the first intermediate electrode layer arranged adjacent to the first intermediate electrode layer in the stacking direction.

6. the intermediate electrode layers include a first intermediate electrode layer, a second intermediate electrode layer, and a third intermediate electrode layer; the first intermediate electrode layer has a first electrode layer side opposing portion opposing the first internal electrode layer arranged adjacent to the first internal electrode layer in the stacking direction, and a first intermediate electrode layer opposing portion opposing the third intermediate electrode layer arranged adjacent to the first internal electrode layer in the stacking direction, the second intermediate electrode layer has a second electrode layer side opposing portion opposing the second internal electrode layer arranged adjacent to the second internal electrode layer in the stacking direction, and a second intermediate electrode layer opposing portion opposing the third intermediate electrode layer arranged adjacent to the second internal electrode layer in the stacking direction, 3. The multilayer ceramic capacitor according to claim 1, wherein the third intermediate electrode layer has a third intermediate electrode layer opposing portion opposing the first intermediate electrode layer arranged adjacent to the stacking direction, and a fourth intermediate electrode layer opposing portion opposing the second intermediate electrode layer arranged adjacent to the stacking direction.

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