Switching control circuit and power source circuit

Abstract

To easily change an operation in a burst mode of a DC-DC converter.SOLUTION: A switching control circuit 40a includes: a comparison circuit 103 that compares each of a first voltage and a second voltage lower than the first voltage with a feedback voltage corresponding to an output voltage; a first adjustment circuit that adjusts a level of the first voltage; and a drive signal output circuit 200 that outputs a drive signal for operating the power source circuit in a normal mode when a state of a load of the power source circuit becomes large, and outputs the drive signal for operating the power source circuit in a burst mode when the state of the load becomes small. The drive signal output circuit enters a first state of outputting the drive signal for gradually increasing an ON period of the first and second transistors when the feedback voltage is higher than the first voltage, and enters a second state of outputting the drive signal for gradually reducing the ON period of the first and second transistors when the feedback voltage is lower than the second voltage.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a switching control circuit and a power supply circuit. [Background technology]

[0002] Current-resonant DC-DC converters generally operate in a normal mode in which the switching element is continuously driven when the load is heavy, and transition to a burst mode when the load becomes light. Some such DC-DC converters transition to multiple states during burst mode (for example, see Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2020 / 17163 [Patent Document 2] Japanese Patent Publication No. 2022-116947 Summary of the Invention [Problem to be solved by the invention]

[0004] Transitions between multiple states in burst mode are generally determined based on a feedback voltage. The feedback voltage varies based on the circuit constants and output voltage of a circuit that generates the feedback voltage in the DC-DC converter. However, it is difficult to change the operation of the DC-DC converter in burst mode by changing the feedback voltage, for example, by changing the circuit constants.

[0005] The present invention has been made in view of the above-mentioned problems of the conventional art, and its object is to provide a switching control circuit that can easily change the operation of a DC-DC converter in burst mode. [Means for solving the problem]

[0006] An aspect of the switching control circuit according to the present invention that solves the above-mentioned problems is a switching control circuit that controls switching of the first and second transistors of a power supply circuit that generates an output voltage of a target level on a secondary side from an input voltage, the power supply circuit including a transformer including a primary coil, a secondary coil, and an auxiliary coil, first and second transistors that control a current in the primary coil, and a resonant circuit that includes the primary coil and a first capacitor, the switching control circuit comprising: a comparator circuit that compares a first voltage and a second voltage that is lower than the first voltage with a feedback voltage according to the output voltage; a first adjustment circuit that adjusts the level of the first voltage; and a drive signal output circuit that outputs a drive signal to operate the power supply circuit in normal mode when the load state of the power supply circuit becomes heavy, and outputs the drive signal to operate the power supply circuit in burst mode when the load state becomes light, wherein the drive signal output circuit enters a first state in which it outputs the drive signal to gradually lengthen the on-periods of the first and second transistors when the feedback voltage becomes higher than the first voltage, and enters a second state in which it outputs the drive signal to gradually shorten the on-periods of the first and second transistors when the feedback voltage becomes lower than the second voltage.

[0007] An aspect of the power supply circuit according to the present invention that solves the above-mentioned problems is a power supply circuit that generates an output voltage of a target level on a secondary side from an input voltage, and includes a transformer including a primary coil, a secondary coil, and an auxiliary coil, first and second transistors that control a current in the primary coil, a resonant circuit that includes the primary coil and a first capacitor, and a switching control circuit that controls switching of the first and second transistors, wherein the switching control circuit includes a comparison circuit that compares a first voltage and a second voltage that is lower than the first voltage with a feedback voltage corresponding to the output voltage, and a first voltage regulator that adjusts the level of the first voltage. and a drive signal output circuit that outputs a drive signal to operate the power supply circuit in a normal mode when the load state of the power supply circuit becomes heavy, and outputs the drive signal to operate the power supply circuit in a burst mode when the load state becomes light, wherein the drive signal output circuit enters a first state in which it outputs the drive signal to gradually lengthen the on-periods of the first and second transistors when the feedback voltage becomes higher than the first voltage, and enters a second state in which it outputs the drive signal to gradually shorten the on-periods of the first and second transistors when the feedback voltage becomes lower than the second voltage. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a switching control circuit that can easily change the operation of a DC-DC converter in burst mode. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a diagram illustrating an example of the configuration of a switching power supply circuit 10. FIG. [Figure 2] FIG. 2 is a diagram illustrating an example of the configuration of a control IC 40a. [Figure 3] 3 is a diagram showing state transitions of the drive signal output circuit 200. FIG. [Figure 4] FIG. 10 is a diagram showing a driving pattern in a "normal mode." [Figure 5] FIG. 10 is a diagram showing a driving method in a "normal mode." [Figure 6] This is a diagram summarizing the drive method in "normal mode." [Figure 7] FIG. 10 is a diagram showing a driving pattern in a "burst mode." [Figure 8] FIG. 10 is a diagram showing the driving method in "State D." [Figure 9] 10 is a diagram showing the relationship between the voltage Vbo, the predetermined number of times N, and the amount of change ΔONW. FIG. [Figure 10] FIG. 10 is a diagram showing the driving method in "State A." [Figure 11] This is a diagram summarizing the drive method in "State A". [Figure 12] FIG. 10 is a diagram showing the relationship between the voltage Vbo and thresholds Thvw_h and Thvw_l. [Figure 13] FIG. 10 is a diagram showing a driving method in "State B." [Figure 14] FIG. 10 is a diagram showing operational waveforms immediately after transition from "normal mode" to "burst mode." [Figure 15] FIG. 10 is a diagram showing a driving pattern during a switching operation period in a "burst mode." [Figure 16A] FIG. 10 is a diagram illustrating the operation of the control IC 40a in the "burst mode." [Figure 16B] FIG. 10 is a diagram illustrating the operation of the control IC 40a in the "burst mode." [Figure 17] FIG. 2 is a diagram illustrating an example of the configuration of a control IC 40b. [Figure 18] FIG. 2 is a diagram illustrating an example of the configuration of a control IC 40c. [Figure 19] FIG. 2 is a diagram illustrating an example of the configuration of a control IC 40d. [Figure 20] FIG. 2 is a diagram illustrating an example of the configuration of a control IC 40e. [Figure 21] FIG. 2 is a diagram illustrating an example of the configuration of a control IC 40f. DETAILED DESCRIPTION OF THE INVENTION

[0010] At least the following matters will become clear from the description of this specification and the accompanying drawings. Preferred embodiments of the present invention will be described below with reference to the drawings. The same or equivalent components, members, etc. shown in each drawing will be designated by the same reference numerals, and duplicate descriptions will be omitted as appropriate. =====This embodiment===== <<<Outline of Switching Power Supply Circuit 10>>> 1 is a diagram showing an example of the configuration of a switching power supply circuit 10 according to one embodiment of the present invention. The switching power supply circuit 10 is an LLC current resonance type power supply circuit that generates an output voltage Vout of a target level to a load 11 from a predetermined input voltage Vin.

[0011] The switching power supply circuit 10 includes capacitors 20, 21, 22, and 32, a resistor 23, NMOS transistors 24 and 25, a transformer 26, a control block 27, diodes 30 and 31, a constant voltage circuit 33, a light emitting diode 34, and resistors 35 and 36.

[0012] Capacitor 20 stabilizes the voltage between the power supply line to which input voltage Vin is applied and the ground line on the ground side, and removes noise, etc. The input voltage Vin is a DC voltage of a predetermined level. Capacitor 21 is a so-called resonant capacitor that forms a resonant circuit with leakage inductance between the primary coil L1 and the secondary coils L2 and L3. Capacitor 21 corresponds to the "first capacitor."

[0013] The capacitor 22 and the resistor 23 constitute a detection circuit that divides and detects the resonant current Icr flowing through the capacitor 21, and the series-connected capacitor 22 and resistor 23 are connected in parallel to the capacitor 21.

[0014] Furthermore, the resistor 23 generates a voltage Vis based on a current obtained by dividing the resonant current Icr. Therefore, the voltage Vis corresponds to the resonant current Icr. When the resonant current Icr flows in the direction of the arrow shown in FIG. 1, the resonant current Icr is referred to as a positive resonant current Icr, and the voltage Vis in this case is a positive voltage. When the resonant current Icr flows in the direction of the arrow, i.e., the resonant current Icr flows through the primary coil L1, the capacitor 22, and the resistor 23 in this order, the direction of the resonant current Icr is positive. When the resonant current Icr flows in the opposite direction to the arrow, i.e., the resonant current Icr flows through the resistor 23, the capacitor 22, and the primary coil L1 in this order, the direction of the resonant current Icr is negative.

[0015] The NMOS transistor 24 is a high-side power transistor, and the NMOS transistor 25 is a low-side power transistor. Specifically, the NMOS transistors 24 and 25 are connected in series between a node to which the input voltage Vin is applied and a node to which the ground voltage is applied. In this embodiment, the NMOS transistors 24 and 25 are used as switching elements, but they may also be PMOS transistors or bipolar transistors, for example. The NMOS transistor 24 corresponds to a "first transistor," and the NMOS transistor 25 corresponds to a "second transistor."

[0016] The transformer 26 includes a primary coil L1, secondary coils L2 and L3, and an auxiliary coil La, and is insulated from the primary coil L1, the secondary coils L2 and L3, and the auxiliary coil La. In the transformer 26, a voltage is generated in the secondary coils L2 and L3 on the secondary side and in the auxiliary coil La in response to a change in voltage across the primary coil L1 on the primary side.

[0017] The primary coil L1 has one end connected to the source of the NMOS transistor 24 and the drain of the NMOS transistor 25, and the other end connected to the source of the NMOS transistor 25 via the capacitor 21.

[0018] Therefore, when switching of the NMOS transistors 24 and 25 starts, there is a change in the voltage of each of the secondary coils L2 and L3 and the auxiliary coil La. The primary coil L1 and the secondary coils L2 and L3 are electromagnetically coupled with opposite polarities, and the primary coil L1 and the auxiliary coil La are electromagnetically coupled with the same polarity.

[0019] The control block 27 is a circuit block for controlling the switching of the NMOS transistors 24 and 25, and will be described in detail later.

[0020] Diodes 30 and 31 rectify the voltages of the secondary coils L2 and L3, and capacitor 32 smoothes the rectified voltage. As a result, a smoothed output voltage Vout is generated in capacitor 32. The output voltage Vout becomes a DC voltage at a target level.

[0021] The constant voltage circuit 33 is a circuit that generates a constant DC voltage, and is configured using, for example, a shunt regulator.

[0022] The light-emitting diode 34 is an element that emits light with an intensity corresponding to the difference between the output voltage Vout and the output of the constant voltage circuit 33, and forms a photocoupler together with a phototransistor 52, which will be described later. In this embodiment, as the level of the output voltage Vout increases, the intensity of the light emitted from the light-emitting diode 34 increases.

[0023] The resistors 35 and 36 form a voltage divider circuit that divides the input voltage Vin, and a voltage Vbo is generated at the connection node of the resistors 35 and 36.

[0024] <<<Control Block 27>>> The control block 27 includes a control IC 40a, a diode 50, capacitors 51, 53, and 54, a phototransistor 52, and resistors 55, 56, 57, and 58. The control IC 40a corresponds to a "switching control circuit."

[0025] The control IC 40a is an integrated circuit that controls the switching of the NMOS transistors 24 and 25, and has terminals VCC, GND, FB, IS, CA, HO, LO, VS, BO, VW, and STB.

[0026] A terminal VCC is a terminal to which a power supply voltage Vcc is applied to operate the control IC 40a. The terminal VCC is connected to the cathode of a diode 50 and a capacitor 51, one end of which is grounded. The capacitor 51 is charged with a voltage from the auxiliary coil La of the transformer 26, and the voltage becomes Vcc. The control IC 40a is started by applying a divided voltage of the input voltage Vin, which is obtained by rectifying an AC input, via a terminal not shown, and after starting up, it operates based on the power supply voltage Vcc.

[0027] The terminal GND is a terminal to which a ground voltage is applied, and is connected to, for example, the housing of a device in which the switching power supply circuit 10 is provided.

[0028] The terminal FB generates a feedback voltage Vfb corresponding to the output voltage Vout, and is connected to a phototransistor 52 and a capacitor 53. The phototransistor 52 passes a bias current I1, whose magnitude corresponds to the intensity of light from the light-emitting diode 34, from the terminal FB to ground, and the capacitor 53 is provided to remove noise between the terminal FB and ground. Therefore, the phototransistor 52 operates as a transistor that generates a sink current.

[0029] Terminal IS is a terminal for detecting the current value of the resonant current of the primary coil L1. Here, a voltage corresponding to the current value of the resonant current of the primary coil L1 is generated at the node where capacitor 22 and resistor 23 are connected. Therefore, a voltage Vis corresponding to the current value of the resonant current of the primary coil L1 is applied to terminal IS.

[0030] The terminal CA is a terminal to which a voltage Vca is applied, which is generated based on the resonant current of the primary coil L1 and corresponds to the input power of the switching power supply circuit 10. A capacitor 54 and a resistor 55 are connected to the terminal CA, as will be described in detail later.

[0031] The terminal HO is a terminal from which the drive voltage Vdr1 for driving the NMOS transistor 24 is output, and the gate of the NMOS transistor 24 is connected.

[0032] The terminal LO is a terminal from which the drive voltage Vdr2 for driving the NMOS transistor 25 is output, and the gate of the NMOS transistor 25 is connected.

[0033] The terminal VS is a terminal to which the voltage of the connection node where the source terminal of the NMOS transistor 24 and the drain terminal of the NMOS transistor 25 are connected is applied. When the NMOS transistor 24 is turned on, the input voltage Vin is applied, and when the NMOS transistor 25 is turned on, the ground voltage is applied.

[0034] Furthermore, the potential of the voltage Vs at the terminal VS becomes the reference potential of the output voltage of a bootstrap circuit (not shown) for turning on the NMOS transistor 24 when the input voltage Vin is applied to the terminal VS.

[0035] The terminal BO is a terminal to which the voltage Vbo generated by the resistors 35 and 36 is applied.

[0036] The terminal VW is a terminal to which Vvw, which is the voltage of the auxiliary coil La divided by resistors 56 and 57, is applied.

[0037] The terminal STB is a terminal for controlling the control circuit 300 (described later) during the manufacturing stage of the control IC 40a. Specifically, the terminal STB and the terminal BO constitute an I2C interface, and a data signal in the I2C interface is input to the terminal STB. Meanwhile, a clock signal in the I2C interface is input to the terminal BO. When the control IC 40a is incorporated into the switching power supply circuit 10, a resistor 58 is connected to the terminal STB. Furthermore, the terminal STB corresponds to a "first terminal," and the resistor 58 corresponds to a "resistor."

[0038] <<<Details of the control IC 40a>>> 2 is a diagram illustrating an example of a control IC 40a. The control IC 40a is an integrated circuit that drives NMOS transistors 24 and 25 based on state transitions that occur in response to voltages applied to each terminal. The control IC 40a includes a resistor 100, selectors 101 and 102, comparators 103 and 109, analog-to-digital conversion circuits (ADCs) 104, 105, and 110, level shift circuits (LSs) 106 and 108, a comparison circuit (CMP) 107, a load detection circuit 111, a digital control circuit 112, and a drive circuit (DRV) 113. Note that the terminals VCC and GND are omitted here for convenience.

[0039] The resistor 100 generates a feedback voltage Vfb based on the bias current I1 from the phototransistor 52. A predetermined voltage Vdd is applied to one end of the resistor 100, and the other end is connected to the terminal FB. Therefore, if the resistance value of the resistor 100 is "R", the feedback voltage Vfb generated at the terminal FB is expressed by equation (1).

[0040] Vfb=Vdd-R×I1 (1) As described above, in this embodiment, the current value of the bias current I1 increases in response to an increase in the output voltage Vout, so that when the output voltage Vout increases, the feedback voltage Vfb decreases.

[0041] The selector 101 adjusts the level of the reference voltage Vref0 to one of the reference voltages Vref120, Vref110, Vref100, and Vref090 output based on a signal Ssel from a digital control circuit 112 (described later). Specifically, when the signal Ssel is "0," the selector 101 adjusts the reference voltage Vref0 to the reference voltage Vref120. Furthermore, when the signal Ssel is "1," "2," or "3," the selector 101 adjusts the reference voltage Vref0 to the reference voltage Vref110, Vref100, or Vref090, respectively. The reference voltage Vref0 is used as the higher reference voltage by a comparator 103 (described later). Moreover, as an example, the reference voltage Vref120 is 1.2 V, the reference voltage Vref110 is 1.1 V, the reference voltage Vref100 is 1.0 V, and the reference voltage Vref090 is 0.9 V. Moreover, the selector 101 corresponds to the "first adjustment circuit."

[0042] The selector 102 applies a reference voltage Vref0 or a reference voltage Vref1 lower than the reference voltage Vref0 to the comparator 103 based on the logic level of the signal Sfb output by the comparator 103. Specifically, when the comparator 103 outputs a low-level (hereinafter referred to as "L" level) signal Sfb, the selector 102 applies the reference voltage Vref0 to the non-inverting input of the comparator 103. On the other hand, when the comparator 103 outputs a high-level (hereinafter referred to as "H" level) signal Sfb, the selector 102 applies the reference voltage Vref1 to the non-inverting input of the comparator 103.

[0043] The comparator 103 is used when the drive signal output circuit 200 (described later) operates in an operation mode (i.e., "burst mode") in which the NMOS transistors 24 and 25 are intermittently driven, and detects whether the feedback voltage Vfb is high. The comparator 103 also compares the feedback voltage Vfb with the reference voltages Vref0 and Vref1.

[0044] Specifically, when the output voltage Vout decreases and the feedback voltage Vfb becomes higher than the reference voltage Vref0, the comparator 103 outputs a signal Sfb at a high level. On the other hand, when the output voltage Vout increases and the feedback voltage Vfb becomes lower than the reference voltage Vref1, the comparator 103 outputs a signal Sfb at a low level. The comparator 103 corresponds to a "comparison circuit," the reference voltage Vref0 corresponds to a "first voltage," and the reference voltage Vref1 corresponds to a "second voltage."

[0045] In this embodiment, the comparator 103 outputs the signal Sfb, but the drive signal output circuit 200 (described later) may generate the signal Sfb based on the feedback voltage Vfb, which is a digital value from the analog-to-digital conversion circuit 104.

[0046] An analog-to-digital converter (ADC) 104 converts the feedback voltage Vfb at the terminal FB into a digital value and outputs it. The feedback voltage Vfb converted into a digital value is used by a drive signal output circuit 200 (described later) to output drive signals ho and lo (described later) in an operation mode (i.e., "normal mode") in which the drive signal output circuit 200 continuously drives at least the NMOS transistors 24 and 25. Note that the analog-to-digital converter 104 stops operating when the drive signal output circuit 200 operates in "burst mode."

[0047] An analog-to-digital converter (ADC) 105 converts the voltage Vbo at the terminal B0 into a digital value and outputs it. The digitally converted voltage Vbo is used by a drive signal output circuit 200 (described later) to output drive signals h0 and l0 (described later) at least during the so-called soft start and soft end.

[0048] The level shift circuit (LS) 106 shifts the level of the voltage Vvw.

[0049] The comparator circuit (CMP) 107 compares the level-shifted voltage Vvw with thresholds Thvw_h and Thvw_l corresponding to the voltage Vbo, and outputs pulse signals LOvwth and HOvwth. Specifically, when the level-shifted voltage Vvw becomes smaller than the threshold Thvw_h, the comparator circuit 107 outputs a pulse signal HOvwth for turning off the NMOS transistor 24. On the other hand, when the level-shifted voltage Vvw becomes larger than the threshold Thvw_l, the comparator circuit 107 outputs a pulse signal LOvwth for turning off the NMOS transistor 25.

[0050] The level shift circuit (LS) 108 shifts the level of the voltage Vis.

[0051] The comparator 109 detects the polarity of the resonant current Icr by comparing the level-shifted voltage Vis with a reference voltage Vref2, and outputs a signal Szero. The reference voltage Vref2 is equal to a voltage obtained by level-shifting the voltage Vis when the resonant current Icr becomes zero. The comparator 109 detects the timing when the resonant current Icr becomes zero, and the timing when the logic level of the signal Szero changes is the timing when the resonant current Icr becomes zero. The comparator 109 corresponds to a "detection circuit," and the signal Szero corresponds to a "detection result."

[0052] An analog-to-digital converter (ADC) 110 converts the voltage Vca at the terminal CA into a digital value and outputs it. The voltage Vca converted into a digital value is used when a drive signal output circuit 200 (described later) switches between a "normal mode" and a "burst mode."

[0053] The load detection circuit 111 detects whether the load 11 is in a light load or heavy load state based on a voltage applied to the terminal IS that corresponds to the power consumption of the load 11 (in other words, a voltage Vis that corresponds to the resonant current flowing through the resonant circuit). Here, the power consumption of the load 11 is greater when the load 11 is in a heavy load state than when it is in a light load state. Therefore, the voltage Vis applied to the terminal IS indicates a voltage that corresponds to the power consumption of the load 11, and so the load detection circuit 111 outputs a voltage Vca that indicates that the load 11 is in a light load state when the voltage Vis is lower than a predetermined value.

[0054] On the other hand, when the voltage Vis is higher than the predetermined value, the load detection circuit 111 outputs a voltage Vca indicating that the load 11 is in a heavy load state. Note that the heavier the load state of the load 11, the higher the voltage Vca becomes.

[0055] Note that "the load 11 is in a heavy load state" refers to, for example, a case where the current value of the load current Iout flowing through the load 11 is equal to or greater than a predetermined value (for example, 1 A). Also, "the load 11 is in a light load state" refers to, for example, a case where the current value of the load current Iout flowing through the load 11 is smaller than a predetermined value (for example, 1 A). Also, "the load 11 is in a no-load state" refers to a case where the current value of the load current Iout flowing through the load 11 is extremely small or 0 (zero) A. Also, although it has been described that the current value of the load current Iout for determining whether the load 11 is in a heavy load state or a light load state is, for example, 1 A, this current value can be set in various ways. Note that the load detection circuit 111 corresponds to a "resonant current amount detection circuit."

[0056] The digital control circuit 112 outputs the drive signals ho and lo and the signal Ssel based on a plurality of signals such as the signal Sfb and digital values. The digital control circuit 112 includes a drive signal output circuit 200 and a setting circuit 201.

[0057] The drive signal output circuit 200, which will be described in detail later, outputs drive signals ho and lo that operate the switching power supply circuit 10 in "burst mode" when the load 11 is in a light load state. On the other hand, the drive signal output circuit 200 outputs drive signals ho and lo that operate the switching power supply circuit 10 in "normal mode" when the load 11 is in a heavy load state.

[0058] The setting circuit 201 receives data indicating the level of the reference voltage Vref0. Specifically, the setting circuit 201 receives the data from an I2C interface that is configured by a clock signal from a terminal BO and a data signal from a terminal STB. The setting circuit 201 includes a control circuit 300 and a memory 301.

[0059] The control circuit 300 outputs a control signal Scnt based on the clock signal from the terminal BO and the data signal from the terminal STB, and writes data to the memory 301. The memory 301 outputs a signal Ssel based on the written data. The selector 101 then adjusts the level of the reference voltage Vref0 based on the signal Ssel. The data corresponds to "first data."

[0060] 1. Specifically, when the drive signal output circuit 200 outputs a drive signal ho of "H" level, the drive circuit 113 outputs the drive voltage Vdr1 that turns on the NMOS transistor 24, and when the drive signal output circuit 200 outputs a drive signal ho of "L" level, the drive circuit 113 outputs the drive voltage Vdr1 that turns off the NMOS transistor 24. Furthermore, when the drive signal output circuit 200 outputs a drive signal ho of "H" level, the drive circuit 113 outputs the drive voltage Vdr2 that turns on the NMOS transistor 25, and when the drive signal output circuit 200 outputs a drive signal ho of "L" level, the drive circuit 113 outputs the drive voltage Vdr2 that turns off the NMOS transistor 25.

[0061] ===State Transition of the Drive Signal Output Circuit 200=== Fig. 3 is a diagram showing state transitions of the drive signal output circuit 200. Note that Fig. 3 is a diagram showing how the states of the drive signal output circuit 200 transition, and how the drive signal output circuit 200 outputs the drive signals ho and lo in each state will be described later. Also, "State A" to "State D" show the states of the drive signal output circuit 200 when the switching power supply circuit 10 operates in "burst mode." First, it is assumed that the control IC 40a operates the switching power supply circuit 10 in "normal mode."

[0062] In "normal mode," when the load 11 is in a light load state, the feedback voltage Vfb becomes lower than the voltage Va, and the voltage Vca remains lower than the threshold value Vca_l for a predetermined period of time Ta, the state of the drive signal output circuit 200 changes from "normal mode" to "State A," which is a state during "burst mode" (process S10). In addition, in this embodiment, the state of the drive signal output circuit 200 is set to "State A" based on the feedback voltage Vfb and the voltage Vca. However, the state of the drive signal output circuit 200 may also be set to "State A" on the condition that the voltage Vca remains lower than the threshold value Vca_l for a predetermined period of time Ta. Note that the voltage Va corresponds to a "fourth voltage," and the magnitude of the resonant current when the voltage Vca becomes the threshold value Vca_l corresponds to a "second predetermined amount."

[0063] "State A," the details of which will be described later, is a state in which the drive signal output circuit 200 outputs drive signals ho and lo based on the voltage Vvw (i.e., performs peak power control). Immediately after the operation of the switching power supply circuit 10 is shifted from "normal mode" to "burst mode," the state of the drive signal output circuit 200 changes from "State A" to "State C" (described later) without passing through "State B" (described later).

[0064] On the other hand, when the switching power supply circuit 10 operates in "burst mode" other than immediately after the switching power supply circuit 10 has started operating in "burst mode", the state of the drive signal output circuit 200 repeatedly changes from "State C" to "State D" (described below), "State A", and then to "State B".

[0065] In this way, by changing the path of the state transition from "State A" to "State D" between immediately after the transition from "Normal Mode" to "State A" and other cases, it is possible to prevent the output voltage Vout from becoming an overvoltage until the state of the drive signal output circuit 200 becomes "State C".

[0066] Returning to FIG. 3, in "State A," immediately after transitioning from "normal mode," if the load 11 state becomes lightly loaded, the output voltage Vout rises, and the feedback voltage Vfb becomes lower than the reference voltage Vref1, the state of the drive signal output circuit 200 changes from "State A" to "State C" without passing through "State B" (described later) (process S20).

[0067] 1 is stopped. Then, in "State C," when the load 11 is in a heavy load state, the output voltage Vout drops, and the feedback voltage Vfb becomes higher than the reference voltage Vref0, which is higher than the reference voltage Vref1, the state of the drive signal output circuit 200 changes from "State C" to "State D" (Process S21). As will be described in detail later, in this embodiment, immediately after the operation of the switching power supply circuit 10 is shifted to "burst mode" to suppress an increase in the output voltage Vout, the state of the drive signal output circuit 200 changes from "State A" to "State C," and the soft end operation is not performed.

[0068] "State D" is a state in which drive signals ho and lo are output (so-called soft start operation) to gradually lengthen the on-period of the NMOS transistors 24 and 25. Then, when the soft start period is completed in "State D", the state of the drive signal output circuit 200 changes from "State D" to "State A" (process S22).

[0069] So far, the operation immediately after transition from "normal mode" to "burst mode" has been explained. On the other hand, after the switching power supply circuit 10 enters "state C" immediately after starting operation in "burst mode", the NMOS transistors 24 and 25 are driven intermittently, and the state of the drive signal output circuit 200 then repeatedly changes from "state A" to "state D."

[0070] Furthermore, if the state of the drive signal output circuit 200 is "State A" other than immediately after transitioning to "burst mode," when the output voltage Vout rises and the feedback voltage Vfb becomes lower than the reference voltage Vref1, the state of the drive signal output circuit 200 changes from "State A" to "State B" (process S23).

[0071] "State B" is a state in which drive signals ho and lo are output (so-called soft end operation) to gradually shorten the on-period of the NMOS transistors 24 and 25. Then, when the soft end period is completed in "State B", the state of the drive signal output circuit 200 changes from "State B" to "State C" (process S24).

[0072] In this way, when the switching power supply circuit 10 continues to operate in "burst mode," the state of the drive signal output circuit 200 repeatedly changes from "State C" to "State D" and "State A" and then to "State B." This makes it possible to suppress audible noise in the transformer 26 in FIG. 1 when driving the NMOS transistors 24 and 25 in FIG. 1 in "burst mode."

[0073] Furthermore, in "State A," if the load 11 becomes a heavy load and the feedback voltage Vfb becomes higher than the voltage Vb, which is higher than the voltage Va, or the voltage Vca becomes higher than the threshold value Vca_h, the state of the drive signal output circuit 200 changes from "State A" in "burst mode" to "normal mode" so that the switching power supply circuit 10 operates in "normal mode" (process S11). Note that the voltage Vb (e.g., 2.5 V) is higher than the voltage Va (e.g., 2.4 V), and the reference voltage Vref0 is lower than the voltage Va. Furthermore, the voltage Vb corresponds to a "third voltage," and the magnitude of the resonant current when the voltage Vca becomes the threshold value Vca_h corresponds to a "first predetermined amount."

[0074] ===Output method of drive signals ho and lo in "normal mode"=== 4 is a diagram showing a drive pattern in "normal mode." When the switching power supply circuit 10 is operated in "normal mode," the drive signal output circuit 200 outputs drive signals ho and lo that continuously drive the NMOS transistors 24 and 25 without intermittently stopping the switching operation, as shown in FIG.

[0075] ===Drive system in "normal mode"=== 5 is a diagram showing a drive method in "normal mode." When the switching power supply circuit 10 is operated in "normal mode," the drive signal output circuit 200 outputs drive signals ho and lo using a drive method known as phase ratio control. Note that "phase ratio control" is a drive method that controls the switching of the NMOS transistors 24 and 25 based on the direction (i.e., polarity) of the resonance current Icr and the feedback voltage Vfb.

[0076] A specific driving method for phase ratio control will be described below with reference to Fig. 5. In Fig. 5, the drive signal output circuit 200 outputs a drive signal lo at a low level, and then outputs a drive signal h0 at a high level after a dead time Td has elapsed, as shown in Fig. 6. Similarly, the drive signal output circuit 200 outputs a drive signal h0 at a low level, and then outputs a drive signal lo at a high level after a dead time Td has elapsed, as shown in Fig. 6. The "dead time" refers to the time during which the NMOS transistors 24 and 25 are simultaneously turned on and both NMOS transistors 24 and 25 are turned off to prevent a through current from flowing between the node to which the input voltage Vin is applied and the node to which the ground voltage is applied.

[0077] At time t0, the drive signal output circuit 200 outputs a drive signal lo at the "L" level. Then, the drive signal output circuit 200 starts measuring the time Tbh from time t0. The drive signal output circuit 200 also acquires the feedback voltage Vfb at time t0. Note that time t0 marks the start of a half cycle.

[0078] At time t1, the resonant current Icr becomes zero, and the comparator 109 in Fig. 2 outputs a signal Szero of "H" level. At this time, the drive signal output circuit 200 finishes measuring the time Tbh and calculates the time Tah until the end of the half cycle based on the previously acquired feedback voltage Vfb and the time Tbh.

[0079] At time t2, which is a time Tah after time t1, the drive signal output circuit 200 outputs a drive signal ho at an "L" level, as shown in Fig. 6. The drive signal output circuit 200 then starts measuring the time Tbl from time t2, and acquires the feedback voltage Vfb at time t2. Note that time t2 marks the start of a half cycle.

[0080] At time t3, the resonant current Icr becomes zero, and the comparator 109 outputs a signal Szero at an "L" level. At this time, the drive signal output circuit 200 finishes measuring the time Tbl and calculates the time Tal until the end of the half cycle based on the previously acquired feedback voltage Vfb and the time Tbl.

[0081] At time t4, when time Tal has elapsed since time t3, the drive signal output circuit 200 outputs a drive signal lo at the "L" level, as shown in Figure 6. Thereafter, the same operation is repeated.

[0082] As described above, the drive signal output circuit 200 calculates the end time of a half cycle based on, for example, the period Tbh measured from the time when the "L" level drive signal lo is output and the feedback voltage Vfb when the "L" level drive signal lo is output. That is, the drive signal output circuit 200 controls, for example, the ratio between the period Tbh and the period Tah (i.e., the phase ratio) using the feedback voltage Vfb. By performing this control using the period Tbh and feedback voltage Vfb, which change depending on the state of the load 11, the drive signal output circuit 200 can maintain the output voltage Vout at a target level while following changes in the state of the load 11.

[0083] ===Output method for drive signals ho and lo in "burst mode"=== Fig. 7 is a diagram showing a drive pattern in "burst mode." When the switching power supply circuit 10 is operated in "burst mode," the drive signal output circuit 200 outputs drive signals ho and lo that drive the NMOS transistors 24 and 25 intermittently (i.e., during the switching operation period) while providing a stop operation period, as shown in Fig. 7. Furthermore, the state of the drive signal output circuit 200 transitions through "State D," "State A," and "State B" in that order during the switching operation period, and then enters "State C," in which the drive of the NMOS transistors 24 and 25 is stopped, during the stop operation period.

[0084] ===Driving method in "State D" during "Burst Mode"=== FIG. 8 is a diagram showing a drive method in "State D." When the switching power supply circuit 10 is operated in "burst mode," if the state of the drive signal output circuit 200 enters "State D," the drive signal output circuit 200 outputs drive signals ho and lo using a drive method known as soft start. Note that "soft start" is an operation of outputting drive signals ho and lo with an on-period that gradually becomes longer according to the amount of change ΔONW every predetermined number of times N (for example, N=2), as shown in the enlarged view of FIG. 8. The soft start operation will be described below with reference to FIG. 8.

[0085] At time t10, the state of the drive signal output circuit 200 changes to "state D." Then, the drive signal output circuit 200 outputs the drive signal lo at "H" level.

[0086] At time t11, when a predetermined on-period has elapsed since time t10, the drive signal output circuit 200 outputs an "L" level drive signal lo. After time t11, the drive signal output circuit 200 outputs the drive signal lo every predetermined number of times N, with the on-period gradually increasing according to the amount of change ΔONW. The drive signal output circuit 200 also outputs a drive signal ho, which has the same on-period as the drive signal lo, alternately with the drive signal lo.

[0087] After time t12, when the drive signal output circuit 200 outputs the drive signal l0 a predetermined number N of times from time t11, the drive signal output circuit 200 increases the on period of the drive signal l0 by a change amount ΔONW every predetermined number N and outputs the drive signal l0.

[0088] Similar operations are repeated from time t12 onward, causing the drive signal output circuit 200 to output drive signals ho and lo whose on-periods gradually become longer during soft start. Furthermore, the predetermined number of times N is set to increase as the voltage Vbo increases, as shown by the solid line in FIG. 9, and the amount of change ΔONW is set to decrease as the voltage Vbo increases, as shown by the dashed line in FIG. 9. As a result, the drive signal output circuit 200 operates to gradually lengthen the on-periods of the drive signals ho and lo as the voltage Vbo indicating the input voltage Vin increases, thereby reducing the effect of the input voltage Vin on the output voltage Vout. Note that "State D" corresponds to the "first state."

[0089] ===Driving method in "State A" during "Burst Mode"=== 10 is a diagram showing a drive method in "State A." When the switching power supply circuit 10 is operated in "burst mode," if the state of the drive signal output circuit 200 becomes "State A," the drive signal output circuit 200 outputs drive signals ho and lo using a drive method known as peak power control. Note that "peak power control" is a drive method that controls the switching of the NMOS transistors 24 and 25 based on the voltage Vvw, the comparison result between high and low thresholds, and the dead time Td.

[0090] A specific driving method for peak power control will be described below with reference to Fig. 10. It is assumed that before time t20, the drive signal output circuit 200 outputs a drive signal h0 at an "L" level and a drive signal l0 at an "H" level.

[0091] At time t20 when the voltage Vvw becomes greater than the threshold value Thvw_l, the comparator circuit 107 outputs a pulse signal LOvwth. When the pulse signal LOvwth is input, the drive signal output circuit 200 outputs a drive signal lo at an "L" level, as shown in FIG.

[0092] At time t21, when the dead time Td has elapsed since time t20, the drive signal output circuit 200 outputs the drive signal ho at "H" level, as shown in FIG.

[0093] At time t22 when the voltage Vvw becomes smaller than the threshold value Thvw_h, the comparator circuit 107 outputs a pulse signal HOvwth. When the pulse signal HOvwth is input, the drive signal output circuit 200 outputs a drive signal ho of the "L" level, as shown in FIG.

[0094] At time t23, when the dead time Td has elapsed since time t22, the drive signal output circuit 200 outputs the drive signal lo at the "H" level, as shown in FIG.

[0095] At time t24 when the voltage Vvw becomes greater than the threshold value Thvw_l, the comparator circuit 107 outputs a pulse signal LOvwth. When the pulse signal LOvwth is input, the drive signal output circuit 200 outputs a drive signal lo at an "L" level, as shown in Fig. 11. Thereafter, the same operation is repeated.

[0096] Furthermore, as shown by the solid line in FIG. 12, the threshold value Thvw_h is set to increase as the voltage Vbo increases. On the other hand, as shown by the dashed line in FIG. 12, the threshold value Thvw_l is set to decrease as the voltage Vbo increases. Therefore, when the voltage Vbo increases, the drive signal output circuit 200 shortens the on-period of the drive signals ho and lo, thereby reducing the influence of the input voltage Vin on the output voltage Vout. Note that "State A" corresponds to the "third state."

[0097] ===Driving method in "State B" during "Burst Mode"=== FIG. 13 is a diagram showing a drive method in "State B." When the switching power supply circuit 10 is operated in "burst mode," if the state of the drive signal output circuit 200 enters "State B," the drive signal output circuit 200 outputs drive signals ho and lo using a drive method known as soft end. Note that "soft end" refers to an operation in which drive signals ho and lo are output with an on-period that gradually shortens according to the amount of change ΔONW every predetermined number of times N (for example, N=2), as shown in the enlarged view of FIG. 13. The soft end operation will be described below with reference to FIG. 13.

[0098] At time t30 when the drive signal output circuit 200 outputs the drive signal ho at the "L" level, the state of the drive signal output circuit 200 becomes "state B."

[0099] At time t31, when the dead time Td has elapsed since time t30, the drive signal output circuit 200 outputs an "H" level drive signal lo. Thereafter, the drive signal output circuit 200 outputs the drive signal lo every predetermined number of times N (for example, twice), with an on-period that gradually shortens according to the amount of change ΔONW. The drive signal output circuit 200 also outputs a drive signal ho, which has the same on-period as the drive signal lo, alternately with the drive signal lo.

[0100] As a result, during the soft end, the drive signal output circuit 200 outputs drive signals ho and lo whose on-periods gradually shorten. Similar to the soft start, the predetermined number of times N is set to increase as the voltage Vbo increases, as shown by the solid line in FIG. 9, and the amount of change ΔONW is set to decrease as the voltage Vbo increases, as shown by the dashed line in FIG. 9. As a result, the drive signal output circuit 200 operates to gradually shorten the on-periods of the drive signals ho and lo as the voltage Vbo indicating the input voltage Vin increases, thereby reducing the effect of the input voltage Vin on the output voltage Vout. Note that "State B" corresponds to the "second state."

[0101] ===Operation immediately after transition from "Normal Mode" to "Burst Mode"=== FIG. 14 is a diagram showing the operating waveforms immediately after the transition from the "normal mode" to the "burst mode."

[0102] When the load 11 becomes lightly loaded, the feedback voltage Vfb becomes lower than the voltage Va, and the voltage Vca remains lower than the threshold value Vca_l, and a predetermined period of time Ta has elapsed, at time t40, the state of the drive signal output circuit 200 changes from "normal mode" to "state A" in "burst mode."

[0103] At time t41, when the output voltage Vout rises and the feedback voltage Vfb becomes lower than the reference voltage Vref1, the comparator 103 outputs a low-level signal Sfb. The drive signal output circuit 200, to which the low-level signal Sfb has been input, enters state C. As a result, the drive signal output circuit 200 outputs drive signals ho and lo, each having a predetermined on-period, and then stops driving the NMOS transistors 24 and 25 as a final process.

[0104] Therefore, after the output voltage Vout rises to a certain extent and the feedback voltage Vfb falls below the reference voltage Vref1, the drive signal output circuit 200 stops driving the NMOS transistors 24 and 25. As a result, the drive signal output circuit 200 does not perform a soft end, and can therefore prevent the output voltage Vout from becoming an overvoltage.

[0105] ===Driving pattern during switching operation in "burst mode"=== FIG. 15 is a diagram showing a driving pattern during a switching operation period in the "burst mode."

[0106] At time t50, when the output voltage Vout decreases, the feedback voltage Vfb exceeds the reference voltage Vref0, and the comparator 103 outputs the "H" level signal Sfb, the state of the drive signal output circuit 200 enters "State D." Therefore, the drive signal output circuit 200 initiates a soft start, outputs the drive signal l0, and then outputs the drive signal h0. The drive signal output circuit 200 also gradually lengthens the on-period of the NMOS transistors 24 and 25. However, until time t51, the inactive switching period occurs, and the output current lout does not flow to the secondary side of the transformer 26.

[0107] At time t52 when the soft start is completed, the state of the drive signal output circuit 200 becomes "State A." Therefore, the drive signal output circuit 200 performs peak power control and outputs the drive signals ho and lo in accordance with the timing determined by the voltage Vvw. Furthermore, time t52 is determined based on the timing at which the on-period used in "State A" becomes shorter than the on-period used in "State D."

[0108] At time t53 when the output voltage Vout rises, the feedback voltage Vfb falls below the reference voltage Vref1, and the comparator 103 outputs the "L" level signal Sfb, the state of the drive signal output circuit 200 enters "State B." Therefore, the drive signal output circuit 200 starts a soft end and outputs drive signals ho and lo that become gradually shorter.

[0109] As in the case of soft start, when the ON period of the drive signals ho and lo becomes shorter, for example, after time t54, an ineffective switching period occurs and the output current Iout does not flow to the secondary side of the transformer 26.

[0110] Then, when the soft end is completed, the state of the drive signal output circuit 200 becomes "State C," and the drive signal output circuit 200 stops driving the NMOS transistors 24 and 25. Furthermore, after time t53, when the on-period used in "State B" becomes shorter than the on-period used in "State A," the NMOS transistors 24 and 25 are driven by the drive signals ho and lo based on the soft end. However, when the feedback voltage Vfb becomes lower than the reference voltage Vref1, the on-period of "State B" often becomes shorter than the on-period of "State A," so the transition from "State A" to "State B" at time t53 was described above.

[0111] ===Operation of control IC40a based on feedback voltage Vfb during "burst mode"=== FIG. 16A is a diagram showing the operation of the control IC 40a in the "burst mode."

[0112] At time t60, when the feedback voltage Vfb rises and becomes higher than the reference voltage Vref0 due to a drop in the output voltage Vout, the control IC 40a starts driving the NMOS transistors 24 and 25. As the NMOS transistors 24 and 25 are driven, the output voltage Vout, which had been falling, begins to rise, and as a result, the feedback voltage Vfb rises and then falls.

[0113] At time t61, when the output voltage Vout rises and the feedback voltage Vfb drops to become lower than the reference voltage Vref1, the control IC 40a stops the peak power control and enters the soft end.

[0114] At time t62, when the soft end is complete and the switching operation period P1 has elapsed since time t60, the control IC 40a stops driving the NMOS transistors 24 and 25. Thereafter, if the feedback voltage Vfb is lower than the reference voltage Vref0, the control IC 40a stops driving the NMOS transistors 24 and 25. This period is referred to as the stop operation period P2. The combined period of the switching operation period P1 and the stop operation period P2 is referred to as the burst period T1. Similar operations are then repeated from time t63 onward.

[0115] Figure 16B shows the operation of control IC 40a in "burst mode." Note that reference voltage Vref0 in Figure 16B is higher than reference voltage Vref0 in Figure 16A, but lower than voltages Va (e.g., 2.4V) and Vb (e.g., 2.5V) used in the transition between "normal mode" and "burst mode." Also, the operation of control IC 40a from t70 to t72 is similar to the operation from times t60 to t62 in Figure 16A, and similar operations are repeated from time t73 onwards.

[0116] 16B, both reference voltages Vref0 are higher than those in FIG. 16A, and the switching operation period P3 during which the control IC 40a drives the NMOS transistors 24 and 25 is shorter than the switching operation period P1. This makes it difficult for the switching power supply circuit 10 to sufficiently increase the output voltage Vout. Consequently, the output voltage Vout drops again within a short period of time, resulting in a quiescent operation period P4 that is shorter than the quiescent operation period P2. Therefore, the burst period P4 is also shorter than the burst period T2.

[0117] Furthermore, conventionally, in order to adjust the operation of the control IC 40a in "burst mode" like this, it was necessary to adjust the circuit constants of the elements for generating the feedback voltage Vfb included in the switching power supply circuit 10. However, in reality, the circuit constants of external components vary and the circuit configuration is complex, making it difficult to adjust the generation of the feedback voltage Vfb by adjusting the circuit constants.

[0118] On the other hand, if the level of the reference voltage Vref0 is adjusted to one of a predetermined number of voltage levels as in this embodiment, the operation of the control IC 40a in "burst mode" can be easily adjusted without adjusting the generation of the feedback voltage Vfb as described above.

[0119] === Variations === 17 is a diagram illustrating an example of a control IC 40b. Similar to the control IC 40a, the control IC 40b is an integrated circuit that drives NMOS transistors 24 and 25 based on state transitions that occur in response to voltages applied to their respective terminals. The control IC 40b includes a resistor 100, selectors 101 and 102, comparators 103 and 109, analog-to-digital converters (ADCs) 104, 105, 110, and 116, level shift circuits (LSs) 106 and 108, a comparison circuit (CMP) 107, a load detection circuit 111, a digital control circuit 114, a drive circuit (DRV) 113, and a constant current source 115. Note that the terminals VCC and GND are omitted here for convenience.

[0120] The digital control circuit 114 outputs the drive signals ho and lo and the signal Ssel based on a plurality of signals such as the signal Sfb and digital values. The digital control circuit 114 includes a drive signal output circuit 200 and a state setting circuit 202.

[0121] The state setting circuit 202, the details of which will be described later, outputs a signal Ssel based on a voltage Vstb generated at a terminal STB.

[0122] The constant current source 115 supplies a predetermined current I2 to the resistor 58 (see FIG. 1) connected to the terminal STB. The voltage Vstb generated at the terminal STB varies depending on the resistance value of the resistor 58, and the state setting circuit 202 outputs the signal Ssel based on the level of the voltage Vstb. Therefore, the selector 101 adjusts the level of the reference voltage Vref0 based on the voltage Vstb. The constant current source 115 corresponds to a "constant current circuit."

[0123] An analog-to-digital converter (ADC) 116 converts the voltage Vstb at the terminal STB into a digital value and outputs it. The voltage Vstb converted into a digital value is used by the state setting circuit 202 to output the signal Ssel.

[0124] ===Other variations=== Furthermore, the control IC 40a in FIG. 2 and the control IC 40b in FIG. 17 use the selector 101, but as shown in FIG. 18, a selector 117 may be added to adjust both the reference voltages Vref0 and Vref1 to a plurality of predetermined voltage levels.

[0125] The selector 117 adjusts the level of the reference voltage Vref1 to one of the reference voltages Vref090, Vref080, Vref070, and Vref060 output based on the signal Ssel from the digital control circuit 112. Specifically, when the signal Ssel is "0," the selector 117 adjusts the reference voltage Vref1 to the reference voltage Vref090. When the signal Ssel is "1," "2," or "3," the selector 117 adjusts the reference voltage Vref1 to one of the reference voltages Vref080, Vref070, or Vref060. The reference voltage Vref1 is used by the comparator 103 as the lower reference voltage. For example, the reference voltage Vref090 is 0.9 V, the reference voltage Vref080 is 0.8 V, the reference voltage Vref070 is 0.7 V, and the reference voltage Vref060 is 0.6 V. The selector 117 corresponds to the "second adjustment circuit."

[0126] In the control IC 40c of FIG. 18, the selectors 101 and 117 adjust the reference voltages Vref0 and Vref1 based on the same signal Ssel. On the other hand, as shown in FIG. 19, the selectors 101 and 117 may adjust the reference voltages Vref0 and Vref1 using two different signals Ssel0 and Ssel1, respectively. In this case, the setting circuit 203 receives data indicating the level of the reference voltage Vref1, and the selector 117 adjusts the level of the reference voltage Vref1 based on the data indicating the level of the reference voltage Vref1. The data indicating the level of the reference voltage Vref1 corresponds to "second data."

[0127] 20, when a state setting circuit 202 is used, the state setting circuit 202 outputs the signal Ssel based on the voltage Vstb. Also, when a state setting circuit 204 is used, the state setting circuit 204 outputs the signals Ssel0 and Ssel1 based on the voltage Vstb.

[0128] Furthermore, in this embodiment, the switching power supply circuit 10 is operated in "burst mode" under the conditions of voltage Vca and feedback voltage Vfb, but the switching power supply circuit 10 may also be operated in "burst mode" under the condition of only feedback voltage Vfb. Specifically, the drive signal output circuit 200 may be configured to output drive signals ho and lo that cause the switching power supply circuit 10 to operate in "burst mode" when the feedback voltage Vfb becomes voltage Va. Even with such a configuration, the same effects as those of this embodiment can be obtained.

[0129] ===Summary=== The above describes the switching power supply circuit 10 of this embodiment. The control IC 40a includes a selector 101 and a drive signal output circuit 200. The feedback voltage Vfb is compared with the reference voltage Vref0 and reference voltage Vref1 from the selector 101 to determine the operation of the switching power supply circuit 10 when it operates in "burst mode." At this time, the reference voltage Vref0 is adjusted to a plurality of predetermined levels, which makes it easy to adjust the operation in "burst mode," as shown in FIGS. 16A and 16B. This makes it possible to provide a switching control circuit that can easily change the operation of the DC-DC converter in burst mode.

[0130] Furthermore, when the feedback voltage Vfb reaches voltage Vb, the drive signal output circuit 200 outputs drive signals ho and lo that cause the switching power supply circuit 10 to operate in "normal mode." On the other hand, when the feedback voltage Vfb reaches voltage Va, the drive signal output circuit 200 outputs drive signals ho and lo that cause the switching power supply circuit 10 to operate in "burst mode." Furthermore, the reference voltage Vref0 is lower than voltage Va. This allows the switching power supply circuit 10 to operate in "burst mode" when the output voltage Vout is high.

[0131] The control IC 40a also includes a load detection circuit 111, and the drive signal output circuit 200 outputs drive signals ho and lo that cause the switching power supply circuit 10 to operate in "normal mode" when the voltage Vca becomes higher than the voltage Vca_h. On the other hand, the drive signal output circuit 200 outputs drive signals ho and lo that cause the switching power supply circuit 10 to operate in "burst mode" when the voltage Vca becomes lower than the voltage Vca_l and the feedback voltage Vfb becomes the voltage Va. This allows the switching power supply circuit 10 to transition to either the "normal mode" or the "burst mode" more appropriately.

[0132] Furthermore, when the switching power supply circuit 10 operates in the burst mode, the drive signal output circuit 200 is in the state D and the state B. This suppresses audible noise from the transformer 26 when the NMOS transistors 24 and 25 are intermittently driven.

[0133] Furthermore, when the switching power supply circuit 10 operates in "burst mode," the state of the drive signal output circuit 200 transitions from "State A" to "State D." Then, during the switching operation period, the state of the drive signal output circuit transitions in the order of "State D," "State A," and "State B." At this time, the timing at which the state of the drive signal output circuit 200 transitions from "State D" (soft start) to "State A" (peak power control) is the timing at which the on-period in "State A" becomes shorter than the on-period in "State D." This ensures continuity of operation, contributes to preventing audible noise, and improves the system stability of the switching power supply circuit 10.

[0134] Furthermore, when the switching power supply circuit 10 operates in "burst mode", the drive signal output circuit 200 controls the switching of the NMOS transistors 24, 25 so as to have a "switching operation period" in which the state changes from "state D" to "state B" via "state A" and a "stop operation period" in which the NMOS transistors 24, 25 are not switched. This allows the control IC 40a to output appropriate drive signals ho, lo according to the state of the load 11.

[0135] Furthermore, the "suspended operation period" is the period included between the completion of "State B" and the start of "State D." This reduces the power consumption of the switching power supply circuit 10 when the output voltage Vout is high and it is not necessary to send much power to the secondary side of the switching power supply circuit 10.

[0136] Furthermore, the timing at which the state of the drive signal output circuit 200 transitions from "State A" (peak power control) to "State B" (soft end) is the timing at which the on-period in "State B" becomes shorter than the on-period in "State A." This ensures continuity of operation, contributes to preventing noise and improving the system stability of the switching power supply circuit 10.

[0137] The control IC 40a also includes a setting circuit 201. The selector 101 adjusts the level of the reference voltage Vref0 based on data received by the setting circuit 201. This allows the reference voltage Vref0 to be adjusted at the manufacturing stage, making it easier to manufacture the switching power supply circuit 10.

[0138] The control IC 40d also includes a selector 117. This allows the level of the reference voltage Vref1 to be adjusted, making it easier to change the operation of the switching power supply circuit 10 in the "burst mode".

[0139] Furthermore, the setting circuit 201 receives data indicating the level of the reference voltage Vref1. The selector 117 then adjusts the level of the reference voltage Vref1 based on the data indicating the level of the reference voltage Vref1. This allows the reference voltage Vref1 to be adjusted during the manufacturing stage, making it easier to manufacture the switching power supply circuit 10.

[0140] Furthermore, the control IC 40b is an integrated circuit including a terminal STB and a constant current source 115, and the selector 101 adjusts the level of the reference voltage Vref0 based on the voltage of a resistor 58 connected to the terminal STB. This makes it easier to change the operation of the control IC 40b in the "burst mode" when designing the switching power supply circuit 10.

[0141] Furthermore, the control IC 40a includes a comparator 109, and the drive signal output circuit 200 outputs drive signals ho and lo based on the signal Szero from the comparator 109 and the feedback voltage Vfb when the switching power supply circuit 10 operates in "normal mode." This allows the control IC 40a to switch the NMOS transistors 24 and 25 using "phase ratio control."

[0142] The above-described embodiments are intended to facilitate understanding of the present invention and are not intended to limit the present invention. Furthermore, the present invention may be modified or improved without departing from the spirit thereof, and the present invention includes equivalents thereof. [Explanation of symbols]

[0143] 10 Switching power supply circuit 11 Load 20, 21, 22, 32, 51, 53, 54 capacitors 23,35,36,55,56,57,100 Resistance 24,25 NMOS transistor 26 Transformer 27 Control Blocks 30, 31, 50 Diodes 33 Constant voltage circuit 34 Light-emitting diode 40a, 40b, 40c, 40d, 40e, 40f Control IC 52 Phototransistor 101,102,117 selectors 103,109 Comparator 104, 105, 110, 116 Analog-to-digital conversion circuit 106,108 Level shift circuit 107 Comparison circuit 111 Load detection circuit 113 Drive circuit 112, 114, 118, 119 Digital control circuit 115 Constant current source 200 Drive signal output circuit 201,203 Setting circuit 202, 204 Status setting circuit 300 Control circuit 301 Memory

Claims

1. A switching control circuit for controlling switching of the first and second transistors of a power supply circuit that generates an output voltage of a target level on a secondary side from an input voltage, the power supply circuit including: a transformer including a primary coil, a secondary coil, and an auxiliary coil; first and second transistors that control a current in the primary coil; and a resonant circuit that includes the primary coil and a first capacitor, a comparison circuit that compares a first voltage, a second voltage lower than the first voltage, and a feedback voltage according to the output voltage; a first adjusting circuit for adjusting the level of the first voltage; a drive signal output circuit that outputs a drive signal for operating the power supply circuit in a normal mode when the load state of the power supply circuit becomes heavy, and outputs the drive signal for operating the power supply circuit in a burst mode when the load state of the power supply circuit becomes light; Equipped with The drive signal output circuit When the feedback voltage becomes higher than the first voltage, a first state is entered in which the drive signal for gradually lengthening the on-periods of the first and second transistors is output, and when the feedback voltage becomes lower than the second voltage, a second state is entered in which the drive signal for gradually shortening the on-periods of the first and second transistors is output. Switching control circuit.

2. 2. The switching control circuit according to claim 1, The drive signal output circuit When the feedback voltage reaches a third voltage, the drive signal for operating the power supply circuit in the normal mode is output, and when the feedback voltage reaches a fourth voltage lower than the third voltage, the drive signal for operating the power supply circuit in the burst mode is output; the first voltage is lower than the fourth voltage; Switching control circuit.

3. 3. The switching control circuit according to claim 2, a resonance current amount detection circuit for detecting the magnitude of a resonance current flowing through the resonance circuit; When the resonance current amount detection circuit detects that the magnitude of the resonance current is a first predetermined amount, the drive signal output circuit outputs the drive signal that causes the power supply circuit to operate in the normal mode; When the resonance current amount detection circuit detects that the magnitude of the resonance current is a second predetermined amount and the feedback voltage becomes the fourth voltage, the drive signal output circuit outputs the drive signal that causes the power supply circuit to operate in the burst mode. Switching control circuit.

4. 2. The switching control circuit according to claim 1, The drive signal output circuit When the power supply circuit operates in the burst mode, the first and second states are established. Switching control circuit.

5. 2. The switching control circuit according to claim 1, As a state of the drive signal output circuit, a third state between the first state and the second state in which the drive signal is output, the on-period of the first and second transistors being in accordance with the voltage of the auxiliary coil; The drive signal output circuit When the on-period of the first and second transistors determined according to the voltage of the auxiliary coil becomes shorter than the on-period of the first and second transistors in the first state, the first state transitions to the third state. Switching control circuit.

6. 6. The switching control circuit according to claim 5, The drive signal output circuit controlling switching of the first and second transistors so as to have a switching operation period during which the first state is changed to the second state via the third state when the power supply circuit operates in the burst mode, and a stop operation period during which the first and second transistors are not switched; Switching control circuit.

7. 7. A switching control circuit according to claim 6, The stop operation period is a period included between the completion of the second state and the start of the first state. Switching control circuit.

8. 6. The switching control circuit according to claim 5, The drive signal output circuit When the on-period of the first and second transistors in the second state becomes shorter than the on-period of the first and second transistors determined in accordance with the voltage of the auxiliary coil, the third state transitions to the second state. Switching control circuit.

9. 2. The switching control circuit according to claim 1, a setting circuit configured to receive first data indicating a level of the first voltage; The first adjustment circuit adjusting the level of the first voltage based on the first data; Switching control circuit.

10. 10. The switching control circuit of claim 9, a second adjusting circuit for adjusting the level of the second voltage; Switching control circuit.

11. 11. The switching control circuit of claim 10, The setting circuit receiving second data indicative of a level of the second voltage; The second adjustment circuit adjusting the level of the second voltage based on the second data; Switching control circuit.

12. 2. The switching control circuit according to claim 1, a first terminal to which a resistor is connected; a constant current circuit that supplies a predetermined current to the resistor; an integrated circuit comprising: The first adjustment circuit adjusting the level of the first voltage based on the voltage across the resistor; Switching control circuit.

13. 13. The switching control circuit of claim 12, a second adjusting circuit for adjusting the level of the second voltage; Switching control circuit.

14. 14. The switching control circuit of claim 13, The second adjustment circuit adjusting the level of the second voltage based on the voltage across the resistor; Switching control circuit.

15. The switching control circuit according to any one of claims 1 to 14, a detection circuit for detecting the polarity of a resonant current flowing through the resonant circuit; The drive signal output circuit When the power supply circuit is operating in the normal mode, the drive signal is output based on the detection result of the detection circuit and the feedback voltage. Switching control circuit.

16. A power supply circuit that generates an output voltage of a target level on a secondary side from an input voltage, a transformer including a primary coil, a secondary coil, and an auxiliary coil; first and second transistors for controlling the current in the primary coil; a resonant circuit including the primary coil and a first capacitor; a switching control circuit for controlling switching of the first and second transistors; Equipped with The switching control circuit a comparison circuit that compares a first voltage, a second voltage lower than the first voltage, and a feedback voltage according to the output voltage; a first adjusting circuit for adjusting the level of the first voltage; a drive signal output circuit that outputs a drive signal for operating the power supply circuit in a normal mode when the load state of the power supply circuit becomes heavy, and outputs the drive signal for operating the power supply circuit in a burst mode when the load state of the power supply circuit becomes light; Including, The drive signal output circuit When the feedback voltage becomes higher than the first voltage, a first state is entered in which the drive signal for gradually lengthening the on-periods of the first and second transistors is output, and when the feedback voltage becomes lower than the second voltage, a second state is entered in which the drive signal for gradually shortening the on-periods of the first and second transistors is output. power circuit.

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