Semiconductor device

Abstract

To provide a semiconductor device with which surge current resistance can be improved by arranging a diode region without being restricted by the shape of a lead frame.SOLUTION: A semiconductor device 1A includes: a semiconductor element 100 having a diode region 103 and a transistor region 102 which are continuous and adjacent to each other between an obverse-surface electrode and a reverse-surface electrode; a lead frame 108 which is joined to the obverse-surface electrode in a junction region on the obverse-surface-electrode side; and a joining member 106 which is provided so as to cover the diode region 103, the joining member joining the obverse-surface electrode and the lead frame 108. In plan view, the region in which the diode region 103 and the joining region of the lead frame 108 overlap is smaller than the diode region 103.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] A reverse conducting IGBT (hereafter referred to as RC-IGBT), which incorporates an insulated gate bipolar transistor (IGBT) and a diode on the same chip, has the advantages of reducing chip size by sharing the termination area between the IGBT chip and the diode chip, and reducing thermal resistance because losses generated in the transistor area (also called the IGBT area) or diode area can be dissipated across the entire chip. There is also a technology for forming electrical wiring by connecting a lead frame to the surface electrodes of a power semiconductor chip with a bonding material. This technology allows for a larger cross-sectional area of ​​the wiring compared to conventional electrical wiring formed by wire bonding, making it possible to handle higher current densities. However, there is a problem of thermal breakdown due to surge currents such as inrush currents when the power is turned on. For example, Patent Document 1 describes a reverse conducting semiconductor device in which the entire area of ​​the diode section of an RC-IGBT is covered with a flat portion of a wiring member. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-201159 Summary of the Invention [Problem to be solved by the invention]

[0004] In the reverse conducting semiconductor device of Cited Document 1, the increase in heat capacity due to the flat plate portion of the wiring member contributes to improving the surge current resistance of the diode portion, so the entire area of ​​the diode portion needs to be covered by the flat plate portion. Therefore, the arrangement of the diode portion within the chip is restricted by the shape of the flat plate portion. However, in general, in an RC-IGBT, it is desirable from the viewpoint of thermal resistance that the IGBT region and the diode region are uniformly distributed within the chip. The present invention has been made to solve the above problems, and has as its object to provide a semiconductor device in which a diode region is arranged without being restricted by the shape of a lead frame, thereby improving surge current resistance. [Means for solving the problem]

[0005] In order to solve this problem, the semiconductor device of the present invention comprises a semiconductor element having a diode region and a transistor region that are continuous and adjacent to each other between a front electrode and a back electrode, a lead frame that is joined to the front electrode at a joining region on the front electrode side, and a joining member that is arranged to cover the diode region and joins the front electrode and the lead frame, and in a planar view, the area where the diode region and the joining region of the lead frame overlap is smaller than the diode region. [Effects of the Invention]

[0006] According to the present invention, it is possible to provide a semiconductor device in which a diode region is arranged without being restricted by the shape of a lead frame, thereby improving surge current resistance. [Brief explanation of the drawings]

[0007] [Figure 1A] 1 is a plan view illustrating an outline of a semiconductor device according to a first embodiment. [Figure 1B] FIG. 1B is a plan view seen through the lead frame in FIG. 1A. [Figure 1C] FIG. 1C is an enlarged view of a portion of FIG. 1B. [Figure 2] FIG. 1B is a cross-sectional view taken along line II-II in FIG. 1A. [Figure 3A] FIG. 10 is a plan view illustrating an outline of a state in which a semiconductor device according to a first modification is arranged on a wiring substrate. [Figure 3B] FIG. 10 is a plan view illustrating an outline of a semiconductor device according to a first modified example, seen through a lead frame. [Figure 4A] FIG. 3B is a side view in the IVA direction of FIG. 3A. [Figure 4B] FIG. 3B is a side view of FIG. 3A in the direction IVB. [Figure 5A] FIG. 10 is a plan view illustrating an outline of a semiconductor device according to a second modification. [Figure 5B] FIG. 5B is a plan view seen through the lead frame in FIG. 5A. [Figure 6A] FIG. 10 is a plan view illustrating an outline of a semiconductor device according to a third modification. [Figure 6B] FIG. 6B is a plan view seen through the lead frame in FIG. 6A. [Figure 7A] FIG. 10 is a plan view illustrating an outline of a semiconductor device according to a fourth modification. [Figure 7B] FIG. 7B is a cross-sectional view taken along line VIIB-VIIB in FIG. 7A. [Figure 7C] 7B is an enlarged plan view of a part of FIG. 7A, showing the lead frame. FIG. [Figure 8A] FIG. 10 is a plan view illustrating an outline of a semiconductor device according to a second embodiment. [Figure 8B] FIG. 8B is a plan view seen through the lead frame in FIG. 8A. [Figure 8C] FIG. 8B is a side view in the IIIVC direction of FIG. 8A. [Figure 9A] FIG. 10 is a plan view illustrating an outline of a semiconductor device according to a third embodiment. [Figure 9B] FIG. 9B is a plan view seen through the lead frame in FIG. 9A. DETAILED DESCRIPTION OF THE INVENTION

[0008] Embodiments and modifications of the present invention will be described with reference to the drawings. Note that the present invention is not limited to these embodiments and modifications. In addition, in the drawings, some components may be omitted, and the size, shape, and positional relationship of each component may be exaggerated. Expressions such as upper surface and lower surface are examples of relative positional relationships, and do not limit the direction when used.

[0009] [First embodiment] A semiconductor device 1A according to a first embodiment will be described with reference to Figures 1A to 2. The semiconductor device 1A is a device that constitutes a part of a power semiconductor module. As illustrated in Figures 1A and 1B, semiconductor device 1A includes a semiconductor element 100, a lead frame 108A which is a wiring member, and a joining member 106 which joins lead frame 108A to semiconductor element 100. Note that Figure 1B is a plan view seen through lead frame 108A. Figures 3B, 5B, 6B, 8B, and 9B are also plan views seen through the lead frame. Each component of semiconductor device 1A will be described below.

[0010] (semiconductor element) The semiconductor element 100 is a semiconductor chip on which transistors, diodes, etc. are formed. As an example, the semiconductor element 100 is an RC-IGBT. As illustrated in Fig. 2, the semiconductor element 100 has a diode region 103 and a transistor region 102 that are adjacent to each other and are continuous between a front electrode 113 and a back electrode 115. The front surface electrode 113 is an electrode provided on the front surface of the semiconductor element, and the back surface electrode 115 is an electrode provided on the back surface of the semiconductor element. The front surface electrode 113 is provided so as to cover the entire area of ​​the semiconductor element 100 excluding the termination region 101, which is the peripheral portion of the semiconductor element. The back surface electrode 115 is provided so as to face the front surface electrode 113. No diode region or transistor region is arranged in the termination region 101, and dummy wiring 117 and the like may be provided therein. A protective layer 119 is provided in the termination region 101. In the following description, the surface bonded to the lead frame of the semiconductor element is referred to as the front surface, and the surface bonded to the wiring board described below is referred to as the back surface.

[0011] The diode region 103 is a region that continues between the front electrode 113 and the back electrode 115, and functions as a diode with one of the front electrode 113 and the back electrode 115 as an anode electrode and the other as a cathode electrode. The transistor region 102 is a region that continues between the front electrode 113 and the back electrode 115, and functions as a transistor, in this case an IGBT, with one of the front electrode 113 and the back electrode 115 as an emitter electrode and the other as a collector electrode.

[0012] The diode region 103 and the transistor region 102 share a common electrode, and current during operation flows in the thickness direction of the semiconductor element 100. The diode region 103 and the transistor region 102 are arranged adjacent to each other and alternately in the semiconductor element 100 in a repeated manner. As shown in Fig. 1B, the diode regions 103 are arranged in stripes that extend parallel to each other in a plan view. The stripes allow the diode regions to be arranged efficiently. Incidentally, the stripes in the example of Fig. 1B are shown to be composed of seven vertical stripes, each of which is a diode region 103.

[0013] (jointing material) The bonding member 106 is a member that bonds the semiconductor element 100 and the lead frame 108. The bonding member 106 is provided so as to cover the diode region 103. As illustrated in FIGS. 1A and 1B, the bonding member 106 encompasses the diode region 103 in a plan view. Here, the bonding member 106 is, for example, a Pb-based solder or an Sn-based solder. The bonding member 106 covering the diode region 103 means that, as illustrated in FIG. 2, the thickness t1 of the bonding member 106 is at least equal to or greater than the thickness t2 of the surface electrode 113 at the end of the diode region 103. The thickness t2 of the surface electrode 113 can be, for example, 3 μm to 10 μm. The bonding member 106 can be formed to a thickness of, for example, 100 μm to 1000 μm. Therefore, the thickness t1 of the bonding member 106 is greater than the thickness t2 of the surface electrode 113. However, for example, the thickness t1 may gradually decrease at the periphery of the bonding member 106. Even if the thickness t1 of the bonding member 106 decreases at the end of the diode region 103, the bonding member 106 is considered to cover the diode region 103 as long as the thickness t1 of the bonding member 106 is equal to or greater than the thickness t2 of the surface electrode 113.

[0014] (lead frame) The lead frame 108 is a member that connects the semiconductor element 100 to a wiring board on which the semiconductor element 100 is disposed. The lead frame 108 is bonded to the surface electrode 113 in a bonding region 107 on the surface electrode 113 side by a bonding member 106. The bonding region 107 is a region where the bonding member 106 and the lead frame 108 are bonded. As illustrated in FIG. 1B, in plan view, the bonding area 107 is smaller than the bonding members 106 and is included in the bonding members 106.

[0015] As illustrated in FIG. 1C , in a plan view, the diode region 103 has a region R1 overlapping with the junction region 107 of the lead frame, and the region R1 where the diode region 103 and the junction region 107 of the lead frame overlap is smaller (has a smaller area) than the diode region 103. That is, the region R1 where the diode region 103 and the junction region 107 of the lead frame overlap is a part, but not the entire, of the diode region 103. Also, in a plan view, the diode region 103 has a region R2 overlapping with the lead frame 108, and the region R2 where the diode region 103 and the lead frame 108 overlap is smaller (has a smaller area) than the diode region 103. That is, the region R2 where the diode region 103 and the lead frame 108 overlap is a part, but not the entire, of the diode region 103. Note that in FIG. 1C , the region R1 and the region R2 are the same region.

[0016] In the semiconductor device 1A, the entire diode region 103 is covered by the bonding member 106, and a portion of the diode region 103 is covered by the lead frame 108. A portion of the diode region 103 is not covered by the lead frame 108 and is not covered by the bonding region 107 either. In lead frame 108A, diode region 103 is arranged outside junction region 107 in plan view, and diode region 103 is arranged outside lead frame 108A.

[0017] The lead frame 108A has a through hole 116 that exposes the bonding member 106, and in plan view, the diode region 103 is disposed in the through hole 116. The through hole 116 is formed in a position facing the bonding member 106. There are no particular limitations on the orientation, shape, or position of the through hole. Here, the through hole 116 is oval-shaped and is formed in the center of the bonding member 106 with its longitudinal direction intersecting the striped diode region. The size of the through holes is preferably 50% or less of the bonding area of ​​the lead frame in plan view, and the through holes are preferably located near the center of the bonding area, in order to ensure a sufficient bonding area with the bonding member. The lead frame 108 may have multiple through holes.

[0018] In this way, in the semiconductor device 1A, diode regions are arranged not only in positions covered by the lead frame but also in positions not covered by the lead frame. There are no particular restrictions on the shape of the lead frame. The material of the lead frame 108 can be a metal such as gold, silver, copper, aluminum, etc., and copper is used here. The thickness of the lead frame 108 can be, for example, 1 mm to 3 mm.

[0019] In the semiconductor device 1A having the above-described configuration, the bonding member covers the diode region, thereby suppressing the temperature rise in the diode region due to the heat capacity of the bonding member, and improving the surge current withstand capability. This allows the diode region to be arranged without being restricted by the shape of the lead frame. According to the inventors' research, the heat capacity of the bonding member contributes overwhelmingly more to improving the surge current withstand capability of the diode than the heat capacity of the lead frame. Therefore, by covering the diode region with the bonding member, sufficient surge current withstand capability can be ensured. In the semiconductor device 1A, in a plan view, the region where the diode region and the junction region of the lead frame overlap is smaller (has a smaller area) than the diode region, and the diode region can also be arranged in a region that does not overlap the junction region of the lead frame. Also, in a plan view, the region where the diode region and the lead frame overlap is smaller (has a smaller area) than the diode region, and the diode region can also be arranged in a region that does not overlap the lead frame.

[0020] In the semiconductor device 1A, in a plan view, the diode regions are arranged outside the junction regions, and the diode regions can be distributed, including the junction regions. Also, in a plan view, the diode regions are arranged outside the lead frame, and the diode regions can be distributed, including the lead frame region. By distributing the diode regions, heat generation in the semiconductor element can be uniformed, suppressing temperature rise. In the semiconductor device 1A, the lead frame has through holes that expose the bonding material, and excess bonding material is concentrated in the through holes, preventing the bonding material from protruding outside the lead frame and enabling bonding with a uniform thickness. In addition, in a plan view, diode regions are arranged in the through holes, and the diode regions are dispersed, including in the areas that overlap with the through holes, thereby reducing thermal resistance.

[0021] [Variations] Next, modified examples of the semiconductor device 1A according to the first embodiment will be described with reference to FIGS. 3A to 7C. The modified examples described here are the first to fourth modified examples. The semiconductor devices 1B, 1C, 1D, and 1E according to the first to fourth modified examples differ from the semiconductor device 1A according to the first embodiment in the lead frame, but share other features. Therefore, the lead frame of each modified example will be described. Note that in the first modified example, the wiring substrate on which the semiconductor device is mounted will also be described.

[0022] (First Modification) FIG. 3A illustrates a semiconductor device 1B according to a first modification, placed on a wiring substrate. The wiring substrate will be described later. The lead frame 108B of the semiconductor device 1B has recessed portions 118 formed by cutting out corners of the lead frame 108B. Here, the recessed portions 118 are formed to a size that exposes approximately 1 / 8 of the area of ​​the semiconductor element 100. The size of the recessed portions 118 may be larger or smaller. The semiconductor element 100 has pads 104 at its exposed corners. The pads 104 are connected to a wiring substrate by bonding wires 105. The pads 104 are connected to, for example, the gate of a transistor region 102 inside the semiconductor element 100. Note that, although pads 104 can be similarly provided on the surface of the semiconductor element 100 in other modifications and embodiments, they are not shown in the drawings of the other modifications and embodiments.

[0023] In the first modified example, the diode region 103 and the bonding member 106 can also be cut out. The diode region 103 and a portion of the bonding member 106 are arranged in the recessed portion 118. In a plan view, the diode region 103 is arranged in the recessed portion 118, and the bonding member 106 also covers the diode region 103 in the recessed portion 118. In the recessed portion 118, a portion of the diode region 103 is located outside the lead frame 108B. On the other hand, on the outer periphery excluding the recessed portion 118, the diode region 103 is not arranged outside the lead frame 108B. Except for the recessed portion 118, the lead frame 108B is formed to a size that covers the transistor region 102 and the bonding members 106. As illustrated in FIG. 3B, the bonding region 107 is slightly smaller than the bonding members 106.

[0024] As illustrated in FIGS. 4A and 4B, lead frame 108B has a protrusion 121B on its lower surface, and the surface of protrusion 121B facing bonding member 106 forms bonding region 107. Here, a recess 121A is formed on the upper surface of protrusion 121B. Recess 121A and protrusion 121B can be formed, for example, by half-blanking a plate-shaped lead frame. Recess 121A does not necessarily have to be provided. Note that FIGS. 4A and 4B are side views taken along the IVA and IVB directions of FIG. 3A, respectively. 3A, 4A, and 4B, semiconductor device 1B is disposed on wiring substrate 150. Here, the wiring substrate 150 will be described. As illustrated in FIG. 4A, wiring substrate 150 is a substrate in which a conductor pattern 110 is formed on the upper surface of an insulating substrate 111 and a conductor layer 112 is formed on the lower surface. Conductive pattern 110 is formed in a predetermined pattern to which semiconductor element 100 and wiring members are connected. A back electrode of semiconductor element 100, lead frame 108, and bonding wire 105 are bonded to conductor pattern 110. The bonded portion between conductor pattern 110 and the back electrode of semiconductor element 100 is illustrated as substrate bonded portion 109.

[0025] Conductor layer 112 is formed with a uniform thickness on the lower surface of insulating substrate 111. Conductor layer 112 is joined to a base that serves as the bottom plate of the power semiconductor module. A case that surrounds semiconductor device 1B and wiring substrate 150, a sealing member that seals the components on the base that the case surrounds, and a lid are then provided to form the power semiconductor module. Note that other modifications and embodiments can also be similarly arranged on wiring substrate 150 to form a power semiconductor module. The material of the insulating substrate 111 can be a ceramic such as aluminum oxide, aluminum nitride, or silicon nitride. The material of the conductive pattern 110 and the conductive layer 112 can be a metal such as gold, silver, copper, or aluminum, and copper is used here. The material of the substrate joint 109 and the joint between the conductive pattern 110 and the lead frame 108 can be the same material as the joint member 106.

[0026] As shown in FIG. 3B, the bonding member 106 is formed in a pentagonal shape with one corner of a rectangular shape cut off. The bonding member 106 can be formed, for example, by preparing a preformed sheet solder. In this case, the semiconductor element 100, the sheet solder, and the lead frame 108 are layered in this order and bonded by reflow. Alternatively, solder paste may be printed on the surface electrodes of the semiconductor element 100, and the reflow may be performed with the lead frame placed on top of it.

[0027] In the semiconductor device 1B according to the first modification, the lead frame has recessed portions formed by cutting out the corners of the lead frame, which prevents interference with the tool of the bonding device that joins the bonding wires to the pads at the corners of the semiconductor element. Note that, because the height of the bonding material is shorter than that of the lead frame, there is no problem even if the bonding material spreads to the vicinity of the pads. In the semiconductor device 1B, the diode region is disposed in the recessed portion, and the diode region can be dispersed and disposed including the recessed portion, so that heat generation in the semiconductor element can be uniformed and temperature rise can be suppressed.

[0028] (Second Modification) 5A, lead frame 108C of semiconductor device 1C according to the second modification has an elongated rectangular shape in plan view, with a width that is less than half the width of semiconductor element 100 in the short direction and a length that is longer than semiconductor element 100. One end side in the long direction is disposed at the center of bonding member 106 and bonded thereto. 5B, the bonding area 107 is located at the center of the bonding member 106 and is smaller than the bonding area in the first embodiment. The lead frame 108C is shortened in the short direction to reduce the area facing the bonding member 106 and thereby reduce the bonding area 107. The area of ​​the bonding area 107 can be adjusted by adjusting the shape and size of the lead frame 108C. The area of ​​the bonding area 107 can be set to, for example, 20% to 60% of the area of ​​the bonding member 106 in a plan view.

[0029] In the second modification, in plan view, the diode region is disposed outside the junction region, and the proportion of the diode region disposed outside the junction region is larger than in the first embodiment. For example, in plan view, the area of ​​the diode region disposed outside the junction region can be two to four times the area of ​​the diode region disposed in the junction region. In the semiconductor device 1C according to the second modification, the bonding area of ​​the lead frame is small, so that the thermal stress acting on the bonding members and the surface electrodes is small, and the thermal fatigue life can be improved.

[0030] (Third Modification) The lead frame may be separated into multiple pieces. As illustrated in FIG. 6A, the lead frame 108D of the semiconductor device 1D according to the third modification is separated into two lead frames 108D. The lead frames 108D are rectangular with shorter short sides than the lead frame 108C of the second modification, and are arranged parallel to each other. In plan view, the diode region 103 is arranged in the gap between the separated lead frames 108D. The lead frame may be separated into three or more pieces. In the third modification, the bonding area 107 is also separated into two, and each bonding area 107 is smaller than that in the second modification. For example, the total area of ​​the bonding areas may be the same as that in the second modification.

[0031] In the semiconductor device 1D according to the third modification, the lead frame is separated into multiple parts, which allows the bonding area of ​​one lead frame to be further reduced, thereby further improving the thermal fatigue life.

[0032] (Fourth Modification) 7A, the lead frame 108E of the semiconductor device 1E according to the fourth modification encompasses the outer shape of the semiconductor element 100 in plan view. Meanwhile, the bonding region 107 has the same shape and size as the semiconductor device 1A according to the first embodiment. Also, like the first embodiment, the bonding member 106 has a through hole 116 at the center thereof. 7B, lead frame 108E has protrusions 123 on the lower surface side in the figure that face bonding member 106 to form bonding region 107. Here, protrusions 123 are formed by increasing the thickness of lead frame 108E.

[0033] In the fourth modified example, the relationship between the junction region 107 and the diode region 103 in plan view is the same as in the first embodiment. The region R1 where the diode region 103 and the junction region 107 overlap is the region exemplified in FIG. 1C. On the other hand, the relationship between the lead frame 108E and the diode region 103 is different from that in the first embodiment. As exemplified in FIG. 7C, in the fourth modified example, the region R2 where the diode region 103 and the lead frame 108 overlap extends to the outside of the junction region 107. Note that in FIG. 7C, the region R1 is not shown, and the region R2 is indicated by diagonal lines. In plan view, the diode region 103 is arranged outside the junction region 107, but the diode region 103 is not arranged outside the lead frame 108E. The fourth modification has a through hole 116 that exposes the bonding member 106, and the diode region 103 is disposed in the through hole 116 in plan view.

[0034] In the semiconductor device 1E according to the fourth modification, the shape of the junction region and the shape of the lead frame can be adjusted independently, which allows the diode regions to be distributed to suppress temperature rise, while the junction region is made smaller to reduce thermal stress and increase the degree of freedom in the shape of the lead frame.

[0035] [Second embodiment] Next, a semiconductor device 2 according to a second embodiment will be described with reference to Figures 8A to 8C. As illustrated in Figures 8A and 8B, the bonding member 106 of the semiconductor device 2 is divided into two regions in a plan view. The linear boundary between the bonding members 106A and 106B of the two regions is perpendicular to the extension direction of the striped diode region 103. The semiconductor element 200 of the semiconductor device 2 is, for example, an RC-IGBT, but is different from the semiconductor element 100 of the first embodiment. In the semiconductor element 200, the diode region 103 is divided into a diode region 103A on the bonding member 106A side and a diode region 103B on the bonding member 106B side. The bonding member 106A covers the diode region 103A, and the bonding member 106B covers the diode region 103B.

[0036] The semiconductor element 200 has internal wiring 114 extending between the divided bonding members. In a plan view, the internal wiring 114 extends linearly along the boundary between the bonding members 106A and 106B in the two regions. In FIG. 8B, the internal wiring 114 is provided so as to cross the center of the semiconductor element 200. The internal wiring 114 can be, for example, gate wiring to a transistor region or a temperature detection diode and its wiring. 8A and 8C, lead frame 108F is disposed so as to straddle two bonding members 106A and 106B. Here, lead frame 108F has two legs 125 formed with increased thickness so as to face two bonding members 106A and 106B, respectively, and the surfaces of leg portions 125 on the front electrode side form bonding regions 107A and 107B.

[0037] In plan view, diode region 103A is arranged outside junction region 107A, and diode region 103B is arranged outside junction region 107B. In addition, in plan view, diode region 103 is arranged outside lead frame 108F. In semiconductor device 2, diode regions 103 can be arranged in a dispersed manner, similar to the first embodiment and the modified examples.

[0038] As in the first embodiment, the semiconductor device 2 according to the second embodiment can ensure surge current resistance by covering the diode region with a bonding member. Furthermore, the diode region can be distributed, which can uniformly distribute heat in the semiconductor element and suppress temperature rise. Furthermore, internal wiring can be provided across or across the semiconductor element while suppressing the effects of thermal stress from the lead frame. Furthermore, by using metal for the internal wiring, wiring resistance can be reduced. The bonding member may be divided into three or more regions in a plan view. The lead frame may be a separated lead frame, like lead frame 108D of the third modified example. The lead frame 108F having two legs 125 may be bonded to the non-separated bonding member 106 as in the first embodiment. In this case, two separated bonding regions can be formed on the non-separated bonding member 106.

[0039] [Third embodiment] Next, a semiconductor device 3 according to a third embodiment will be described with reference to Figures 9A and 9B. The semiconductor device 3 has the same bonding members 106 and lead frames 108A as the first embodiment, and therefore their description will be omitted. On the other hand, the semiconductor element 300 is an RC-IGBT, for example, but is different from the semiconductor element 100 of the first embodiment. 9A and 9B, in the semiconductor element 300, the diode regions 103C are arranged in an island shape, with circular regions arranged at equal intervals in a plan view. The diode regions 103C do not have to extend linearly, and their arrangement is not limited to a stripe shape. In the semiconductor element 300, the circular diode regions 103C are arranged at equal intervals so as to be located at the lattice points of a triangular lattice.

[0040] As in the first embodiment, the semiconductor device 3 according to the third embodiment can ensure surge current resistance by covering the diode region with a bonding member. Furthermore, the diode region can be dispersed, which can uniformly distribute heat in the semiconductor element and suppress temperature rise. Furthermore, by arranging the diode region in an island shape, the total length of the boundary line between the transistor region and the diode region can be increased, improving thermal coupling between the transistor region and the diode region and reducing thermal resistance. The semiconductor element 300 of the third embodiment can be replaced with the semiconductor element of the first embodiment, its modified example, or the second embodiment. [Explanation of symbols]

[0041] 1A Semiconductor Device 100 Semiconductor element 101 Termination Area 102 Transistor Area 103 Diode Region 104 Pad 105 Bonding Wire 106 Joint members 107 Joint area 108 Lead Frame 109 Substrate joint 110 Conductor pattern 111 Insulating substrate 112 Conductor layer 113 Surface electrode 114 Internal wiring of element 115 Back electrode 116 Through Hole

Claims

1. a semiconductor element having a diode region and a transistor region adjacent to each other and continuous between a front electrode and a back electrode; a lead frame joined to the surface electrode at a joining region on the surface electrode side; a bonding member provided to cover the diode region and bonding the surface electrode to a lead frame, A semiconductor device, wherein an overlapping area between the diode region and the junction region of the lead frame is smaller than the diode region in a plan view.

2. The semiconductor device according to claim 1 , wherein the diode region is disposed outside the junction region in a plan view.

3. The semiconductor device according to claim 1 , wherein an area where the diode region overlaps with the lead frame is smaller than the diode region in a plan view.

4. The semiconductor device according to claim 3 , wherein the diode region is disposed outside the lead frame in a plan view.

5. the lead frame has a through hole that exposes the bonding member; The semiconductor device according to claim 4 , wherein the diode region is disposed in the through hole in a plan view.

6. the lead frame has recessed portions formed by cutting out corners thereof, The semiconductor device according to claim 4 , wherein the diode region is disposed in the recessed portion in a plan view.

7. The lead frame is separated into a plurality of parts, 5. The semiconductor device according to claim 4, wherein the diode region is disposed in a gap between the separated lead frames in a plan view.

8. The joining member is divided into a plurality of regions in a plan view, 5. The semiconductor device according to claim 4, wherein the semiconductor element has internal wiring extending between the divided portions of the joining member.

9. 9. The semiconductor device according to claim 1, wherein the diode regions are arranged in stripes extending parallel to each other in a plan view.

10. 9. The semiconductor device according to claim 1, wherein the diode region is arranged in an island shape in plan view, with circular regions arranged at equal intervals.

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