Resonant tunneling diode element and nonvolatile memory

Abstract

To provide an RTD element with improved stable operation.SOLUTION: The present disclosure provides a resonant tunneling diode element 10 in which a quantum well structure 18 having an emitter layer, multiple barrier layers 11 and 12 with a gradient potential, and a well layer 13 present between the multiple barrier layers, and a collector layer are stacked, and the quantum well structure includes an intermediate layer 15 in contact with the emitter layer side of the barrier layer 11 closest to the emitter layer, the intermediate layer having a defect level lower than the defect level of the barrier layer.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a resonant tunneling diode (hereinafter also referred to as "RTD") element and a nonvolatile memory using the same. [Background technology]

[0002] Research and development of tunnel devices has been ongoing in the field of semiconductor technology. Among tunnel diodes, tunnel diodes that utilize the resonant tunneling phenomenon are called RTDs. Here, the resonant tunneling phenomenon refers to the phenomenon in which electron or hole carriers with energy equal to the quantum level of a quantum well sandwiched between potential barriers tunnel through the quantum well. Resonant tunneling diodes are expected to be used as negative resistance elements and oscillators.

[0003] However, with the recent dramatic advances in information and communication technology, there are concerns about the increasing power consumption of information and communication devices. In current computer systems, components other than those that are required to operate are also running while the system is in operation. In response to this, a new technology called "normally-off computing" has been proposed, which achieves significant power savings by actively cutting off power to components other than those that are required to operate, even while the system is in operation. It is expected that the use of this technology will significantly reduce the power consumption of computing systems.

[0004] Currently, non-volatile memory has the excellent features of low power consumption, high integration, and high read speed, and is already in practical use. Examples include flash memory that uses silicon semiconductors.

[0005] In normally-off computing technology, in addition to non-volatile memories such as flash memory that are currently in practical use, new non-volatile memories that can operate at different speeds and reduce power consumption are essential. There is a demand for new non-volatile memories that can achieve even lower power consumption, higher integration, and ultra-high speed operation than current models.

[0006] As a candidate for nonvolatile memory, a resistive memory (RRAM) using an RTD and intersubband transitions has been proposed, taking advantage of the bistable resistance state (high and low resistance states) of a Si / CaF2 / CdF2-based RTD. This RRAM utilizes the RTD's negative differential resistance and fast LO (Longitudinal Optical) phonon scattering (scattering time: approximately 0.02-0.2 ps), enabling ultra-high-speed operation on the order of picoseconds. Furthermore, this RRAM exhibits low loss, making it promising for use as a low-power nonvolatile memory. This RRAM may potentially achieve high-speed operation equivalent to or even faster than MRAM (Magnetoresistive Random Access Memory) and FeRAM (Ferroelectric Random Access Memory).

[0007] The present inventors have proposed that for a semiconductor device utilizing intersubband transitions, an intermediate layer be provided inside the barrier layer of a quantum well, thereby suppressing the release of electrons accumulated in the quantum well even if crystal defects are present in the barrier layer (see Patent Document 1). [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Patent No. 6278419 [Non-patent literature]

[0009] [Non-Patent Document 1] K.Ooyama et al., Jpn.J.Appl.Phys.49,No.10,101001(2010) [Non-patent document 2] M. Nagase et al., Phys.Status Solidi A 218, 2000495(2021) [Non-patent document 3] R. Hache et al., J. Appl. Phys. 76, p304-309 (1994) [Non-patent document 4] P. Kamyczek et al., J. Appl. Phys. 111, 113105 (2012) [Non-patent document 5] J.Li et al., Appl.Phys.Lett.81, p3365-3367(2002) [Non-patent document 6] LAYang et al., J.Appl.Phys.119,164501(2016) Summary of the Invention [Problem to be solved by the invention]

[0010] FIG. 1 is a diagram illustrating the energy levels in each layer of the resistance change type memory described in Patent Document 1. In FIG.

[0011] The resistance change type memory of FIG. 1 has intermediate layers (924b, 925b) between the well layer 96b and the barrier layers (95b, 97b) (on the well layer side of the barrier layer). In the figure, the energy level (Fermi level) E above the emitter electrode f 91b, the bottom energy level of the emitter electrode E c At 92b, the energy level E above the collector electrode f ' 910b, the bottom energy level of the collector electrode E c '911b, the energy level E due to crystal defects in the barrier layer DL The intermediate layer is shown as 921b and 922b. For example, a u-AlN (undoped-AlN) layer having a lower band gap than the u-AlN layer used in the barrier layers (95b and 97b) is used. x Ga 1-x According to Non-Patent Document 1, the energy level caused by crystal defects decreases as the band gap decreases. x Ga 1-x In the middle layer consisting of N layers, E R1 E with energy close to (915b) DLTherefore, by inserting the intermediate layer (924b, 925b), E DL The release of the accumulated electrons (919b) through the intermediate layer (921b) becomes difficult. This state is shown in the figure as leakage current (923b) blocked by the intermediate layer. Based on the above-mentioned principle, by inserting the intermediate layers (924b, 925b) between the well layer 96b and the barrier layers (95b, 97b), it is possible to suppress the leakage of electrons accumulated inside the quantum well to the outside, thereby enabling long-term stable operation of the resistance change type memory.

[0012] However, the structure in Figure 1 does not adequately suppress electron leakage from the outside to the inside. In addition, when forming the intermediate layer, it is necessary to consider both the growth conditions for growing an AlGaN layer on an AlN layer and the conditions for growing an AlN layer on an AlGaN layer.

[0013] The present disclosure seeks to solve these problems, and aims to provide an RTD element with improved operational stability, and to provide a nonvolatile resistance change memory using the RTD element. [Means for solving the problem]

[0014] In order to achieve the above object, the present disclosure has the following features.

[0015] According to one aspect of the present disclosure, there is provided a resonant tunneling diode element including a collector layer and a stack of a quantum well structure having an emitter layer, a plurality of barrier layers with a potential gradient, and a well layer present between the plurality of barrier layers, wherein the quantum well structure includes an intermediate layer that is in contact with the emitter layer side of the barrier layer closest to the emitter layer and has a defect level lower than the defect level of the barrier layer closest to the emitter layer.

[0016] According to another aspect of the present disclosure, there is provided a nonvolatile memory including the resonant tunneling diode element of the above aspect.

[0017] A nonvolatile memory including the resonant tunneling diode element of the present disclosure is characterized by storing a bistable state by electron accumulation and electron emission due to intersubband transition. [Effects of the Invention]

[0018] It is possible to provide a resonant tunneling diode element that suppresses electron leakage and improves stable memory operation. [Brief explanation of the drawings]

[0019] [Figure 1] FIG. 2 is a diagram illustrating the energy levels in each layer of an RTD. [Figure 2] FIG. 1 is an explanatory diagram of an electronic leak in an RTD. [Figure 3] FIG. 1 is a diagram showing the potential gradient of an RTD. [Figure 4] FIG. 1 is a diagram showing the material dependence of defect energy levels. [Figure 5] FIG. 1 is a voltage-current characteristic diagram of an RTD. [Figure 6] 1 is a diagram showing a schematic configuration and energy levels of an RTD according to a first embodiment. FIG. [Figure 7] FIG. 10 is a diagram showing the difference between the band offset and the defect energy level when a u-Al0.6Ga0.4N intermediate layer is disposed on the emitter side (left side) of the u-AlN barrier layer. [Figure 8] 1 is a schematic diagram illustrating an example of a laminated structure of an RTD according to a first embodiment. [Figure 9] FIG. 10 is a diagram showing a schematic configuration and energy levels of an RTD according to a second embodiment. [Figure 10] FIG. 10 is a schematic diagram illustrating an example of a laminated structure of an RTD according to a second embodiment. [Figure 11] FIG. 10 is a diagram showing a schematic configuration and energy levels of an RTD according to a third embodiment. [Figure 12] FIG. 10 is a diagram showing a schematic configuration and energy levels of a modified example of the RTD according to the third embodiment. [Figure 13] FIG. 10 is a diagram showing a schematic configuration and energy levels of an RTD according to a fourth embodiment. [Figure 14] FIG. 10 is a diagram showing a schematic configuration of an RTD according to a fifth embodiment. [Figure 15] FIG. 10 is a diagram showing a schematic configuration of an RTD according to a sixth embodiment. [Figure 16] FIG. 2 is a voltage-current characteristic diagram of the RTD of the embodiment. [Figure 17] FIG. 10 is a voltage-current characteristic diagram of an RTD of a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0020] Embodiments of the present disclosure will be described below.

[0021] (First embodiment) FIG. 2 is an explanatory diagram of electronic leakage of an RTD.

[0022] As shown in Figure 2, the nonvolatile memory has a quantum well with barrier layers (u-AlN) on both sides of the well layer (u-GaN), and electrons are stored in the well layer. Each layer constituting the nonvolatile memory may be formed by any method, for example, MOVPE (Metalorganic Vapor Phase Epitaxy).

[0023] In nitride semiconductors, the potential gradient of the barrier layer can be made positive (or negative) and the potential gradient of the spacer layer and well layer adjacent to the barrier layer can be made negative (or positive) due to the polarization effect unique to nitride semiconductors.

[0024] 2, when forward biased, the potential gradient of the barrier layer is positive, while the potential gradients of the spacer layer and well layer adjacent to the barrier layer are negative, resulting in a low potential (energy level) in the emitter-side spacer layer on the left side of the emitter-side barrier layer and a high potential in the well layer on the right side of the emitter-side barrier layer. Also, the potential of the well layer on the left side of the collector-side barrier layer is low, while the potential of the collector-side spacer layer on the right side of the collector-side barrier layer is high.

[0025] FIG. 3 is a diagram showing the potential gradient of an RTD.

[0026] In the quantum well structure of the RTD shown in Figure 3, P k is the polarization strength of the k layer (the sum of spontaneous polarization and piezoelectric polarization). The spontaneous polarization of u-GaN is -0.034 cm -2 The spontaneous polarization of u-AlN is -0.09cm -2 The piezoelectric polarization of u-GaN and u-AlN is -0.047 cm -2 , and GaN and u-Al 1-x Ga x The piezoelectric polarization due to N is 0 to -0.047 cm -2 is.

[0027] Referring to Figure 3, the electric field strength (gradient of the potential gradient) due to polarization when the thickness of the emitter-side spacer layer is l1 and the dielectric constant is ε1 is F1, the electric field strength due to polarization when the thickness of the emitter-side barrier layer is l2 and the dielectric constant is ε2 is F2, the electric field strength due to polarization when the thickness of the well layer is l3 and the dielectric constant is ε3 is F3, the electric field strength due to polarization when the thickness of the collector-side barrier layer is l4 and the dielectric constant is ε4 is F4, and the electric field strength due to polarization when the thickness of the collector-side spacer layer is l5 and the dielectric constant is ε5 is F5.

[0028] According to Non-Patent Document 2, the electric field strength F due to polarization in each layer is i teeth,

number

number

[0029] That is, the potential gradient of the RTD depends on the thickness and dielectric constant of each layer, namely the emitter-side spacer layer, emitter-side barrier layer, well layer, collector-side barrier layer, and collector-side spacer layer, as well as their composition.

[0030] In terms of manufacturing, it is extremely difficult to avoid crystal defects in the barrier layer. Figure 4 is a diagram showing the material dependency of the defect level (defect energy level) (Non-Patent Documents 1, 3-5).

[0031] Referring to FIG. 4, the depth of the defect energy level from the energy level of the bottom of the conduction band in u-AlN constituting the barrier layer is 1.8 eV.

[0032] Figure 5 shows the voltage-current characteristics of an RTD, and is a graph showing the results of measuring the voltage-current characteristics 10 times for an RTD formed on a Si substrate with the configuration shown in Figure 2. The solid line shows the first measurement, and the dotted lines show the second to tenth measurements. It can be seen that electronic leakage exists, and that since the electronic leakage is not stable, fluctuations occur with each measurement.

[0033] In addition, the higher the stored electron density, the larger the change in the RTD potential and the higher the Fermi level in the quantum well, according to the Poisson equation. DL (u-AlN) and E' DL Electron leakage through (u-AlN) becomes more likely to occur.

[0034] To prevent electron leakage, an intermediate layer is provided in the barrier layer. For example, the intermediate layer is u-Al. 0.6 Ga 0.4 N is used.

[0035] FIG. 6 is a diagram showing the schematic configuration and energy levels of the RTD according to the first embodiment, and shows the case where a forward bias (the emitter side has a higher potential) is applied in a configuration in which an intermediate layer is provided on the emitter side (left side) of the barrier layer closest to the emitter layer (hereinafter also referred to as "emitter").

[0036] 6, the RTD 10 according to the first embodiment has barrier layers 11 and 12 and a well layer 13 therebetween, and is provided with a quantum well structure 18 having an intermediate layer 15 in contact with the emitter 14 side of the barrier layer 11 closest to the emitter 14, an intermediate layer 17 in contact with the well layer 13 side of the barrier layer 12 closest to the collector 16, and spacer layers 19 and 20. The potential gradient of the barrier layers 11 and 12 is positive, while the potential gradient of the spacer layers 19 and 20 adjacent to the barrier layers 11 and 12 and the well layer 13 is negative. This means that the potential (energy level) of the emitter-side spacer layer 19 on the emitter 14 side (left side) of the emitter-side barrier layer 11 is low, and the potential of the well layer 13 on the collector 16 side (right side) of the emitter-side barrier layer 11 is high. In addition, the well layer 13 on the emitter 14 side (left side) of the collector-side barrier layer 12 has a low potential, and the collector-side spacer layer 20 on the collector 16 side (right side) of the collector-side barrier layer 12 has a high potential.

[0037] Therefore, since the potential differs between the left and right sides of each barrier layer 11, 12, the difference in defect energy levels between the barrier layer 11 and the intermediate layer 15 when the intermediate layer 15 is provided on the left side of the barrier layer 11 differs from the difference in defect energy levels between the barrier layer 11 and the intermediate layer when the intermediate layer is provided on the right side of the barrier layer 11.

[0038] If the difference in defect energy level between the barrier layer 11 and the intermediate layer 15 and the difference in defect energy level between the barrier layer 12 and the intermediate layer 17 are small, the Fermi level E fDue to the effects of increased thermal fluctuations and thickness mismatches and thickness fluctuations of each layer in the quantum well structure, electrons are more likely to leak through both defect energy levels. On the other hand, increasing the difference in defect energy levels between the barrier layer 11 and the intermediate layer 15 and the difference in defect energy levels between the barrier layer 12 and the intermediate layer 17 can effectively prevent electron leakage due to the above effects. Therefore, the intermediate layers 15 and 17 are provided on the side where the difference in defect level energy between the barrier layers 11 and 12 and the intermediate layers 15 and 17 is greater. In particular, by providing the intermediate layer 15 on the emitter 14 side (left side) of the barrier layer 11 closest to the emitter 14, the potential on the emitter 14 side (left side) of the barrier layer 11 can be reduced by polarization, thereby suppressing electron penetration from the emitter 14 side.

[0039] The band gaps of the intermediate layers 15 and 17 are different from the band gaps of the well layer 13 and the barrier layers 11 and 12. For example, referring to FIG. 0.6 Ga 0.4 The band gap of N is 4.8 eV, which is different from the band gap of 6.2 eV of u-AlN of the barrier layers 11 and 12 and the band gap of 3.4 eV of u-GaN of the well layer 13 .

[0040] Also, according to FIG. 4, the u-Al of the intermediate layers 15 and 17 0.6 Ga 0.4 The defect energy level of N is 1.0 eV, which is lower than that of the u-AlN of the barrier layers 11 and 12. Therefore, if an intermediate layer is provided on the side of the barrier layers 11 and 12 where the potential gradient is high, the difference in the defect energy levels between the intermediate layer and the barrier layer will be reduced by the amount of the potential gradient, but if the intermediate layers 15 and 17 are provided on the side of the barrier layers 11 and 12 where the potential gradient is low, the difference in the defect energy levels between the intermediate layers 15 and 17 and the barrier layers 11 and 12 will be increased by the amount of the potential gradient. 0.6 Ga 0.4In the case of N, by inserting the intermediate layers 15 and 17 on the emitter side (left side) of the barrier layers 11 and 12, which have a low potential gradient, the difference in defect energy levels between the barrier layers 11 and 12 and the intermediate layers 15 and 17 can be increased, thereby effectively preventing electron leakage.

[0041] That is, the intermediate layer 15 is adjacent to the emitter-side barrier layer 11 on the emitter 14 side.

[0042] By utilizing the potential gradient, electron leakage can be suppressed even when the difference in defect energy levels between the intermediate layer and the barrier layer is small. Because the potential gradient depends on the thickness and composition of the well layer 13, barrier layers 11 and 12, and spacer layers 19 and 20, electron leakage can be suppressed by changing the thickness and composition of each layer even when the difference in defect energy levels between the intermediate layers 15 and 17 and the barrier layers 11 and 12 is small.

[0043] In the RTD 10 shown in FIG. 6, the defect energy levels of the intermediate layers 15 and 17 are E DL (u-Al 1-x Ga x N), E' DL (u-Al 1-x Ga x N), the defect energy levels of the barrier layers 11 and 12 are E DL (u-AlN), E' DL (u-AlN), respectively.

[0044] The defect energy level E of the barrier layer 11 on the emitter 14 side DL The defect energy level E of (u-AlN) and the intermediate layer 15 DL (u-Al 1-x Ga x N), the intermediate layer 15 can prevent electron leakage from the barrier 11 layer.

[0045] FIG. 7 shows the intermediate layers 15 and 17 made of u-Al. 0.6 Ga 0.4 N, and the band offset ΔE when placed (inserted) on the emitter side (left side) of the u-AlN barrier layer 12c and the defect energy level difference E DL (u-AlN)-E DL (u-Al 0.6 Ga 0.4 N) (Non-Patent Document 6).

[0046] Referring to FIG. 7, the band offset is 1.0 eV, and the difference in defect energy levels is 0.8 eV.

[0047] FIG. 8 is a schematic diagram illustrating an example of the laminated structure of the RTD according to the first embodiment.

[0048] 8, the RTD 30 has a structure in which a plurality of layers 802 to 814 are stacked on a substrate 801. The RTD 30 has a structure in which a buffer layer or strain relaxation layer 802, a contact layer 803, an emitter layer 804, an emitter-side spacer layer 805, an intermediate layer 806, an emitter-side barrier layer 807, a well layer 808, an intermediate layer 809, a collector-side barrier layer 810, a collector-side spacer layer 811, a collector layer 812, and a contact layer 813 are stacked in this order on the substrate 801. The substrate 801 is a sapphire substrate, a GaN substrate, an AlN substrate, a Si substrate, a SiC substrate, or a diamond substrate. The buffer layer or strain relaxation layer 802 is, for example, a 1 μm-thick n-GaN layer. The contact layer 803 is, for example, a 500 nm-thick n-GaN layer. + The emitter layer 804 is, for example, a 50 nm thick u-GaN layer. The emitter-side spacer layer 805 is, for example, a 3 nm thick u-GaN layer. The intermediate layer 806 is, for example, a 1 nm thick u-Al 0.4 Ga 0.6 The emitter-side barrier layer 807 is, for example, a u-AlN layer having a thickness of 2 nm. The well layer 808 is, for example, a u-GaN layer having a thickness of 3 nm. The intermediate layer 809 is, for example, a u-Al 0.4 Ga 0.6 The collector-side barrier layer 810 is, for example, a 2-nm-thick u-AlN layer. The collector-side spacer layer 811 is, for example, a 3-nm-thick u-GaN layer. The collector layer 812 is, for example, a 50-nm-thick n-GaN layer. The contact layer 813 is, for example, a 30-nm-thick n-GaN layer.+ The RTD 30 has a quantum well structure 814 composed of layers from an emitter-side spacer layer 805 to a collector-side spacer 811. The RTD 30 uses a substrate 801 as a conductive material, and a lower electrode 815 and an upper electrode 816 are formed on the lower surface of the substrate 801 and the upper surface of a contact layer 813, respectively, to form a resonant tunneling diode element (RTD).

[0049] When RTD 30 is fabricated by MOVPE, it is possible to grow other layers by changing the composition of the source gases once each layer has reached a predetermined thickness. In particular, when fabricating intermediate layers 806 and 809, it is necessary to consider only the growth conditions for growing an AlGaN layer on the AlN layer of emitter-side spacer layer 805 or well layer 808, which reduces manufacturing costs.

[0050] Intermediate layers 806 and 809 are u-Al 0.4 Ga 0.6 N is used, but u-Al 1-x Ga x In terms of N, x is preferably 0.1 to 0.9 in order to be able to sufficiently prevent electron leakage, and it is particularly preferable that x is 0.2 to 0.8 in order to be able to further sufficiently prevent electron leakage.

[0051] The thickness of each layer of RTD 30 may be other thicknesses. Emitter-side spacer layer 805 may be 1 to 30 nm, and emitter-side barrier layer 807 may be 0.5 to 5 nm. For example, well layer 808 may be 0.5 to 5 nm, and collector-side spacer layer 811 may be 1 to 30 nm.

[0052] The thickness of the intermediate layers 806 and 809 is preferably 0.5 nm to 5 nm, and the thickness of the barrier layers 807 and 810 adjacent to the respective intermediate layers 806 and 809 is preferably 1 nm to 6 nm.

[0053] (Second embodiment) When a nitride semiconductor is used, the potential gradient due to the polarization effect varies depending on the thickness of each layer, so electron leakage does not necessarily occur in both the emitter-side barrier layer and the collector-side barrier layer.

[0054] Furthermore, since electron leakage from the outside to the inside occurs in the emitter-side barrier layer, providing an intermediate layer only on the emitter-side barrier layer can prevent electron leakage while reducing manufacturing costs.

[0055] FIG. 9 is a diagram showing a schematic configuration and energy levels of the RTD according to the second embodiment, in which an intermediate layer is provided on the well layer side (left side) of the emitter-side barrier layer closest to the emitter layer, and shows the case where a forward bias (the emitter side has a higher potential) is applied.

[0056] 9, the RTD 40 according to the second embodiment has a quantum well structure 48 in which, from the emitter 14 side, a spacer layer 19, an intermediate layer 15, an emitter-side barrier layer 11, a well layer 13, a collector-side barrier layer 12, and a spacer layer 20 are arranged, and no intermediate layer 17 is provided in contact with the collector-side barrier layer 12. The RTD 40 is otherwise similar in structure, material, composition, and thickness to the RTD 10, and therefore description thereof will be omitted.

[0057] FIG. 10 is a schematic diagram of an example of a laminated structure of an RTD according to the second embodiment.

[0058] The RTD 50 has a structure in which multiple layers 802-808 and 810-813 are stacked on a substrate 801, and has a quantum well structure 914 made up of each layer from an emitter-side spacer layer 805 to a collector-side spacer 811. The RTD 50 uses a conductive material for the substrate 801, and a lower electrode 815 and an upper electrode 816 are formed on the lower surface of the substrate 801 and the upper surface of a contact layer 813, respectively, to form a resonant tunneling diode element (RTD). The RTD 50 has the same configuration as the RTD 30 shown in FIG. 8, except that the intermediate layer 809 in contact with the well layer 808 side of the collector-side barrier layer 810 is omitted.

[0059] (Third embodiment) In the RTD according to the third embodiment, the intermediate layers 15 and 17 of the RTD according to the first and second embodiments shown in FIGS. 6 and 9 are made of a u-Al alloy having a compositional gradient of the alloy crystal material. 1-x Ga x When it is difficult to form a thin intermediate layer, a graded u-Al alloy material is used. 1-x Ga x It is effective to use N.

[0060] FIG. 11 is a diagram showing a schematic configuration and energy levels of an RTD according to the third embodiment.

[0061] 11, the RTD 60 according to the third embodiment has a quantum well structure 61 in which, from the emitter 14 side, a spacer layer 19, an intermediate layer 65, an emitter-side barrier layer 11, a well layer 13, an intermediate layer 67, a collector-side barrier layer 12, and a spacer layer 20 are arranged. The barrier layers 11 and 12 are provided with intermediate layers 65 and 67 on the emitter 14 side, respectively. The intermediate layers 65 and 67 are represented by triangles because they have a compositional gradient. The intermediate layers 65 and 67 are u-Al 1-x Ga x In the case of N, x is made small on the barrier layer 11, 12 side and made larger as it moves away from the barrier layer 11, 12. This makes it possible to realize the energy band structure shown in Fig. 11. The x of the intermediate layers 65, 67 closest to the barrier layers 11, 12 may be set to 0 (i.e., u-AlN). 1-x Ga x The x of N can be in a range of 0 to 1 and can have a composition gradient.

[0062] When MOVPE is used to form the intermediate layers 65 and 67, the composition of the source gases can be gradually changed to form intermediate layers with a gradient composition.

[0063] The RTD 60 can prevent electronic leakage by the compositionally graded intermediate layers 65 and 67 .

[0064] The compositionally graded intermediate layers 65 and 67 may be provided on only one of the barrier layers 11 and 12 .

[0065] 12 is a diagram showing the schematic configuration and energy levels of a modified example of the RTD according to the third embodiment. Referring to FIG. 12, an RTD 70 according to the modified example has a quantum well structure 71 with a compositionally graded intermediate layer 65 only in the barrier layer 11 (emitter-side barrier layer) closest to the emitter 14. This provides the same effect as the intermediate layer 65 / barrier layer 11 on the emitter 14 side of the RTD 60 shown in FIG. 11.

[0066] (Fourth embodiment) 13 is a diagram showing a schematic configuration and energy levels of an RTD according to the fourth embodiment. Referring to FIG. 13, an RTD 80 according to the fourth embodiment is a modified example of the RTD 10 according to the first embodiment, and has a quantum well structure 88 in which, from the emitter 14 side, a spacer layer 19, an intermediate layer 15, a barrier layer (emitter-side barrier layer) 11, a well layer 13, an intermediate layer 81, a barrier layer 82, a well layer 83, an intermediate layer 17, a barrier layer 12 (collector-side barrier layer), and a spacer layer 20 are arranged in this order. The intermediate layer 81, the barrier layer 82, and the well layer 83 can be made of the same material, composition, and thickness as the intermediate layers 15 and 17, the barrier layers 11 and 12, and the well layer 13, respectively.

[0067] In the RTD 80, the well layer 13 is used to store electrons, similar to the well layer 13 of the first embodiment. The well layer 83, the intermediate layer 17, and the barrier layer 12 (collector-side barrier layer) can more effectively prevent electron leakage.

[0068] The RTD 80 has a quantum well structure that allows two quantum levels to intersect when a reverse bias is applied, which allows electron emission (erase operation) by a reverse tunnel current. If the electron leakage from the barrier layer 82 is not sufficiently suppressed, it can be more effectively suppressed by combining it with the electron leakage suppression using the intermediate layer 81.

[0069] (Fifth embodiment) 14 is a diagram showing a schematic configuration of an RTD according to the fifth embodiment. Referring to FIG. 14, the RTD 100 has a structure in which a buffer layer or strain relaxation layer 102 and a contact layer 103 are stacked in this order on a substrate 101. An emitter layer 104, a quantum well structure 105, a collector layer 106, a contact layer 107, and an upper collector electrode 108 are stacked in this order on a portion of the surface of the contact layer 103. A lower emitter electrode 109 is stacked on another portion of the surface of the contact layer 103. The quantum well structure 105 has a configuration similar to the quantum well structure 18 of the first embodiment, and has a structure in which, from the emitter layer 104 side, an emitter-side spacer layer 19, an intermediate layer 15, an emitter-side barrier layer 11, a well layer 13, an intermediate layer 17, a collector-side barrier layer 12, and a collector-side spacer layer 20 are stacked in this order. The quantum well structure 105 may be the quantum well structure 814 of the first embodiment, the quantum well structure 48 of the second embodiment, the quantum well structures 61 and 71 of the third embodiment, or the quantum well structure 88 of the fourth embodiment, and may have the same material, composition, and thickness. As a result, by applying a voltage between the lower emitter electrode 109 and the upper collector electrode 108, it functions as an RTD.

[0070] (Sixth embodiment) The RTDs according to the first to fifth embodiments are in the case of Ga-polar crystal growth, in which the potential gradient of the barrier layer is positive and the potential gradient of the spacer layer and well layer adjacent to the barrier layer is negative. However, they may also be in the case of N-polar crystal growth, in which the potential gradient of the barrier layer is negative and the potential gradient of the spacer layer and well layer adjacent to the barrier layer is positive.

[0071] 15 is a diagram showing a schematic configuration of an RTD according to a sixth embodiment. Referring to FIG. 15, the RTD 110 is formed by N-polarity crystal growth, and the substrate 111 is a sapphire substrate whose primary surface is nitrided, a SiC substrate whose primary surface is a C (carbon atom) plane, such as a 4H- or 6H-SiC substrate whose primary surface is a (000-1) plane or a 3C-SiC substrate whose primary surface is a (-1-1-1) plane, a GaN substrate whose primary surface is an N (nitrogen atom) plane, such as a GaN substrate whose primary surface is a (000-1) plane, an AlN substrate whose primary surface is an N (nitrogen atom) plane, or a Si substrate on which a SiC thin film whose primary surface is a C (carbon atom) plane is stacked. By using these substrates, the RTD 110 is formed by N-polarity crystal growth, and a collector layer 114 is formed on the substrate side (lower side) of a quantum well structure 115, and an emitter layer 116 is formed on the opposite side (upper side). When forming a quantum well structure on the order of several nanometers using crystal growth methods such as MOVPE, the quality of the barrier and intermediate layers may vary slightly depending on the order of deposition. This is particularly effective in the present invention, where an intermediate layer is provided on the emitter side of the barrier layer and the composition and thickness of the layer are controlled.

[0072] The RTD 110 has a structure in which a buffer layer or strain relaxation layer 112 and a contact layer 113 are stacked in this order on a substrate 111, a collector layer 114, a quantum well structure 115, an emitter layer 116, a contact layer 117, and an upper emitter electrode 118 are stacked in this order on a portion of the surface of the contact layer 113, and a lower collector electrode 119 is stacked on another portion of the surface of the contact layer 113. The quantum well structure 115 has a configuration similar to that of the quantum well structure 18 of the first embodiment. The quantum well structure 115 has a structure in which the stacking order is reversed from that of the quantum well structure 18 of the first embodiment, and the following are stacked in this order from the collector layer 114 side: a collector-side spacer layer 20, a collector-side barrier layer 12, an intermediate layer 17, a well layer 13, an emitter-side barrier layer 11, an intermediate layer 15, and an emitter-side spacer layer 19. The quantum well structure 115 may be the quantum well structure 814 of the first embodiment, the quantum well structure 48 of the second embodiment, the quantum well structures 61 and 71 of the third embodiment, or the quantum well structure 88 of the fourth embodiment. As a result, it functions as an RTD by applying a voltage between the lower collector electrode 119 and the upper emitter electrode 118. Each layer of the RTD 110 may be of the same material, composition, and thickness as each layer of the fifth embodiment.

[0073] (Other embodiments) u-AlN as the barrier layer and u-Al as the intermediate layer 1-x Ga x Although N is used, other materials may also be used. In the present disclosure, electron leakage is prevented by utilizing the difference in defect energy level between the barrier layer and the intermediate layer, so other materials may be used for the intermediate layer, barrier layer, and well layer as long as the intermediate layer and barrier layer have different defect energy levels and the band gap of the intermediate layer is different from the band gap of the well layer and the band gap of the barrier layer.

[0074] (Example) As an example, an RTD was fabricated that had the structure of the RTD according to the fifth embodiment shown in Fig. 14, and whose quantum well structure 105 had the layer configuration of the quantum well structure 914 according to the second embodiment shown in Fig. 10. That is, in the quantum well structure 105 shown in Fig. 14, the example had a configuration in which the intermediate layer 15 was formed between the emitter-side barrier layer 11 and the emitter-side spacer layer 19 (i.e., on the emitter electrode side of the emitter-side barrier layer 11), and the intermediate layer 17 was not formed between the collector-side barrier layer 12 and the well layer 13.

[0075] In the example, a sapphire substrate having a (0001) plane as a main surface was prepared as a substrate, and a u-GaN layer (thickness: 4 μm, substrate temperature: 1080° C.) was grown on the main surface of the sapphire substrate by MOVPE (MOCVD method is also called MOVPE method because it emphasizes the viewpoint of crystal growth) using an MOCVD apparatus (model SR4338KS) manufactured by Taiyo Nippon Sanso Corporation. + -GaN layer (thickness: 500 nm, Si concentration: 3 × 10 18 cm -3 , substrate temperature: 1120°C), and then an n-GaN layer (thickness: 50 nm, Si concentration: 1.5 × 10) was deposited as an emitter layer on a part of the surface of the contact layer. 18 cm -3 , substrate temperature: 1120°C), a u-GaN layer (thickness: 3 nm, substrate temperature: 950°C) as the emitter-side spacer layer, and a u-Al layer as the intermediate layer. 0.6 Ga 0.4 N layer (thickness: 2 nm, substrate temperature: 950°C), u-AlN layer (thickness: 2 nm, substrate temperature: 950°C) as emitter-side barrier layer, u-GaN layer (thickness: 3 nm, substrate temperature: 950°C) as well layer, u-AlN layer (thickness: 2 nm, substrate temperature: 950°C) as collector-side barrier layer, u-GaN layer (thickness: 3 nm, substrate temperature: 950°C) as collector-side spacer layer, and n-GaN layer (thickness: 50 nm, Si concentration: 1.5 × 10) as collector layer. 18 cm -3 , substrate temperature: 950°C), and n as a contact layer + -GaN layer (thickness: 30 nm, Si concentration: 3 × 10 18 cm -3Furthermore, using an EB evaporation system manufactured by Eiko Engineering Co., Ltd. (owned by the AIST Joint Research and Development Facility, control number NPF023), a Cr / Au layer was formed as a lower emitter electrode on another part of the surface of the contact layer on the sapphire substrate side by vacuum evaporation, and a Cr / Au layer was formed as an upper collector electrode on the surface of the contact layer on the collector layer.

[0076] (Comparative Example) The comparative example is the u-Al intermediate layer of the example. 0.6 Ga 0.4 An RTD having the same configuration as in the example was fabricated, except that the N layer was not formed.

[0077] The voltage-current characteristics of the RTDs of the example and comparative example, i.e., the nonvolatile memory characteristics, were measured using a Keysight Technology semiconductor device evaluation system (Model B2912A). A write operation (a change from low resistance to high resistance) was performed by applying a forward bias (positive voltage) between the lower emitter electrode and the upper collector electrode. After the write operation, an erase operation (a change from high resistance to low resistance) was performed by applying a reverse bias (negative voltage). This write and erase operation was repeated 10 times to evaluate stability. Considering the change in polarization value in each layer of the quantum well structure due to the insertion of an intermediate layer and the resulting changes in the write and erase voltages, the maximum forward bias value was set to 1.5 V and the minimum reverse bias value was set to -3.5 V in the example. On the other hand, the maximum forward bias value and minimum reverse bias value were set to 3.0 V and -3.0 V in the comparative example.

[0078] Fig. 16 is a voltage-current characteristic diagram of the RTD of the example, and Fig. 17 is a voltage-current characteristic diagram of the RTD of the comparative example. In Fig. 16 and Fig. 17, the solid lines show the results of the first measurement, and the dashed lines show the results of the second to tenth repeated measurements. The graph showing the measurement results follows the curve in step 1 when a forward voltage is applied, the curve in step 2 when an applied voltage of 0V is applied, the curve in step 3 when a reverse voltage is applied, and the curve in step 4 when an applied voltage of 0V is applied.

[0079] Referring to FIG. 16, in the example, the voltage-current characteristics of the initial measurement shown by the solid line almost overlap with the voltage-current characteristics of the second to tenth repeated measurements shown by the dashed line, indicating that the write and erase operations were stable.

[0080] Referring to FIG. 17, it was found that in the comparative example, there is a deviation between the voltage-current characteristics of the first measurement shown by the solid line and the voltage-current characteristics of the second to tenth repeated measurements shown by the dashed line. In particular, it is found that the erase voltage in the erase operation of step 3 fluctuates between -1.1V and -2.1V. In contrast, it was found that the erase voltage of the example shown in FIG. 15 fluctuates between -2.7V and -2.8V, which is an extremely smaller fluctuation range than the comparative example. This is because the example has a u-AlN intermediate layer on the emitter electrode side of the u-AlN layer, which is the emitter-side barrier layer. 0.6 Ga 0.4 This is because the N layer prevents electron leakage to the emitter electrode side via the u-AlN layer.

[0081] For example, the present disclosure can also be applied to III-V semiconductors such as GaAs, AlAs, and InP, IV semiconductors such as Si and Ge, and II-VI semiconductors such as ZnO, CdTe, and ZnSe.

[0082] The RTDs according to the first to sixth embodiments can be used as nonvolatile memories. In a write operation, electrons are stored in the quantum well structure by applying a forward bias to the RTD (making the potential on the emitter 14 side higher than that on the collector 16 side). In a memory retention operation, electrons are stored and retained without applying a bias. In an erase operation, electrons are released by applying a reverse bias. This allows the RTD to function as a nonvolatile memory.

[0083] The examples shown in the above embodiments are described to make the invention easier to understand, and the invention is not limited to these forms. [Industrial Applicability]

[0084] This disclosure is expected to enable ultra-high-speed operation in the subpicosecond range, leading to the development of low-loss, low-power nonvolatile memories. It may be possible to achieve high-speed operation equivalent to or even higher than MRAM or FeRAM, making it industrially useful. [Explanation of symbols]

[0085] 10, 20, 30, 40, 50, 60, 70, 80, 100, 110:RTD 11, 12: Barrier layer 13, 808: Well layer 14: Emitter 15, 17, 65, 67: Middle class 16: Collector 18, 48, 61, 88, 105, 115, 814, 914: Quantum well structures 19, 20: Spacer layer 101, 111, 801: PCB 102, 112, 802: Buffer layer or strain relief layer 103, 113, 107, 117, 803, 813: Contact layer 104, 116, 804: Emitter layer 108, 816: Upper collector electrode 109, 815: Lower emitter electrode 118: Upper emitter electrode 119: Lower collector electrode 805: Emitter side spacer layer 806, 809: Middle class 807: Emitter side barrier layer 810: Collector-side barrier layer 811: Collector-side spacer layer 812: Collector layer

Claims

1. A resonant tunneling diode element in which a quantum well structure having an emitter layer, a plurality of barrier layers with a gradient potential, and a well layer present between the plurality of barrier layers, and a collector layer are stacked, the quantum well structure includes an intermediate layer that is in contact with the emitter layer side of the barrier layer that is closest to the emitter layer and has a defect level lower than the defect level of the barrier layer that is closest to the emitter layer.

2. The barrier layer is u-AlN and the intermediate layer is u-AlGaN.

2. The resonant tunneling diode device according to claim 1.

3. 2. The resonant tunneling diode element according to claim 1, wherein the quantum well structure further comprises another intermediate layer in contact with the well layer side of the barrier layer closest to the collector layer and having a defect level lower than the defect level of the barrier layer closest to the collector layer.

4. The barrier layer is u-AlN, and the other intermediate layer is u-AlGaN.

4. The resonant tunneling diode device according to claim 3.

5. 2. The resonant tunneling diode element according to claim 1, wherein the quantum well structure has a periodic structure in which the barrier layers and the well layers are repeatedly stacked, and the barrier layer sandwiched between two of the well layers further comprises another intermediate layer in contact with the emitter layer side and having a defect level lower than a defect level of the barrier layer sandwiched between the two well layers.

6. the barrier layer sandwiched between the two well layers is u-AlN, and the other intermediate layer is u-AlGaN; 6. The resonant tunneling diode device according to claim 5.

7. The intermediate layer, the other intermediate layer, or the further intermediate layer is u-Al １－ｘ Ga ｘ N (x = 0.1 to 0.9), 7. The resonant tunneling diode device according to claim 2, 4 or 6.

8. the resonant tunneling diode element is formed by stacking the emitter layer, the quantum well structure, and the collector layer in this order; further comprising a substrate below the emitter layer; 7. The resonant tunneling diode element according to claim 1, wherein the substrate is a sapphire substrate, a GaN substrate, an AlN substrate, a Si substrate, a SiC substrate, or a diamond substrate.

9. the resonant tunneling diode element is formed by stacking the collector layer, the quantum well structure, and the emitter layer in this order; Further comprising another substrate below the collector layer; The resonant tunneling diode element according to any one of claims 1 to 6, wherein the other substrate is a nitrided sapphire substrate, a SiC substrate having a C (carbon atom) face as its main surface, a GaN substrate having an N (nitrogen atom) face as its main surface, an AlN substrate having an N (nitrogen atom) face as its main surface, or a Si substrate having a SiC thin film laminated thereon and having a C (carbon atom) face as its main surface.

10. A nonvolatile memory comprising the resonant tunneling diode element according to any one of claims 1 to 6.

11. A nonvolatile memory comprising the resonant tunneling diode element according to claim 8.

12. A nonvolatile memory comprising the resonant tunneling diode element according to claim 9.

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