Multilayer ceramic capacitor

Abstract

To provide a highly reliable multilayer ceramic capacitor that is capable of suppressing the generation of electrostriction cracks.SOLUTION: A multilayer ceramic capacitor 1 includes a laminate including a plurality of inner dielectric layers 20i and a plurality of internal electrode layers 30 laminated therein, and external electrodes. As viewed at a cross section parallel to a length direction L and a lamination direction T, each of the inner dielectric layers 20i includes a central region disposed at a central portion in the length direction L and end regions disposed at end portions in the length direction L. When a thickness of each of the inner dielectric layers 20i in the lamination direction T is defined as Td, the central region includes a rectangular region A1 with a dimension in the length direction L of Td / 2 and a dimension in the lamination direction T of Td, and rectangular regions A2 adjacent to the region A1 with a dimension in the length direction L of Td / 2 and a dimension in the lamination direction T of Td. The region A1 has a higher porosity than other regions, and a difference between a porosity P1 in the region A1 and a porosity P2 in each of the regions A2 is 1% or more and 5% or less.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor. [Background technology]

[0002] Conventionally, a multilayer ceramic capacitor includes a laminate in which dielectric layers and internal electrode layers are alternately stacked, with dielectric layers further stacked on the top and bottom surfaces of the laminate, and a pair of external electrodes formed on both end surfaces of the laminate.

[0003] Generally, a multilayer ceramic capacitor is manufactured by alternately stacking ceramic green sheets made of a dielectric ceramic such as barium titanate and unsintered internal electrode layers to form a green chip, firing the green chip, and then forming external electrodes on the end faces of the resulting laminate. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-237137 Summary of the Invention [Problem to be solved by the invention]

[0005] However, when the green chips are fired in the process of manufacturing the laminate, the dielectric ceramic shrinks, causing voids to form in the dielectric layers. Furthermore, because barium titanate is a high-dielectric-constant ceramic, stress is easily applied to the voids due to electrostriction when voltage is applied. If the voids are concentrated in a specific area in the dielectric layer, electrostrictive cracks will occur in that area, deteriorating the insulation resistance of the dielectric layer and reducing the reliability of the multilayer ceramic capacitor.

[0006] An object of the present invention is to provide a highly reliable multilayer ceramic capacitor that suppresses the occurrence of electrostrictive cracks. [Means for solving the problem]

[0007] The present inventors have discovered that the incidence of electrostrictive cracks can be reduced by controlling the distribution of voids in the dielectric layer, and have completed the present invention.

[0008] That is, the present invention provides a laminate including an inner layer portion including a plurality of inner layer dielectric layers and a plurality of internal electrode layers alternately stacked in a stacking direction, and outer layer portions sandwiching the inner layer portion from the stacking direction, the laminate including a first main surface and a second main surface opposing each other in the stacking direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the stacking direction and the width direction; a pair of external electrodes arranged at both ends in the longitudinal direction of the laminate so as to cover at least the first end face and the second end face, respectively, and connected to the internal electrode layers; Equipped with When viewed in a cross section parallel to the length direction and the stacking direction, the inner dielectric layer includes a central region disposed in a central portion in the length direction and end regions disposed at end portions in the length direction, When the thickness of the inner dielectric layer in the stacking direction is Td, the central region includes a rectangular region A1 having a lengthwise dimension of Td / 2 and a stacking direction dimension of Td, and a rectangular region A2 adjacent to the region A1 and having a lengthwise dimension of Td / 2 and a stacking direction dimension of Td, The region A1 has a higher porosity than other regions, In the multilayer ceramic capacitor, the difference between the porosity P1 in the region A1 and the porosity P2 in the region A2 is 1% or more and 5% or less. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide a highly reliable multilayer ceramic capacitor in which the distribution of voids in the dielectric layers is controlled and the occurrence of electrostrictive cracks is suppressed. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a perspective view showing a multilayer ceramic capacitor. [Figure 2] 2 is a cross-sectional view (LT cross section) taken along line II-II of the multilayer ceramic capacitor shown in FIG. [Figure 3] 3 is a cross-sectional view (WT cross section) taken along line III-III of the multilayer ceramic capacitor shown in FIG. [Figure 4] 2 is a schematic diagram showing the structure of an inner layer portion of the multilayer ceramic capacitor shown in FIG. [Figure 5] FIG. 2 is a schematic diagram showing the distribution of voids in a dielectric layer. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the multilayer ceramic capacitor of the present invention will be described, but the present invention is not limited thereto. Furthermore, the drawings may be drawn in a simplified and schematic manner to explain the contents of the invention, and the dimensional ratios of the depicted components or between the components may not match the dimensional ratios of those components described in the specification. Furthermore, components described in the specification may be omitted in the drawings, or the number of components may be omitted.

[0012] (multilayer ceramic capacitors) Fig. 1 is a perspective view showing a multilayer ceramic capacitor, Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 1 taken along line II-II, and Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 1 taken along line III-III. Fig. 4 is a schematic view showing the structure of an inner layer portion of the multilayer ceramic capacitor shown in Fig. 1. The multilayer ceramic capacitor 1 shown in Figs. 1 to 4 includes a laminate 10 and external electrodes 40. The external electrodes 40 include a first external electrode 41 and a second external electrode 42.

[0013] 1 to 3 show an XYZ Cartesian coordinate system. The X direction is the length direction L of the multilayer ceramic capacitor 1 and the laminate 10, the Y direction is the width direction W of the multilayer ceramic capacitor 1 and the laminate 10, and the Z direction is the lamination direction T of the multilayer ceramic capacitor 1 and the laminate 10. Therefore, the cross section shown in FIG. 2 is also called an LT cross section, and the cross section shown in FIG. 3 is also called a WT cross section. The length direction L, width direction W, and stacking direction T do not necessarily have to be perpendicular to each other, and may intersect each other.

[0014] The size of the multilayer ceramic capacitor is preferably such that the length L is 0.2 mm to 10 mm, the width W is 0.1 mm to 10 mm, and the stacking direction T is 0.1 mm to 10 mm.

[0015] (Laminate) The laminate 10 has a substantially rectangular parallelepiped shape and has a first main surface TS1 and a second main surface TS2 facing in the stacking direction T, a first side surface WS1 and a second side surface WS2 facing in the width direction W, and a first end surface LS1 and a second end surface LS2 facing in the length direction L. The surface of each surface may be uneven or may be roughened.

[0016] It is preferable to round the corners and ridges of the laminate 10. A corner is a portion where three faces of the laminate 10 intersect, and a ridge is a portion where two faces of the laminate 10 intersect.

[0017] 2 and 3, the laminate 10 has a plurality of inner dielectric layers 20i and a plurality of internal electrode layers 30 stacked in a stacking direction T. The laminate 10 also has, in the stacking direction T, an inner layer portion 100, and a first outer layer portion 201 and a second outer layer portion 202 arranged to sandwich the inner layer portion 100 therebetween.

[0018] The inner dielectric layer 20i constituting the inner layer portion 100 and the outer dielectric layer 20o constituting the outer layer portion 200 may have different component compositions because the inner layer portion 100 and the outer layer portion 200 are required to have different functions. For example, the inner dielectric layer 20i is required to have a high dielectric constant, and the outer dielectric layer 20o is required to have high moisture resistance, weather resistance, and strength. For this reason, the dielectric layer constituting the inner layer portion 100 will be described as the inner dielectric layer 20i, and the dielectric layer constituting the outer layer portion 200 will be described as the outer dielectric layer 20o, but when there is no need to particularly distinguish between the inner dielectric layer 20i and the outer dielectric layer 20o, they will be collectively described as the dielectric layer 20.

[0019] (inner layer) 4 is a schematic diagram showing the structure of the inner layer portion 100. The inner layer portion 100 includes a plurality of inner dielectric layers 20i and a plurality of internal electrode layers 30. In the inner layer portion 100, the plurality of internal electrode layers 30 are arranged facing each other with the inner dielectric layers 20i interposed therebetween. The inner layer portion 100 is a portion that generates electrostatic capacitance and essentially functions as a capacitor.

[0020] The material of the dielectric layer 20 may be, for example, a dielectric ceramic containing BaTiO3, CaTiO3, SrTiO3, CaZrO3, or the like as a main component. The material of the dielectric layer 20 may also contain a Mn compound, an Fe compound, a Cr compound, a Co compound, a Ni compound, or the like as a secondary component.

[0021] The thickness of the inner dielectric layer 20i is not particularly limited, but is preferably, for example, 0.2 μm or more and 15 μm or less. By reducing the thickness of the inner dielectric layer 20i, the capacitance can be improved.

[0022] (outer layer) The first outer layer portion 201 is disposed on the first main surface TS1 side of the laminate 10, and the second outer layer portion 202 is disposed on the second main surface TS2 side of the laminate 10. More specifically, the first outer layer portion 201 is disposed between the first main surface TS1 and an internal electrode layer 30 of the plurality of internal electrode layers 30 that is closest to the first main surface TS1, and the second outer layer portion 202 is disposed between the second main surface TS2 and an internal electrode layer 30 of the plurality of internal electrode layers 30 that is closest to the second main surface TS2. The first outer layer portion 201 and the second outer layer portion 202 do not include an internal electrode layer 30.

[0023] The outer layer portion 200 is formed of an insulating material. The first outer layer portion 201 and the second outer layer portion 202 can each be composed of multiple outer dielectric layers 20o, or may be composed of a single outer dielectric layer 20o. The outer dielectric layer 20o can be composed of the same type of dielectric material as the inner dielectric layer 20i, or may contain a different component from the inner dielectric layer 20i depending on the desired function.

[0024] The multiple internal electrode layers 30 include multiple first internal electrode layers 31 and multiple second internal electrode layers 32. The multiple first internal electrode layers 31 and the multiple second internal electrode layers 32 are alternately arranged in the stacking direction T of the laminate 10.

[0025] The first internal electrode layer 31 includes a first opposing electrode portion 311 and a first lead electrode portion 312 , and the second internal electrode layer 32 includes a second opposing electrode portion 321 and a second lead electrode portion 322 .

[0026] The first opposing electrode portion 311 and the second opposing electrode portion 321 face each other via the inner dielectric layer 20i in the stacking direction T of the laminate 10. The shapes of the first opposing electrode portion 311 and the second opposing electrode portion 321 are not particularly limited and may be, for example, approximately rectangular. The first opposing electrode portion 311 and the second opposing electrode portion 321 are portions that generate electrostatic capacitance and essentially function as a capacitor.

[0027] The first extraction electrode portion 312 extends from the first opposing electrode portion 311 toward the first end face LS1 of the laminate 10 and is exposed at the first end face LS1. The second extraction electrode portion 322 extends from the second opposing electrode portion 321 toward the second end face LS2 of the laminate 10 and is exposed at the second end face LS2. The lengths in the width direction W of the first opposing electrode portion 311 and the first extraction electrode portion 312 may be the same or different. Furthermore, the lengths in the width direction W of these portions may gradually change toward the exposed first end face LS1. The lengths in the width direction W of the second opposing electrode portion 321 and the second extraction electrode portion 322 may be the same or different. Furthermore, the lengths in the width direction W of these portions may gradually change toward the exposed second end face LS2.

[0028] As a result, the first internal electrode layer 31 is connected to the first external electrode 41, and a gap is provided between the first internal electrode layer 31 and the second end face LS2 of the laminate 10, i.e., the second external electrode 42. In addition, the second internal electrode layer 32 is connected to the second external electrode 42, and a gap is provided between the second internal electrode layer 32 and the first end face LS1 of the laminate 10, i.e., the first external electrode 41.

[0029] The first internal electrode layer 31 and the second internal electrode layer 32 contain metal Ni as a main component. The first internal electrode layer 31 and the second internal electrode layer 32 may contain at least one selected from metals such as Cu, Ag, Pd, Sn, or Au, or alloys containing at least one of these metals, such as Ag-Pd alloys, as a main component or a component other than the main component. Furthermore, the first internal electrode layer 31 and the second internal electrode layer 32 may contain, as a component other than the main component, particles of a dielectric material having the same composition as the ceramic contained in the inner dielectric layer 20i. In this specification, the term "main component metal" refers to the metal component with the highest weight percentage.

[0030] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but is preferably 0.2 μm or more and 2.0 μm or less, and more preferably 0.3 μm or more and 0.35 μm or less. The number of the first internal electrode layer 31 and the second internal electrode layer 32 is also not particularly limited.

[0031] The thicknesses of the inner dielectric layers 20i and the internal electrode layers 30 can be measured by, for example, observing the LT cross section near the center in the width direction of the laminate exposed by polishing with a scanning electron microscope. Each value may be an average value of measurements taken at multiple locations in the length direction, or may be an average value of measurements taken at multiple locations in the stacking direction.

[0032] As shown in FIG. 3 , the laminate 10 has, in the width direction W, an electrode facing portion W30 where the internal electrode layers 30 face each other, and a first side gap portion WG1 and a second side gap portion WG2 arranged to sandwich the electrode facing portion W30. The first side gap portion WG1 is located between the electrode facing portion W30 and the first side surface WS1, and the second side gap portion WG2 is located between the electrode facing portion W30 and the second side surface WS2. More specifically, the first side gap portion WG1 is located between the end of the internal electrode layer 30 on the first side surface WS1 side and the first side surface WS1, and the second side gap portion WG2 is located between the end of the internal electrode layer 30 on the second side surface WS2 side and the second side surface WS2. The first side gap portion WG1 and the second side gap portion WG2 do not include the internal electrode layer 30, but only include the dielectric layer 20. The first side gap portion WG1 and the second side gap portion WG2 are also called W gaps.

[0033] 2, the laminate 10 has, in the longitudinal direction L, an electrode facing portion L30 where the first internal electrode layer 31 and the second internal electrode layer 32 of the internal electrode layer 30 face each other, a first end gap LG1, and a second end gap LG2. The first end gap LG1 is located between the electrode facing portion L30 and the first end face LS1, and the second end gap LG2 is located between the electrode facing portion L30 and the second end face LS2. More specifically, the first end gap LG1 is located between the end of the second internal electrode layer 32 on the first end face LS1 side and the first end face LS1, and the second end gap LG2 is located between the end of the first internal electrode layer 31 on the second end face LS2 side and the second end face LS2. The first end gap LG1 does not include the second internal electrode layer 32 but includes the first internal electrode layer 31 and the inner dielectric layer 20i, while the second end gap LG2 does not include the first internal electrode layer 31 but includes the second internal electrode layer 32 and the inner dielectric layer 20i. The first end gap LG1 is a portion that functions as an extraction electrode portion to the first end face LS1 of the first internal electrode layer 31, and the second end gap LG2 is a portion that functions as an extraction electrode portion to the second end face LS2 of the second internal electrode layer 32. The first end gap LG1 and the second end gap LG2 are also referred to as L gaps.

[0034] The electrode opposing portion L30 is located at the first opposing electrode portion 311 of the first internal electrode layer 31 and the second opposing electrode portion 321 of the second internal electrode layer 32. The first end gap portion LG1 is located at the first lead-out electrode portion 312 of the first internal electrode layer 31, and the second end gap portion LG2 is located at the second end gap portion LG2.

[0035] The thickness of the laminate 10 may be measured, for example, by observing, with a scanning electron microscope, an LT cross section near the center in the width direction of the laminate exposed by polishing, or a WT cross section near the center in the length direction of the laminate exposed by polishing. Each value may also be an average of measurements taken at multiple locations in the length direction or width direction. Similarly, the length of the laminate 10 can be measured by, for example, observing the LT cross section near the center in the width direction of the laminate exposed by polishing with a scanning electron microscope. Each value may also be the average value of measurements taken at multiple locations in the stacking direction. Similarly, the width of the laminate 10 can be measured by, for example, observing a WT cross section of the laminate exposed by polishing near the center in the longitudinal direction with a scanning electron microscope. Each value may also be an average value of measurements taken at multiple locations in the stacking direction.

[0036] (external electrode) The external electrodes 40 include a first external electrode 41 and a second external electrode 42 .

[0037] The first external electrode 41 is disposed on a first end face LS1 of the laminate 10 and is connected to the first internal electrode layer 31. The first external electrode 41 may extend from the first end face LS1 to a portion of the first main face TS1 and a portion of the second main face TS2. The first external electrode 41 may also extend from the first end face LS1 to a portion of the first side face WS1 and a portion of the second side face WS2.

[0038] The second external electrode 42 is disposed on the second end face LS2 of the laminate 10 and is connected to the second internal electrode layer 32. The second external electrode 42 may extend from the second end face LS2 to a portion of the first main face TS1 and a portion of the second main face TS2. The second external electrode 42 may also extend from the second end face LS2 to a portion of the first side face WS1 and a portion of the second side face WS2.

[0039] The first external electrode 41 has a first base electrode layer 415 and a first plating layer 416, and the second external electrode 42 has a second base electrode layer 425 and a second plating layer 426. The first external electrode 41 may be composed of only the first plating layer 416, and the second external electrode 42 may be composed of only the second plating layer 426.

[0040] The first base electrode layer 415 and the second base electrode layer 425 may be fired layers containing a metal and glass. The glass may be a glass component containing at least one selected from B, Si, Ba, Mg, Al, Li, etc. A specific example is borosilicate glass. The metal may contain Cu as a main component. The metal may contain at least one selected from metals such as Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys, as a main component or as a component other than the main component.

[0041] The fired layer is a layer formed by applying a conductive paste containing metal and glass to the laminate by a dipping method and firing the layer. The fired layer may be fired after firing the internal electrode layer or simultaneously with firing the internal electrode layer. The fired layer may also be a multi-layer structure.

[0042] Alternatively, the first base electrode layer 415 and the second base electrode layer 425 may be resin layers containing conductive particles and a thermosetting resin. The resin layers may be formed on the fired layer described above, or may be formed directly on the laminate without forming a fired layer.

[0043] The resin layer is a layer formed by applying a conductive paste containing conductive particles and a thermosetting resin to the laminate by a coating method and then firing the layer. The resin layer may be fired after firing the internal electrode layer or simultaneously with firing the internal electrode layer. The resin layer may also be a multi-layered layer.

[0044] The thickness of each of the first base electrode layer 415 and the second base electrode layer 425 as the fired layer or resin layer is not particularly limited, and may be 2 μm or more and 220 μm or less.

[0045] Alternatively, the first base electrode layer 415 and the second base electrode layer 425 may be thin film layers of 1 μm or less formed by a thin film forming method such as sputtering or vapor deposition, on which metal particles are deposited.

[0046] The first plating layer 416 covers at least a portion of the first base electrode layer 415, and the second plating layer 426 covers at least a portion of the second base electrode layer 425. The first plating layer 416 and the second plating layer 426 include, for example, at least one selected from metals such as Cu, Ni, Ag, Pd, and Au, and alloys such as Ag-Pd alloys.

[0047] The first plating layer 416 and the second plating layer 426 may each be formed of multiple layers. Preferably, they have a two-layer structure of Ni plating and Sn plating. The Ni plating layer can prevent the base electrode layer from being eroded by solder when mounting the ceramic electronic component, and the Sn plating layer improves the wettability of the solder when mounting the ceramic electronic component, facilitating mounting. The first plating layer 416 and the second plating layer 426 may each have a three-layer structure, for example, by stacking Cu plating, Ni plating, and Sn plating. The outermost layer may be Au plating.

[0048] The thickness of each of first plating layer 416 and second plating layer 426 is not particularly limited, and may be 1 μm or more and 10 μm or less.

[0049] (porosity) In the multilayer ceramic capacitor 1 according to the present invention, when viewed in a cross section LT parallel to the longitudinal direction L and the lamination direction T, the inner dielectric layer 20i includes a central region located in the central portion of the longitudinal direction L and end regions located at the ends of the longitudinal direction L. Here, the central region refers to a region located in the center when the electrode facing portion L30 is divided into thirds in the longitudinal direction L. The end regions refer to regions located in ranges excluding the central region when the electrode facing portion L30 is divided into thirds in the longitudinal direction L.

[0050] Assuming that the thickness of the inner dielectric layer 20i in the stacking direction T is Td, the central region of the inner dielectric layer 20i, as shown in FIG. 5, comprises a rectangular region A1 having a dimension in the length direction L of Td / 2 and a dimension in the stacking direction of Td, and a rectangular region A2 adjacent to region A1 and having a dimension in the length direction of Td / 2 and a dimension in the stacking direction T of Td, and region A1 has a higher porosity than the other regions, and the difference between the porosity P1 in region A1 and the porosity P2 in region A2 is 1% or more and 5% or less.

[0051] In the inner dielectric layer 20i, portions where there are many voids P have lower strength than other portions. Therefore, if many voids P exist in locations where electrostrictive stress is concentrated, cracks are likely to occur starting from the voids. In particular, if there are areas within the inner dielectric layer 20i where there is a large difference in density due to the distribution of voids, stress will concentrate in the sparse areas with many voids. As shown in FIG. 5, the multilayer ceramic capacitor according to the present invention comprises, in a central region of the inner dielectric layer 20i, a rectangular region A1 whose dimension in the length direction L is Td / 2 and whose dimension in the stacking direction is Td, and a rectangular region A2 adjacent to the region A1 whose dimension in the length direction L is Td / 2 and whose dimension in the stacking direction T is Td. The difference between the porosity P1 in the region A1 and the porosity P2 in the region A2 is set to be 1% or more and 5% or less, thereby reducing the difference in density of voids and enabling the reduction of the occurrence of electrostrictive cracks. The difference between the porosity P1 and the porosity P2 is set to 1% to 5%, but if it is less than 1%, it is not suitable for mass production depending on the manufacturing conditions, and if it exceeds 5%, the effect of suppressing the occurrence of electrostrictive cracks decreases.

[0052] As shown in Figure 2, when the height of the laminate 10 in the stacking direction T is Ts, it is preferable that the regions A1 and A2 are located within a range of height Ts / 10 at the center of the laminate 10 in the stacking direction T.

[0053] Electrostrictive stress in a multilayer ceramic capacitor tends to concentrate at the center of the laminate 10 in the stacking direction T. For this reason, reducing the density difference due to voids in the inner dielectric layers 20i present within a range of height Ts / 10 located at the center of the laminate 10 in the stacking direction T is effective in reducing the occurrence of electrostrictive cracks. Therefore, in the inner dielectric layer 20i located at the center of the stacking direction T of the laminate 10 and within the range of height Ts / 10, by setting the difference between the porosity P1 of the region A1 and the porosity P2 of the region A2 to 1% or more and 5% or less, the occurrence of electrostrictive cracks can be more efficiently reduced.

[0054] (Porosity measurement) The porosity can be measured by observing the LT cross section of the laminate 10 exposed by polishing at the center in the width direction W with a scanning electron microscope (SEM). The captured SEM image is binarized to identify the voids P. Then, based on the area of ​​the target region in the SEM image and the area of ​​the voids P within the target region, the porosity is calculated using the following formula (1). For example, the observation range is set to 10 μm x 10 μm, and the target region within that range is analyzed to calculate the porosity. Porosity (%) = (area of ​​voids / area of ​​target area) × 100 (1)

[0055] (Manufacturing of multilayer ceramic capacitors) Next, an example of a method for manufacturing a multilayer ceramic capacitor will be described.

[0056] First, ceramic green sheets for forming the dielectric layers and conductive paste for the internal electrodes are prepared. The conductive paste for the internal electrodes contains a binder and a solvent, and known organic binders and organic solvents can be used. The conductive paste for the internal electrodes forms the internal electrodes 53.

[0057] Next, a conductive paste for internal electrodes is printed in a predetermined pattern on the ceramic green sheets by, for example, screen printing or gravure printing, thereby forming an internal electrode pattern.

[0058] Next, a predetermined number of ceramic green sheets for outer layers without internal electrode patterns are stacked, and then ceramic green sheets with internal electrodes formed thereon are stacked in order, and a predetermined number of ceramic green sheets for outer layers are stacked on top of those to produce a laminate sheet. The ceramic green sheets form the dielectric layers 20 that constitute the multilayer ceramic capacitor 1.

[0059] The resulting laminated sheet is pressed in the lamination direction using a means such as a hydrostatic press to produce a laminated block. The laminated block is then cut to a predetermined size to produce laminated chips. At this time, the corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0060] The laminated chip is then fired to produce the laminate 10. The firing temperature at this time depends on the materials of the dielectric and internal electrodes, but is preferably 900°C or higher and 1300°C or lower.

[0061] The laminated chip is fired by applying pressure from the center to both ends of the laminated chip. The distribution of voids in the dielectric layer is controlled by adjusting the pressure applied to the laminated chip, the moving speed of the pressure application point, the firing temperature, and the firing time.

[0062] Next, the first end surface LS1 of the laminate 10 is immersed in a conductive paste, which is an electrode material for the base electrode layer, using a dipping method, to apply the conductive paste for the first base electrode layer 415 to the first end surface LS1. Similarly, the second end surface LS2 of the laminate 10 is immersed in a conductive paste, which is an electrode material for the base electrode layer, using a dipping method, to apply the conductive paste for the second base electrode layer 425 to the second end surface LS2. These conductive pastes are then fired to form the first base electrode layer 415 and the second base electrode layer 425, which are fired layers. The firing temperature is preferably 600°C or higher and 900°C or lower.

[0063] As described above, the first base electrode layer 415 and the second base electrode layer 425, which are resin layers, may be formed by applying a conductive paste containing conductive particles and a thermosetting resin by a coating method and then firing the paste, or the first base electrode layer 415 and the second base electrode layer 425, which are thin films, may be formed by a thin film formation method such as a sputtering method or a vapor deposition method.

[0064] Thereafter, a first plating layer 416 is formed on the surface of the first base electrode layer 415 to form the first external electrode 41, and a second plating layer 426 is formed on the surface of the second base electrode layer 425 to form the second external electrode 42. Through the above steps, the multilayer ceramic capacitor 1 is obtained. [Example]

[0065] Electrostriction test (crack detection evaluation) An electrostriction test was carried out on the multilayer ceramic capacitor. Following the manufacturing method described above, samples were manufactured in lots with manufacturing conditions adjusted to vary the void distribution as samples for each experimental level. Samples within each lot were manufactured with the same design and under the same manufacturing conditions. For each experimental level (five chip sizes x four levels), 20 samples for porosity measurement and 100 samples for electrostriction testing were taken from the same lot and prepared. The average value of the porosity measurement results was used for evaluation.

[0066] The electrostriction test of the multilayer ceramic capacitor was carried out using a BDV device by increasing the voltage up to DC 150V at a voltage increase rate of 100V / sec. The samples were evaluated by observing the presence or absence of cracks using an ultrasonic flaw detector. Specifically, first, the multilayer ceramic capacitor samples were aligned so that their main surfaces faced upward. Next, ultrasonic waves were irradiated onto the top surface of the aligned multilayer ceramic capacitors using an ultrasonic probe, and the presence or absence of cracks was confirmed by observing the reflected waves of the ultrasonic waves and detecting the reflected waves that returned earlier than the bottom waves. Here, the products in which cracks were confirmed were counted as electrostrictively defective, and the crack occurrence rate was calculated using the number of samples from the same lot, n=100, as the parameter.

[0067] The evaluation criteria were as follows: a crack occurrence rate of 10% or less was ◯ (pass), and a crack occurrence rate of more than 10% was × (fail). The results are shown in Table 1.

[0068] [Table 1]

[0069] As shown in Table 1, it was confirmed that good results were obtained when the difference between the porosity P1 in the region A1 and the porosity P2 in the region A2 was 1% or more and 5% or less.

[0070] Although the embodiments of the present invention have been described above, the present invention is not limited to the embodiments, and can be embodied in various forms without departing from the gist of the present invention. [Explanation of symbols]

[0071] 1. Multilayer ceramic capacitors 10 Laminate 20 dielectric layer 30 Internal electrode layer 31 First internal electrode layer 311 first opposing electrode portion 312 first extraction electrode part 32 Second internal electrode layer 321 Second opposing electrode section 322 Second extraction electrode part 40 External electrode 41 First external electrode 415 First base electrode layer 416 First plating layer 42 Second external electrode 425 Second base electrode layer 426 Second plating layer 100 Inner layer 200 Outer layer 201 First Outer Layer 202 Second Outer Layer P void L30 Electrode facing part LG1 First end gap LG2 Second end gap W30 Electrode facing part WG1 First side gap WG2 Second side gap L lengthwise T Stacking direction W width direction LS1 First end face LS2 Second end face TS1 First principal surface TS2 Second principal surface WS1 First Aspect WS2 Second Aspect

Claims

1. a laminate including an inner layer portion including a plurality of inner layer dielectric layers and a plurality of internal electrode layers alternately stacked in a stacking direction, and outer layer portions sandwiching the inner layer portion from the stacking direction, the laminate having a first main surface and a second main surface opposing each other in the stacking direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the stacking direction and the width direction; a pair of external electrodes disposed at both ends in the longitudinal direction of the laminate so as to cover at least the first end face and the second end face, respectively, and connected to the internal electrode layers; Equipped with When viewed in a cross section parallel to the length direction and the stacking direction, the inner dielectric layer includes a central region disposed in a central portion in the length direction and end regions disposed at end portions in the length direction, When the thickness of the inner dielectric layer in the stacking direction is Td, the central region includes a rectangular region A1 having a lengthwise dimension of Td / 2 and a stacking direction dimension of Td, and a rectangular region A2 adjacent to the region A1 and having a lengthwise dimension of Td / 2 and a stacking direction dimension of Td, The region A1 has a higher porosity than other regions, A multilayer ceramic capacitor, wherein a difference between a porosity P1 in the region A1 and a porosity P2 in the region A2 is 1% or more and 5% or less.

2. When the height of the laminate in the stacking direction is Ts, 2. The multilayer ceramic capacitor according to claim 1, wherein the region A1 and the region A2 are present within a range of height Ts / 10 located at the center of the laminate in the lamination direction.

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