Receiving circuit, semiconductor device, and display device

Abstract

To provide a receiving circuit that enables an increase in a data transfer rate via serial communication.SOLUTION: A receiving circuit (10Y) includes a first receiving unit (RX) configured to have serial data inputted, a second receiving unit (RX_CLK) configured to have an input clock inputted, a serial / parallel conversion unit (1) configured to perform serial / parallel conversion on a data signal (DT) output from the first receiving unit based on a clock signal (CLK) output from the second receiving unit, a first transmission circuit (3) arranged between the first receiving unit and a data input end of the serial / parallel conversion unit, and a second transmission circuit (40) arranged between the second receiving unit and a clock input end of the serial / parallel conversion unit and having the same circuit configuration as a circuit included in the first transmission circuit.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to a receiving circuit. [Background technology]

[0002] BACKGROUND ART Conventionally, a receiving circuit capable of receiving serial data using differential signals is known (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-144392

[0004] [overview] There is a demand for a serial interface with a higher data transfer rate.

[0005] In view of the above circumstances, an object of the present disclosure is to provide a receiving circuit that enables an increase in the data transfer rate through serial communication.

[0006] A receiving circuit according to one aspect of the present disclosure includes: a first receiving unit configured to receive serial data; a second receiving unit configured to receive an input clock; a serial / parallel conversion unit configured to serially / parallel convert the data signal output from the first receiving unit based on the clock signal output from the second receiving unit; a first transmission circuit disposed between the first receiving unit and a data input terminal of the serial / parallel conversion unit; a second transmission circuit that is arranged between the second receiving unit and a clock input terminal of the serial / parallel conversion unit and has the same circuit configuration as the circuit included in the first transmission circuit; The configuration is provided with the following. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing a signal transmission system using LVDS. [Figure 2] FIG. 2 is a diagram illustrating an example of the configuration of a receiving circuit. [Figure 3] FIG. 3 is a diagram illustrating a configuration of a receiving circuit according to a comparative example. [Figure 4] FIG. 4 is a diagram showing an example of the waveform of a signal on each transmission path in FIG. [Figure 5] FIG. 5 is a graph showing an example of variations in delay difference in a configuration according to a comparative example. [Figure 6] FIG. 6 is a diagram for explaining the necessary variations in delay difference. [Figure 7] FIG. 7 is a diagram illustrating a configuration of a receiving circuit according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a graph showing an example of the variation in delay difference in the configuration according to the embodiment of the present disclosure. [Figure 9] FIG. 9 is a diagram illustrating an example of the configuration of a data transmission circuit. [Figure 10] FIG. 10 is a diagram illustrating an example of the configuration of a clock transmission circuit. [Figure 11] FIG. 11 is a block diagram showing an example of the overall configuration of a display device. [Figure 12] FIG. 12 is a diagram showing an example of the configuration of a panel driving device. [Figure 13] FIG. 13 is an external view showing an example of an in-vehicle display.

[0008] [Detailed explanation] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0009] <LVDS(Low Voltage Differential Signaling)> Here we will explain about LVDS. LVDS is a high-speed serial communication technology that transmits signals using small amplitude differential signals. Because signals are transmitted using small amplitude differential signals, it is resistant to EMI (Electromagnetic Interference) and EMS (Electromagnetic Susceptibility). LVDS is used, for example, for image transfer.

[0010] Figure 1 shows a signal transmission system using LVDS. A small-amplitude differential signal output from a transmitter (TX) is sent to a receiver (RX) via a transmission path (TP) (such as a twisted pair cable) and amplified by the receiver (RX).

[0011] <Receiving circuit> Next, the configuration of a receiving circuit using an LVDS interface will be described. Fig. 2 is a diagram showing an example of the configuration of a receiving circuit. The receiving circuit 10 shown in Fig. 2 includes receiving units RX1 to RX4, a receiving unit RX_CLK, a serial / parallel conversion unit 1, and a DLL (Delay Locked Loop) 2.

[0012] The receiving circuit 10 is provided with four LVDS data transmission paths and one LVDS clock transmission path. Receiving units RX1 to RX4 are provided for each of the data transmission paths. The receiving units RX1 to RX4 respectively amplify the input small amplitude differential signals and output data signals DT1 to DT4. The clock transmission path is provided with a receiving unit RX_CLK. The receiving unit RX_CLK amplifies the input small amplitude differential signals and output a clock signal CLK. Note that in the case of image transfer using LVDS, the number of data transmission paths is limited to four, but is not limited to four in other cases.

[0013] The serial / parallel conversion unit 1 is a circuit that converts data signals DT1 to DT4, which are input as serial data, into parallel data PDT. The serial / parallel conversion unit 1 has flip-flop groups FF1 to FF4. Each of the flip-flop groups FF1 to FF4 is provided corresponding to each of the data signals DT1 to DT4. Each of the flip-flop groups FF1 to FF4 has A D flip-flops. Each of the data signals DT1 to DT4 has A pieces of data in one cycle of the clock signal CLK, so A D flip-flops are provided to capture each of the A pieces of data.

[0014] DLL2 is a type of phase-locked loop circuit that delays the input clock signal CLK and outputs a delayed clock signal DLY_CLK. The delay time between the delayed clock signal DLY_CLK and the clock signal CLK is controlled to be a predetermined delay time. A delayed clock signals DLY_CLK are output. The A delayed clock signals DLY_CLK have different delay times. Each of the A delayed clock signals DLY_CLK is commonly input to the clock terminal of a corresponding D flip-flop in each of the flip-flop groups FF1 to FF4. More specifically, the delayed clock signal DLY_CLK with the shortest delay time among the A delayed clock signals DLY_CLK is input to the D flip-flop corresponding to the earliest data in each of the data signals DT1 to DT4, and the delayed clock signal DLY_CLK with the next shortest delay time is input to the D flip-flop corresponding to the next earliest data in each of the data signals DT1 to DT4, and so on up to the delayed clock signal DLY_CLK with the longest delay time.

[0015] The data captured by each of the flip-flop groups FF1 to FF4 is output as B-bit parallel data PDT, where B = A × 4. For example, if the A-bit serial data is 7 bits, the parallel data PDT will be B = 28 bits.

[0016] <Comparative Example> FIG. 3 is a diagram showing the configuration of a receiving circuit 10X according to a comparative example. The receiving circuit 10X is provided with a transmission circuit 3 and a buffer 4. The transmission circuit 3 is provided between a data receiving unit RX and a data input terminal of a serial / parallel conversion unit 1. Note that in FIG. 3, the receiving unit RX representatively shows the receiving units RX1 to RX4. That is, a transmission circuit 3 is provided for each of the receiving units RX1 to RX4. The buffer 4 is provided between the DLL2 and the clock input terminal of the serial / parallel conversion unit 1. A buffer 4 is provided for each of the A delayed clock signals DLY_CLK.

[0017] 4 is a diagram showing example waveforms of signals on transmission paths (A), (B), and (C). Transmission path (A) is located upstream of the receiving unit RX and receiving unit RX_CLK. In FIG. 4, example waveforms of input data DATA and input clock IN_CLK, which are small-amplitude differential signals, are shown as signals on transmission path (A). In one cycle of the input clock IN_CLK, the input data DATA includes data D0 to D6 (7 bits of data).

[0018] 4 shows example waveforms of data signal DT and clock signal CLK as signals on transmission path (B). Also shown are example waveforms of delayed clock signals DLY_CLK1 to DLY_CLK7 as signals on transmission path (C). Delayed clock signals DLY_CLK1 to DLY_CLK7 are each provided with a predetermined delay time relative to clock signal CLK and correspond to data D0 to D6, respectively. The delay time gradually increases from delayed clock signal DLY_CLK1 to DLY_CLK7 so that the rising edge of each delayed clock signal DLY_CLK1 to DLY_CLK7 is positioned at the center of each data D0 to D6.

[0019] Since DLL2 itself generates a signal delay in addition to the delay controlled by DLL2, a skew circuit is included in transmission circuit 3 to delay the signal by the delay time of DLL2. Buffer 4 is also used to shape the waveform into a square wave. Transmission circuit 3 is configured with a skew circuit and other components so that the delay time of transmission circuit 3 matches the sum of the delay time caused by the signal delay of DLL2 itself and the delay time caused by the signal delay of buffer 4.

[0020] Therefore, the difference (delay difference) between the delay time in the transmission circuit 3 and the sum of the delay time due to the signal delay of the DLL 2 itself and the delay time due to the signal delay in the buffer 4 is ideally zero. However, in reality, this delay difference varies due to variations in devices, temperature, voltage, and the like. FIG. 5 shows an example of the variation in the delay difference in a configuration according to a comparative example. In the graph of FIG. 5, the horizontal axis shows the delay difference of the rising edge, and the vertical axis shows the delay difference of the falling edge (this also applies to FIG. 8, which will be described later). In the example shown in FIG. 5, a maximum delay difference of approximately 125 ps occurs. In the configuration according to the comparative example (FIG. 3), the transmission circuit 3 and buffer 4 have different circuit configurations, resulting in greater variation in the delay difference.

[0021] As shown in Figure 6, the data width of 1 bit contained in the input data DATA is 1190 ps when the frequency of the input clock CLK is, for example, 120 kHz. However, when the input timing specifications are taken into account, for example, when Setup / Hold is ±300 ps, ​​the data width of 1 bit is effectively 590 ps, ​​and the delay difference between the data and clock from the input to the receiver circuit 10 to the serial / parallel converter 1 (excluding the delay time controlled by the DLL) must be kept to ±295 ps (=590 / 2). Note that there is almost no delay difference between the transmission paths (A) and (B) in Figure 3 because the receivers RX and RX_CLK have the same circuit configuration.

[0022] <Embodiments of the present disclosure> 7 is a diagram showing the configuration of a receiver circuit 10Y according to an embodiment of the present disclosure. The receiver circuit 10Y according to this embodiment differs from the comparative example (FIG. 3) in that a transmission circuit 40 is provided instead of the buffer 4. The transmission circuit 40 has the same circuit configuration as the circuit included in the transmission circuit 3, and is a replica circuit of the transmission circuit 3, so to speak.

[0023] As a result, the difference between the delay in transmission circuit 3 and the delay in transmission circuit 40 is ideally 0. Therefore, the delay difference between the data and clock from the input of receiving circuit 10Y to serial / parallel conversion unit 1 (excluding the delay time controlled by the DLL) is ideally the delay time of DLL 2 itself and will not be 0, but because transmission circuit 3 and transmission circuit 40 have the same circuit configuration, the delay time varies in the same direction, making it possible to suppress the variation in the delay difference.

[0024] Figure 8 shows an example of the variation in the delay difference in the receiver circuit 10Y. In the example shown in Figure 8, a maximum delay difference of about 35 ps occurs, and the variation in the delay difference is suppressed. This reduces the data width of 1 bit included in the input data DATA, which contributes to increasing the data transfer speed.

[0025] 9 is a diagram showing an example of the configuration of the transmission circuit 3. The transmission circuit 3 shown in FIG.

[0026] The test and skew select circuit 31 has NAND circuits 311 to 314. Input signals IN1 to IN4 are input to first input terminals of the NAND circuits 311 to 314, respectively. A data signal DT output from the receiver RX (FIG. 7) is commonly input to second input terminals of the NAND circuits 311 to 314.

[0027] The skew adjustment unit 32 has inverter stages 321 to 324. The inverter stages 321 to 324 are provided after the NAND circuits 311 to 314, respectively. The number of inverter stages 321 to 324 is 0, 2, 4, and 6, respectively.

[0028] The selector 33 has NAND circuits 331 and 332, inverters 333 and 334, a NAND circuit 335, and inverters 336 and 337. The output of the inverter stage 321 is input to a first input terminal of the NAND circuit 331, and the output of the inverter stage 322 is input to a second input terminal of the NAND circuit 331. An inverter 333 is provided downstream of the NAND circuit 331. The output of the inverter stage 323 is input to a first input terminal of the NAND circuit 332, and the output of the inverter stage 324 is input to a second input terminal of the NAND circuit 332. An inverter 334 is provided downstream of the NAND circuit 332. The output of the inverter 333 is input to a first input terminal of the NAND circuit 335, and the output of the inverter 334 is input to a second input terminal of the NAND circuit 335. An inverter 336 is provided downstream of the NAND circuit 335. An inverter 337 is provided downstream of the inverter 336 .

[0029] In the test and skew select circuit 31, the number of inverter stages in the skew adjuster 32 can be selected depending on the levels of the input signals IN1 to IN4. Specifically, of the input signals IN1 to IN4, the input signal corresponding to the inverter stage 321 to 324 to be selected is set to high level, and the others are set to low level. At this time, the selector 33 selects the signal output from the inverter stage to be selected and outputs it from the inverter 337.

[0030] 10 is a diagram showing an example of the configuration of a transmission circuit 40. The transmission circuit 40 includes a NAND circuit 401 corresponding to the NAND circuit 313, an inverter stage 402 corresponding to the inverter stage 323, and a NAND circuit 403, an inverter 404, a NAND circuit 405, and inverters 406 and 407 corresponding to the NAND circuit 332, inverter 334, NAND circuit 335, and inverters 336 and 337 in the selector 33. Note that input signals IN11 to IN13 input to the first input terminals of the NAND circuits 401, 403, and 405 are fixed to a high level. A delayed clock signal DLY_CLK output from the DLL2 is input to the second input terminal of the NAND circuit 401. In this way, the transmission circuit 40 is composed only of circuits having the same circuit configuration as the circuit passing through the inverter stage 323, which serves as the reference in the transmission circuit 3 (the path selected by the input signal IN3). Depending on the application, a time difference may be intentionally set between the data signal and the clock signal, and in consideration of such a case, the transmission circuit 3 is made capable of selecting a path other than the standard path using the input signals IN1, IN2, and IIN4.

[0031] <Examples of applicable applications> The receiver circuit 10Y according to this embodiment can be applied to a variety of applications, but a display device will be described as an example. Fig. 11 is a block diagram showing the overall configuration of a display device 400. The display device 400 of this configuration example includes a panel drive device 100, a display panel 200, and a host controller 300.

[0032] The panel driving device 100 controls the driving of the display panel 200 based on image data (=grayscale data) and control commands input from the host controller 300.

[0033] The display panel 200 is a video output means that uses liquid crystal elements or organic EL (electro-luminescence) elements as pixels, and is driven by the panel driving device 100.

[0034] The host controller 300 is a main body that comprehensively controls the operation of the display device 400, and for example, sends image data and control commands to the panel drive device 100. As the host controller 300, an MPU (micro processing unit) or the like can be suitably used.

[0035] 12 is a diagram showing an example configuration of a panel driving device 100. The panel driving device 100 is a semiconductor device that has an LVDS receiver 100A, an RGB interface 100B, an HSIF controller 100C, a timing controller 100D, a data latch unit 100E, a source DAC (DA converter) 100F, a source driver 100G, and a gate driver 100H integrated together.

[0036] The LVDS receiver 100A is a circuit that receives image data and control commands in LVDS format from the outside and corresponds to the receiving circuit 10Y described above. The RGB interface 100B receives image data in RGB format from the outside. The HSIF controller 100C receives image data from the LVDS receiver 100A or the RGB interface 100B.

[0037] The timing controller 100D performs various data processing (such as rearranging image data) and various timing controls (such as horizontal synchronization control for sources and vertical synchronization control for gates) based on control commands stored in a command register (not shown).

[0038] The data latch unit 100E latches image data from the HSIF controller 100C under the control of the timing controller 100D, and outputs a data signal to the source DAC 100F. The source DAC 100F converts the data signal from a digital signal to an analog signal and outputs it to the source driver 100G. The source driver 100G outputs a source signal based on the analog signal from the source DAC 100F. If the display panel 200 is an active matrix liquid crystal display panel, the source signal is supplied to the source terminals of active elements (e.g., TFTs (thin film transistors)) connected to the liquid crystal elements of each column.

[0039] The gate driver 100H outputs gate signals based on a vertical synchronization signal input from the timing controller 100D. If the display panel 200 is an active matrix liquid crystal display panel, the gate signals are supplied to gate terminals of active elements (e.g., TFTs) connected to the liquid crystal elements in each row.

[0040] The receiving circuit 10Y is not limited to such a panel driving device, but can also be applied to various semiconductor devices.

[0041] <In-vehicle display> The display device 400 described above is particularly suitable for application to an in-vehicle display. The in-vehicle display is provided on the dashboard in front of the driver's seat of a vehicle X, for example, like in-vehicle displays X1 to X3 shown in FIG.

[0042] For example, the in-vehicle display X1 functions as an instrument panel (instrument panel attached to the dashboard) that displays a speedometer, tachometer, etc. The in-vehicle display X2 displays a fuel gauge, a fuel consumption meter, a shift position, etc. The in-vehicle display X3 has a navigation function that displays the current location information of the vehicle, route information to the destination, etc., and also has a back monitor function that displays a captured image of the area behind the vehicle.

[0043] However, the application of the display device 400 is not limited to this, and it can be applied to various applications (consumer equipment, industrial equipment, etc.).

[0044] <Other> In addition to the above-described embodiments, various modifications can be made to the various technical features disclosed in this specification without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0045] <Additional Notes> As described above, the receiving circuit (10Y) according to one embodiment of the present disclosure includes: a first receiving unit (RX) configured to receive serial data; a second receiving unit (RX_CLK) configured to receive an input clock; a serial / parallel conversion unit (1) configured to serially / parallel convert a data signal (DT) output from the first receiving unit based on a clock signal (CLK) output from the second receiving unit; a first transmission circuit (3) disposed between the first receiving unit and a data input terminal of the serial / parallel conversion unit; The configuration includes a second transmission circuit (40) that is arranged between the second receiving unit and the clock input terminal of the serial / parallel conversion unit and has the same circuit configuration as the circuit included in the first transmission circuit (first configuration).

[0046] With this configuration, the delay times in the first transmission circuit and the second transmission circuit vary in the same direction, which reduces the relative variation in the delay difference between the data and the clock, contributing to faster serial data transfer speeds.

[0047] In addition, the first configuration may further include a DLL (2) configured to receive the clock signal (CLK) and output a delayed clock signal (DLY_CLK), and the second transmission circuit may be configured to be disposed between the DLL and the clock input terminal (second configuration).

[0048] In the first or second configuration, the first transmission circuit has a skew adjustment unit (32) configured to adjust a delay time, The second transmission circuit may have a circuit having the same circuit configuration as a circuit included in the skew adjustment unit (third configuration).

[0049] In the third configuration, the skew adjustment unit may have circuits (321 to 324) with different selectable delay times (fourth configuration).

[0050] In the fourth configuration, the circuits with different delay times may be inverter stages (321 to 324) with different numbers of stages (fifth configuration).

[0051] In the fourth or fifth configuration, the first transmission circuit a test and skew select circuit (31) provided upstream of the skew adjustment unit and configured to perform testing and select inputs to the circuits with different delay times; A selector (33) may be provided downstream of the skew adjustment unit and configured to select outputs from the circuits with different delay times (sixth configuration).

[0052] In addition, in any of the fourth to sixth configurations, the second transmission circuit may be configured to have only the same circuit configuration as the circuit through which a reference circuit (323) among the circuits with different delay times passes from the input to the output of the first transmission circuit (seventh configuration).

[0053] In addition, in any of the above first to seventh configurations, the first receiving unit and the second receiving unit may be configured to receive the serial data or the input clock as a differentially amplified signal, respectively (eighth configuration).

[0054] In the eighth configuration, the differentially amplified signal may be LVDS (ninth configuration).

[0055] Moreover, a semiconductor device (100) according to an aspect of the present disclosure includes a receiving circuit having any one of the first to ninth configurations (tenth configuration).

[0056] In addition, in the tenth configuration, the semiconductor device may be configured as a panel driving device configured to drive a display panel (200) (eleventh configuration).

[0057] A display device (400) according to an aspect of the present disclosure includes the semiconductor device of the eleventh configuration and the display panel (twelfth configuration).

[0058] The display device in the twelfth configuration may be mounted on a vehicle (thirteenth configuration). [Industrial Applicability]

[0059] The present disclosure can be used, for example, in semiconductor devices for various applications. [Explanation of symbols]

[0060] 1 Parallel conversion section 3 Transmission circuit 4 Buffer 10, 10X, 10Y receiving circuit 31 Test and skew select circuit 32 SKEW adjustment section 33 Selector 40 Transmission Circuit 100 Panel drive unit 100A LVDS Receiver 100B RGB interface 100C HSIF Controller 100D Timing Controller 100E Data latch section 100G Source Driver 100H Gate Driver 200 Display Panel 300 Host Controller 311~314 NAND circuit 321~324 Inverter stage 331,332 NAND circuit 333,334 Inverter 335 NAND circuit 336,337 Inverter 400 display device 401 NAND circuit 402 inverter stage 403 NAND circuit 404 Inverter 405 NAND circuit 406,407 Inverter FF1~FF4 flip-flops RX receiver RX1~RX4 receiver TP transmission line TX transmitter X vehicle X1~X3 in-car displays

Claims

1. a first receiving unit configured to receive serial data; a second receiving unit configured to receive an input clock; a serial / parallel conversion unit configured to serially / parallel convert the data signal output from the first receiving unit based on the clock signal output from the second receiving unit; a first transmission circuit disposed between the first receiving unit and a data input terminal of the serial / parallel conversion unit; a second transmission circuit arranged between the second receiving unit and a clock input terminal of the serial / parallel conversion unit, the second transmission circuit having the same circuit configuration as the circuit included in the first transmission circuit; A receiving circuit comprising:

2. 2. The receiving circuit according to claim 1, further comprising a DLL configured to receive the clock signal and output a delayed clock signal, wherein the second transmission circuit is disposed between the DLL and the clock input terminal.

3. the first transmission circuit has a skew adjustment unit configured to adjust a delay time; The receiving circuit according to claim 1 , wherein the second transmission circuit has a circuit having the same circuit configuration as a circuit included in the skew adjustment unit.

4. The receiver circuit according to claim 3 , wherein the skew adjustment unit has a circuit in which the selectable delay times are different.

5. 5. The receiving circuit according to claim 4, wherein the circuits with different delay times are inverter stages with different numbers of stages.

6. The first transmission circuit is a test and skew select circuit provided upstream of the skew adjustment unit and configured to perform a test and select an input to the circuits having different delay times; a selector provided downstream of the skew adjustment unit and configured to select outputs from the circuits with different delay times; 5. The receiving circuit of claim 4, comprising:

7. 5. The receiving circuit according to claim 4, wherein the second transmission circuit has only the same circuit configuration as a circuit that passes through a reference circuit among the circuits with different delay times from the input to the output of the first transmission circuit.

8. 2. The receiving circuit according to claim 1, wherein the first receiving unit and the second receiving unit are configured to receive the serial data or the input clock as a differentially amplified signal, respectively.

9. 9. The receiving circuit according to claim 8, wherein the differentially amplified signal is LVDS.

10. A semiconductor device comprising the receiving circuit according to claim 1 .

11. The semiconductor device according to claim 10 , configured as a panel driver configured to drive a display panel.

12. A display device comprising: the semiconductor device according to claim 11; and the display panel.

13. The display device according to claim 12, which is for use in a vehicle.

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