Semiconductor device

Abstract

To provide a semiconductor device capable of reducing the amount of warpage.SOLUTION: A semiconductor device includes a semiconductor substrate and a multilayer wiring layer disposed on the semiconductor substrate. The semiconductor substrate includes, in plan view, a coil region and a peripheral region surrounding the coil region. The multilayer wiring layer includes a first coil, a second coil, a third coil, a fourth coil, and a metal film. The multilayer wiring layer includes a plurality of wiring layers. The first coil and the second coil are formed in a first wiring layer that is one of the plurality of wiring layers disposed on the coil region. The third coil and the fourth coil are formed in a second wiring layer that is another one of the plurality of wiring layers disposed on the coil region. The second wiring layer is disposed above the first wiring layer. The third coil and the fourth coil are disposed so as to face the first coil and the second coil, respectively.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] International Publication No. 2014 / 097425 (Patent Document 1) describes a semiconductor device. The semiconductor device described in Patent Document 1 has multiple transformers. Each transformer is composed of coils that face each other with an insulating layer interposed between them. Each of the multiple transformers forms a channel for transmitting and receiving signals. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2014 / 097425 Summary of the Invention [Problem to be solved by the invention]

[0004] The semiconductor device described in Patent Document 1 may have a large amount of warpage. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0005] The semiconductor device of the present disclosure includes a semiconductor substrate and a multilayer wiring layer disposed on the semiconductor substrate. The semiconductor substrate has, in a plan view, a coil region and a peripheral region surrounding the coil region. The multilayer wiring layer includes a first coil, a second coil, a third coil, and a fourth coil, and a metal film. The multilayer wiring layer includes multiple wiring layers. The first coil and the second coil are formed in a first wiring layer, which is one of the multiple wiring layers disposed above the coil region. The third coil and the fourth coil are formed in a second wiring layer, which is another of the multiple wiring layers disposed above the coil region. The second wiring layer is disposed in a layer above the first wiring layer. The third coil and the fourth coil are disposed to face the first coil and the second coil, respectively. The distance between the upper surface of the first wiring layer and the lower surface of the second wiring layer is a first distance. The metal film is formed in each of the multiple wiring layers disposed above the peripheral region so as to be spaced apart from the third coil and the fourth coil by at least the first distance in a cross-sectional view. [Effects of the Invention]

[0006] According to the semiconductor device of the present disclosure, it is possible to reduce the amount of warpage. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 2 is a block diagram of a semiconductor device DEV1. [Figure 2] 10 is an explanatory diagram showing an example of signal transmission from a control circuit CC to a drive circuit DR. FIG. [Figure 3] FIG. 2 is a first plan view of the semiconductor chip CHP3. [Figure 4] FIG. 2 is a second plan view of the semiconductor chip CHP3. [Figure 5] FIG. 10 is a third plan view of the semiconductor chip CHP3. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8] 10A to 10C are manufacturing process diagrams of the semiconductor chip CHP3. [Figure 9] FIG. 10 is a cross-sectional view illustrating an interlayer insulating film forming step S2. [Figure 10] FIG. 10 is a cross-sectional view illustrating a contact plug forming step S3. [Figure 11] FIG. 10 is a cross-sectional view illustrating a wiring forming step S4. [Figure 12] FIG. 10 is a cross-sectional view illustrating an interlayer insulating film forming step S5. [Figure 13] FIG. 10 is a cross-sectional view illustrating a via plug forming step S6. [Figure 14] FIG. 10 is a cross-sectional view illustrating a wiring forming step S7. [Figure 15] FIG. 10 is a cross-sectional view illustrating a passivation film forming step S8. [Figure 16] 1 is a schematic graph showing the amount of wafer warpage in Sample 1 and Sample 2 as the manufacturing process progresses. [Figure 17] 10 is a schematic graph showing the relationship between the number of wiring layers WL and the amount of wafer warpage. [Figure 18] FIG. 10 is a plan view of a semiconductor chip CHP3 included in the semiconductor device DEV2. [Figure 19] 19 is a cross-sectional view taken along line XIX-XIX in FIG. 18. [Figure 20] FIG. 19 is a first cross-sectional view taken along the line XX-XX in FIG. [Figure 21] 10 is a first cross-sectional view illustrating a singulation step S10 for a semiconductor chip CHP3 included in the semiconductor device DEV2. FIG. [Figure 22] 10 is a second cross-sectional view illustrating the singulation step S10 of the semiconductor chip CHP3 of the semiconductor device DEV2. FIG. [Figure 23] FIG. 10 is a plan view of a semiconductor chip CHP3 included in the semiconductor device DEV3. DETAILED DESCRIPTION OF THE INVENTION

[0008] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant descriptions will not be repeated.

[0009] (First embodiment) A semiconductor device according to the first embodiment will be described below. The semiconductor device according to the first embodiment is referred to as semiconductor device DEV1.

[0010] (Configuration of semiconductor device DEV1) The configuration of the semiconductor device DEV1 will be described below.

[0011] <Schematic configuration of semiconductor device DEV1> The schematic configuration of the semiconductor device DEV1 will be described below.

[0012] Fig. 1 is a block diagram of the semiconductor device DEV1. As shown in Fig. 1, the semiconductor device DEV1 has a semiconductor chip CHP1, a semiconductor chip CHP2, and a semiconductor chip CHP3.

[0013] The semiconductor chip CHP1 has a control circuit CC, a transmitter circuit TX1, and a receiver circuit RX2, and the semiconductor chip CHP2 has a driver circuit DR, a receiver circuit RX1, and a transmitter circuit TX2. The transmitter circuit TX1 and the receiver circuit RX2 are electrically connected to the control circuit CC. The receiver circuit RX1 and the transmitter circuit TX2 are electrically connected to the driver circuit DR.

[0014] The semiconductor chip CHP3 has a transformer TR1, a transformer TR2, and lead-out wiring PL1 and lead-out wiring PL2.

[0015] The transformer TR1 has a transmitting coil CL1 and a receiving coil CL2. The transmitting coil CL1 has a coil CL11 and a coil CL12, and the receiving coil CL2 has a coil CL21 and a coil CL22. The transmitting coil CL1 and the receiving coil CL2 are electrically connected to a transmitting circuit TX1 and a receiving circuit RX1, respectively.

[0016] More specifically, one end of the coil CL11 is electrically connected to the transmitting circuit TX1, the other end of the coil CL11 is electrically connected to one end of the coil CL12, and the other end of the coil CL12 is electrically connected to the transmitting circuit TX1. One end of the coil CL21 is electrically connected to the receiving circuit RX1, and the other end of the coil CL21 is electrically connected to one end of the coil CL22 via the lead-out wiring PL1, and the other end of the coil CL22 is electrically connected to the receiving circuit RX1.

[0017] The transformer TR2 has a transmitting coil CL3 and a receiving coil CL4. The transmitting coil CL3 has coils CL31 and CL32, and the receiving coil CL4 has coils CL41 and CL42. The transmitting coil CL3 and the receiving coil CL4 are electrically connected to the transmitting circuit TX2 and the receiving circuit RX2, respectively.

[0018] More specifically, one end of the coil CL31 is electrically connected to the transmitting circuit TX2, the other end of the coil CL31 is electrically connected to one end of the coil CL32, and the other end of the coil CL32 is electrically connected to the transmitting circuit TX2. One end of the coil CL41 is electrically connected to the receiving circuit RX2, and the other end of the coil CL41 is electrically connected to one end of the coil CL42 via the lead-out wiring PL2, and the other end of the coil CL42 is electrically connected to the receiving circuit RX2.

[0019] In the semiconductor device DEV1, a signal is transmitted from the control circuit CC to the drive circuit DR via the transmitter circuit TX1, the transformer TR1, and the receiver circuit RX1. Also, in the semiconductor device DEV1, a signal is transmitted from the drive circuit DR to the control circuit CC via the transmitter circuit TX2, the transformer TR2, and the receiver circuit RX2.

[0020] FIG. 2 is an explanatory diagram showing an example of signal transmission from the control circuit CC to the drive circuit DR. As shown in FIG. 2, the control circuit CC inputs a signal SG1 to the transmitter circuit TX1. The signal SG1 is a square wave. The transmitter circuit TX1 modulates the signal SG1 to a signal SG2 and sends the signal SG2 to the transmitter coil CL1. When the signal SG2 flows to the transmitter coil CL1, a signal SG3 corresponding to the signal SG2 flows to the receiver coil CL2 due to induced electromotive force. The receiver circuit RX1 amplifies the signal SG3 and demodulates it to a signal SG4 (square wave), which it then outputs to the driver circuit DR. In this manner, signals are transmitted from the control circuit CC to the driver circuit DR. Note that signals are transmitted from the driver circuit DR to the control circuit CC in a similar manner. In this manner, in the semiconductor device DEV1, signal transmission between the transmitter circuit TX1 and the receiver circuit RX1 and between the transmitter circuit TX2 and the receiver circuit RX2 are performed using a pulse communication method.

[0021] <Detailed configuration of the CHP3 semiconductor chip> The detailed configuration of the semiconductor chip CHP3 will be described below.

[0022] Fig. 3 is a first plan view of the semiconductor chip CHP3. Fig. 4 is a second plan view of the semiconductor chip CHP3. Fig. 5 is a third plan view of the semiconductor chip CHP3. Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 5. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 5. As shown in Figs. 3 to 7, the semiconductor chip CHP3 has a semiconductor substrate SUB, a multilayer wiring layer, a passivation film PV, and a cover film CF.

[0023] The semiconductor substrate SUB has a first face F1 and a second face F2. The first face F1 and the second face F2 are end faces in the thickness direction of the semiconductor substrate SUB. The second face F2 is the face opposite to the first face F1. The semiconductor substrate SUB is made of, for example, single crystal silicon. In a plan view, the semiconductor substrate SUB has a coil region and a peripheral region. In a plan view, the peripheral region surrounds the coil region.

[0024] The multilayer wiring layer includes a plurality of interlayer insulating films ILD and a plurality of wiring layers WL. The interlayer insulating films ILD are made of, for example, silicon oxide. The main component of the material constituting the wiring layers WL is, for example, aluminum. Note that the main component of the material constituting the wiring layers WL being aluminum means that the aluminum content in the material constituting the wiring layers WL is 50 mass percent or more.

[0025] The lowest interlayer insulating film ILD is referred to as interlayer insulating film ILD1. The interlayer insulating film ILD on the interlayer insulating film ILD1 is referred to as interlayer insulating film ILD2. Each of the multiple interlayer insulating films ILD arranged on the interlayer insulating film ILD2 is referred to as interlayer insulating film ILD3. The wiring layer WL arranged on the interlayer insulating film ILD1 is referred to as wiring layer WL1. The wiring layer WL arranged on the interlayer insulating film ILD2 is referred to as wiring layer WL2. The wiring layer WL arranged on the interlayer insulating film ILD3 is referred to as wiring layer WL3. However, the wiring layer WL arranged on the uppermost interlayer insulating film ILD3 is referred to as wiring layer WL4.

[0026] The wiring layer WL2 has a transmitter coil CL1 (coil CL11, coil CL12), a receiver coil CL4 (coil CL41, coil CL42), and a lead-out wiring PL2. The wiring layer WL2 further has wiring WL2a, wiring WL2b, wiring WL2c, and wiring WL2d. The transmitter coil CL1 and receiver coil CL4 are arranged on the coil region of the semiconductor substrate SUB. The transmitter coil CL1 and receiver coil CL4 are aligned along the first direction DR1 in a plan view.

[0027] The coils CL11 and CL12 are aligned along the first direction DR1 in plan view. The coils CL11 and CL12 are spirally wound in plan view. The coil CL11 is wound counterclockwise from the innermost circumference to the outermost circumference. The coil CL12 is wound clockwise from the outermost circumference to the innermost circumference. The outermost end of the coil CL11 is connected to the outermost end of the coil CL12. From another perspective, the coils CL11 and CL12 have a serial aiding configuration.

[0028] The coils CL41 and CL42 are aligned along the first direction DR1 in plan view. The coils CL41 and CL42 are spirally wound in plan view. The coil CL41 is wound counterclockwise from the innermost circumference to the outermost circumference. The coil CL42 is wound clockwise from the outermost circumference to the innermost circumference. The outermost end of the coil CL41 is connected to the outermost end of the coil CL42 via one end of the lead-out wiring PL2. From another perspective, the coils CL41 and CL42 are configured in a series mutually complementary manner.

[0029] The lead wiring PL2 extends in a second direction DR2, which is perpendicular to the first direction DR1.

[0030] The wiring WL2a, wiring WL2b, wiring WL2c, and wiring WL2d extend along the second direction DR2 in a plan view. One end of the wiring WL2a in the second direction DR2 and one end of the wiring WL2b in the second direction DR2 are adjacent to the coils CL11 and CL12, respectively. One end of the wiring WL2c in the second direction DR2 and one end of the wiring WL2d in the second direction DR2 are adjacent to the coils CL41 and CL42, respectively.

[0031] The wiring layer WL1 has wirings WL1a, WL1b, WL1c, and WL1d, which extend in a first direction DR1 in plan view.

[0032] One end and the other end of the wiring WL1a in the first direction DR1 overlap one end of the wiring WL2a and the innermost end of the coil CL11, respectively. One end and the other end of the wiring WL1b in the first direction DR1 overlap one end of the wiring WL2b and the innermost end of the coil CL12, respectively. One end and the other end of the wiring WL1c in the first direction DR1 overlap one end of the wiring WL2c and the innermost end of the coil CL41, respectively. One end and the other end of the wiring WL1d in the first direction DR1 overlap one end of the wiring WL2d and the innermost end of the coil CL42, respectively.

[0033] One end and the other end of the wiring WL1a in the first direction DR1 are electrically connected to one end of the wiring WL2a and the innermost end of the coil CL11 by via plugs VP, respectively. One end and the other end of the wiring WL1b in the first direction DR1 are electrically connected to one end of the wiring WL2b and the innermost end of the coil CL12 by via plugs VP, respectively. One end and the other end of the wiring WL1c in the first direction DR1 are electrically connected to one end of the wiring WL2c and the innermost end of the coil CL41 by via plugs VP, respectively. One end and the other end of the wiring WL1d in the first direction DR1 are electrically connected to one end of the wiring WL2d and the innermost end of the coil CL42 by via plugs VP, respectively. The via plugs VP are embedded in via holes formed in the interlayer insulating film ILD. The via plugs VP are made of, for example, tungsten.

[0034] The wiring layer WL4 has a receiving coil CL2 (coil CL21, coil CL22) and a transmitting coil CL3 (coil CL31, coil CL32). The wiring layer WL4 also has pads PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, and PD10. The wiring layer WL4 also has a guard ring GR1 and a lead-out wiring PL1.

[0035] The receiver coil CL2 and the transmitter coil CL3 are aligned along the first direction DR1 in a plan view. The receiver coil CL2 and the transmitter coil CL3 overlap the transmitter coil CL1 and the receiver coil CL4, respectively, in a plan view. That is, the coils CL21 and CL22 face the coils CL11 and CL12, respectively, with an insulating layer (plurality of interlayer insulating films ILD3) therebetween, and the coils CL31 and CL32 face the coils CL41 and CL42, respectively, with an insulating layer (plurality of interlayer insulating films ILD3) therebetween. From another perspective, the coils CL21 and CL22 are magnetically coupled to the coils CL11 and CL12, respectively, and the coils CL31 and CL32 are magnetically coupled to the coils CL41 and CL42, respectively.

[0036] The distance between the bottom surface of the wiring layer WL4 and the top surface of the wiring layer WL2 is defined as a distance DIS1. The distance DIS1 corresponds to the distance between the transmitter coil CL1 and the receiver coil CL2 and the distance between the transmitter coil CL3 and the receiver coil CL4. The distance DIS1 is, for example, 5 μm or more and 20 μm or less.

[0037] The coils CL21 and CL22 are aligned along the first direction DR1 in plan view. The coils CL21 and CL22 are spirally wound in plan view. The coil CL21 is wound counterclockwise from the innermost circumference to the outermost circumference. The coil CL22 is wound clockwise from the outermost circumference to the innermost circumference. The outermost end of the coil CL21 is connected to the outermost end of the coil CL22 via the pad PD1. From another perspective, the coils CL21 and CL22 are configured in a series mutually complementary configuration.

[0038] The coils CL31 and CL32 are aligned along the first direction DR1 in plan view. The coils CL31 and CL32 are spirally wound in plan view. The coil CL31 is wound counterclockwise from the innermost circumference to the outermost circumference. The coil CL32 is wound clockwise from the outermost circumference to the innermost circumference. The outermost end of the coil CL31 is connected to the outermost end of the coil CL32. From another perspective, the coils CL31 and CL32 are configured in a series mutually complementary configuration.

[0039] Pads PD2 and PD3 are connected to the innermost ends of coils CL21 and CL22, respectively. Pads PD4 and PD5 are connected to the innermost ends of coils CL31 and CL32, respectively.

[0040] The pads PD6, PD7, PD8, PD9, and PD10 are arranged on the peripheral region of the semiconductor substrate SUB. The pads PD6, PD7, PD8, PD9, and PD10 are aligned along the first direction DR1 in a plan view. The pads PD6 and PD7 overlap the other end of the wiring WL2a and the other end of the wiring WL2b in a plan view. The pads PD8 and PD9 overlap the other end of the wiring WL2c and the other end of the wiring WL2d in a plan view. The pad PD10 overlaps the other end of the lead-out wiring PL2 in a plan view.

[0041] Although not shown, pads PD6, PD7, PD8, PD9, and PD10 are electrically connected to the other end of wiring WL2a, the other end of wiring WL2b, the other end of wiring WL2c, the other end of wiring WL2d, and the other end of lead-out wiring PL2, respectively, by via plugs VP and multiple wiring layers WL3.

[0042] The guard ring GR1 surrounds the receiver coil CL2 and the transmitter coil CL3 in a plan view. The lead-out wiring PL1 extends along a first direction DR1 in a plan view. One end of the lead-out wiring PL1 is connected to the pad PD1, and the other end is connected to the guard ring GR1. A reference potential is applied to the pad PD1. Therefore, the same reference potential is also applied to the guard ring GR1. A higher reference potential is applied to the pad PD10 than to the pad PD1.

[0043] The multilayer wiring layer further includes a plurality of metal films MF. The plurality of metal films MF are arranged on the peripheral region of the semiconductor substrate SUB. More specifically, the wiring layer WL1, the wiring layer WL2, and the plurality of wiring layers WL3 each include a metal film MF. Each of the plurality of metal films MF is spaced a distance DIS1 or more from the receiving coil CL2 (coils CL21 and CL22). From another perspective, each of the plurality of metal films MF is not arranged inside the arcs indicated by dotted lines in FIG. 7, and the upper metal films MF occupy smaller areas. Although not shown, each of the plurality of metal films MF is also spaced a distance DIS1 or more from the transmitting coil CL3 (coils CL31 and CL32). Adjacent metal films MF are connected to each other by via plugs VP, and the metal film MF (the lowest metal film MF) formed in the wiring layer WL1 is connected to the semiconductor substrate SUB by contact plugs CP. The contact plugs CP are embedded in contact holes formed in the interlayer insulating film ILD1.

[0044] The passivation film PV is disposed on the uppermost interlayer insulating film ILD3 so as to cover the wiring layer WL4. Openings are formed in the passivation film PV. Pads PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, and PD10 are exposed through the openings in the passivation film PV. The passivation film PV is made of, for example, silicon nitride.

[0045] The cover film CF is disposed on the passivation film PV and is made of, for example, polyimide.

[0046] <Manufacturing method for semiconductor chip CHP3> A method for manufacturing the semiconductor chip CHP3 will be described below.

[0047] 8 is a manufacturing process diagram of the semiconductor chip CHP3. As shown in Fig. 8, the manufacturing method of the semiconductor chip CHP3 includes a preparation step S1, an interlayer insulating film forming step S2, a contact plug forming step S3, a wiring forming step S4, an interlayer insulating film forming step S5, a via plug forming step S6, a wiring forming step S7, a passivation film forming step S8, a cover film forming step S9, and a singulation step S10.

[0048] In the preparation step S1, a semiconductor substrate SUB is prepared. Fig. 9 is a cross-sectional view illustrating the interlayer insulating film formation step S2. As shown in Fig. 9, in the interlayer insulating film formation step S2, an interlayer insulating film ILD, more specifically, an interlayer insulating film ILD1, is formed. The interlayer insulating film ILD1 is formed by depositing a constituent material of the interlayer insulating film ILD1 on the semiconductor substrate SUB by, for example, a CVD (Chemical Vapor Deposition) method, and then planarizing the deposited constituent material of the interlayer insulating film ILD1 by a CMP (Chemical Mechanical Polishing) method.

[0049] FIG. 10 is a cross-sectional view illustrating the contact plug formation step S3. As shown in FIG. 10, the contact plug CP is formed. In the contact plug formation step S3, first, a contact hole is formed in the interlayer insulating film ILD1. The contact hole is formed by disposing a resist pattern on the interlayer insulating film ILD1 and etching the interlayer insulating film ILD1 using the resist pattern as a mask. The resist pattern is formed by disposing a photoresist on the interlayer insulating film ILD1 and patterning the photoresist by photolithography. Second, the constituent material of the contact plug CP is buried in the via hole by, for example, a CVD method. Third, the constituent material of the contact plug CP that protrudes from the contact hole is removed by, for example, a CMP method. In this manner, the contact plug CP is formed.

[0050] FIG. 11 is a cross-sectional view illustrating the wiring formation step S4. As shown in FIG. 11, in the wiring formation step S4, a wiring layer WL, more specifically, a wiring layer WL1, is formed. In the wiring formation step S4, first, a constituent material of the wiring layer WL1 is deposited on the interlayer insulating film ILD1 by, for example, sputtering. Second, a resist pattern is formed on the deposited constituent material of the wiring layer WL1. The resist pattern is formed by placing a photoresist on the deposited constituent material of the wiring layer WL1 and patterning the photoresist by photolithography. Third, the deposited constituent material of the wiring layer WL1 is etched using the resist pattern as a mask. In this way, the wiring layer WL1 is formed. After the wiring layer WL1 is formed, the resist pattern is removed.

[0051] 12 is a cross-sectional view illustrating the interlayer insulating film forming step S5. As shown in FIG. 12, in the interlayer insulating film forming step S5, the interlayer insulating film ILD, more specifically the interlayer insulating film ILD2, is formed. The interlayer insulating film ILD2 is formed by depositing a constituent material of the interlayer insulating film ILD2 on the semiconductor substrate SUB by, for example, a CVD method on the interlayer insulating film ILD1 so as to cover the wiring layer WL1, and then planarizing the deposited constituent material of the interlayer insulating film ILD2 by a CMP method.

[0052] FIG. 13 is a cross-sectional view illustrating the via plug forming step S6. As shown in FIG. 13, in the via plug forming step S6, a via plug VP is formed. In the via plug forming step S6, first, a via hole is formed in the interlayer insulating film ILD2. The via hole is formed by disposing a resist pattern on the interlayer insulating film ILD2 and etching the interlayer insulating film ILD2 using the resist pattern as a mask. The resist pattern is formed by disposing a photoresist on the interlayer insulating film ILD2 and patterning the photoresist by photolithography. Second, a constituent material of the via plug VP is embedded in the via hole by, for example, a CVD method. Third, the constituent material of the via plug VP that protrudes from the via hole is removed by, for example, a CMP method. In this manner, the via plug VP is formed.

[0053] 14 is a cross-sectional view illustrating the wiring formation step S7. As shown in FIG. 14, in the wiring formation step S7, a wiring layer WL2 is formed on the interlayer insulating film ILD2 in the same manner as in the wiring formation step S4. Thereafter, the interlayer insulating film formation step S5, the via plug formation step S6, and the wiring formation step S7 are repeatedly performed, thereby forming a plurality of interlayer insulating films ILD3 and a plurality of wiring layers WL3 and WL4.

[0054] FIG. 15 is a cross-sectional view illustrating the passivation film formation step S8. In the passivation film formation step S8, the passivation film PV is formed. In the passivation film formation step S8, first, a constituent material of the passivation film PV is deposited on the uppermost interlayer insulating film ILD3 by, for example, a CVD method so as to cover the wiring layer WL4. Second, a resist pattern is placed on the constituent material of the deposited passivation film PV, and the constituent material of the passivation film PV is etched using the resist pattern as a mask. The resist pattern is formed by placing a photoresist on the constituent material of the deposited passivation film PV and patterning the photoresist by photolithography. In this manner, the passivation film PV is formed.

[0055] In a cover film forming step S9, a cover film CF is formed on the passivation film PV. In a singulation step S10, the semiconductor substrate SUB, the multilayer wiring layer, the passivation film PV, and the cover film CF are cut along the scribe lanes to obtain a plurality of semiconductor chips CHP3.

[0056] <Effects of the CHP3 semiconductor chip> The effects of the semiconductor chip CHP3 will be described below.

[0057] FIG. 16 is a schematic graph showing the amount of wafer warpage as the manufacturing process progresses in Sample 1 and Sample 2. Sample 1 is a sample on which a metal film MF is not formed. Sample 2 is a sample on which a metal film MF is formed. That is, Sample 1 does not correspond to the semiconductor chip CHP3, but Sample 2 corresponds to the semiconductor chip CHP3. As shown in FIG. 16, in Sample 1 and Sample 2, the amount of wafer warpage decreases each time a wiring layer WL is formed, but overall the amount of wafer warpage increases as the manufacturing process progresses.

[0058] The reduction in the amount of wafer warpage when the wiring layers WL are formed increases as the area occupied by the wiring layers WL increases. In Sample 2, the wiring layers WL (wiring layers WL1, WL2, and WL3) have metal films MF, so the area occupied by the wiring layers WL is larger than in Sample 1. As a result, the reduction in the amount of wafer warpage when the wiring layers WL are formed increases in Sample 2 compared to Sample 1, and the amount of wafer warpage is reduced when viewed as the entire wafer.

[0059] In the semiconductor chip CHP3, the metal film MF located in the upper layer occupies a smaller area. Figure 17 is a schematic graph showing the relationship between the number of wiring layers WL and the amount of wafer warpage. As shown in Figure 17, the amount of wafer warpage per wiring layer WL decreases as the wiring layer WL located in the upper layer. Therefore, even if the area occupied by the metal film MF in the upper layer is smaller than that of the metal film MF in the lower layer, the effect of suppressing the amount of wafer warpage does not decrease significantly.

[0060] Furthermore, in the semiconductor chip CHP3, the metal film MF is spaced from the receiving coil CL2 (transmitting coil CL3) by a distance DIS1 or more. Therefore, even if the multilayer wiring layer has the metal film MF, the dielectric strength does not decrease compared to when the multilayer wiring layer does not have the metal film MF. In this way, the semiconductor chip CHP3 can reduce the amount of warpage while maintaining the dielectric strength.

[0061] One possible method of connecting the guard ring GR1 and the receiving coil CL2 is to arrange the pad PD1 in contact with the guard ring GR1, connect one end of the lead-out wiring PL1 to the pad PD1, and connect the coils CL11 and CL12 via the other end of the lead-out wiring PL1. In the semiconductor chip CHP3, the coils CL11 and CL12 are connected via the pad PD1, which means that the pad PD1 is arranged inside the guard ring GR1, improving the dielectric strength.

[0062] (Second embodiment) A semiconductor device according to a second embodiment will be described. The semiconductor device according to the second embodiment will be referred to as semiconductor device DEV2. Here, differences from the semiconductor device DEV2 will be mainly described, and overlapping descriptions will not be repeated.

[0063] <Configuration of semiconductor device DEV2> The configuration of the semiconductor device DEV2 will be described below.

[0064] The semiconductor device DEV2 has semiconductor chips CHP1, CHP2, and CHP3. In the semiconductor device DEV2, the semiconductor chip CHP3 has a semiconductor substrate SUB, a multilayer wiring layer (multiple wiring layers WL, multiple interlayer insulating films ILD), a passivation film PV, and a cover film CF. In these respects, the configuration of the semiconductor device DEV2 is common to the configuration of the semiconductor device DEV2. Note that in the semiconductor device DEV2, the multilayer wiring layer may or may not have multiple metal films MF.

[0065] 18 is a plan view of the semiconductor chip CHP3 included in the semiconductor device DEV2. FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 18. As shown in FIGS. 18 and 19, in the semiconductor device DEV2, a recess RCS1 is formed in the passivation film PV. The recess RCS1 extends along the first direction DR1 in plan view. The row of pads PD6, PD7, PD8, PD9, and PD10 is referred to as the pad row. The recess RCS1 is arranged between the guard ring GR1 and the pad row in the second direction DR2.

[0066] 18 and 19, one recess RCS1 is formed, but multiple recesses RCS1 may be arranged in the second direction DR2. That is, multiple recesses RCS1 may be formed in a stripe pattern. Also, the recess RCS1 does not have to extend along the first direction DR1. For example, multiple recesses RCS1 may be formed in a dot pattern or a staggered pattern in a plan view.

[0067] The recess RCS1, for example, penetrates the passivation film PV. The bottom of the recess RCS1 may reach below the upper surface of the uppermost interlayer insulating film ILD3. The cover film CF is disposed not only on the passivation film PV but also in the recess RCS1. In these respects, the configuration of the semiconductor device DEV2 differs from the configuration of the semiconductor device DEV1.

[0068] <Manufacturing method for semiconductor chip CHP3> A method for manufacturing the semiconductor chip CHP3 included in the semiconductor device DEV2 will be described below.

[0069] The manufacturing method of the semiconductor chip CHP3 included in the semiconductor device DEV2 includes a preparation step S1, an interlayer insulating film forming step S2, a contact plug forming step S3, a wiring forming step S4, an interlayer insulating film forming step S5, a via plug forming step S6, a wiring forming step S7, a passivation film forming step S8, a cover film forming step S9, and a singulation step S10. In this respect, the manufacturing method of the semiconductor chip CHP3 included in the semiconductor device DEV2 is common to the manufacturing method of the semiconductor chip CHP3 included in the semiconductor device DEV1.

[0070] In the passivation film forming step S8 of the method for manufacturing the semiconductor chip CHP3 of the semiconductor device DEV2, when an opening is formed in the passivation film PV, the recess RCS1 is also formed. In this respect, the method for manufacturing the semiconductor chip CHP3 of the semiconductor device DEV2 differs from the method for manufacturing the semiconductor chip CHP3 of the semiconductor device DEV1.

[0071] <Effects of the semiconductor chip CHP3 in the semiconductor device DEV2> The effects of the semiconductor chip CHP3 included in the semiconductor device DEV2 will be described below.

[0072] In the semiconductor chip CHP3 of the semiconductor device DEV2, the recess RCS1 is formed, which increases the creepage distance between the guard ring GR1 and the pad row. Therefore, the semiconductor chip CHP3 of the semiconductor device DEV2 improves the creepage breakdown voltage between the guard ring GR1 and the pad row. Since the recess RCS1 can be formed during the passivation film formation process S8, there is no need to introduce a new process for forming the recess RCS1.

[0073] <Modification> 20 is a cross-sectional view taken along line XX-XX in FIG. 18. As shown in FIG. 20, the semiconductor chip CHP3 included in the semiconductor device DEV2 may further include a recess RCS2. The recess RCS2 is formed on the outer periphery of the passivation film PV in a plan view. The recess RCS2 may reach the outer periphery of the semiconductor chip CHP3 in a plan view. The recess RCS2 penetrates the passivation film PV and reaches below the upper surface of the uppermost interlayer insulating film ILD3. This results in a configuration in which the corners of the semiconductor chip CHP3 are ground (removed), thereby suppressing chipping (chip breakage) during dicing. This also increases the creepage distance between the wiring layer WL4 and the outer periphery of the semiconductor chip CHP3, thereby improving the dielectric strength between the wiring layer WL4 and the outer periphery of the semiconductor chip CHP3.

[0074] The semiconductor chip CHP3 of the semiconductor device DEV2 may further include a step STP. The recess RCS2 is located outside the recess RCS2 in plan view and reaches the outer periphery of the semiconductor chip CHP3. The step STP penetrates the multilayer wiring layer, and the semiconductor substrate SUB is exposed from the step STP.

[0075] Fig. 21 is a first cross-sectional view illustrating the singulation step S10 for the semiconductor chip CHP3 included in the semiconductor device DEV2. As shown in Fig. 21, the step STP is formed by, for example, irradiating laser light L to remove the multilayer wiring layer. Fig. 22 is a second cross-sectional view illustrating the singulation step S10 for the semiconductor chip CHP3 included in the semiconductor device DEV2. As shown in Fig. 22, after the step STP is formed, the semiconductor substrate SUB is cut along the step STP using a dicing blade DB.

[0076] In this case, since the recess RCS2 and the step STP are formed, even if a seal ring is not formed in the multilayer wiring layer, cracks are unlikely to propagate through the multilayer wiring layer when cutting with the dicing blade DB. In the above example, two-stage dicing was performed using the laser light L and the dicing blade DB, but the combination of the laser light L and the dicing blade DB is not limited as long as two-stage dicing is performed.

[0077] (Third embodiment) A semiconductor device according to a third embodiment will be described. The semiconductor device according to the second embodiment will be referred to as semiconductor device DEV3. Here, differences from the semiconductor device DEV2 will be mainly described, and overlapping descriptions will not be repeated.

[0078] <Configuration of semiconductor device DEV3> The configuration of the semiconductor device DEV3 will be described below.

[0079] The semiconductor device DEV3 has a semiconductor chip CHP1, a semiconductor chip CHP2, and a semiconductor chip CHP3. In the semiconductor device DEV3, the semiconductor chip CHP3 has a semiconductor substrate SUB, a multilayer wiring layer (multiple wiring layers WL, multiple interlayer insulating films ILD), a passivation film PV, and a cover film CF. In these respects, the configuration of the semiconductor device DEV3 is common to the configuration of the semiconductor device DEV2.

[0080] Fig. 23 is a plan view of the semiconductor chip CHP3 included in the semiconductor device DEV3. As shown in Fig. 23, in the semiconductor chip CHP3 included in the semiconductor device DEV3, the wiring layer WL4 has a guard ring GR2 and a wiring WL4a.

[0081] The guard ring GR2 has a central portion GR2a and end portions GR2b and GR2c. The central portion GR2a extends along the first direction DR1 in a plan view. The central portion GR2a is disposed between the pad row and the guard ring GR1 in the second direction DR2. The end portions GR2b and GR2c are connected to one end and the other end of the central portion GR2a in the first direction DR1, respectively.

[0082] The end GR2b curves in the first direction DR1 toward the outer periphery of the semiconductor substrate SUB and in the second direction DR2 away from the receiver coil CL2 and the transmitter coil CL3. The end GR2c curves in the first direction DR1 toward the outer periphery of the semiconductor substrate SUB and in the second direction DR2 away from the receiver coil CL2 and the transmitter coil CL3. From another perspective, the guard ring GR2 is disposed to shield the pad row from the guard ring GR1, but does not surround the pad row on the side opposite the guard ring GR2.

[0083] The distance DIS2 is the shortest distance between the guard rings GR1 and GR2. The distance DIS2 is, for example, 50 μm or more and 150 μm or less. One end of the wiring WL4a is connected to the guard ring GR2, and the other end is connected to the pad PD10. As described above, a reference potential is applied to the pad PD10, and therefore the same reference potential as that of the pad PD10 is also applied to the guard ring GR2.

[0084] In the semiconductor device DEV3, the multilayer wiring layer may or may not have a plurality of metal films MF. In addition, in the semiconductor device DEV3, the recesses RCS1, RCS2, and the steps STP may or may not be formed.

[0085] <Effects of the semiconductor chip CHP3 in the semiconductor device DEV3> The effects of the semiconductor chip CHP3 included in the semiconductor device DEV3 will be described below.

[0086] In the semiconductor chip CHP3 of the semiconductor device DEV3, the guard ring GR2 is disposed between the guard ring GR1 and the pad row, and different reference potentials are applied to the guard ring GR1 and the guard ring GR2, thereby improving the dielectric strength between the guard ring GR1 and the pad row. In addition, the guard ring GR2 has ends GR2b and GR2c that curve away from the receiving coil CL2 and the transmitting coil CL3, making it difficult for a singular point to occur between the guard ring GR1 and the guard ring GR2, further improving the dielectric strength between the guard ring GR1 and the pad row.

[0087] (Addendum) The above embodiment includes the following configurations.

[0088] <Appendix 1> a first semiconductor chip; a second semiconductor chip; a third semiconductor chip; the first semiconductor chip has a first transceiver circuit; the second semiconductor chip has a second transceiver circuit; the third semiconductor chip has a semiconductor substrate and a multilayer wiring layer disposed on the semiconductor substrate; the multilayer wiring layer includes a first coil, a second coil, a third coil, a fourth coil, and a metal film; the semiconductor substrate has, in a plan view, a coil region and a peripheral region surrounding the coil region; the multilayer wiring layer has a plurality of wiring layers, the first coil and the second coil are formed in a first wiring layer which is one of the plurality of wiring layers arranged on the coil region, the third coil and the fourth coil are formed in a second wiring layer which is another wiring layer of the plurality of wiring layers arranged on the coil region, the second wiring layer is disposed above the first wiring layer, the third coil and the fourth coil are arranged to face the first coil and the second coil, respectively; a distance between an upper surface of the first wiring layer and a lower surface of the second wiring layer is a first distance; the metal film is formed on each of the plurality of wiring layers arranged on the peripheral region so as to be spaced apart from the third coil and the fourth coil by the first distance or more in a cross-sectional view, The first transmitting / receiving circuit transmits signals to and from the second transmitting / receiving circuit via the first coil, the second coil, the third coil, and the fourth coil.

[0089] <Appendix 2> 2. The semiconductor device according to claim 1, wherein a signal transmission method between the first transceiver circuit and the second transceiver circuit is a pulse communication method.

[0090] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0091] CF cover film, CHP1 semiconductor chip, CHP2 semiconductor chip, CHP3 semiconductor chip, CL1 transmitting coil, CL11, CL12 coils, CL2 receiving coil, CL21, CL22 coils, CL3 transmitting coil, CL31, CL32 coils, CL4 receiving coil, CL41, CL42 coils, CP contact plug, DB dicing blade, DEV1, DEV2, DEV3 semiconductor device, DIS1 distance, DIS2 distance, DR drive circuit, DR1 first direction, DR2 second direction, F1 first surface, F2 second surface, GR1, GR2 guard ring, GR2a center, GR2b end, GR2c end, ILD, ILD1, ILD2, ILD3 interlayer insulating film, L laser light, MF metal film, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10 Pad, PL1 lead wiring, PL2 lead wiring, PV passivation film, RCS1 recess, RCS2 recess, RX1 receiving circuit, RX2 receiving circuit, S1 preparation process, S2 interlayer insulating film formation process, S3 contact plug formation process, S4 wiring formation process, S5 interlayer insulating film formation process, S6 via plug formation process, S7 wiring formation process, S8 passivation film formation process, S9 cover film formation process, S10 singulation process, SG1, SG2, SG3, SG4 signals, STP step, SUB semiconductor substrate, TR1 transformer, TR2 transformer, TX1 transmitting circuit, TX2 transmitting circuit, VP via plug, WL, WL1, WL2, WL3, WL4 wiring layers, WL1c, WL1d, WL1a, WL1b, WL2b, WL2c, WL2d, WL2a, WL4a wiring.

Claims

1. a semiconductor substrate; a multilayer wiring layer disposed on the semiconductor substrate, the multilayer wiring layer includes a first coil, a second coil, a third coil, a fourth coil, and a metal film; the semiconductor substrate has, in a plan view, a coil region and a peripheral region surrounding the coil region; the multilayer wiring layer has a plurality of wiring layers, the first coil and the second coil are formed in a first wiring layer which is one of the plurality of wiring layers arranged on the coil region, the third coil and the fourth coil are formed in a second wiring layer which is another wiring layer of the plurality of wiring layers arranged on the coil region, the second wiring layer is disposed above the first wiring layer, the third coil and the fourth coil are arranged to face the first coil and the second coil, respectively; a distance between an upper surface of the first wiring layer and a lower surface of the second wiring layer is a first distance; A semiconductor device, wherein the metal film is formed on each of the plurality of wiring layers arranged on the peripheral region so as to be spaced apart from the third coil and the fourth coil by at least the first distance in a cross-sectional view.

2. the second wiring layer is the uppermost layer of the plurality of wiring layers, 2. The semiconductor device according to claim 1, wherein said metal film is formed on said first wiring layer and on each of said plurality of wiring layers located between said first wiring layer and said second wiring layer.

3. The semiconductor device according to claim 1 , wherein the first distance is not less than 5 μm and not more than 20 μm.

4. The semiconductor device according to claim 1 , wherein the first coil and the second coil overlap with the third coil and the fourth coil, respectively.

5. A first lead-out wiring; A first pad; a first guard ring; the second wiring layer is the uppermost layer of the plurality of wiring layers, the first lead wiring is formed in one of the plurality of wiring layers below the first wiring layer and is electrically connected to the first coil; the first pad is formed in the second wiring layer disposed in the peripheral region and is electrically connected to the first lead-out wiring; 2. The semiconductor device according to claim 1, wherein the first guard ring is disposed in the peripheral region so as to shield the third coil and the fourth coil from the first pad.

6. The semiconductor device according to claim 5 , wherein an end of said first guard ring is curved so as to move away from said third coil and said fourth coil in a plan view as it approaches an outer periphery of said peripheral region.

7. The semiconductor device according to claim 5 , wherein a side of said first pad near the outer periphery of said peripheral region is not surrounded by said first guard ring.

8. a passivation film disposed on an uppermost wiring layer of the plurality of wiring layers; a first recess is formed in the passivation film between the third coil and the fourth coil and the first guard ring in a plan view, and the passivation film is at least partially removed; The semiconductor device according to claim 5 , wherein the first recess extends in a direction in which the first guard ring extends.

9. The semiconductor device according to claim 8 , wherein a plurality of the first recesses are formed.

10. The semiconductor device according to claim 9 , wherein the first recesses are formed in a stripe pattern, a staggered pattern, or a dot pattern in a plan view.

11. the multilayer wiring layer has a plurality of interlayer insulating films, 9. The semiconductor device according to claim 8, wherein the first recess penetrates the passivation film and is formed so that a bottom of the first recess is lower than an upper surface of a first interlayer insulating film that is an uppermost layer of the plurality of interlayer insulating films.

12. the multilayer wiring layer has a plurality of interlayer insulating films, a second recess is formed in the passivation film disposed on the outer periphery of the peripheral region; 2. The semiconductor device according to claim 1, wherein the second recess penetrates the passivation film and is formed so that the bottom of the second recess is lower than the top surface of a first interlayer insulating film, which is the top layer of the multilayer wiring layer.

13. a step penetrating the multilayer wiring layer is formed on the outer periphery of the peripheral region outside the second recess in plan view, 13. The semiconductor device according to claim 12, wherein the step is formed by a second dicing performed before a first dicing for cutting the semiconductor substrate.

14. a second guard ring formed in the second wiring layer so as to surround the third coil and the fourth coil in a plan view; 6. The semiconductor device according to claim 5, wherein the shortest distance between said first guard ring and said second guard ring is not less than 50 [mu]m and not more than 150 [mu]m.

15. a first reference potential and a second reference potential are applied to the first guard ring and the second guard ring, respectively; 15. The semiconductor device according to claim 14, wherein the second reference potential is higher than the first reference potential.

16. Further comprising a second pad; 15. The semiconductor device according to claim 14, wherein the second pad is formed on the second wiring layer between the third coil and the fourth coil.

17. The semiconductor device according to claim 16 , wherein the second pad is electrically connected to the second guard ring.

18. 2. The semiconductor device according to claim 1, wherein said metal film is made of a material containing aluminum as a main component.

19. the first coil and the third coil are magnetically coupled to each other, The semiconductor device according to claim 1 , wherein the second coil and the fourth coil are magnetically coupled to each other.

20. a semiconductor substrate; a multilayer wiring layer disposed on the semiconductor substrate, a first coil, a second coil, a third coil, a fourth coil, a fifth coil, a sixth coil, a seventh coil, and an eighth coil; a metal film; the semiconductor substrate has, in a plan view, a coil region and a peripheral region surrounding the coil region; the multilayer wiring layer has a plurality of wiring layers, the first coil, the second coil, the third coil, and the fourth coil are formed in a first wiring layer which is one wiring layer of the plurality of wiring layers arranged on the coil region, the fifth coil, the sixth coil, the seventh coil, and the eighth coil are formed in a second wiring layer which is another wiring layer of the plurality of wiring layers arranged on the coil region, the second wiring layer is disposed above the first wiring layer, the fifth coil, the sixth coil, the seventh coil, and the eighth coil are arranged to face the first coil, the second coil, the third coil, and the fourth coil, respectively; a distance between an upper surface of the first wiring layer and a lower surface of the second wiring layer is a first distance; A semiconductor device, wherein the metal film is formed on each of the plurality of wiring layers arranged on the peripheral region so as to be spaced apart from the fifth coil and the sixth coil by the first distance or more in a cross-sectional view, and so as to be spaced apart from the seventh coil and the eighth coil by the first distance or more.

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