Semiconductor device

Abstract

To provide a semiconductor device with high reliability and high on-state current.SOLUTION: A semiconductor device includes an oxide insulating film 14b, metal oxide layers 18-1 and 18-2 including a first region 19-1 and a second region 19-2 provided apart from each other on the oxide insulating film, an oxide semiconductor layer 24 provided in contact with the first region and the second region, a gate insulating film 26 provided so as to cover the oxide semiconductor layer, and a gate electrode 32GE provided over the oxide semiconductor layer with the gate insulating film therebetween. The oxide semiconductor layer includes a channel region 24a overlapping with the gate electrode, and a source region and a drain region 24b having the channel region therebetween. The channel region is in contact with the oxide insulating film between the first region and the second region. The third region 24c is a region in the oxide semiconductor layer, that overlaps with the metal oxide layer vertically below the gate electrode 32GE.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] An embodiment of the present invention relates to a semiconductor device. In particular, an embodiment of the present invention relates to a semiconductor device using an oxide semiconductor for a channel. Also, an embodiment of the present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] In recent years, development of semiconductor devices using oxide semiconductors for the channel instead of amorphous silicon, low-temperature polysilicon, and single-crystal silicon has been progressing (for example, Patent Documents 1 to 6). Like semiconductor devices using amorphous silicon for the channel, semiconductor devices using oxide semiconductors for the channel have a simple structure and can be formed by a low-temperature process. It is known that semiconductor devices using oxide semiconductors for the channel have higher mobility than semiconductor devices using amorphous silicon for the channel.

[0003] In order to ensure stable operation of a semiconductor device using an oxide semiconductor for a channel, it is important to supply oxygen to the oxide semiconductor layer during the manufacturing process and reduce oxygen defects formed in the oxide semiconductor layer. For example, a technique has been disclosed as a method for supplying oxygen to an oxide semiconductor layer, in which the oxide semiconductor layer is covered with an insulating film formed under conditions in which the oxide semiconductor layer contains a large amount of oxygen and then heat treated. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2021-141338 [Patent Document 2] Japanese Patent Application Laid-Open No. 2014-099601 [Patent Document 3] Japanese Patent Publication No. 2021-153196 [Patent Document 4] Japanese Patent Application Publication No. 2018-006730 [Patent Document 5] Japanese Patent Application Laid-Open No. 2016-184771 [Patent Document 6] Patent Publication No. 2021-108405 Summary of the Invention [Problem to be solved by the invention]

[0005] When a heat treatment is performed on an oxide semiconductor layer covered with an insulating film formed under conditions containing a large amount of oxygen, oxygen is uniformly supplied to the oxide semiconductor layer. This reduces oxygen defects in the channel region of the oxide semiconductor layer, thereby suppressing abnormal transistor characteristics or fluctuations in characteristics in reliability tests that occur due to hydrogen-induced electron trapping in the defects. On the other hand, reducing oxygen defects in the source and drain regions increases the resistance of the source and drain regions, thereby reducing the on-current of the transistor.

[0006] Therefore, one object of one embodiment of the present invention is to realize a semiconductor device with high reliability and high on-current. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment of the present invention includes an oxide insulating film, a metal oxide layer having a first region and a second region spaced apart from each other on the oxide insulating film, an oxide semiconductor layer provided in contact with the first region and the second region, a gate insulating film provided to cover the oxide semiconductor layer, and a gate electrode provided on the oxide semiconductor layer via the gate insulating film, wherein the oxide semiconductor layer includes a channel region overlapping with the gate electrode, and a source region and a drain region sandwiching the channel region, and the channel region is in contact with the oxide insulating film between the first region and the second region.

[0008] A semiconductor device according to one embodiment of the present invention comprises: an oxide insulating film; a metal oxide layer having a first region and a second region spaced apart on the oxide insulating film, and a third region between the first and second regions; an oxide semiconductor layer provided in contact with the metal oxide layer; a gate insulating film provided to cover the oxide semiconductor layer; and a gate electrode provided on the oxide semiconductor layer via the gate insulating film, wherein the oxide semiconductor layer includes a channel region overlapping with the gate electrode, and a source region and a drain region sandwiching the channel region, the source region being in contact with the first region, the drain region being in contact with the second region, and the channel region being in contact with the third region; and the thickness of the metal oxide layer in the first and second regions being greater than the thickness of the metal oxide layer in the third region. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view showing an overview of a semiconductor device according to an embodiment of the present invention; [Figure 2] FIG. 2 is an enlarged view of a part of the semiconductor device shown in FIG. [Figure 3] 1 is a plan view showing an overview of a semiconductor device according to an embodiment of the present invention; [Figure 4] 1 is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 5] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11]1 is a cross-sectional view showing an overview of a semiconductor device according to an embodiment of the present invention; [Figure 12] 11 is an enlarged view of a part of the semiconductor device shown in FIG. 10. FIG. [Figure 13] 1 is a cross-sectional view showing an overview of a semiconductor device according to an embodiment of the present invention; [Figure 14] 1 is a cross-sectional view showing an overview of a semiconductor device according to an embodiment of the present invention; [Figure 15] 1 is a plan view showing an overview of a semiconductor device according to an embodiment of the present invention; [Figure 16] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17] 1 is a cross-sectional view showing an overview of a semiconductor device according to an embodiment of the present invention; [Figure 18] 1 is a cross-sectional view showing an overview of a semiconductor device according to an embodiment of the present invention; [Figure 19] 19 is an enlarged view of a part of the semiconductor device shown in FIG. 18. [Figure 20] 1 is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 21] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 22] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 23] 1 is a cross-sectional view showing an overview of a semiconductor device according to an embodiment of the present invention; [Figure 24] 24 is an enlarged view of a part of the semiconductor device shown in FIG. 23. FIG. [Figure 25] 1 is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 26] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 27] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 28] 1 is a cross-sectional view showing an overview of a semiconductor device according to an embodiment of the present invention; [Figure 29] 1 is a cross-sectional view showing an overview of a semiconductor device according to an embodiment of the present invention; [Figure 30] 1 is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 31] 1 is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0010] Each embodiment of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. Configurations that a person skilled in the art can easily arrive at by appropriately modifying the configuration of the embodiments while maintaining the gist of the invention are naturally included within the scope of the present invention. For clarity of explanation, the drawings may show the width, film thickness, shape, etc. of each part more schematically than the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, elements similar to those described above with reference to the previous drawings are given the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0011] The term "semiconductor device" refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are examples of semiconductor devices. The semiconductor device of the following embodiments may be, for example, a display device, an integrated circuit (IC) such as a microprocessor (micro-processing unit: MPU), or a transistor used in a memory circuit.

[0012] The term "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical components (e.g., a polarizing component, a backlight, a touch panel, etc.) are attached to a display cell. The term "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless technically inconsistent. Therefore, the embodiments described below will be described using a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer as examples of display devices, but the structure of this embodiment can be applied to display devices including the other electro-optical layers described above.

[0013] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upper." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "downper." For convenience of explanation, the terms "up" or "downper" are used in the description. However, for example, the top-down relationship between the substrate and the oxide semiconductor layer may be reversed from that illustrated. In the following description, for example, the expression "oxide semiconductor layer on a substrate" merely describes the top-down relationship between the substrate and the oxide semiconductor layer as described above, and other members may be disposed between the substrate and the oxide semiconductor layer. "Top" or "bottom" refers to the stacking order in a structure in which multiple layers are stacked. Note that a plan view refers to a view from a direction perpendicular to the surface of the substrate.

[0014] In this specification and the like, the terms "film" and "layer" can be used interchangeably in some cases.

[0015] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0016] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0017] First Embodiment Semiconductor devices 10 to 10E according to one embodiment of the present invention will be described with reference to FIGS.

[0018] <Configuration of Semiconductor Device 10> The configuration of a semiconductor device 10 according to one embodiment of the present invention will be described with reference to Figs. 1 to 3. Fig. 1 is a cross-sectional view showing an overview of the semiconductor device 10 according to one embodiment of the present invention. Fig. 2 is an enlarged view of a portion of the semiconductor device shown in Fig. 1. Fig. 3 is a plan view showing an overview of the semiconductor device 10 according to one embodiment of the present invention. The cross section taken along the dashed dotted line shown in Fig. 3 corresponds to the cross-sectional view shown in Fig. 1.

[0019] 1, the semiconductor device 10 is provided above a substrate 11. The semiconductor device 10 includes at least an oxide insulating film 14b, metal oxide layers 18-1 and 18-2, an oxide semiconductor layer 24, a gate insulating film 26, and a gate electrode 32GE. The oxide semiconductor layer 24, the gate insulating film 26, and the gate electrode 32GE may be collectively referred to as a transistor. The semiconductor device 10 may further include a gate electrode 12GE, a nitride insulating film 14a, an interlayer insulating film 34, a source electrode 36SE, and a drain electrode 36DE.

[0020] In this embodiment, a configuration in which a dual-gate transistor in which gate electrodes are provided both above and below an oxide semiconductor layer is used as the semiconductor device 10 is exemplified, but the present invention is not limited to this configuration. For example, the semiconductor device 10 may be a bottom-gate transistor in which a gate electrode is provided only below the oxide semiconductor layer, or a top-gate transistor in which a gate electrode is provided only above the oxide semiconductor layer. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0021] The gate electrode 12GE functions as a bottom gate of the semiconductor device 10 and as a light-shielding film for the oxide semiconductor layer 24. The gate insulating film 14 functions as a gate insulating film for the bottom gate. The gate insulating film 14 also has a nitride insulating film 14a and an oxide insulating film 14b. The nitride insulating film 14a functions as a barrier film that blocks impurities diffusing from the substrate 11 toward the oxide semiconductor layer 24. The oxide insulating film 14b also has a function of releasing oxygen by heat treatment in the manufacturing process.

[0022] The metal oxide layer 18 has the function of suppressing the permeation of oxygen and hydrogen released from an adjacent insulating film. The metal oxide layer 18 is, for example, a layer containing a metal oxide whose main component is aluminum. If the film thickness of the metal oxide layer 18 is at least 5 nm or more, the permeation of oxygen and hydrogen from an adjacent insulating film can be suppressed. The metal oxide layer 18 has a first region 19-1 and a second region 19-2 that are spaced apart from each other. The first region 19-1 and the second region 19-2 refer to regions of the metal oxide layer 18 that are in contact with the oxide semiconductor layer 24. In FIGS. 1 to 3, the metal oxide layer 18 includes a metal oxide layer 18-1 including the first region 19-1 and a metal oxide layer 18-2 including the second region 19-2.

[0023] An oxide semiconductor layer 24 is provided on the oxide insulating film 14b and the metal oxide layers 18-1 and 18-2. The oxide semiconductor layer 24 is in contact with the oxide insulating film 14b, the first region 19-1, and the second region 19-2. The edge of the oxide semiconductor layer 24 is substantially aligned with the edge of the metal oxide layer 18-1 and the edge of the metal oxide layer 18-2. In FIG. 1, the sidewall of the metal oxide layer 18 and the sidewall of the oxide semiconductor layer 24 are aligned on a straight line, but this configuration is not limited thereto. The angle of the sidewall of the metal oxide layer 18 with respect to the major surface of the substrate 11 may be different from the angle of the sidewall of the oxide semiconductor layer 24. The cross-sectional shape of the sidewall of at least one of the metal oxide layer 18 and the oxide semiconductor layer 24 may be curved. The sidewall of the metal oxide layer 18 and the sidewall of the oxide semiconductor layer 24 do not have to be aligned on a straight line.

[0024] acid An oxide semiconductor such as indium gallium zinc oxide (IGZO) may be used as the oxide semiconductor layer 24. The use of IGZO as the oxide semiconductor layer 24 will be described in detail later in a modified example.

[0025] The gate electrode 32GE functions as a top gate of the semiconductor device 10 and as a light-shielding film for the oxide semiconductor layer 24. The gate insulating film 26 functions as a gate insulating film for the top gate and has the function of releasing oxygen by heat treatment in the manufacturing process. The operation of the semiconductor device 10 is controlled mainly by the voltage supplied to the gate electrode 32GE. An auxiliary voltage is supplied to the gate electrode 12GE. However, when the gate electrode 12GE is used simply as a light-shielding film, no specific voltage may be supplied to the gate electrode 12GE, and the gate electrode 12GE may be in a floating state. In this case, the gate electrode 12GE may be simply called a "light-shielding film."

[0026] The interlayer insulating film 34 is provided on the gate insulating film 26 and the gate electrode 32GE. Contact holes CH2 and CH3 are provided in the interlayer insulating film 34, reaching the oxide semiconductor layer 24. The source electrode 36SE is provided inside the contact hole CH2, and is in contact with the oxide semiconductor layer 24 at the bottom of the contact hole CH2. The drain electrode 36DE is provided inside the contact hole CH3, and is in contact with the oxide semiconductor layer 24 at the bottom of the contact hole CH3.

[0027] The gate wiring 12GL electrically connected to the gate electrode 12GE is connected to the gate wiring 32GL electrically connected to the gate electrode 32GE via a contact hole CH1 provided in the gate insulating films 14 and .

[0028] In the semiconductor device 10, during the heat treatment process of the manufacturing process, the upper surface of the oxide semiconductor layer is affected by processes (e.g., a patterning process or an etching process) performed after the oxide semiconductor layer is formed. As a result, oxygen defects are generated on the surface of the oxide semiconductor layer. Electrons resulting from hydrogen contained in the surrounding insulating film tend to be trapped in the oxygen defects. Therefore, when electrons are trapped in the oxygen defects, the resistance of the oxide semiconductor layer decreases. If the resistance of the oxide semiconductor layer decreases uniformly, the resistance in the channel region also decreases, making it impossible for the oxide semiconductor layer to function as a transistor.

[0029] Even if oxygen defects are generated in the oxide semiconductor layer, the resistance of the oxide semiconductor layer can be increased if the oxygen defects can be repaired by subsequent heat treatment. For example, when heat treatment is performed in a state where the oxide semiconductor layer is covered with an insulating film formed under conditions in which the oxide semiconductor layer contains more oxygen, oxygen is uniformly supplied to the oxide semiconductor layer. As a result, oxygen defects in the oxide semiconductor layer are uniformly reduced. Resistance can be increased by repairing oxygen defects in the channel region. On the other hand, when oxygen defects in the source and drain regions are repaired, the resistance increases similarly to the channel region, resulting in a decrease in the on-state current of the transistor.

[0030] Therefore, in a transistor using an oxide semiconductor layer, it is necessary to promote the repair of oxygen defects in the oxide semiconductor layer in the channel region, while suppressing the repair of oxygen defects in the oxide semiconductor in the source and drain regions.

[0031] Therefore, in the semiconductor device 10 according to one embodiment of the present invention, a metal oxide layer 18 including a first region 19-1 and a second region 19-2 spaced apart from each other is provided on the oxide insulating film 14b, and an oxide semiconductor layer 24 is provided on the oxide insulating film 14b and the metal oxide layer 18. A gate electrode 32GE is provided to cover the area between the first region 19-1 and the second region 19-2.

[0032] 2, the oxide semiconductor layer 24 is divided into a first region 24a, a second region 24b, and a third region 24c. The first region 24a is a region of the oxide semiconductor layer 24 vertically below the gate electrode 32GE and does not overlap with the metal oxide layer 18. The second region 24b is a region of the oxide semiconductor layer 24 that does not overlap with the gate electrode 32GE and is in contact with the metal oxide layer 18. The third region 24c is a region of the oxide semiconductor layer 24 vertically below the gate electrode 32GE and overlaps with the metal oxide layers 18-1 and 18-2.

[0033] The thickness of the metal oxide layer 18 is sufficient as long as it is greater than 5 nm, for example, greater than 5 nm and less than 50 nm, greater than 5 nm and less than 30 nm, greater than 5 nm and less than 20 nm, or greater than 5 nm and less than 10 nm. When the thickness of the metal oxide layer 18 is at least greater than 5 nm, it is possible to suppress the migration of oxygen and hydrogen from the nearby insulating film.

[0034] Oxygen is supplied to the first region 24a from both the oxide insulating film 14b and the gate insulating film 26 by the heat treatment. This increases the resistance of the first region 24a, allowing it to function as a semiconductor. Therefore, the first region 24a can function as a channel region. The channel region is provided between the first region 19-1 and the second region 19-2 of the metal oxide layer 18.

[0035] The second region 24b and the third region 24c are regions in contact with the metal oxide layers 18-1 and 18-2. Oxygen is supplied to the second region 24b and the third region 24c from the gate insulating film 26 by heat treatment, but the movement of oxygen from the oxide insulating film 14b is suppressed by the metal oxide layers 18-1 and 18-2. Therefore, the resistance of the second region 24b and the third region 24c is less increased than that of the first region 24a. Furthermore, impurity elements are added to the second region 24b after heat treatment, increasing oxygen defects. Hydrogen-induced electrons are trapped in the oxygen defects, thereby reducing the resistance of the second region 24b. The second region 24b can function as a source region and a drain region. The third region 24c overlaps with the gate electrode 32GE, so no impurity elements are added. Therefore, hydrogen-induced electrons are less likely to be trapped in the oxygen defects. This allows the resistance of the third region 24c to be lower than the resistance of the first region 24a and higher than the resistance of the second region 24b, thereby allowing the third region 24c to function like an LDD (Lightly Doped Drain) region.

[0036] The concentration of impurity elements contained in the second region 24b is 1×10 18 cm -3 More than 1×10 21 cm -3 The impurity element is preferably argon (Ar), phosphorus (P), or boron (B). 18 cm -3 More than 1×10 21 cm -3 If the following is present, it is presumed that impurity elements have been intentionally added by ion implantation or doping. 18 cm -3 Impurity elements other than argon (Ar), phosphorus (P), or boron (B) may be contained at concentrations less than 100000000000000.

[0037] As shown in FIG. 3, in a plan view, the gate wiring 12GL and the gate wiring 32GL extend in the D1 direction, and the gate electrodes 12GE and 32GE extend in the D2 direction. The source wiring SL extends in the D2 direction. The planar patterns of the metal oxide layers 18-1 and 18-2 overlap with the planar pattern of the oxide semiconductor layer 24. In the D1 direction, the width of the gate electrode 12GE is greater than the width of the gate electrode 32GE. The widths of the gate electrodes 12GE and 32GE in the D1 direction are greater than the distance between the metal oxide layers 18-1 and 18-2. The distance between the metal oxide layers 18-1 and 18-2 is the same as the length of the first region 24a. In FIG. 3, the D1 direction is the direction connecting the source electrode SE and the drain electrode DE, and indicates the channel length L of the semiconductor device 10. Specifically, the length in the D1 direction of a first region 24a (channel region) where the oxide semiconductor layer 24 and the gate electrode 32GE overlap is the channel length L, and the length in the D2 direction of the first region 24a is the channel width W.

[0038] In the semiconductor device 10, the resistance can be increased by supplying sufficient oxygen to the first region 24a of the oxide semiconductor layer 24, where the channel region is formed. On the other hand, the resistance can be reduced by suppressing the supply of oxygen to the second region 24b of the oxide semiconductor layer 24, where the source and drain regions of the transistor are formed. This makes it possible to appropriately control the resistance in the channel region and the resistance in the source and drain regions of the semiconductor device 10. As a result, good reliability test results can be obtained for the semiconductor device 10, and the on-current can be increased.

[0039] Here, the reliability test refers to, for example, a negative gate bias-temperature (NGBT) stress test in which a negative voltage is applied to the gate, or a positive gate bias-temperature (PGBT) stress test in which a positive voltage is applied to the gate. BT stress tests, such as those for NGBT and PGBT, are a type of accelerated test that can quickly evaluate changes in transistor characteristics (aging) that occur over long periods of use. In particular, the amount of change in a transistor's threshold voltage before and after a BT stress test is an important indicator for examining reliability. The smaller the amount of change in threshold voltage before and after a BT stress test, the more reliable the transistor.

[0040] <Method for manufacturing semiconductor device 10> A method for manufacturing a semiconductor device 10 according to one embodiment of the present invention will be described with reference to Figures 4 to 10. Figure 4 is a sequence diagram showing a method for manufacturing a semiconductor device 10 according to one embodiment of the present invention. Figures 5 to 10 are cross-sectional views showing a method for manufacturing a semiconductor device 10 according to one embodiment of the present invention.

[0041] As shown in FIGS. 4 and 5, a gate electrode 12GE is formed on the substrate 11, and a gate insulating film 14 is formed on the gate electrode 12GE (see steps S1001 and S1002 shown in FIG. 4).

[0042] As the substrate 11, a rigid substrate having optical transparency, such as a glass substrate, a quartz substrate, or a sapphire substrate, is used. When the substrate 11 needs to be flexible, a polyimide substrate, an acrylic substrate, a siloxane substrate, a fluororesin substrate, or a substrate containing a resin is used as the substrate 11. When a substrate containing a resin is used as the substrate 11, an impurity element may be introduced into the resin to improve the heat resistance of the substrate 11. When the semiconductor device 10 is used as an integrated circuit, a substrate having no optical transparency, such as a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, or a compound semiconductor substrate, or a conductive substrate such as a stainless steel substrate, may be used as the substrate 11.

[0043] The gate electrode 12GE is formed by processing a conductive film formed by sputtering. A common metal material is used for the gate electrode 12GE. For example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof are used for the gate electrode 12GE. The above materials may be used as a single layer or a stacked layer for the gate electrode 12GE.

[0044] The gate insulating film 14 is formed by a CVD (Chemical Vapor Deposition) method or a sputtering method. A general insulating material is used as the gate insulating film 14. For example, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon oxynitride (SiN x O y ) or other inorganic insulating materials are used in a single layer or laminated form. x N y is a silicon compound containing a smaller proportion of nitrogen (N) than oxygen (O) (x>y). SiN x O y is a silicon compound containing a smaller proportion of oxygen than nitrogen (x>y).

[0045] In this embodiment, a nitride insulating film 14a and an oxide insulating film 14b are used as the gate insulating film 14. The nitride insulating film 14a is formed using, for example, silicon nitride. By using silicon nitride, for example, it is possible to block impurities diffusing from the substrate 11 toward the oxide semiconductor layer 24. Furthermore, the oxide insulating film 14b is formed using, for example, silicon oxide. By using silicon oxide, oxygen can be released by heat treatment. The heat treatment temperature at which an oxygen-containing insulating material releases oxygen is, for example, 500°C or less, 450°C or less, or 400°C or less. In other words, silicon oxide releases oxygen at the heat treatment temperature performed in the manufacturing process of the semiconductor device 10 when a glass substrate is used as the substrate 11.

[0046] 4 and 5, a metal oxide film 17 is formed on the oxide insulating film 14b (step S1003 shown in FIG. 4). The metal oxide film 17 is formed by sputtering or atomic layer deposition (ALD).

[0047] For example, a metal oxide containing aluminum as a main component is used as the metal oxide film 17. For example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum oxide nitride (AlN x O y ), aluminum nitride (AlN x) is used. A metal oxide film containing aluminum as a main component means that the ratio of aluminum contained in the metal oxide film is 1% or more of the entire metal oxide film 17. The ratio of aluminum contained in the metal oxide film 17 may be 5% to 70%, 10% to 60%, or 30% to 50% of the entire metal oxide film 17. The above ratio may be a mass ratio or a weight ratio. Alternatively, an oxide semiconductor such as indium gallium zinc oxide (IGZO) may be used as the metal oxide film 17. The use of IGZO as the metal oxide film 17 will be described in detail in a modified example below.

[0048] The thickness of the metal oxide film 17 may be, for example, greater than 5 nm, and may be greater than 5 nm and less than 50 nm, greater than 5 nm and less than 30 nm, greater than 5 nm and less than 20 nm, or greater than 5 nm and less than 10 nm. In this embodiment, aluminum oxide is used as the metal oxide film 17. Aluminum oxide has high barrier properties against gases such as oxygen and hydrogen. In other words, barrier properties refer to the ability to prevent gases such as oxygen and hydrogen from permeating through aluminum oxide. If the thickness of the metal oxide film 17 is greater than 5 nm, it has the effect of preventing gases such as oxygen and hydrogen from migrating from a layer below the aluminum oxide film to a layer above the aluminum oxide film. Alternatively, it has the effect of preventing gases such as oxygen and hydrogen from migrating from a layer above the aluminum oxide film to a layer below the aluminum oxide film. On the other hand, if the thickness of the metal oxide film 17 is 5 nm or less, gases such as oxygen and hydrogen may permeate. In this embodiment, aluminum oxide used as the metal oxide film 17 blocks hydrogen and oxygen released from the oxide insulating film 14b, and prevents the released hydrogen and oxygen from reaching the oxide semiconductor layer to be formed later.

[0049] As shown in FIGS. 4 and 5, an opening OP1 is formed in the metal oxide film 17 (step S1004 shown in FIG. 4). The opening OP1 provided in the metal oxide film 17 is formed in a region overlapping with the gate electrode 12GE. Although not shown, the opening OP1 is formed parallel to the direction in which the gate electrode 12GE extends. The opening OP1 may be formed by wet etching using hydrofluoric acid, for example. In the semiconductor device 10, the width W2 (length in the D1 direction) of the opening OP1 is smaller than the width W1 of the gate electrode 12GE. Furthermore, the width W2 (length in the D1 direction) of the opening OP1 corresponds to the channel length L of a channel region to be formed later. Furthermore, the length (length in the D2 direction) of the opening OP1 is preferably longer than the width (length in the D2 direction) of the oxide semiconductor layer 24 to be formed later.

[0050] 4 and 5, an oxide semiconductor film 21 is formed on the metal oxide film 17 (step S1005 shown in FIG. 4). The oxide semiconductor film 21 is formed by sputtering or atomic layer deposition (ALD). The thickness of the oxide semiconductor film 21 is, for example, greater than 10 nm and less than or equal to 30 nm.

[0051] The oxide semiconductor film 21 can be made of a metal oxide having semiconductor properties. .acid An oxide semiconductor such as indium gallium zinc oxide (IGZO) may be used as the oxide semiconductor film 21 (oxide semiconductor layer 24). The use of IGZO as the oxide semiconductor film 21 will be described in detail later in a modified example.

[0052] When a film is formed on an object by sputtering, ions generated in the plasma and atoms recoiled from the sputtering target collide with the object, causing the temperature of the object to rise during the film formation process. . coveredTo control the temperature of the film-forming object, for example, the film can be formed while the film is being cooled. For example, the film can be cooled from the surface opposite to the surface on which the film is to be formed so that the temperature of the surface on which the film is to be formed (hereinafter referred to as "film formation temperature") is 100°C or less, 70°C or less, 50°C or less, or 30°C or less. In particular, the film formation temperature of the oxide semiconductor film 21 in this embodiment is preferably 50°C or less. Book In this embodiment, the oxide semiconductor film 21 is formed at a film-forming temperature of 50° C. or less, and the OS annealing described below is performed at a heating temperature of 400° C. or more. As described above, in this embodiment, the difference between the temperature when the oxide semiconductor film 21 is formed and the temperature when the oxide semiconductor film 21 is subjected to the OS annealing is preferably 350° C. or more.

[0053] As shown in FIGS. 4 and 6, a pattern of the oxide semiconductor layer 22 is formed (step S1006 shown in FIG. 4). A resist mask 23 is formed on the oxide semiconductor film 21, and the oxide semiconductor film 21 is etched using the resist mask 23. The oxide semiconductor film 21 may be etched by wet etching or dry etching. Wet etching can be performed using an acidic etchant. Examples of the etchant that can be used include oxalic acid, PAN, sulfuric acid, hydrogen peroxide solution, and hydrofluoric acid. This allows the formation of a patterned oxide semiconductor layer 22. Thereafter, the resist mask 23 is removed.

[0054] As shown in FIGS. 4 and 7, after the oxide semiconductor layer 22 is patterned, the oxide semiconductor layer 22 is subjected to a heat treatment (OS annealing) (step S1007 shown in FIG. 4). In the OS annealing, the oxide semiconductor layer 22 is held at a predetermined temperature for a predetermined time. The predetermined temperature is 300° C. or higher and 500° C. or lower, and preferably 350° C. or higher and 450° C. or lower. The holding time at the temperature is 15 minutes or higher and 120 minutes or lower, and preferably 30 minutes or higher and 60 minutes or lower. 。

[0055] In this embodiment, when the oxide semiconductor film 21 is formed by sputtering, the film is formed at a low oxygen partial pressure of 3% or more and 5% or less. 。

[0056] As shown in FIGS. 4 and 8, the metal oxide film 17 is patterned to form a metal oxide layer 18-1 having a first region 19-1 and a metal oxide layer 18-2 having a second region 19-2 (step S1008 shown in FIG. 4). .gold The metal oxide film 17 may be etched by wet etching or dry etching. Book In the embodiment, the length in the D2 direction of the opening OP formed in the metal oxide film 17 is longer than the channel width W of the oxide semiconductor layer. In this state, by etching the metal oxide film 17, the metal oxide film 17 can be separated into a metal oxide layer 18-1 including a first region 19-1 and a metal oxide layer 18-2 including a second region 19-2.

[0057] 4 and 9, the gate insulating film 26 is formed on the oxide semiconductor layer 24 (Step S1009 shown in FIG. 4). The thickness of the gate insulating film 26 is, for example, 50 nm to 300 nm, 60 nm to 200 nm, or 70 nm to 150 nm.

[0058] It is preferable to use an insulating material containing oxygen for the gate insulating film 26. It is also preferable to use an insulating film with few defects for the gate insulating film 26. For example, when the oxygen composition ratio in the gate insulating film 26 is compared with the oxygen composition ratio in an insulating film having the same composition as the gate insulating film 26 (hereinafter referred to as "another insulating film"), the oxygen composition ratio in the gate insulating film 26 is closer to the stoichiometric ratio for the insulating film than the oxygen composition ratio in the other insulating film. For example, when silicon oxide (SiO x) is used, the oxygen composition ratio in the silicon oxide used as the gate insulating film 26 is closer to the stoichiometric ratio of silicon oxide than the oxygen composition ratio in the silicon oxide used as the interlayer insulating film 34. For example, a layer in which no defects are observed when evaluated by electron spin resonance (ESR) may be used as the gate insulating film 26.

[0059] In order to form an insulating film with few defects as the gate insulating film 26, the gate insulating film 26 may be formed at a film formation temperature of 350° C. or higher. Furthermore, after forming the gate insulating film 26, a process of implanting oxygen into a part of the gate insulating film 26 may be performed. In this embodiment, in order to form an insulating film with few defects as the gate insulating film 26, silicon oxide is formed at a film formation temperature of 350° C. or higher.

[0060] 4 and 9, a metal oxide film 28 is formed on the gate insulating film 26 (step S1010 shown in FIG. 4). For the material and film formation method of the metal oxide film 28, refer to the material and film formation method described for the metal oxide film 17. The thickness of the metal oxide film 28 may be greater than 5 nm, and is, for example, greater than 5 nm and less than 50 nm, greater than 5 nm and less than 30 nm, greater than 5 nm and less than 20 nm, or greater than 5 nm and less than 10 nm.

[0061] As shown in FIGS. 4 and 9, with the gate insulating film 26 and the metal oxide film 28 formed on the oxide semiconductor layer 24, a heat treatment (oxidation annealing) is performed to supply oxygen to the oxide semiconductor layer 24 (step S1011 shown in FIG. 4).

[0062] Furthermore, the upper surface of the oxide semiconductor layer 22 is affected by processes (for example, a patterning process or an etching process) performed after the formation of the oxide semiconductor layer 22. On the other hand, the lower surface of the oxide semiconductor layer 22 (the surface of the oxide semiconductor layer 22 on the substrate 11 side) is less susceptible to such effects.

[0063] Therefore, the number of oxygen defects formed on the upper surface of the oxide semiconductor layer 22 is greater than the number of oxygen defects formed on the lower surface of the oxide semiconductor layer 22. In other words, the oxygen defects in the oxide semiconductor layer 22 are not uniformly distributed in the thickness direction of the oxide semiconductor layer 22, but are distributed unevenly in the thickness direction of the oxide semiconductor layer 22. Specifically, the number of oxygen defects in the oxide semiconductor layer 22 is fewer on the lower surface side of the oxide semiconductor layer 22 and more on the upper surface side of the oxide semiconductor layer 22.

[0064] When a uniform oxygen supply process is performed on the oxide semiconductor layer 22 having the above-described distribution of oxygen defects, supplying an amount of oxygen necessary to repair the oxygen defects formed on the upper surface side of the oxide semiconductor layer 22 results in excessive oxygen being supplied to the lower surface side of the oxide semiconductor layer 22. As a result, defect levels different from the oxygen defects are formed on the lower surface side due to the excess oxygen, causing phenomena such as fluctuations in characteristics in reliability tests or a decrease in field-effect mobility. Therefore, in order to suppress such phenomena, it is necessary to supply oxygen to the upper surface side of the oxide semiconductor layer 22 while suppressing the supply of oxygen to the lower surface side of the oxide semiconductor layer 22.

[0065] As described above, oxygen defects are preferably repaired in the channel region of a transistor compared to the source and drain regions.

[0066] Oxygen released from the gate insulating film 26 and the oxide insulating film 14b by the oxidation annealing is blocked by the metal oxide film 28. As a result, oxygen released from the gate insulating film 26 and the oxide insulating film 14b is supplied to the upper surface and side surfaces of the oxide semiconductor layer 24. This reduces oxygen defects on the upper surface and side surfaces of the oxide semiconductor layer 24. Furthermore, oxygen released from the oxide insulating film 14b is blocked by the metal oxide layers 18-1 and 18-2 but is supplied to the first region 24a of the oxide semiconductor layer 24 that is in contact with the oxide insulating film 14b. This reduces oxygen defects in the first region 24a of the oxide semiconductor layer 24 that is in contact with the oxide insulating film 14b. Furthermore, on the lower surface of the oxide semiconductor layer 24, there are regions where oxygen supply is suppressed and regions where oxygen is supplied. Thus, by providing the metal oxide layers 18-1 and 18-2 spaced apart from each other below the oxide semiconductor layer 24, the region where oxygen defects are repaired can be controlled. After the oxidation annealing, the metal oxide film 28 is removed (step S1012 shown in FIG. 4). When the gate wiring 32GL formed in the next step is to be connected to the gate wiring 12GL, contact holes CH1 are formed in the gate insulating films 14 and 16 at this time.

[0067] Next, as shown in FIGS. 4 and 10, a gate electrode 32GE is formed on the gate insulating film 26 (step S1013 shown in FIG. 4).

[0068] The gate electrode 32GE is formed by processing a conductive film formed by sputtering. As with the gate electrode 12GE, a general metal material is used for the gate electrode 32GE. For materials that can be used for the gate electrode 32GE, please refer to the description of the material for the gate electrode 12GE. For the gate electrode 32GE, the above materials may be used in a single layer or a stacked layer.

[0069] 4 and 10, an impurity element is added to the oxide semiconductor layer 24 using the gate electrode 32GE as a mask (step S1014 shown in FIG. 4). In this embodiment, the case where the impurity element is added by ion implantation will be described, but the addition may also be performed by ion doping.

[0070] Specifically, an impurity element is added to the second region 24b of the oxide semiconductor layer 24 by ion implantation through the gate insulating film 26. For example, argon (Ar), phosphorus (P), or boron (B) may be used as the impurity element. When adding boron (B) by ion implantation, the acceleration energy is set to 20 keV or more and 40 keV or less, and the implantation amount of boron (B) is set to 1×10 14 cm -2 More than 1×10 16 cm -2 The following would suffice.

[0071] The second region 24b is doped with an impurity element of 1×10 18 cm -3 More than 1×10 21 cm -3 The impurity element can be added at the following concentration. At this time, oxygen defects are formed in the oxide semiconductor in the second region 24b by adding the impurity element. Electrons are easily trapped in the oxygen defects. This reduces the resistance of the second region 24b, allowing it to function as a conductor.

[0072] The first region 24a and the third region 24c of the oxide semiconductor layer 24 overlap the gate electrode 32GE, and therefore are not doped with impurity elements. Furthermore, oxygen is supplied to the first region 24a from both the oxide insulating film 14b and the gate insulating film 26 by oxygen annealing. This increases the resistance of the first region 24a, allowing it to function as a semiconductor. Oxygen is supplied to the third region 24c from the gate insulating film 26 by oxidation annealing, but oxygen from the oxide insulating film 14b is blocked by the metal oxide layers 18-1 and 18-2. This allows the resistance of the third region 24c to be lower than that of the first region 24a and higher than that of the third region 24c. Therefore, the third region 24c can function like an LDD region.

[0073] As shown in FIG. 4, an interlayer insulating film 34 is formed as an interlayer film on the gate insulating film 26 and the gate electrode 32GE (step S1015 shown in FIG. 4).

[0074] For the film formation method and insulating material of the interlayer insulating film 34, refer to the description of the material of the gate insulating film 14. The film thickness of the interlayer insulating film 34 is 50 nm or more and 500 nm or less. The film thickness of the interlayer insulating film 34 is 50 nm or more and 500 nm or less. In this embodiment, the interlayer insulating film 34 is formed by stacking, for example, silicon oxide and silicon nitride.

[0075] 1, contact holes CH2 and CH3 are formed in the gate insulating film 26 and the interlayer insulating film 34 (step S1016 shown in FIG. 4). The second region 24b of the oxide semiconductor layer 24 is exposed through the contact holes CH2 and CH3.

[0076] Finally, the source electrode 36SE and the drain electrode 36DE are formed on the oxide semiconductor layer 24 exposed by the contact holes and on the interlayer insulating film 34 (step S1017 shown in FIG. 4), thereby completing the semiconductor device 10 shown in FIG. 1.

[0077] The source electrode 36SE and the drain electrode 36DE are formed by processing a conductive film formed by, for example, a sputtering method. As with the gate electrode 12GE, the source electrode 36SE and the drain electrode 36DE are made of a common metal material. For materials that can be used for the source electrode 36SE and the drain electrode 36DE, see the description of the gate electrode 12GE. The above materials may be used as a single layer or a multilayer structure for the source electrode 36SE and the drain electrode 36DE.

[0078] Through the above steps, the semiconductor device 10 shown in FIG. 1 can be manufactured.

[0079] <Variations> Next, semiconductor devices 10A to 10E, which have a structure partially different from that of semiconductor device 10, will be described with reference to FIGS. 11 to 22. In the semiconductor devices 10A to 10E, unless otherwise specified, the case where Poly-OS is used as the oxide semiconductor layer 24 and aluminum oxide is used as the metal oxide film 17 and the metal oxide layer 18 will be described.

[0080] FIG. 11 shows a semiconductor device 10A according to one embodiment of the present invention. FIG. 12 is an enlarged view of a portion of the semiconductor device 10A shown in FIG. 11. The semiconductor device 10A shown in FIG. 11 has a structure in which the gate electrode 32GE does not overlap with the first region 19-1 and the second region 19-2. In other words, the gate electrode 32GE is provided between the metal oxide layer 18-1 and the metal oxide layer 18-2, which are spaced apart from each other. The manufacturing method of the semiconductor device 10A shown in FIG. 11 is the same as that of the semiconductor device 10, and therefore will be described with appropriate reference thereto.

[0081] In FIG. 11, the width of the gate electrode 12GE in the D1 direction is longer than the length of the metal oxide layer 18-1 and the metal oxide layer 18-2, and the width of the gate electrode 32GE is shorter than the length of the metal oxide layer 18-1 and the metal oxide layer 18-2.

[0082] 4, oxygen is supplied to the oxide semiconductor layer 24 in contact with the oxide insulating film 14b from both the oxide insulating film 14b and the gate insulating film 26, thereby reducing oxygen defects. Furthermore, oxygen is supplied to the oxide semiconductor layer 24 in contact with the metal oxide layers 18-1 and 18-2 from the gate insulating film 26, but oxygen supply from the oxide insulating film 14b is suppressed, thereby suppressing repair of oxygen defects. After steps S1012 and S1013 shown in FIG. 4, an impurity element is added to the oxide semiconductor layer 24 using the gate electrode 32GE as a mask in step S1014.

[0083] The region of the oxide semiconductor layer 24 that overlaps with the gate electrode 32GE is not doped with impurity elements because it overlaps with the gate electrode 32GE. Oxygen defects in this region are repaired by oxidation annealing, and no impurity elements are then added. This region can function as a semiconductor and can function as a channel region (first region 24a). In the region of the oxide semiconductor layer 24 that does not overlap with the gate electrode 32GE and overlaps with the metal oxide layers 18-1 and 18-2, oxygen repair is suppressed by oxidation annealing, and impurity elements are also added. This region can function as a conductor and can function as a source region and a drain region (second region 24b). In addition, in the region of the oxide semiconductor layer 24 that does not overlap with the gate electrode 32GE and overlaps with the metal oxide layers 18-1 and 18-2, oxygen defects are repaired by oxidation annealing, and impurity elements are added. Therefore, the resistance of this region can be made higher than that of the second region 24b and lower than that of the first region 24a. This allows the region to function like an LDD region. The region that functions as an LDD region is called a third region 24c.

[0084] <Variation 2> 13 shows a semiconductor device 10B according to one embodiment of the present invention. In the semiconductor device 10B, the gate insulating film 26 is removed except for areas below the gate electrode 32GE and the gate wiring 32GL. In other words, the second region 24b of the oxide semiconductor layer 24 is exposed. Note that the manufacturing method of the semiconductor device 10B shown in FIG. 13 is the same as that of the semiconductor device 10, and therefore will be described with reference to the method as appropriate.

[0085] When manufacturing the semiconductor device 10B, in step S1013 shown in FIG. 4, the gate insulating film 26 may be continuously removed even after the gate electrode 32GE and the gate wiring 32GL are formed by etching. .figure During step S1015 shown in FIG. 4, the oxygen defects tend to trap electrons resulting from hydrogen contained in the interlayer insulating film 34. This can reduce the resistance of the second region 24b.

[0086] <Variation 3> FIG. 14 shows a semiconductor device 10C according to one embodiment of the present invention. FIG. 15 is a plan view showing an overview of the semiconductor device 10C according to one embodiment of the present invention. The semiconductor device 10C has an opening OP1 provided in a metal oxide film 17. The metal oxide film 17 has an opening OP1 between a first region 19-1 and a second region 19-2. The metal oxide film 17 also has an opening OP2 in a region where the gate wiring 12GL and the gate wiring 32GL are connected. In the metal oxide film 17, a region in contact with the second region 24b of the oxide semiconductor layer 24 corresponds to the first region 19-1 and the second region 19-2. Note that the manufacturing method of the semiconductor device 10C shown in FIG. 14 is similar to the manufacturing method of the semiconductor device 10, and therefore will be described with reference to the method as appropriate.

[0087] When manufacturing the semiconductor device 10C, in step S1004 shown in FIG. 4, an opening OP1 is formed in the region overlapping the gate electrode 12GE, and an opening OP2 is also formed in the region overlapping the gate wiring 12GL. The openings OP1 and OP2 may be formed by, for example, wet etching using hydrofluoric acid. In the semiconductor device 10C, the metal oxide film 17 is formed in a film form over the entire surface of the substrate 11. Therefore, the process of patterning the metal oxide film 17 in step S1008 shown in FIG. 4 is omitted. Because the metal oxide film 17 is difficult to etch, it is difficult to form a contact hole in the nitride insulating film 14a, the oxide insulating film 14b, and the gate insulating film 26 in the same process. Therefore, by forming the opening OP2 in advance in step S1004 shown in FIG. 4, it becomes easier to form the contact hole CH1 in the nitride insulating film 14a, the oxide insulating film 14b, and the gate insulating film 26 in a later process.

[0088] When manufacturing the semiconductor device 10C, oxidation annealing is performed in step S1011 shown in FIG. 4 with the metal oxide film 17 and the gate insulating film 26 in contact with each other. FIG. 16 is a diagram illustrating the oxidation annealing process when manufacturing the semiconductor device 10C. As a result, oxygen released from the oxide insulating film 14b is blocked by the metal oxide film 17 but is supplied to the region of the oxide semiconductor layer 24 in contact with the oxide insulating film 14b. In FIG. 16, the metal oxide film 17 is in film form and provided over the entire surface of the substrate 11, so the oxide insulating film 14b and the gate insulating film 26 are hardly in contact with each other. Therefore, during oxidation annealing, oxygen released from the oxide insulating film 14b can be prevented from migrating to the gate insulating film 26. This can prevent oxygen from being supplied to the second region 24b of the oxide semiconductor layer 24. Furthermore, oxygen is supplied intensively to the first region 24a of the oxide semiconductor layer 24, thereby repairing oxygen defects in the first region 24a.

[0089] <Variation 4> 17 shows a semiconductor device 10D according to one embodiment of the present invention. The semiconductor device 10D has the same structure as the semiconductor device 10C, except that the gate insulating film 26 is removed from areas other than those below the gate electrode 32GE and the gate wiring 32GL. In other words, the second region 24b of the oxide semiconductor layer 24 is exposed. The method for manufacturing the semiconductor device 10D shown in FIG. 17 is the same as the method for manufacturing the semiconductor device 10C, and therefore will be described with reference to the method for manufacturing the semiconductor device 10C as appropriate.

[0090] When manufacturing the semiconductor device 10D, in step S1013 shown in FIG. 4, the gate insulating film 26 may be continuously removed even after the gate electrode 32GE and the gate wiring 32GL are formed by etching. .figure During step S1015 shown in FIG. 4, the oxygen defects tend to trap electrons resulting from hydrogen contained in the interlayer insulating film 34. This can reduce the resistance of the second region 24b.

[0091] <Variation 5> Fig. 18 shows a semiconductor device 10E according to one embodiment of the present invention. Fig. 19 is an enlarged view of a portion of the semiconductor device 10E shown in Fig. 11. In the semiconductor device 10E shown in Fig. 18, an oxide semiconductor is used as the metal oxide layers 18-1 and 18-2 instead of aluminum oxide. In the semiconductor device 10E, the oxide semiconductor layers are referred to as oxide semiconductor layers 44-1 and 44-2 to distinguish them from the metal oxide layers 18-1 and 18-2 using aluminum oxide. The oxide semiconductor layers 44-1 and 44-2 may also be referred to as oxide semiconductor layer 44.

[0092] The oxide semiconductor layers 44-1 and 44-2 have a function of suppressing the permeation of oxygen and hydrogen released from the adjacent insulating films. Metal oxides having semiconductor properties can be used as the oxide semiconductor layers 44-1 and 44-2. 。 The content of indium contained in the oxide semiconductor layer 24 is greater than the content of indium contained in the oxide semiconductor layers 44-1 and 44-2. In the semiconductor device 10E, the oxide semiconductor layer 24 and the oxide semiconductor layers 44-1 and 44-2 may be made of different oxide semiconductor materials.

[0093] The oxide semiconductor layers 44-1 and 44-2 may have thicknesses of, for example, greater than 5 nm and less than 50 nm, greater than 5 nm and less than 30 nm, greater than 5 nm and less than 20 nm, or greater than 5 nm and less than 10 nm. When the thicknesses of the oxide semiconductor layers 44-1 and 44-2 are at least 5 nm, permeation of oxygen and hydrogen from adjacent insulating layers can be suppressed. The oxide semiconductor layer 44 has a first region 19-1 and a second region 19-2 that are spaced apart from each other. That is, the first region 19-1 and the second region 19-2 refer to regions of the oxide semiconductor layer 44 that are in contact with the oxide semiconductor layer 24. In FIG. 18, the oxide semiconductor layer 44 includes an oxide semiconductor layer 44-1 including the first region 19-1 and a metal oxide layer 18-2 including the second region 19-2.

[0094] The oxide semiconductor layers 44-1 and 44-2 block oxygen released from the oxide insulating film 14b and also function as semiconductor layers in the semiconductor device 10E. Therefore, the oxide semiconductor layer 24 and the oxide semiconductor layers 44-1 and 44-2 can be regarded as a single semiconductor layer. In this case, the thickness t ch is the thickness of only the oxide semiconductor layer 24. The thickness t SD is the thickness of the oxide semiconductor layer 24, and the oxide semiconductor layer 44-1 or 44-2. The thickness of the region of the second region 24b where the contact hole CH3 is formed is t cnt is the thickness of the oxide semiconductor layer 24, and the oxide semiconductor layer 44-1 or 44-2. When the contact hole CH3 is formed, the second region 24b may be thinned. Therefore, when the film thickness of the oxide semiconductor layers 24 and 44 is ch <t cnt ≦t SD The thinner the oxide semiconductor layer 24, the less oxygen supply is required to oxidize the oxide semiconductor layer 24. Therefore, the thinner the oxide semiconductor layer 24, the lower the resistance can be achieved with a smaller oxygen supply. Therefore, the thickness of the oxide semiconductor layer 24, 44 is set to t ch <t cnt ≦t SDBy satisfying the above relationship, the resistance of the channel region can be reduced, and the resistance of the source region and the drain region can be easily reduced.

[0095] 20 is a sequence diagram showing a method for manufacturing a semiconductor device 10E according to one embodiment of the present invention. The method for manufacturing the semiconductor device 10E shown in FIG. 20 includes many steps similar to those of the semiconductor device 10, so only the differences will be described.

[0096] 20, an IGZO oxide semiconductor film 43 is formed on the oxide insulating film 14b (step S1103 shown in FIG. 20). The oxide semiconductor film 43 is formed by sputtering or atomic layer deposition (ALD). The thickness of the oxide semiconductor film 43 is, for example, greater than 5 nm and less than 50 nm, greater than 5 nm and less than 30 nm, greater than 5 nm and less than 20 nm, or greater than 5 nm and less than 10 nm.

[0097] As shown in FIG. 20, an opening OP1 is formed in the oxide semiconductor film 43 (step S1104 shown in FIG. 4). The opening OP1 provided in the oxide semiconductor film 43 is provided in a region overlapping with the gate electrode 12GE. Although not shown, the opening OP1 is provided so as to be parallel to the direction in which the gate electrode 12GE extends. The width of the opening OP1 corresponds to the channel length L of a channel region to be formed later.

[0098] 20, the oxide semiconductor film 21 is formed on the oxide semiconductor film 43 (Step S1105 shown in FIG. 20). Here, the indium content of the oxide semiconductor film 21 is higher than the indium content of the oxide semiconductor film 43.

[0099] 20 and 21, patterns of the oxide semiconductor layer 44 and the oxide semiconductor layer 24 are formed (step S1106 shown in FIG. 20). A resist mask is formed on the oxide semiconductor film 21, and the oxide semiconductor films 43 and 21 are etched using the resist mask 23. This allows patterned oxide semiconductor layers 22 and 44 to be formed. Thereafter, the resist mask 23 is removed. Steps S1107 to S1116 shown in FIG. 20 are the same as steps S1007 and S1009 to S1017 shown in FIG. 4.

[0100] In the semiconductor device 10E, the oxide semiconductor layers 44-1 and 44-2 have the effect of blocking oxygen released from the oxide insulating film 14b, similar to when aluminum oxide is used for the metal oxide layers 18-1 and 18-2. Therefore, the semiconductor device 10E can obtain good reliability test results and increase the on-current.

[0101] Although not described in detail, IGZO may be used instead of aluminum oxide for the metal oxide layer 18 in the semiconductor devices 10A and 10B as well. When IGZO is used for the metal oxide layer 18, the description of the oxide semiconductor layer 44 of the semiconductor device 10E may be referred to. In this case, the indium content of the oxide semiconductor layer 24 is greater than the indium content of the metal oxide layer 18. In the semiconductor device 10F, the oxide semiconductor material used for the oxide semiconductor layer 24 and the metal oxide layer 18 may be different.

[0102] Second Embodiment Semiconductor devices 10F to 10H according to one embodiment of the present invention will be described with reference to FIGS. . Special Unless otherwise stated in ,gold A case where aluminum oxide is used as the metal oxide films 17, 37 and the metal oxide layers 18, 38 will be described.

[0103] <Configuration of semiconductor device 10F> The configuration of a semiconductor device 10F according to one embodiment of the present invention will be described with reference to Figures 23 to 26. Figure 23 is a cross-sectional view showing an overview of the semiconductor device 10F according to one embodiment of the present invention. Figure 24 is an enlarged view of a portion of the semiconductor device 10F shown in Figure 1.

[0104] As shown in FIG. 23 , the semiconductor device 10F is provided above the substrate 11. The semiconductor device 10F includes at least an oxide insulating film 14b, a metal oxide layer 38, metal oxide layers 18-1 and 18-2, an oxide semiconductor layer 24, a gate insulating film 26, and a gate electrode 32GE. The oxide semiconductor layer 24, the gate insulating film 26, and the gate electrode 32GE may be collectively referred to as a transistor. The semiconductor device 10F may further include a gate electrode 12GE, a nitride insulating film 14a, an interlayer insulating film 34, a source electrode 36SE, and a drain electrode 36DE. The configuration of the semiconductor device 10F is similar to that of the semiconductor device 10, except that a metal oxide layer 38 is provided between the metal oxide layers 18-1 and 18-2 and the oxide semiconductor layer 24.

[0105] The metal oxide layers 18 and 38 are layers containing a metal oxide layer primarily composed of aluminum and function as gas barrier films that block gases such as oxygen and hydrogen. The metal oxide layers 18 and 38 have a first region 19-1 and a second region 19-2 spaced apart from each other, and a third region 19-3 located between the first region 19-1 and the second region 19-2. Specifically, the metal oxide layers 18 and 38 include a metal oxide layer 18-1 located below the first region 19-1, a metal oxide layer 18-2 located below the second region 19-2, and a metal oxide layer 18-3 located below the second region 19-2.

[0106] The metal oxide layers 18 and 38 have the function of suppressing the permeation of oxygen supplied from the adjacent oxide insulating film 14b, and therefore the metal oxide layers 18 and 38 can be regarded as one metal oxide layer.

[0107] The metal oxide layer 38 is provided on the oxide insulating film 14b and the metal oxide layers 18-1 and 18-2. The metal oxide layer 38 is made of aluminum oxide. The film thickness of the metal oxide layers 18-1 and 18-2 is greater than the film thickness of the metal oxide layer 38. The film thickness of the metal oxide layer 38 is 5 nm or less. The metal oxide layers 18-1 and 18-2 are also made of aluminum oxide. The film thickness of the metal oxide layer 18-1 and the metal oxide layer 18-2 is, for example, greater than 5 nm and less than 50 nm, greater than 5 nm and less than 30 nm, greater than 5 nm and less than 20 nm, or greater than 5 nm and less than 10 nm. When the metal oxide layers 18 and 38 are considered as a single metal oxide layer, it is sufficient that the film thickness of the metal oxide layer in the first region 19-1 and the second region 19-2 is greater than the film thickness of the metal oxide layer in the third region 19-3. When the metal oxide layers 18, 38 are regarded as one metal oxide layer, the total thickness of the metal oxide layers 18, 38 in the first region 19-1 and the second region 19-2 may be greater than 5 nm and less than or equal to 50 nm.

[0108] <Method for manufacturing semiconductor device 10F> A method for manufacturing a semiconductor device 10F according to one embodiment of the present invention will be described with reference to Figures 25 to 27. Figure 25 is a sequence diagram showing a method for manufacturing a semiconductor device 10F according to one embodiment of the present invention. In Figure 25, steps S1213 to S1216 are omitted, but since these are the same as steps S1012 to S1015 shown in Figure 4, they may be referred to as appropriate. Figures 26 to 27 are cross-sectional views showing a method for manufacturing a semiconductor device 10F according to one embodiment of the present invention.

[0109] The processes of steps S1201 to S1204 shown in Fig. 25 are the same as the processes of S1001 to S1004 shown in Fig. 3. An opening OP is formed in the metal oxide film 17 by the process of step S1204.

[0110] As shown in FIG. 25, a metal oxide film 37 is formed on the metal oxide film 17 (step S1205 shown in FIG. 25). Like the metal oxide film 17, the metal oxide film 37 is made of a metal oxide containing aluminum as a main component. The metal oxide film 37 may be formed using the same film formation method as the metal oxide film 17. Furthermore, the thickness of the metal oxide film 37 is preferably 5 nm or less.

[0111] The processes of steps S1206 to S1208 shown in FIG. 25 are the same as the processes of steps S1005 to S1007 shown in FIG. 。

[0112] 25, the metal oxide films 17 and 37 are patterned using the oxide semiconductor layer 24 as a mask. As a result, a metal oxide layer 38 and metal oxide layers 18-1 and 18-2 can be formed as shown in Fig. 27. As shown in Fig. 25, the sidewalls of the metal oxide layer 18-1 and 18-2, the sidewall of the metal oxide layer 38, and the sidewall of the oxide semiconductor layer 24 are aligned in a straight line.

[0113] 25 are similar to steps S1009 to S1011 shown in Fig. 4. By the oxidation annealing shown in step S1212, oxygen released from the gate insulating film 26 and the oxide insulating film 14b is blocked by the metal oxide film 28. As a result, oxygen released from the gate insulating film 26 and the oxide insulating film 14b is supplied to the upper surface and side surfaces of the oxide semiconductor layer 24.

[0114] As described above, oxygen defects in the oxide semiconductor layer 24 are not uniformly distributed in the thickness direction of the oxide semiconductor layer 22, and there are more oxygen defects on the upper surface of the oxide semiconductor layer 24 than on the lower surface. When the lower surface of the oxide semiconductor layer 24 is in contact with the oxide insulating film 14b, excess oxygen may be supplied to the lower surface of the oxide semiconductor layer 24. As a result, defect levels different from oxygen defects are formed on the lower surface side due to the excess oxygen, causing phenomena such as fluctuations in characteristics in reliability tests or a decrease in field-effect mobility. Therefore, to suppress such phenomena, it is necessary to supply oxygen to the upper surface side of the oxide semiconductor layer 22 while suppressing the supply of oxygen to the lower surface side of the oxide semiconductor layer 22.

[0115] In the semiconductor device 10F, a metal oxide layer 38 having a thickness of 5 nm or less is provided between the oxide semiconductor layer 24 and the oxide insulating film 14b. Because the metal oxide layer 38 is thin, it can transmit and block oxygen from the oxide insulating film 14b.

[0116] Oxygen is supplied to the first region 24a from both the oxide insulating film 14b and the gate insulating film 26 by the heat treatment. The first region 24a is provided with a metal oxide layer 38, but its thin thickness of 5 nm or less allows oxygen from the oxide insulating film 14b to pass through. Therefore, compared to the semiconductor device 10, excessive oxygen supply to the first region 24a can be suppressed, thereby suppressing the generation of defect levels. The resistance of the first region 24a can be increased by oxidation annealing, allowing it to function as a semiconductor. Therefore, the first region 24a functions as a channel region. The resistance of the first region 24a is higher than the resistances of the second region 24b and the third region 24c.

[0117] The second region 24b and the third region 24c overlap with the metal oxide layers 18-1 and 18-2 and the metal oxide layer 38. Oxygen is supplied to the second region 24b from the gate insulating film 26 by heat treatment, but the movement of oxygen from the oxide insulating film 14b is suppressed by the metal oxide layers 18-1, 18-2, and 38. Therefore, the resistance of the second region 24b and the third region 24c can be reduced more than that of the first region 24a. Furthermore, by adding an impurity element to the second region 24b after oxidation annealing, the resistance can be reduced more than that of the third region 24c. The second region 24b functions as a source region and a drain region, and the third region 24c can function like an LDD region.

[0118] Providing the metal oxide layer 38 having a thickness of 5 nm or less in the third region 19-3 can prevent excessive oxygen from being supplied from the oxide insulating film 14b to the oxide semiconductor layer 24. As a result, it is possible to prevent the formation of defect levels due to oxygen defects excessively supplied to the lower surface side, thereby suppressing characteristic fluctuations in reliability tests and increasing the field-effect mobility.

[0119] Steps S1213 to S1218 in Fig. 25 are the same as steps S1011 to S1017 shown in Fig. 4. Through the above steps, the semiconductor device 10F shown in Fig. 23 can be manufactured.

[0120] In the semiconductor device 10F, IGZO may be used instead of aluminum oxide for the metal oxide layer 18. When IGZO is used for the metal oxide layer 18, the description of the oxide semiconductor layer 44 of the semiconductor device 10E may be referred to. When IGZO is used for the metal oxide layer 18, aluminum oxide is preferably used for the metal oxide layer 38. In this case, the indium content of the oxide semiconductor layer 24 is greater than the indium content of the metal oxide layer 18. In the semiconductor device 10F, the oxide semiconductor material used for the oxide semiconductor layer 24 and the metal oxide layer 18 may be different.

[0121] Next, semiconductor devices 10G to 10H, which have a structure partially different from that of the semiconductor device 10F, will be described with reference to FIGS. 28 to 31. .gold A case where aluminum oxide is used as the metal oxide film 17 and the metal oxide layer 18 will be described.

[0122] Variation 6 FIG. 28 illustrates a semiconductor device 10G according to one embodiment of the present invention. In the semiconductor device 10G, openings OP1 and OP2 are formed in a metal oxide film 17. A first region 19-1 and a second region 19-2 are formed in the metal oxide film 17, sandwiching the opening OP1. Specifically, the metal oxide layer includes a metal oxide layer 38 having a 1-1 portion corresponding to the first region 19-1, a 1-2 portion corresponding to the second region 19-2, and a 1-3 portion corresponding to the third region 19-3; and a metal oxide film 17 having an opening OP1 between the first region 19-1 and the second region 19-2, provided below the 1-1 portion and the 1-2 portion, and corresponding to the first region 19-1 and the second region 19-2. The manufacturing method of the semiconductor device 10G is similar to the manufacturing method of the semiconductor device 10F, and only the differences will be described.

[0123] The manufacturing method of the semiconductor device 10G differs from the manufacturing method of the semiconductor device 10F in step S1109 shown in Fig. 25. In the manufacturing method of the semiconductor device 10G, the metal oxide film 37 is etched using the oxide semiconductor layer 24 as a mask, but it is not necessary to etch the metal oxide film 17. This allows the side surfaces of the oxide semiconductor layer 24 and the metal oxide layer 38 to be linear.

[0124] In the semiconductor device 10G, IGZO may be used instead of aluminum oxide for the metal oxide film 17. When IGZO is used for the metal oxide film 17, the description of the oxide semiconductor film 43 of the semiconductor device 10E may be referred to. When IGZO is used for the metal oxide film 17, aluminum oxide is preferably used for the metal oxide layer 38. When IGZO is used for the metal oxide film 17, the indium content of the oxide semiconductor layer 24 is greater than the indium content of the metal oxide film 17. In the semiconductor device 10G, the oxide semiconductor material used for the oxide semiconductor layer 24 and the metal oxide film 17 may be different. When IGZO is used for the metal oxide film 17 in the manufacturing method of the semiconductor device 10G, the oxide semiconductor film 21 may be etched in step S1207 shown in FIG. 25, and then, in step S1208, only the metal oxide film 37 may be etched in step S1209 to form the metal oxide layer 38.

[0125] <Variation 7> 29 shows a semiconductor device 10H according to one embodiment of the present invention. In the semiconductor device 10H, an opening OP1 and an opening OP2 are provided in the metal oxide film 17. A first region 19-1 and a second region 19-2 are provided in the metal oxide film 17 so as to sandwich the opening OP1. The manufacturing method of the semiconductor device 10H is the same as the manufacturing method of the semiconductor device 10F, and therefore only the differences will be described.

[0126] The manufacturing method of semiconductor device 10H differs from the manufacturing method of semiconductor device 10F in step S1209 of FIG. 25. In the manufacturing method of semiconductor device 10, etching of metal oxide film 17 is not necessary, so step S1209 is omitted. When forming contact hole CH1 in gate insulating film 26, metal oxide film 37, and gate insulating film 14 before forming gate electrode 32GE and gate wiring 32GL, because insulating films made of different materials are included, contact hole CH1 cannot be formed in a single etching step. Therefore, different etching methods must be used for each.

[0127] As a first method, the gate insulating film 26 may be etched by dry etching using a fluorine-based gas, the metal oxide film 37 inside the opening OP2 may be removed by wet etching, and the gate insulating film 14 may be etched by dry etching using a fluorine-based gas. As a second method, the gate insulating film 26 may be etched by dry etching using a fluorine-based gas, the metal oxide film 37 inside the opening OP2 may be removed by dry etching using a chlorine-based gas, and the gate insulating film 14 may be etched by dry etching using a fluorine-based gas. As a third method, the gate insulating film 26 and the metal oxide film 37 may be etched by dry etching using a chlorine-based gas, and the gate insulating film 14 may be etched by dry etching using a fluorine-based gas. As a fourth method, the gate insulating film 26 and the metal oxide film 37 may be etched by wet etching, and the gate insulating film 14 may be etched by dry etching using a fluorine-based gas. Alternatively, the gate insulating film 26, the metal oxide film 37, and the gate insulating film 14 may be etched by dry etching using a fluorine-based gas. However, it is preferable to increase the bias when etching the metal oxide film 37. As shown in FIG. 29, the metal oxide film 37 is also provided inside the opening OP2 of the metal oxide film 37.

[0128] In the semiconductor device 10H, IGZO may be used instead of aluminum oxide for the metal oxide film 17. When IGZO is used for the metal oxide film 17, it is preferable to use aluminum oxide for the metal oxide film 37.

[0129] Variation 8 In the semiconductor devices 10 and 10A to 10E, the oxide semiconductor layer 24 ,stomachIndium gallium zinc oxide (IGZO) may also be used. For the cross-sectional structure when IGZO is used as the oxide semiconductor layer 24, please refer to the description of each of the semiconductor devices 10 and 10A to 10E. .acid A method for manufacturing a semiconductor device in the case where IGZO is used as the oxide semiconductor layer 24 is shown in FIG. 30. The differences between the sequence diagram shown in FIG. 4 and the sequence diagram shown in FIG. 30 are steps S1305, S1306, and S1308. . rear Considering the etching process, it is preferable to form the IGZO film in step S1305 to a thickness of 10 nm to 50 nm, preferably 10 nm to 30 nm. .vinegar In step S1306, it is preferable to etch the oxide semiconductor film 21 using a resist mask and then etch the metal oxide film 17, thereby forming the oxide semiconductor layer 46 and the metal oxide layer 18. The subsequent processes in steps S1307 to S1316 are similar to the processes in steps S1007 and S1009 to S1017 shown in FIG. 4, and therefore detailed description thereof will be omitted.

[0130] <Variation 9> In the semiconductor device 10F, the oxide semiconductor layer 24 is ,stomach Indium gallium zinc oxide (IGZO) may also be used. For the cross-sectional structure when IGZO is used as the oxide semiconductor layer 24, the description of the semiconductor device 10F may be referred to. FIG. 31 shows a method for manufacturing a semiconductor device when IGZO is used as the oxide semiconductor layer 24 in the semiconductor device 10F. The difference between FIG. 31 and the sequence diagram shown in FIG. 25 is the processes of steps S1406 to S1407. .vinegar In step S1406, the IGZO film is preferably formed to a thickness of 10 nm to 50 nm, more preferably 10 nm to 30 nm. .vinegarIn step S1407, it is preferable to etch the oxide semiconductor film 21 using a resist mask and then etch the metal oxide films 17 and 37, thereby forming the oxide semiconductor layer 22 and the metal oxide layers 18 and 38. The subsequent processes in steps S1408 to S1417 are similar to the processes in steps S1007 and S1009 to S1017 shown in FIG. 25, and therefore detailed description thereof will be omitted.

[0131] Variation 10 In the semiconductor device 10G, the oxide semiconductor layer 24 is TE I 25 , in the manufacturing method of the semiconductor device 10G, when IGZO is used as the oxide semiconductor layer 24, both the oxide semiconductor film 21 and the metal oxide film 37 may be etched to form the oxide semiconductor layer 22 and the metal oxide layer 38. When IGZO is used as the oxide semiconductor layer 24, IGZO may be used as the metal oxide film 17 and aluminum oxide may be used as the metal oxide layer 38. In the manufacturing method of the semiconductor device 10G, when IGZO is used as the oxide semiconductor layer 24, the oxide semiconductor layer 22 and the metal oxide layer 38 may be formed by etching both the oxide semiconductor film 21 and the metal oxide film 37 in step S1207 shown in FIG.

[0132] Variation 11 In the semiconductor device 10H, the oxide semiconductor layer 24 is TE I 25 , in the manufacturing method of the semiconductor device 10H, when IGZO is used as the oxide semiconductor layer 24, only the oxide semiconductor film 21 is etched to form the oxide semiconductor layer 22 and the metal oxide layer 38. When IGZO is used as the oxide semiconductor layer 24, aluminum oxide may be used as the metal oxide films 17 and 37. Alternatively, IGZO may be used as the metal oxide film 17, and aluminum oxide may be used as the metal oxide layer 38. In the manufacturing method of the semiconductor device 10H, when IGZO is used as the oxide semiconductor layer 24, only the oxide semiconductor film 21 may be etched to form the oxide semiconductor layer 22 and the metal oxide layer 38 in step S1207 shown in FIG.

[0133] <Variation 12> Although the semiconductor devices 10B to 10H have been described as being such that the width of the gate electrode 32GE in the D1 direction is longer than the length of the first region 24a, the present invention is not limited to this. In the semiconductor devices 10B to 10H, the width of the gate electrode 32GE in the D1 direction may be shorter than the length of the first region 24a of the oxide semiconductor layer 24.

[0134] The above-described embodiments and modifications of the present invention may be combined as appropriate as long as they are not mutually inconsistent. Furthermore, those in which a person skilled in the art appropriately adds or deletes components or modifies designs, or adds or omits processes or modifies conditions, based on the semiconductor device and display device of each embodiment or modification, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0135] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0136] 10: semiconductor device, 10A to 10H: semiconductor device, 12GE: gate electrode, 12GL: gate wiring, 13: gate insulating film, 14: gate insulating film, 14a: nitride insulating film, 14b: oxide insulating film, 17: metal oxide film, 18: metal oxide layer, 18-1: metal oxide layer, 18-2: metal oxide layer, 19-1: first region, 19-2: second region, 19-3: third region, 21: oxide semiconductor film, 22: oxide semiconductor layer, 23: resist mask, 24: oxide semiconductor layer, 24a: first region, 24b: second region, 24c: third region, 26: gate insulating film, 28: metal oxide film, 32GE: gate electrode, 32GL: gate wiring, 34: interlayer insulating film, 36DE: drain electrode, 36SE: source electrode, 36SL: source wiring, 37: metal oxide film, 38: metal oxide layer, 43: oxide semiconductor film, 44: oxide semiconductor layer, 44-1: oxide semiconductor layer, 44-2: oxide semiconductor layer, 46: oxide semiconductor layer, OP1: opening, OP2: opening

Claims

1. an oxide insulating film; a metal oxide layer on the oxide insulating film, the metal oxide layer having a first region and a second region spaced apart from each other; an oxide semiconductor layer provided in contact with the first region and the second region; a gate insulating film provided to cover the oxide semiconductor layer; a gate electrode provided on the oxide semiconductor layer via the gate insulating film, the oxide semiconductor layer includes a channel region overlapping with the gate electrode, and a source region and a drain region sandwiching the channel region; The channel region is in contact with the oxide insulating film between the first region and the second region.

2. The semiconductor device according to claim 1 , wherein the metal oxide layer includes a first metal oxide layer including the first region and a second metal oxide layer including the second region.

3. The semiconductor device according to claim 1 , wherein said metal oxide layer has an opening between said first region and said second region.

4. 2. The semiconductor device according to claim 1, wherein the metal oxide layer has a thickness of more than 5 nm and not more than 10 nm.

5. The semiconductor device according to claim 1 , wherein the metal oxide layer is aluminum oxide or indium gallium zinc oxide.

6. When the metal oxide layer is indium gallium zinc oxide, The semiconductor device according to claim 5 , wherein the content of indium contained in said oxide semiconductor layer is greater than the content of indium contained in said indium gallium zinc oxide.

7. the oxide semiconductor layer contains indium and at least one metal element, the ratio of the indium to the at least one metal element is 50% or more; The semiconductor device according to claim 1 , wherein the oxide semiconductor layer has a polycrystalline structure.

8. an oxide insulating film; a metal oxide layer on the oxide insulating film, the metal oxide layer having a first region and a second region spaced apart from each other, and a third region between the first region and the second region; an oxide semiconductor layer provided in contact with the metal oxide layer; a gate insulating film provided to cover the oxide semiconductor layer; a gate electrode provided on the oxide semiconductor layer via the gate insulating film, the oxide semiconductor layer includes a channel region overlapping with the gate electrode, and a source region and a drain region sandwiching the channel region; the source region contacts the first region, the drain region contacts the second region, and the channel region contacts the third region; a thickness of the metal oxide layer in the first region and the second region being greater than a thickness of the metal oxide layer in the third region;

9. 9. The semiconductor device according to claim 8, wherein the metal oxide layer is aluminum oxide.

10. The metal oxide layer is a first metal oxide layer having a 1-1 portion corresponding to the first region, a 1-2 portion corresponding to the second region, and a 1-3 portion corresponding to the third region; a second metal oxide layer provided under the 1-1 portion and corresponding to the first region; 9. The semiconductor device according to claim 8, further comprising: a third metal oxide layer provided under said first-second portion and corresponding to said second region.

11. the first metal oxide layer has a thickness of 5 nm or less; 11. The semiconductor device according to claim 10, wherein the second metal oxide layer and the third metal oxide layer have a thickness greater than 5 nm and equal to or less than 10 nm.

12. the first metal oxide layer is aluminum oxide; The semiconductor device according to claim 10 , wherein the second metal oxide layer and the third metal oxide layer are aluminum oxide or indium gallium zinc oxide.

13. When the second metal oxide layer and the third metal oxide layer are indium gallium zinc oxide, The semiconductor device according to claim 12 , wherein the content of indium contained in the oxide semiconductor layer is higher than the content of indium contained in the second metal oxide layer and the third metal oxide layer.

14. The metal oxide layer is a first metal oxide layer having a 1-1 portion corresponding to the first region, a 1-2 portion corresponding to the second region, and a 1-3 portion corresponding to the third region; 9. The semiconductor device according to claim 8, further comprising: a second metal oxide layer having an opening between the first region and the second region, the second metal oxide layer being provided under the 1-1 portion and the 1-2 portion, and corresponding to the first region and the second region.

15. the first metal oxide layer has a thickness of 5 nm or less; The semiconductor device according to claim 10 , wherein the second metal oxide layer has a thickness greater than 5 nm and equal to or less than 10 nm.

16. the first metal oxide layer is aluminum oxide; 16. The semiconductor device of claim 15, wherein the second metal oxide layer is aluminum oxide or indium gallium zinc oxide.

17. The semiconductor device according to claim 16 , wherein the content of indium contained in the oxide semiconductor layer is greater than the content of indium contained in the second metal oxide layer.

18. the oxide semiconductor layer contains indium and at least one metal element, the ratio of the indium to the at least one metal element is 50% or more; The semiconductor device according to claim 8 , wherein the oxide semiconductor layer has a polycrystalline structure.

Images