Semiconductor device, and method for manufacturing semiconductor device

Abstract

To provide a semiconductor device which is suitable for improving heat dissipation property of heat generated in a semiconductor element.SOLUTION: A semiconductor device A10 includes a conductive member 10, a semiconductor element 30 and a sealing resin 40. The conductive member 10 includes a wiring part 11 having main surfaces 111 and 112 facing a z1 side and a z2 side in a thickness direction z, and a terminal part 12 having a main surface 121 which is connected to the z2 side in the thickness direction z to the wiring part 11 and faces the z2 side in the thickness direction z. The semiconductor element 30 is positioned on the z2 side in the thickness direction z to the wiring part 11, and is joined to the main surface 112. The semiconductor element 30 has element main surfaces 31 and 32. The wiring part 11 has a side surface 113 facing a direction perpendicular to the thickness direction z. The terminal part 12 has a side surface 122 which faces a direction perpendicular to the thickness direction z and is connected to the side surface 113. The element main surface 32 is exposed from the sealing resin 40, and at least one of the side surfaces 113 and 122 is exposed from the sealing resin 40.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Various configurations have been proposed for semiconductor devices including semiconductor elements. Patent Document 1 discloses an example of a conventional semiconductor device. The semiconductor device disclosed in this document includes leads, a semiconductor element, and a sealing resin. In the semiconductor device described in Patent Document 1, the semiconductor element is mounted on the leads by flip-chip mounting. The leads have a main surface facing one side in the thickness direction and a back surface facing the other side in the thickness direction. The semiconductor element is disposed opposite the main surface of the leads and is bonded to the main surface of the leads via a bonding layer made of, for example, solder. The sealing resin covers the entire semiconductor element and part of the leads. The back surfaces of the leads are exposed from the sealing resin and are bonded to a circuit board via, for example, a bonding material.

[0003] In the semiconductor device having the above configuration, heat generated in the semiconductor element is dissipated through the bonding layer and the leads. However, as the amount of heat generated in the semiconductor element increases due to an increase in the current of the semiconductor device, there is a concern that the heat dissipation through the leads as described above may become insufficient. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-77694

[0005] [overview] The present disclosure has been devised in light of the above-mentioned circumstances, and its main objective is to provide a semiconductor device suitable for improving the heat dissipation properties of heat generated in a semiconductor element mounted on a conductive member by flip-chip bonding.

[0006] A semiconductor device provided by a first aspect of the present disclosure comprises at least one conductive member including a wiring portion having a first main surface facing one side in a thickness direction and a second main surface facing the other side in the thickness direction, and a terminal portion connected to the other side in the thickness direction of the wiring portion and having a third main surface facing the other side in the thickness direction; a semiconductor element located on the other side in the thickness direction of the wiring portion and having a first element main surface facing one side in the thickness direction and a second element main surface facing the other side in the thickness direction; and a sealing resin covering each of the at least one conductive member and the semiconductor element, wherein the semiconductor element is bonded to the second main surface, the wiring portion has a first side surface facing a direction perpendicular to the thickness direction, the terminal portion has a second side surface facing a direction perpendicular to the thickness direction and connected to the first side surface, the second element main surface is exposed from the sealing resin, and at least one of the first side surface and the second side surface is exposed from the sealing resin.

[0007] A second aspect of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising the steps of: preparing a conductive member including a wiring portion having a first main surface facing one side in a thickness direction and a second main surface facing the other side in the thickness direction, and a terminal portion connected to the other side in the thickness direction of the wiring portion, the conductive member being configured by a lead frame; and arranging a semiconductor element on the second main surface; The method includes the steps of: forming a sealing resin to cover the second main surface, the terminal portion, and the semiconductor element; grinding the sealing resin from the other side in the thickness direction to expose the terminal portion and the semiconductor element; and cutting the sealing resin, the terminal portion, and the wiring portion along a plane including the thickness direction.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view (through an insulating layer) showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 3] FIG. 3 is a plan view (transparent to an insulating layer and a sealing resin) showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 4] FIG. 4 is a bottom view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 5] FIG. 5 is a front view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a cross-sectional view showing a step of an example of a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. [Figure 9] FIG. 9 is a cross-sectional view showing a step subsequent to FIG. [Figure 10] FIG. 10 is a cross-sectional view showing a step subsequent to FIG. [Figure 11] FIG. 11 is a cross-sectional view showing a step subsequent to FIG. [Figure 12] FIG. 12 is a cross-sectional view showing a step subsequent to FIG. [Figure 13] FIG. 13 is a cross-sectional view showing a step subsequent to FIG. [Figure 14] FIG. 14 is a cross-sectional view showing a step subsequent to FIG. [Figure 15] FIG. 15 is a cross-sectional view showing a step subsequent to FIG. [Figure 16] FIG. 16 is a cross-sectional view showing an example of a state in which the semiconductor device according to the first embodiment of the present disclosure is used. [Figure 17] FIG. 17 is a cross-sectional view similar to FIG. 6, showing a semiconductor device according to a first modification of the first embodiment. [Figure 18] FIG. 18 is a cross-sectional view similar to FIG. 6, showing a semiconductor device according to a second modification of the first embodiment. [Figure 19]FIG. 19 is a cross-sectional view showing a step of an example of a method for manufacturing a semiconductor device according to the second modification of the first embodiment. [Figure 20] FIG. 20 is a cross-sectional view showing a step subsequent to FIG. [Figure 21] FIG. 21 is a cross-sectional view showing a step subsequent to FIG. [Figure 22] FIG. 22 is a cross-sectional view similar to FIG. 6, showing a semiconductor device according to a second embodiment of the present disclosure. [Figure 23] FIG. 23 is a cross-sectional view showing a step of an example of a method for manufacturing a semiconductor device according to the second embodiment of the present disclosure. [Figure 24] FIG. 24 is a cross-sectional view showing a step subsequent to FIG. [Figure 25] FIG. 25 is a cross-sectional view showing a step subsequent to FIG. [Figure 26] FIG. 26 is a cross-sectional view showing a step subsequent to FIG. [Figure 27] FIG. 27 is a cross-sectional view showing a step subsequent to FIG. [Figure 28] FIG. 28 is a cross-sectional view showing a step subsequent to FIG. [Figure 29] FIG. 29 is a cross-sectional view showing a step subsequent to FIG. [Figure 30] FIG. 30 is a cross-sectional view showing a step subsequent to FIG. [Figure 31] FIG. 31 is a cross-sectional view showing a step subsequent to FIG.

[0010] [Detailed explanation] Preferred embodiments of the present disclosure will now be described in detail with reference to the drawings.

[0011] In the following, identical or similar components are denoted by the same reference numerals, and redundant explanations will be omitted. Terms such as "first," "second," and "third" in this disclosure are used merely as labels and are not intended to necessarily assign any order to their objects.

[0012] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on (an object) B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on (an object) B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on (an object) B" includes "a certain object A is in contact with a certain object B and is located on (an object) B" and "a certain object A is located on (an object) B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, the phrase "object A overlaps object B when viewed in a certain direction" includes "object A overlaps the entire object B" and "object A overlaps a part of object B." Furthermore, the phrase "object A (its material) contains material C" includes "object A (its material) is made of material C" and "object A (its material) is mainly composed of material C." Furthermore, in this disclosure, the phrase "a surface A faces direction B (on one side or the other side of direction B)" is not limited to the case where surface A is at an angle of 90° to direction B, but also includes the case where surface A is tilted with respect to direction B.

[0013] First Embodiment A semiconductor device according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 7. The semiconductor device A10 of this embodiment includes a plurality of conductive members 10, a semiconductor element 30, and a sealing resin 40. In this embodiment, the semiconductor device A10 further includes a bonding layer 39, a first metal layer 51, a seed layer 52, a second metal layer 53, and an insulating layer 60. As shown in FIGS. 1 to 5, the package format of the semiconductor device A10 is a QFN (Quad For Non-Lead Package). However, the package format of the semiconductor device A10 is not limited to QFN.

[0014] FIG. 1 is a plan view of the semiconductor device A10. FIG. 2 is a plan view of the semiconductor device A10, seen through the insulating layer 60. FIG. 3 is a plan view of the semiconductor device A10, seen through the insulating layer 60 and the sealing resin 40. FIG. 4 is a bottom view of the semiconductor device A10. In FIG. 4, the first metal layer 51, the seed layer 52, and the second metal layer 53 are omitted. FIG. 5 is a front view of the semiconductor device A10. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 3. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 3. In FIG. 3, the sealing resin 40 seen through is indicated by an imaginary line (double-dashed line).

[0015] In the description of the semiconductor device A10, the thickness direction (direction in a plan view) of the semiconductor device A10 (conductive member 10) is referred to as the "thickness direction z." A direction perpendicular to the thickness direction z is referred to as the "first direction x." A direction perpendicular to both the thickness direction z and the first direction x is referred to as the "second direction y." As shown in FIGS. 1 and 2, the semiconductor device A10 is rectangular when viewed in the thickness direction z. In the description of the semiconductor device A10, one side of the first direction x is referred to as the "x1 side of the first direction x," and the other side of the first direction x is referred to as the "x2 side of the first direction x." Furthermore, one side of the second direction y is referred to as the "y1 side of the second direction y," and the other side of the second direction y is referred to as the "y2 side of the second direction y." Furthermore, one side of the thickness direction z is referred to as the "z1 side of the thickness direction z," and the other side of the thickness direction z is referred to as the "z2 side of the thickness direction z."

[0016] As shown in FIGS. 2 to 7, the sealing resin 40 covers a portion of each of the plurality of conductive members 10 and a portion of the semiconductor element 30. The sealing resin 40 has electrical insulating properties. An example of a material for the sealing resin 40 is a black epoxy resin. When viewed in the thickness direction z, the sealing resin 40 has a rectangular shape.

[0017] The sealing resin 40 has a first resin main surface 41, a second resin main surface 42, a pair of resin side surfaces 43, and a pair of resin side surfaces 44. The first resin main surface 41 and the second resin main surface 42 face opposite each other in the thickness direction z. The first resin main surface 41 faces the z1 side in the thickness direction z. The second resin main surface 42 faces the z2 side in the thickness direction z. The pair of resin side surfaces 43 are connected to both the first resin main surface 41 and the second resin main surface 42 and face opposite each other in the first direction x. One resin side surface 43 faces the x1 side in the first direction x, and the other resin side surface 43 faces the x2 side in the first direction x. The pair of resin side surfaces 43 are spaced apart from each other in the first direction x. The pair of resin side surfaces 44 are connected to both the first resin main surface 41 and the second resin main surface 42 and face opposite each other in the second direction y. One resin side surface 44 faces the y1 side in the second direction y, and the other resin side surface 44 faces the y2 side in the second direction y. The pair of resin side surfaces 44 are spaced apart from each other in the second direction y.

[0018] As shown in FIGS. 3, 4, and 6, the plurality of conductive members 10 carries a semiconductor element 30. The plurality of conductive members 10 constitute, for example, a conductive path between the semiconductor element 30 and a circuit board or the like on which the semiconductor device A10 is mounted. As shown in FIGS. 1 to 6, the plurality of conductive members 10 are arranged spaced apart from one another along the periphery of the rectangular sealing resin 40 when viewed in the thickness direction z. In the illustrated example, four conductive members 10 are arranged spaced apart in the second direction y along the resin side surfaces 43 on both sides of the sealing resin 40 in the first direction x. Furthermore, four conductive members 10 are arranged spaced apart in the first direction x along the resin side surfaces 44 on both sides of the sealing resin 40 in the second direction y. The arrangement of the plurality of conductive members 10 is not limited to the illustrated example.

[0019] As shown in FIG. 6, a portion of the conductive member 10 is covered with sealing resin 40. Each of the plurality of conductive members 10 includes a wiring portion 11 and a terminal portion 12. The plurality of wiring portions 11 in each of the plurality of conductive members 10 are located at the same position in the thickness direction z. The wiring portion 11 of each of the plurality of conductive members 10 extends inward from the peripheral portion of the sealing resin 40 (either the pair of resin side surfaces 43 or the pair of resin side surfaces 44) as viewed in the thickness direction z.

[0020] The wiring portion 11 has a first main surface 111, a second main surface 112, and a first side surface 113. The first main surface 111 and the second main surface 112 face opposite each other in the thickness direction z. The first main surface 111 faces the z1 side in the thickness direction z. The first main surface 111 is exposed from a first resin main surface 41 of the sealing resin 40. The second main surface 112 faces the z2 side in the thickness direction z and faces the semiconductor element 30. The semiconductor element 30 is mounted on the second main surface 112. The second main surface 112 is covered with the sealing resin 40.

[0021] The first side surface 113 faces in a direction perpendicular to the thickness direction z. The first side surface 113 faces any of the x1 side in the first direction x, the x2 side in the first direction x, the y1 side in the second direction y, and the y2 side in the second direction y. In the illustrated example, in the conductive member 10 arranged along the resin side surface 43 of the sealing resin 40 facing the x1 side in the first direction x, the first side surface 113 faces the x1 side in the first direction x. In the conductive member 10 arranged along the resin side surface 43 of the sealing resin 40 facing the x2 side in the first direction x, the first side surface 113 faces the x2 side in the first direction x. In the conductive member 10 arranged along the resin side surface 44 of the sealing resin 40 facing the y1 side in the second direction y, the first side surface 113 faces the y1 side in the second direction y. In the conductive member 10 arranged along the resin side surface 44 of the sealing resin 40 facing the y2 side in the second direction y, the first side surface 113 faces the x2 side in the first direction x. As shown in FIGS. 5 and 6 , the first side surface 113 is exposed from the sealing resin 40 (either the pair of resin side surfaces 43 or the pair of resin side surfaces 44). The first side surface 113 is flush with the corresponding one of the pair of resin side surfaces 43 or the pair of resin side surfaces 44.

[0022] The terminal portion 12 is connected to the z2 side in the thickness direction z of the wiring portion 11. In each of the plurality of conductive members 10, the terminal portion 12 is located on the periphery of the sealing resin 40 as seen in the thickness direction z.

[0023] The terminal portion 12 has a third main surface 121 and a second side surface 122. The third main surface 121 faces the z2 side in the thickness direction z. The third main surface 121 is exposed from the second resin main surface 42 of the sealing resin 40. The third main surface 121 is flush with the second resin main surface 42. The surface roughness of the third main surface 121 is greater than the surface roughness of the first main surface 111.

[0024] The second side surface 122 faces in a direction perpendicular to the thickness direction z. The second side surface 122 faces any of the x1 side in the first direction x, the x2 side in the first direction x, the y1 side in the second direction y, and the y2 side in the second direction y. In the illustrated example, in the conductive member 10 arranged along the resin side surface 43 of the sealing resin 40 facing the x1 side in the first direction x, the second side surface 122 faces the x1 side in the first direction x. In the conductive member 10 arranged along the resin side surface 43 of the sealing resin 40 facing the x2 side in the first direction x, the second main surface 112 faces the x2 side in the first direction x. In the conductive member 10 arranged along the resin side surface 44 of the sealing resin 40 facing the y1 side in the second direction y, the second main surface 112 faces the y1 side in the second direction y. In the conductive member 10 arranged along the resin side surface 44 of the sealing resin 40 facing the y2 side in the second direction y, the second main surface 112 faces the x2 side in the first direction x. As shown in FIGS. 5 and 6 , the second side surface 122 is connected to the first side surface 113 and is exposed from the sealing resin 40 (either the pair of resin side surfaces 43 or the pair of resin side surfaces 44). The second side surface 122 is flush with the first side surface 113. In addition, the second side surface 122 is flush with the corresponding one of the pair of resin side surfaces 43 or the pair of resin side surfaces 44.

[0025] The conductive members 10 configured as described above may be made of, for example, copper (Cu). These conductive members 10 may be made of, for example, leads and may be obtained from the same lead frame. The conductive member 10 has a second main surface 112 (wiring portion 11) recessed from the third main surface 121 toward the z1 side in the thickness direction z by half-etching to remove a portion corresponding to the wiring portion 11 from the third main surface 121 side of the conductive member 10 (terminal portion 12). As a result of this half-etching, the boundary between the second main surface 112 of the wiring portion 11 and the terminal portion 12 connected thereto has a rounded shape, as shown in FIG. 6.

[0026] As an example of the dimensions of the wiring portion 11 and the terminal portion 12 in the thickness direction z, the first dimension L1 of the wiring portion 11 in the thickness direction z is approximately 50 μm to 100 μm, preferably approximately 75 μm to 100 μm. The second dimension L2 of the terminal portion 12 in the thickness direction z is approximately 65 μm to 140 μm, preferably approximately 65 μm to 90 μm. For example, the first dimension L1 of the wiring portion 11 in the thickness direction z is 35% to 150% of the second dimension L2 of the terminal portion 12 in the thickness direction z. Preferably, the first dimension L1 is 115% to 150% of the second dimension L2, and the first dimension L1 is larger than the second dimension L2. In the illustrated example, the first dimension L1 of the wiring portion 11 in the thickness direction z is, for example, approximately 100 μm, and the second dimension L2 of the terminal portion 12 in the thickness direction z is, for example, approximately 80 μm.

[0027] The semiconductor element 30 is an element that performs a major electrical function in the semiconductor device A10. Specific examples of the semiconductor element 30 are not particularly limited, and include, for example, an LSI (Large Scale Integration) or an IC (Integrated Circuit). The specific shape and size of the semiconductor element 30 are not particularly limited, and in this embodiment, for example, the semiconductor element 30 is rectangular when viewed in the thickness direction z. As shown in FIG. 6 , the semiconductor element 30 has a first element main surface 31 and a second element main surface 32. The first element main surface 31 faces the z1 side in the thickness direction z. The first element main surface 31 faces the second main surface 112 of the wiring portion 11. The first element main surface 31 is covered with the sealing resin 40. The second element main surface 32 faces the z2 side in the thickness direction z. The second element main surface 32 is exposed from a second resin main surface 42 of the sealing resin 40. The second element main surface 32 is flush with the second resin main surface 42.

[0028] As shown in FIG. 6, the semiconductor element 30 is electrically connected to a plurality of conductive members 10 (a plurality of wiring portions 11) by flip-chip bonding. Specifically, a plurality of electrode pads (not shown) are provided on the first element main surface 31. The semiconductor element 30 (the plurality of electrode pads) is electrically connected to at least one of the plurality of wiring portions 11 via a bonding layer 39. The bonding layer 39 is disposed between the second element main surface 112 and the first element main surface 31 (the electrode pads) and is in contact with both the second main surface 112 and the first element main surface 31 (the electrode pads). The bonding layer 39 is conductive. As a result, the semiconductor element 30 (the plurality of electrode pads) is conductively bonded to the second main surface 112 of the plurality of conductive members 10 (the plurality of wiring portions 11). The bonding layer 39 is, for example, solder (a metal containing tin and silver).

[0029] As described above, the terminal portions 12 of the conductive members 10 are located on the periphery of the rectangular sealing resin 40 when viewed in the thickness direction z. As shown in FIGS. 2 to 4 and 6, the terminal portions 12 of the conductive members 10 surround the semiconductor element 30 when viewed in the thickness direction z. The semiconductor element 30 is disposed on the z2 side (the same side as the terminal portions 12) of the wiring portion 11 in the thickness direction z, and each of the terminal portions 12 overlaps the semiconductor element 30 when viewed in a direction perpendicular to the thickness direction z. For example, the dimension of the semiconductor element 30 in the thickness direction z is approximately 25 μm or more and 50 μm or less.

[0030] 5 and 6, the first metal layer 51 is located on the z2 side in the thickness direction z with respect to the third main surface 121 of the terminal portion 12. The first metal layer 51 is in contact with the third main surface 121. The first metal layer 51 is, for example, a plating layer formed on the third main surface 121. The constituent material of the first metal layer 51 is not particularly limited, but is, for example, a metal plating layer formed by laminating nickel (Ni), palladium (Pd), and gold (Au) in this order.

[0031] The seed layer 52 is located on the z2 side in the thickness direction z of the second element main surface 32 of the semiconductor element 30. The seed layer 52 is in contact with the second element main surface 32. The seed layer 52 is a thin film layer formed by stacking, for example, a titanium (Ti) layer and a copper (Cu) layer. The seed layer 52 covers most of the second element main surface 32.

[0032] The second metal layer 53 is located on the z2 side in the thickness direction z with respect to the second element main surface 32 of the semiconductor element 30. The seed layer 52 is interposed between the second element main surface 32 and the second metal layer 53. The second metal layer 53 is in contact with the seed layer 52. The second metal layer 53 is a plating layer formed on the seed layer 52. The constituent material of the second metal layer 53 is not particularly limited, but it is, for example, a metal plating layer formed by stacking nickel (Ni), palladium (Pd), and gold (Au) in this order. In this embodiment, the second metal layer 53 is made of the same material as the first metal layer 51. Unlike this embodiment, the semiconductor device of the present disclosure may be configured without the first metal layer 51, seed layer 52, and second metal layer 53.

[0033] The insulating layer 60 is located on the z1 side in the thickness direction z with respect to the first main surface 111 of the wiring portion 11. The insulating layer 60 is in contact with the first main surface 111. In this embodiment, the insulating layer 60 is in contact with and covers the first main surfaces 111 of the multiple wiring portions 11 (conductive members 10) and the entire first resin main surface 41. The configuration of the insulating layer 60 is not particularly limited, and may be made of, for example, a ceramic sheet or an insulating resin sheet. Note that, unlike this embodiment, the semiconductor device of the present disclosure may be configured without the insulating layer 60.

[0034] Next, an example of a method for manufacturing the semiconductor device A10 will be described below with reference to Figures 8 to 15. Figures 8 to 15 are cross-sectional views showing one step of the method for manufacturing the semiconductor device A10, and correspond to the cross section shown in Figure 6. In Figures 8 to 15, the z1 side in the thickness direction z and the z2 side in the thickness direction z are shown upside down.

[0035] First, a conductive member 10A is prepared as shown in Fig. 8. The conductive member 10A is made of a lead frame. The conductive member 10A is sized to allow multiple semiconductor devices A10 to be fabricated. In other words, the subsequent manufacturing steps are based on a method for manufacturing multiple semiconductor devices A10 at once.

[0036] The conductive member 10A includes a wiring portion 11 and a terminal portion 12. The wiring portion 11 has a first main surface 111 facing the z1 side in the thickness direction z, and a second main surface 112 facing the z2 side in the thickness direction z. The terminal portion 12 is connected to the z2 side in the thickness direction z of the wiring portion 11. This configuration having the second main surface 112 (wiring portion 11) recessed toward the z1 side in the thickness direction z is formed by removing the portion corresponding to the wiring portion 11 from the z2 side in the thickness direction z of the conductive member 10 by half-etching.

[0037] 9, the semiconductor element 30 is placed on the second main surface 112 of the wiring portion 11. Here, the semiconductor element 30 is placed on the second main surface 112 via a bonding layer 39. The bonding layer 39 is, for example, solder, and by placing the semiconductor element 30 and performing a heat treatment (reflow treatment), the constituent material of the bonding layer 39 melts, and the semiconductor element 30 and the second main surface 112 (wiring portion 11) are conductively bonded via the bonding layer 39.

[0038] Next, as shown in FIG. 10 , a sealing resin 40 is formed to cover the second main surface 112 of the wiring portion 11, the terminal portion 12, and the semiconductor element 30. Next, as shown in FIG. 11 , the sealing resin 40 is ground from the z2 side in the thickness direction z. The sealing resin 40 is ground until it reaches the terminal portion 12 and the semiconductor element 30. As a result, the terminal portion 12 and the semiconductor element 30 are exposed from the sealing resin 40, and a third main surface 121, a second element main surface 32, and a second resin main surface 42 are formed. Here, the third main surface 121 and the second element main surface 32 are flush with the second resin main surface 42. The surface roughness of the third main surface 121 formed by grinding is greater than the surface roughness of the unground first main surface 111. After the terminal portion 12 and the semiconductor element 30 are exposed as shown in FIG. 11 , the dimension of the wiring portion 11 in the thickness direction z is 35% to 150% of the dimension of the terminal portion 12 in the thickness direction z.

[0039] Next, as shown in FIG. 12 , a seed layer 52 is formed on the second element main surface 32 of the semiconductor element 30. The seed layer 52 is formed in a predetermined region on the second element main surface 32, for example, by sputtering using a mask. Next, as shown in FIG. 13 , a first metal layer 51 and a second metal layer 53, which are metal plating layers, are formed collectively on the third main surface 121 of the terminal portion 12 and on the seed layer 52. The first metal layer 51 and the second metal layer 53 are formed, for example, by electroless plating. Next, as shown in FIG. 14 , an insulating layer 60 is formed on the first main surface 111 of the wiring portion 11 and on the first resin main surface 41. The insulating layer 60 covers the entire first main surface 111 and the first resin main surface 41.

[0040] 15, the sealing resin 40, the terminal portions 12, and the wiring portions 11 are cut along planes (xz plane and yz plane) including the thickness direction z, for example, by a dicer Dc1. Through these steps, the semiconductor device A10 shown in FIGS. 1 to 7 is manufactured.

[0041] Next, an example of use of the semiconductor device A10 will be described with reference to FIG.

[0042] 16 shows a state in which the semiconductor device A10 is used. In this example of use, the semiconductor device A10 is surface-mounted on a circuit board 90. That is, multiple terminal portions 12 of multiple conductive members 10 are conductively bonded to a wiring pattern (not shown) of the circuit board 90 via a conductive bonding layer 91. The bonding layer 91 is interposed between the first metal layer 51 and the bonding layer 92. Furthermore, the second metal layer 53 formed on the second element main surface 32 (semiconductor element 30) is bonded to the circuit board 90 via a bonding layer 92. The bonding layers 91 and 92 are, for example, solder.

[0043] Next, the operation of this embodiment will be described.

[0044] The semiconductor device A10 includes multiple conductive members 10, semiconductor elements 30, and a sealing resin 40. The conductive members 10 include wiring portions 11 and terminal portions 12 connected to the wiring portions 11 on the z2 side in the thickness direction z. The wiring portions 11 have a first main surface 111 facing the z1 side in the thickness direction z and a second main surface 112 facing the z2 side in the thickness direction z. The terminal portions 12 have a third main surface 121 facing the z2 side in the thickness direction z. The semiconductor elements 30 are located on the z2 side in the thickness direction z of the wiring portions 11, and have a first element main surface 31 facing the z1 side in the thickness direction z and a second element main surface 32 facing the z2 side in the thickness direction z. The semiconductor elements 30 (first element main surface 31) are conductively bonded to the second main surface 112. The second element main surface 32 is exposed from the sealing resin 40. The wiring portion 11 has a first side surface 113 facing in a direction perpendicular to the thickness direction z. The terminal portion 12 has a second side surface 122 facing in a direction perpendicular to the thickness direction z, and the second side surface 122 is connected to the first side surface 113. At least one of the first side surface 113 and the second side surface 122 is exposed from the sealing resin 40. With this configuration, the second element main surface 32 of the semiconductor element 30 is exposed from the sealing resin 40, so that heat generated in the semiconductor element 30 can be efficiently dissipated from the second element main surface 32 to the outside. Furthermore, the heat generated in the semiconductor element 30 can also be dissipated from the first side surface 113 and the second side surface 122 of the conductive member 10 that are exposed from the sealing resin 40. As a result, the heat generated in the semiconductor element 30 is dissipated directly to the outside from the second element main surface 32 of the semiconductor element 30 and is also efficiently dissipated to the outside via the conductive member 10. Therefore, the semiconductor device A10 can improve the heat dissipation performance of the heat generated in the semiconductor element 30.

[0045] The sealing resin 40 has a first resin main surface 41 facing the z1 side in the thickness direction z. The first main surface 111 of the wiring portion 11 is exposed from the first resin main surface 41. With this configuration, heat generated in the semiconductor element 30 can also be released to the outside from the first main surface 111 of the conductive member 10 exposed from the sealing resin 40. This is preferable in terms of improving the heat dissipation performance of the semiconductor device A10.

[0046] A first dimension L1 of the wiring portion 11 in the thickness direction z is larger than a second dimension L2 of the terminal portion 12 in the thickness direction z. With this configuration, heat generation in the conductive member 10 (wiring portion 11) that serves as a conductive path can be suppressed.

[0047] In the semiconductor device A10, the semiconductor element 30 in the multiple conductive members 10 surrounds the semiconductor element 30 when viewed in the thickness direction z. The semiconductor element 30 is disposed on the same side as the terminal portions 12 with respect to the wiring portion 11 in the thickness direction z. With this configuration, each of the multiple terminal portions 12 overlaps the semiconductor element 30 when viewed in a direction perpendicular to the thickness direction z, thereby reducing the dimension of the semiconductor device A10 in the thickness direction z. This allows the volume of the sealing resin 40 to be reduced. This is preferable for improving the heat dissipation of the semiconductor device A10.

[0048] 17 to 31 show modified examples and other embodiments of the semiconductor device of the present disclosure. In these figures, elements that are the same as or similar to those in the above-described embodiment are given the same reference numerals as those in the above-described embodiment, and redundant explanations will be omitted. Furthermore, the configurations of the various parts in each modified example can be combined with each other as appropriate within the scope of not causing technical contradictions.

[0049] <First Modification> 17 shows a first modified example of the semiconductor device A10. FIG. 17 is a cross-sectional view of a semiconductor device A11 according to this modified example, corresponding to the cross section shown in FIG. 6. In this modified example, the relationship between the first dimension L1 of the wiring portion 11 in the thickness direction z and the second dimension L2 of the terminal portion 12 in the thickness direction z differs from that of the semiconductor device A10 of the above embodiment. In the semiconductor device A11, the first dimension L1 of the wiring portion 11 in the thickness direction z is smaller than the second dimension L2 of the terminal portion 12 in the thickness direction z.

[0050] In the semiconductor device A11, the second element main surface 32 of the semiconductor element 30 is exposed from the sealing resin 40, so that heat generated in the semiconductor element 30 can be efficiently dissipated to the outside from the second element main surface 32. Furthermore, the heat generated in the semiconductor element 30 can also be dissipated to the outside from the first side surface 113 and the second side surface 122 of the conductive member 10 that are exposed from the sealing resin 40. As a result, the heat generated in the semiconductor element 30 is dissipated to the outside directly from the second element main surface 32 of the semiconductor element 30 and is also efficiently dissipated to the outside via the conductive member 10. Therefore, the semiconductor device A11 can improve the heat dissipation performance of the heat generated in the semiconductor element 30. In addition, the semiconductor device A11 exhibits the same effects as the semiconductor device A10 within the same configuration as the semiconductor device A10 of the above embodiment.

[0051] <Second Modification> Fig. 18 shows a second modified example of the semiconductor device A10. Fig. 18 is a cross-sectional view of a semiconductor device A12 according to this modified example, corresponding to the cross section shown in Fig. 6. In this modified example, the shape of the terminal portion 12 differs from that of the semiconductor device A10 of the above embodiment. In addition, compared to the semiconductor device A10, a plating layer 54 is further provided.

[0052] In the semiconductor device A12, the second side surface 122 of the terminal portion 12 has a second outer side surface 122a and a second inner side surface 122b. The second outer side surface 122a is flush with the first side surface 113 of the wiring portion 11. The second inner side surface 122b is located on the z2 side in the thickness direction z relative to the second outer side surface 122a. The second inner side surface 122b is located more inward of the sealing resin 40 than the second outer side surface 122a as viewed in the thickness direction z. A plating layer 54 is formed on the second inner side surface 122b. The constituent material of the plating layer 54 is not particularly limited, but may be, for example, a metal plating formed by laminating nickel (Ni), palladium (Pd), and gold (Au) in this order. The plating layer 54 is made of the same material as the first metal layer 51 and is connected to the first metal layer 51.

[0053] 19 to 21 are cross-sectional views showing a step of the manufacturing method of the semiconductor device A12, and correspond to the cross section shown in Fig. 18. In Fig. 19 to 21, the z1 side in the thickness direction z and the z2 side in the thickness direction z are shown upside down.

[0054] In manufacturing the semiconductor device A12, the same steps as in manufacturing the semiconductor device A10 are performed up to the completion of the formation of the seed layer 52. In manufacturing the semiconductor device A12, the state after the formation of the seed layer 52 is completed is the same as that shown in FIG. 12 in the manufacturing method of the semiconductor device A10.

[0055] In manufacturing the semiconductor device A12, as shown in FIG. 19, a dicer Dc1 is used to form grooves of a predetermined depth in the sealing resin 40 and the terminal portions 12 from the z2 side in the thickness direction z. In this step, the sealing resin 40 and the terminal portions 12 are cut partway in the thickness direction z. This forms the second inner side surface 122b. Meanwhile, the z1 side of the terminal portions 12 in the thickness direction z and the wiring portion 11 are not cut.

[0056] 20 , metal plating layers, that is, a first metal layer 51, a plating layer 54, and a second metal layer 53, are formed collectively on the third main surface 121, the second inner side surface 122b, and the seed layer 52 of the terminal portion 12. The first metal layer 51, the plating layer 54, and the second metal layer 53 are formed by, for example, electroless plating.

[0057] 21, the sealing resin 40, the portion of the terminal portion 12 on the z1 side in the thickness direction z, and the wiring portion 11 are cut by a dicer Dc2. Here, the width of the dicer Dc2 is smaller than the width of the dicer Dc1, so the plating layer 54 is not cut. In this manner, the semiconductor device A12 is manufactured.

[0058] In the semiconductor device A12, the second element main surface 32 of the semiconductor element 30 is exposed from the sealing resin 40, so that heat generated in the semiconductor element 30 can be efficiently dissipated to the outside from the second element main surface 32. Furthermore, the heat generated in the semiconductor element 30 can also be dissipated to the outside from the first side surface 113 and the second side surface 122 of the conductive member 10 that are exposed from the sealing resin 40. As a result, the heat generated in the semiconductor element 30 is dissipated to the outside directly from the second element main surface 32 of the semiconductor element 30, and is also efficiently dissipated to the outside via the conductive member 10. Therefore, the semiconductor device A12 can improve the heat dissipation performance of the heat generated in the semiconductor element 30.

[0059] In the semiconductor device A12, the second inner side surface 122b of the terminal portion 12 is covered with a plating layer 54. The plating layer 54 has excellent wettability to solder. With this configuration, for example, when the semiconductor device A12 is joined to a circuit board by soldering, the plating layer 54 is appropriately covered with solder. This increases the bonding strength of the solder fillets formed on the second inner side surface 122b (second side surface 122) of each of the multiple terminal portions 12. In addition, the semiconductor device A12 exhibits the same effects as the semiconductor device A10 of the above embodiment.

[0060] Second Embodiment 22 shows a semiconductor device A20 according to the second embodiment of the present disclosure. Fig. 22 is a cross-sectional view of the semiconductor device A20, and corresponds to the cross section shown in Fig. 6.

[0061] The semiconductor device A20 of this embodiment differs from the above-described embodiment in the configuration of the conductive member 10. Furthermore, the semiconductor device A20 does not include the insulating layer 60. On the other hand, the semiconductor device A20 includes a substrate 70 and a seed layer 81.

[0062] In this embodiment, the plurality of conductive members 10 (wiring portions 11 and terminal portions 12) are made of, for example, metal plating. The metal material constituting the plurality of conductive members 10 is, for example, copper (Cu) or a copper alloy.

[0063] The multiple wiring portions 11 in each of the multiple conductive members 10 are at the same position in the thickness direction z. When viewed in the thickness direction z, the wiring portions 11 of each of the multiple conductive members 10 extend from the peripheral portion of the sealing resin 40 (either the pair of resin side surfaces 43 or the pair of resin side surfaces 44) toward the inside of the sealing resin 40. The first side surfaces 113 of the wiring portions 11 are exposed from the sealing resin 40 (either the pair of resin side surfaces 43 or the pair of resin side surfaces 44).

[0064] In the semiconductor device A20, in each of the multiple conductive members 10, the terminal portion 12 is located slightly inward from the peripheral edge of the sealing resin 40 when viewed in the thickness direction z. The second side surface 122 of the terminal portion 12 is located more inward from the sealing resin 40 than the first side surface 113 when viewed in the thickness direction z. The second side surface 122 is located on the first side surface 113. The second side surface 122 is not connected to the first side surface 113 and is covered by the sealing resin 40. Note that, unlike the configuration illustrated in the present embodiment, the second side surface 122 may be connected to the first side surface 113 and exposed from the sealing resin 40.

[0065] The substrate 70 is located on the z1 side in the thickness direction z with respect to the conductive member 10 and the sealing resin 40. The substrate 70 has a first substrate main surface 71 and a second substrate main surface 72. The first substrate main surface 71 and the second substrate main surface 72 face opposite each other in the thickness direction z. The first substrate main surface 71 faces the z1 side in the thickness direction z. The second substrate main surface 72 faces the z2 side in the thickness direction z. The second substrate main surface 72 contacts the first resin main surface 41. The substrate 70 is made of an insulating material or a semiconductor material. In this embodiment, the substrate 70 is made of a semiconductor material, and the semiconductor material is silicon (Si).

[0066] The seed layer 81 is located on the z1 side in the thickness direction z with respect to the first main surface 111 of the wiring portion 11. The seed layer 81 is interposed between the first main surface 111 and the second substrate main surface 72. The seed layer 81 is in contact with both the first main surface 111 and the second substrate main surface 72. The seed layer 81 is a thin film layer in which, for example, a titanium (Ti) layer and a copper (Cu) layer are stacked.

[0067] Next, an example of a method for manufacturing the semiconductor device A20 will be described below with reference to Figures 23 to 31. Figures 23 to 31 are cross-sectional views showing one step of the method for manufacturing the semiconductor device A20, and correspond to the cross section shown in Figure 22. Note that in Figures 23 to 31, the z1 side in the thickness direction z and the z2 side in the thickness direction z are shown upside down.

[0068] First, a base material 70A is prepared as shown in FIG. 23. The base material 70A is made of a single crystal of a semiconductor material, and in this embodiment, it is made of single crystal Si. The base material 70A is a member that will later become the substrate 70. Although detailed illustration is omitted, an insulating layer is formed on the surface of the base material 70A facing the z2 side in the thickness direction z (second substrate main surface 72). The insulating layer is formed by thermally oxidizing the surface of the base material 70A facing the z2 side in the thickness direction z. The base material 70A has a size that allows multiple semiconductor devices A20 described above to be obtained. In other words, the subsequent manufacturing steps are based on a method of manufacturing multiple semiconductor devices A20 collectively.

[0069] 23, a seed layer 81 is formed on the surface (second substrate main surface 72) of the base material 70A facing the z2 side in the thickness direction z. The seed layer 81 is formed in a predetermined region on the second substrate main surface 72 by, for example, a sputtering method using a mask.

[0070] Next, as shown in FIG. 24, the wiring portion 11 is formed on the surface of the seed layer 81 on the z2 side in the thickness direction z. The wiring portion 11 is formed by depositing a constituent material of the wiring portion 11 on the seed layer 81 by electrolytic plating. Next, as shown in FIG. 25, the terminal portion 12 is formed on the surface of the wiring portion 11 on the z2 side in the thickness direction z (second main surface 112). Although detailed illustration is omitted, the terminal portion 12 is formed by forming an opening by photolithography and electrolytic plating. Here, a resist layer is disposed on the surface of the base material 70A on the z2 side in the thickness direction z (second substrate main surface 72) and the surface of the wiring portion 11 on the z2 side in the thickness direction z (second main surface 112). An opening is formed in a part of the resist layer corresponding to the formation region of the terminal portion 12. By forming the opening, a part of the surface of the wiring portion 11 on the z2 side in the thickness direction z is exposed from the resist layer. Then, the terminal portion 12 that contacts the wiring portion 11 is deposited in the opening by electrolytic plating.

[0071] 26 , the semiconductor element 30 is placed on the second main surface 112 of the wiring portion 11. Here, the semiconductor element 30 is placed on the second main surface 112 via a bonding layer 39. The bonding layer 39 is, for example, solder, and by placing the semiconductor element 30 and performing a heat treatment (reflow treatment), the constituent material of the bonding layer 39 melts, and the semiconductor element 30 and the second main surface 112 (wiring portion 11) are conductively bonded via the bonding layer 39.

[0072] 27, a sealing resin 40 is formed to cover the second main surface 112 of the wiring portion 11, the terminal portions 12, and the semiconductor element 30. Next, as shown in FIG. 28, the sealing resin 40 is ground from the z2 side in the thickness direction z. The sealing resin 40 is ground until it reaches the terminal portions 12 and the semiconductor element 30. As a result, the terminal portions 12 and the semiconductor element 30 are exposed from the sealing resin 40, and a third main surface 121, a second element main surface 32, and a second resin main surface 42 are formed. Here, the third main surface 121 and the second element main surface 32 are flush with the second resin main surface 42.

[0073] Next, as shown in Fig. 29, a seed layer 52 is formed on the second element main surface 32 of the semiconductor element 30. The seed layer 52 is formed in a predetermined region on the second element main surface 32 by, for example, a sputtering method using a mask. Next, as shown in Fig. 30, a first metal layer 51 and a second metal layer 53, which are metal plating layers, are formed collectively on the third main surface 121 of the terminal portion 12 and on the seed layer 52. The first metal layer 51 and the second metal layer 53 are formed by, for example, electroless plating.

[0074] 31, the sealing resin 40, the wiring portion 11, and the base material 70A are cut along planes (xz plane and yz plane) including the thickness direction z, for example, by a dicer Dc1. Through these steps, the semiconductor device A20 shown in FIG. 22 is manufactured.

[0075] In the semiconductor device A20, the second element main surface 32 of the semiconductor element 30 is exposed from the sealing resin 40, so that heat generated in the semiconductor element 30 can be efficiently dissipated to the outside from the second element main surface 32. Furthermore, the heat generated in the semiconductor element 30 can also be dissipated to the outside from the first side surface 113 of the conductive member 10 that is exposed from the sealing resin 40. As a result, the heat generated in the semiconductor element 30 is dissipated to the outside directly from the second element main surface 32 of the semiconductor element 30, and is also efficiently dissipated to the outside via the conductive member 10. Therefore, the semiconductor device A20 can improve the heat dissipation performance of the heat generated in the semiconductor element 30.

[0076] The bonding strength of the sealing resin 40 to the conductive member 10 containing copper (Cu) is greater than the bonding strength of the sealing resin 40 to the substrate 70 made of silicon (Si). That is, the sealing resin 40 is less likely to peel off at the interface between the conductive member 10 and the sealing resin 40 than at the interface between the substrate 70 and the sealing resin 40. In this embodiment, the first side surface 113 of the wiring portion 11 is exposed from the sealing resin 40, and the sealing resin 40 contacts the conductive member 10 (wiring portion 11) near the first side surface 113 of the wiring portion 11. This configuration can prevent the sealing resin 40 from peeling off from the substrate 70. In addition, the semiconductor device A20 exhibits the same effects as the semiconductor device A10 of the above embodiment within the same configuration range.

[0077] The semiconductor device according to the present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the semiconductor device according to the present disclosure can be freely modified in various ways.

[0078] The present disclosure includes configurations relating to the following notes. [Appendix 1] At least one conductive member including a wiring portion having a first main surface facing one side in a thickness direction and a second main surface facing the other side in the thickness direction, and a terminal portion connected to the other side in the thickness direction with respect to the wiring portion and having a third main surface facing the other side in the thickness direction; a semiconductor element located on the other side in the thickness direction with respect to the wiring portion, the semiconductor element having a first element main surface facing one side in the thickness direction and a second element main surface facing the other side in the thickness direction; a sealing resin that covers a portion of each of the at least one conductive member and the semiconductor element, the semiconductor element is bonded to the second main surface, the wiring portion has a first side surface facing a direction perpendicular to the thickness direction, the terminal portion has a second side surface that faces a direction perpendicular to the thickness direction and is connected to the first side surface, the second element main surface is exposed from the sealing resin, At least one of the first side surface and the second side surface is exposed from the sealing resin. [Appendix 2] the sealing resin has a first resin main surface facing one side in the thickness direction, 2. The semiconductor device according to claim 1, wherein the first main surface is exposed from the first resin main surface. [Appendix 3] 3. The semiconductor device according to claim 1, wherein the semiconductor element is conductively bonded to the second main surface via a bonding layer. [Appendix 4] 4. The semiconductor device according to any one of claims 1 to 3, wherein a first dimension of the wiring portion in the thickness direction is 35% to 150% of a second dimension of the terminal portion in the thickness direction. [Appendix 5] 5. The semiconductor device of claim 4, wherein the first dimension is greater than the second dimension. [Appendix 6] a plurality of the conductive members; 6. The semiconductor device according to claim 1, wherein the terminal portions of the conductive members surround the semiconductor element when viewed in the thickness direction. [Appendix 7] the sealing resin has a second resin main surface facing the other side in the thickness direction, 7. The semiconductor device according to any one of claims 1 to 6, wherein the third main surface and the second element main surface are flush with the second resin main surface. [Appendix 8] The semiconductor device according to any one of claims 1 to 7, further comprising a first metal layer located on the other side of the third main surface in the thickness direction and in contact with the third main surface. [Appendix 9] The semiconductor device according to claim 8, further comprising a second metal layer located on the other side of the second element main surface in the thickness direction. [Appendix 10] 10. The semiconductor device according to claim 9, wherein the first metal layer and the second metal layer are made of the same material. [Appendix 11] 11. The semiconductor device according to claim 9, further comprising a seed layer interposed between the second element main surface and the second metal layer. [Appendix 12] 12. The semiconductor device according to claim 1, wherein each of the at least one conductive member is formed of a lead frame. [Appendix 13] the sealing resin has a resin side surface facing a direction perpendicular to the thickness direction, 13. The semiconductor device according to any one of claims 1 to 12, wherein the first side surface is exposed from the resin side surface and is flush with the resin side surface. [Appendix 14] the second side surface has a second outer side surface that is flush with the first side surface, and a second inner side surface that is located on the other side of the second outer side surface in the thickness direction and that is located more inward of the sealing resin than the second outer side surface when viewed in the thickness direction, 14. The semiconductor device of claim 13, further comprising a plating layer formed on the second inner side surface. [Appendix 15] 15. The semiconductor device according to any one of claims 1 to 14, wherein the third main surface has a surface roughness greater than the surface roughness of the first main surface. [Appendix 16] 16. The semiconductor device according to any one of claims 1 to 15, further comprising an insulating layer located on one side of the first main surface in the thickness direction and in contact with the first main surface. [Appendix 17] a step of preparing a conductive member constituted by a lead frame, the conductive member including a wiring portion having a first main surface facing one side in a thickness direction and a second main surface facing the other side in the thickness direction, and a terminal portion connected to the other side in the thickness direction of the wiring portion; disposing a semiconductor element on the second main surface; forming a sealing resin to cover the second main surface, the terminal portion, and the semiconductor element; grinding the sealing resin from the other side in the thickness direction to expose the terminal portion and the semiconductor element; cutting the sealing resin, the terminal portion, and the wiring portion along a plane including the thickness direction. [Appendix 18] 18. The method for manufacturing a semiconductor device according to claim 17, further comprising the step of forming a seed layer on the semiconductor element after the step of exposing the terminal portion and the semiconductor element. [Appendix 19] 19. The method for manufacturing a semiconductor device according to claim 18, further comprising the step of forming a metal plating layer on the terminal portion and on the seed layer all at once after the step of forming a seed layer on the semiconductor element. [Appendix 20] 20. The method for manufacturing a semiconductor device according to any one of appendices 17 to 19, wherein after the step of exposing the terminal portion and the semiconductor element, the dimension of the wiring portion in the thickness direction is 35% or more and 150% or less of the dimension of the terminal portion in the thickness direction. [Explanation of symbols]

[0079] A10, A11, A12, A20: Semiconductor device 10, 10A: Conductive material 11:Wiring section 111: First main surface 112: Second main surface 113 :1st side 12:Terminal section 121: Third main surface 122:Second side 122a: 2nd outer side 122b: 2nd medial side 30: Semiconductor element 31: First element main surface 32: Second element principal surface 39: Bonding layer 40: Sealing resin 41: First resin main surface 42: Second resin main surface 43, 44: Resin side 51: 1st metal layer 52: Seed layer 53: 2nd metal layer 54: Plating layer 60: Insulating layer 70: Circuit board 70A: Base material 71: First substrate main surface 72: Second substrate main surface 90: Circuit board 91,92: Bonding layer Dc1, Dc2: Dicer L1: First dimension L2: Second dimension L3: Dimensions x :1st direction y: second direction z: thickness direction

Claims

1. at least one conductive member including a wiring portion having a first main surface facing one side in a thickness direction and a second main surface facing the other side in the thickness direction, and a terminal portion connected to the other side in the thickness direction with respect to the wiring portion and having a third main surface facing the other side in the thickness direction; a semiconductor element located on the other side in the thickness direction with respect to the wiring portion, the semiconductor element having a first element main surface facing one side in the thickness direction and a second element main surface facing the other side in the thickness direction; a sealing resin covering each part of the at least one conductive member and the semiconductor element, the semiconductor element is bonded to the second main surface, the wiring portion has a first side surface facing a direction perpendicular to the thickness direction, the terminal portion has a second side surface that faces a direction perpendicular to the thickness direction and is connected to the first side surface, the second element main surface is exposed from the sealing resin, At least one of the first side surface and the second side surface is exposed from the sealing resin.

2. the sealing resin has a first resin main surface facing one side in the thickness direction, The semiconductor device according to claim 1 , wherein the first main surface is exposed from the first resin main surface.

3. The semiconductor device according to claim 1 , wherein the semiconductor element is conductively bonded to the second main surface via a bonding layer.

4. 2 . The semiconductor device according to claim 1 , wherein a first dimension of said wiring portion in said thickness direction is 35% to 150% of a second dimension of said terminal portion in said thickness direction.

5. The semiconductor device according to claim 4 , wherein the first dimension is greater than the second dimension.

6. a plurality of the conductive members; The semiconductor device according to claim 1 , wherein the terminal portions of the conductive members surround the semiconductor element when viewed in the thickness direction.

7. the sealing resin has a second resin main surface facing the other side in the thickness direction, The semiconductor device according to claim 1 , wherein the third main surface and the second element main surface are flush with the second resin main surface.

8. 2. The semiconductor device according to claim 1, further comprising a first metal layer located on the other side of said third main surface in said thickness direction and in contact with said third main surface.

9. 9. The semiconductor device according to claim 8, further comprising a second metal layer located on the other side of said second element main surface in said thickness direction.

10. The semiconductor device according to claim 9 , wherein the first metal layer and the second metal layer are made of the same material.

11. The semiconductor device according to claim 10 , further comprising a seed layer interposed between the second element main surface and the second metal layer.

12. The semiconductor device according to claim 1 , wherein each of said at least one conductive member is formed by a lead frame.

13. the sealing resin has a resin side surface facing a direction perpendicular to the thickness direction, The semiconductor device according to claim 1 , wherein the first side surface is exposed from the resin side surface and is flush with the resin side surface.

14. the second side surface has a second outer side surface that is flush with the first side surface, and a second inner side surface that is located on the other side of the second outer side surface in the thickness direction and that is located more inward of the sealing resin than the second outer side surface when viewed in the thickness direction; The semiconductor device according to claim 13 , further comprising a plating layer formed on the second inner side surface.

15. The semiconductor device according to claim 1 , wherein the third main surface has a surface roughness greater than that of the first main surface.

16. The semiconductor device according to claim 1 , further comprising an insulating layer located on one side of said first main surface in said thickness direction and in contact with said first main surface.

17. a step of preparing a conductive member constituted by a lead frame, the conductive member including a wiring portion having a first main surface facing one side in a thickness direction and a second main surface facing the other side in the thickness direction, and a terminal portion connected to the other side in the thickness direction of the wiring portion; disposing a semiconductor element on the second major surface; forming a sealing resin to cover the second main surface, the terminal portion, and the semiconductor element; grinding the sealing resin from the other side in the thickness direction to expose the terminal portion and the semiconductor element; cutting the sealing resin, the terminal portion, and the wiring portion along a plane including the thickness direction.

18. The method for manufacturing a semiconductor device according to claim 17 , further comprising the step of forming a seed layer on the semiconductor element after the step of exposing the terminal portion and the semiconductor element.

19. 20. The method for manufacturing a semiconductor device according to claim 18, further comprising the step of forming a metal plating layer on the terminal portion and on the seed layer all at once after the step of forming a seed layer on the semiconductor element.

20. 20. The method for manufacturing a semiconductor device according to claim 17, wherein after the step of exposing the terminal portion and the semiconductor element, the dimension of the wiring portion in the thickness direction is 35% or more and 150% or less of the dimension of the terminal portion in the thickness direction.

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