Semiconductor device

Abstract

To provide a semiconductor device that can improve mounting reliability during mounting onto a wiring board.SOLUTION: A semiconductor device A10 comprises a semiconductor element 3 having an element main surface 305 oriented in the thickness direction z and on which an electrode 33 is disposed, and a sealing resin 4 having a resin top surface 41 facing the first side z1 in the thickness direction z and covering the semiconductor element 3. The element main surface 305 and the resin top surface 41 are rectangular. Viewed in the thickness direction z, edge 305a of the element main surface 305 is inclined relative to edge 41a of the resin top surface 41.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Various configurations have been proposed for semiconductor devices including semiconductor elements. Patent Document 1 discloses an example of an electronic device packaged in a QFN (Quad Flat Non-Lead Package). The electronic device disclosed in this document includes multiple leads, an electronic component, and a resin member. The electronic component is supported by the multiple leads. The resin member covers a portion of each lead and the electronic component. The resin member and electronic component are rectangular in plan view. In this electronic device, end faces of the multiple leads are exposed so as to be flush with the side surfaces of the resin member. In addition, the back surfaces of the multiple leads are exposed so as to be flush with the back surface of the resin member. Therefore, compared to a QFP (Quad Flat Package) in which the leads protrude from the side surfaces of the resin member, this electronic device has the advantage of being smaller and requiring a smaller mounting area on a wiring board. However, this electronic device has lower mounting reliability compared to a QFP.

[0003] When a semiconductor device (called an electronic device in the patent document) is mounted on a wiring board using solder or the like, the leads located at each corner have lower mounting reliability than other leads because stress due to differences in linear expansion coefficients is concentrated on the solder joined to the backside. Furthermore, the higher the chip occupancy rate, which is the ratio of the area of ​​the semiconductor element to the area of ​​the semiconductor device in a plan view, the lower the mounting reliability. This is because the higher the chip occupancy rate, the shorter the distance between the corners of the semiconductor device and the semiconductor element. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2023-42910

[0005] [overview] The present disclosure has been made in light of the above circumstances, and a main object of the present disclosure is to provide a semiconductor device that can improve the mounting reliability when mounted on a wiring board.

[0006] A semiconductor device provided by a first aspect of the present disclosure comprises a semiconductor element having an element main surface facing a thickness direction and on which electrodes are arranged, and a sealing resin having a resin top surface facing a first side in the thickness direction and covering the semiconductor element, wherein the element main surface and the resin top surface are rectangular, and when viewed in the thickness direction, a first side of the element main surface is inclined with respect to a second side of the resin top surface.

[0007] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 3] FIG. 3 is a plan view (through a sealing resin) showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 4] FIG. 4 is a bottom view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 5] FIG. 5 is a front view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 6] FIG. 6 is a rear view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 7] FIG. 7 is a right side view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 8] FIG. 8 is a left side view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. [Figure 10] FIG. 10 is a cross-sectional view taken along line XX in FIG. [Figure 11] FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. [Figure 12] FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. [Figure 13] FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. [Figure 14] FIG. 14 is a plan view showing a semiconductor device according to a first modification of the first embodiment. [Figure 15] FIG. 15 is a plan view (through a sealing resin) showing a semiconductor device according to a second embodiment of the present disclosure. [Figure 16] FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. [Figure 17] FIG. 17 is a plan view (through the sealing resin) showing a semiconductor device according to a first modified example of the second embodiment. [Figure 18] FIG. 18 is a plan view (through the sealing resin) showing a semiconductor device according to a second modification of the second embodiment. [Figure 19] FIG. 19 is a plan view (through a sealing resin) showing a semiconductor device according to a third embodiment of the present disclosure. [Figure 20] FIG. 20 is a plan view showing a semiconductor device according to a fourth embodiment of the present disclosure. [Figure 21] FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG.

[0009] [Detailed explanation] The details of the present disclosure will be described with reference to the accompanying drawings.

[0010] Terms such as "first," "second," and "third" in this disclosure are used merely as labels and are not necessarily intended to dictate any ordering of their objects.

[0011] In this disclosure, unless otherwise specified, the terms "a certain object A is formed on an object B" and "a certain object A is formed on an object B" include "a certain object A is formed directly on an object B" and "a certain object A is formed on an object B with another object interposed between the objects A and B." Similarly, the terms "a certain object A is disposed on an object B" and "a certain object A is disposed on an object B" include "a certain object A is disposed directly on an object B" and "a certain object A is disposed on an object B with another object interposed between the objects A and B," unless otherwise specified. Similarly, the term "a certain object A is located on an object B" includes "a certain object A is located on an object B in contact with the object B" and "a certain object A is located on an object B with another object interposed between the objects A and B," unless otherwise specified. Furthermore, unless otherwise specified, the phrase "an object A overlaps an object B when viewed in a certain direction" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." Furthermore, in this disclosure, "a surface A faces (one side or the other side of) direction B" is not limited to the case where the angle of surface A with respect to direction B is 90°, but also includes the case where surface A is tilted with respect to direction B.

[0012] First Embodiment A semiconductor device A10 according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 13. The semiconductor device A10 of this embodiment includes a conductive member 1, a semiconductor element 3, and a sealing resin 4. As shown in FIG. 1, the semiconductor device A10 is packaged in a QFN (Quad For Non-Lead Package) format. The specific configuration of the semiconductor element 3 is not particularly limited, and in this embodiment, the semiconductor element 3 is, for example, a flip-chip LSI (Large Scale Integration) having a switching circuit and a control circuit (each of which will be described in detail later) configured therein. In the semiconductor device A10, DC power (voltage) is converted into AC power (voltage) by the switching circuit. The semiconductor device A10 is used, for example, as one element constituting a circuit of a DC / DC converter. The functions and uses of the semiconductor device A10 are not limited.

[0013] FIG. 1 is a perspective view showing the semiconductor device A10. FIG. 2 is a plan view showing the semiconductor device A10. FIG. 3 is a plan view showing the semiconductor device A10. FIG. 4 is a bottom view showing the semiconductor device A10. FIG. 5 is a front view showing the semiconductor device A10. FIG. 6 is a rear view showing the semiconductor device A10. FIG. 7 is a right side view showing the semiconductor device A10. FIG. 8 is a left side view showing the semiconductor device A10. FIG. 9 is a cross-sectional view of FIG. 3 taken along line IX-IX in FIG. 3. FIG. 10 is a cross-sectional view of FIG. 3 taken along line XX in FIG. 3. FIG. 11 is a cross-sectional view of FIG. 3 taken along line XI-XI in FIG. 3. FIG. 12 is a cross-sectional view of FIG. 3 taken along line XII-XII in FIG. 3. FIG. 13 is a cross-sectional view of FIG. 3 taken along line XIII-XIII in FIG. 3. For ease of understanding, FIG. 3 shows the sealing resin 4 through which light passes. In FIG. 3, the through sealing resin 4 is indicated by an imaginary line (double-dashed line).

[0014] The semiconductor device A10 has a rectangular shape when viewed in the thickness direction (plan view). For ease of explanation, the thickness direction (plan view) of the semiconductor device A10 is referred to as the thickness direction z, the direction along one side of the semiconductor device A10 perpendicular to the thickness direction z (the left-right direction in FIGS. 2 and 3) is referred to as the first direction x, and the direction perpendicular to the thickness direction z and the first direction x (the up-down direction in FIGS. 2 and 3) is referred to as the second direction y. Furthermore, one side of the thickness direction z (the upper side in FIGS. 5 to 8) is referred to as the first side z1, and the other side (the lower side in FIGS. 5 to 8) is referred to as the second side z2. One side of the first direction x (the right side in FIGS. 2 and 3) is referred to as the first side x1, and the other side (the left side in FIGS. 2 and 3) is referred to as the second side x2. One side of the second direction y (the upper side in FIGS. 2 and 3) is referred to as the first side y1, and the other side (the lower side in FIGS. 2 and 3) is referred to as the second side y2. The dimensions of the semiconductor device A10 are not limited.

[0015] 2, the conductive member 1 includes a plurality of leads 11, 12, 13, 14, a lead 15, a lead 16, a pair of leads 17, a lead 18, a plurality of leads 19, a lead 20, a plurality of leads 21, a lead 22, a lead 23, and a plurality of leads 25. The conductive member 1 supports the semiconductor element 3 and serves as a terminal for mounting the semiconductor device A10 on a wiring board. The plurality of leads 11 to 14, the lead 15, the lead 16, the pair of leads 17, the lead 18, the plurality of leads 19, the lead 20, the plurality of leads 21, the lead 22, the lead 23, and the plurality of leads 25 are all formed from the same lead frame. The lead frame is made of, for example, copper or a copper alloy. As shown in Figures 3 to 4 and Figures 9 to 13, each of the multiple leads 11 to 14, lead 15, lead 16, a pair of leads 17, lead 18, multiple leads 19, lead 20, multiple leads 21, lead 22, lead 23 and multiple leads 25 is partially covered with sealing resin 4.

[0016] As shown in FIGS. 3 and 4, the multiple leads 11, 12, 13, and 14 are arranged on a first side x1 in the first direction x and a second side x2 in the first direction x in the semiconductor device A10. In this embodiment, two (a pair of) leads 11, 12 are arranged on the first side x1 in the first direction x, and the other two (a pair of) leads 13, 14 are arranged on the second side x2 in the first direction x. In this embodiment, the multiple leads 11 to 14 each extend substantially in the first direction x. The pair of leads 11, 12 located on the first side x1 in the first direction x are arranged spaced apart in the second direction y. Furthermore, the pair of leads 13, 14 located on the second side x2 in the first direction x are arranged spaced apart in the second direction y. Each of the multiple leads 11 to 14 outputs AC power (voltage) converted by a switching circuit configured in the semiconductor element 3.

[0017] 3, 4, and 9, each of the multiple leads 11, 12, 13, and 14 has a main surface 111, a back surface 112, a back surface 113, a concave surface 114, and an end surface 115. The main surface 111 faces a first side z1 in the thickness direction z and faces the semiconductor element 3. The main surface 111 is covered with a sealing resin 4. The semiconductor element 3 is supported by the main surface 111.

[0018] The back surface 112, the back surface 113, and the concave surface 114 face the side opposite to the main surface 111 (the second side z2 in the thickness direction z). The back surfaces 112 and 113 are spaced apart in the first direction x with the concave surface 114 sandwiched therebetween and are exposed from the sealing resin 4. The concave surface 114 is located closer to the first side z1 in the thickness direction z than the back surfaces 112 and 113, and is closer to the main surface 111 than the back surfaces 112 and 113. The concave surface 114 is covered with the sealing resin 4. The end surface 115 is connected to both the main surface 111 and the back surface 112, and faces either the first side x1 in the first direction x or the second side x2 in the first direction x. The end surface 115 is exposed from the sealing resin 4. As shown in FIG. 4, the lead 14 has two back surfaces 112 and two end surfaces 115. The back surface 112 and the end surface 115 on one side are spaced apart from the back surface 112 and the end surface 115 on the other side in the second direction y.

[0019] In each of the plurality of leads 11 to 14, main surface 111 on which semiconductor element 3 is supported may be plated with, for example, silver. Furthermore, back surface 112, back surface 113, and end surface 115 exposed from sealing resin 4 may be plated with, for example, tin. Note that instead of tin plating, multiple metal platings may be employed, for example, in which nickel, palladium, and gold are layered in this order.

[0020] 3 and 4, the lead 15 extends in the first direction x. In this embodiment, the lead 15 is located at the middle of the semiconductor device A10 in the second direction y. The lead 15 is an input terminal to which DC power (voltage) to be converted into power is input in the semiconductor device A10. The lead 15 is a positive terminal (P terminal).

[0021] 11 , lead 15 has a main surface 151, a back surface 152, a back surface 153, a concave surface 154, and end surfaces 155 and 156. Main surface 151 faces the same side as main surfaces 111 of leads 11 to 14 in the thickness direction z, and faces the semiconductor element 3. Main surface 151 is covered with sealing resin 4. The semiconductor element 3 is supported by main surface 151.

[0022] The back surface 152, the back surface 153, and the concave surface 154 face the side opposite to the main surface 151 (the second side z2 in the thickness direction z). The back surface 152 and the back surface 153 are located apart in the first direction x with the concave surface 154 sandwiched therebetween, and are exposed from the sealing resin 4. The back surface 152 is located on the second side x2 in the first direction x, and the back surface 153 is located on the first side x1 in the first direction x. The concave surface 154 is located closer to the first side z1 in the thickness direction z than the back surfaces 152 and 153, and is located closer to the main surface 151 than the back surfaces 152 and 153. The concave surface 154 is covered with the sealing resin 4. The end surface 155 is connected to both the main surface 151 and the back surface 152, and faces the second side x2 in the first direction x. The end surface 156 is connected to both the main surface 151 and the back surface 153, and faces the first side x1 in the first direction x. The end surface 155 and the end surface 156 are exposed from the sealing resin 4.

[0023] Lead 15 may be plated with silver, for example, on main surface 151 on which semiconductor element 3 is supported. Furthermore, back surface 152, back surface 153, end surface 155, and end surface 156 exposed from sealing resin 4 may be plated with tin, for example. Note that instead of tin plating, multiple metal platings, for example, nickel, palladium, and gold layered in this order, may be used.

[0024] 3 and 4, the lead 16 extends in the first direction x. In this embodiment, the lead 16 is located at the middle of the semiconductor device A10 in the second direction y. The lead 16 is an input terminal to which DC power (voltage) to be converted into power is input in the semiconductor device A10. The lead 16 is a negative electrode (N terminal).

[0025] 10, the lead 16 has a main surface 161, a back surface 162, an end surface 163, and an end surface 164. The main surface 161 faces the same side as the main surfaces 111 of the leads 11 to 14 in the thickness direction z, and faces the semiconductor element 3. The main surface 161 is covered with a sealing resin 4. The semiconductor element 3 is supported by the main surface 161.

[0026] The back surface 162 faces the opposite side to the main surface 161 (the second side z2 in the thickness direction z). The back surface 162 is exposed from the sealing resin 4. In this embodiment, the main surface 161 and the back surface 162 are arranged over the entire length of the semiconductor device A10 in the first direction x. The end surface 163 is connected to both the main surface 161 and the back surface 162 and faces the second side x2 in the first direction x. The end surface 164 is connected to both the main surface 161 and the back surface 162 and faces the first side x1 in the first direction x. The end surfaces 163 and 164 are exposed from the sealing resin 4.

[0027] In the lead 16, the main surface 161 on which the semiconductor element 3 is supported may be plated with silver, for example. Furthermore, the back surface 162, end surface 163, and end surface 164 exposed from the sealing resin 4 may be plated with tin, for example. Note that instead of tin plating, multiple metal platings may be used, for example, in which nickel, palladium, and gold are layered in this order.

[0028] 3 and 4, the pair of leads 17 are disposed at the middle of the semiconductor device A10 in the first direction x. Each of the pair of leads 17 extends in the second direction y. One lead 17 is located on a first side y1 in the second direction y, and the other lead 17 is located on a second side y2 in the second direction y. Each of the pair of leads 17 receives, for example, power (voltage) for driving a control circuit or an electrical signal for transmission to the control circuit.

[0029] 12, each of the pair of leads 17 has a main surface 171, a back surface 172, and an end surface 173. The main surface 171 faces the same side as the main surfaces 111 of the leads 11 to 14 in the thickness direction z, and faces the semiconductor element 3. The main surface 171 is covered with a sealing resin 4. The semiconductor element 3 is supported by the main surface 171.

[0030] The back surface 172 faces the opposite side to the main surface 171 (the second side z2 in the thickness direction z). The back surface 172 is exposed from the sealing resin 4. The end surface 173 is connected to both the main surface 171 and the back surface 172 and faces the second direction y. More specifically, the end surface 173 of one lead 17 faces the first side y1 in the second direction y, and the end surface 173 of the other lead 17 faces the second side y2 in the second direction y. The end surfaces 173 are exposed from the sealing resin 4.

[0031] In each of the pair of leads 17, the main surface 171 on which the semiconductor element 3 is supported may be plated with, for example, silver. Furthermore, the back surface 172 and end surface 173 exposed from the sealing resin 4 may be plated with, for example, tin. Note that instead of tin plating, multiple metal platings may be used, for example, in which nickel, palladium, and gold are layered in this order.

[0032] As shown in FIGS. 3 and 4 , the lead 18 is disposed near a corner of the semiconductor device A10 on a first side x1 in the first direction x and on a second side y2 in the second direction y. An electrical signal is input to the lead 18 to transmit to, for example, a control circuit. The lead 18 has a main surface 181, back surfaces 182, 183, and 184, and end surfaces 185, 186, 187, and 188. The main surface 181 faces the same side as the main surfaces 111 of the leads 11 to 14 in the thickness direction z and faces the semiconductor element 3. The main surface 181 is covered with a sealing resin 4. The semiconductor element 3 is supported by the main surface 181. The back surfaces 182, 183, and 184 face the opposite side to the main surface 181 (the second side z2 in the thickness direction z). Each of the back surfaces 182 to 184 is exposed from the sealing resin 4. The back surface 183 is disposed at a corner of the semiconductor device A10 on a first side x1 in the first direction x and on a second side y2 in the second direction y. The back surface 182 is disposed adjacent to the back surface 183 on the first side y1 in the second direction y. The back surface 184 is disposed adjacent to the back surface 183 on the second side x2 in the first direction x. The end surface 185 is connected to both the main surface 181 and the back surface 182 and faces the first side x1 in the first direction x. The end surface 186 is connected to both the main surface 181 and the back surface 183 and faces the first side x1 in the first direction x. The end surface 187 is connected to both the main surface 181 and the back surface 183 and faces the second side y2 in the second direction y. The end surface 188 is connected to both the main surface 181 and the back surface 184 and faces the second side y2 in the second direction y. The end faces 185 to 188 are exposed from the sealing resin 4.

[0033] The lead 18 may be plated with silver, for example, on the main surface 181 on which the semiconductor element 3 is supported. Furthermore, the back surfaces 182 to 184 and end surfaces 185 to 188 exposed from the sealing resin 4 may be plated with tin, for example. Note that instead of tin plating, multiple metal platings, for example, nickel, palladium, and gold layered in this order, may be used.

[0034] As shown in FIGS. 3 and 4, the multiple leads 19 are arranged on a second side y2 in the second direction y in the semiconductor device A10. The multiple leads 19 are arranged at intervals from one another in the first direction x. An electrical signal is input to each of the multiple leads 19, for example, to be transmitted to a control circuit. As shown in FIGS. 3, 4, and 13, each of the multiple leads 19 has a main surface 191, a back surface 192, and an end surface 193. The main surface 191 faces the same side as the main surfaces 111 of the leads 11 to 14 in the thickness direction z and faces the semiconductor element 3. The main surface 191 is covered with the sealing resin 4. The semiconductor element 3 is supported by the main surface 191. The back surface 192 faces the opposite side to the main surface 191 (the second side z2 in the thickness direction z). The back surface 192 is exposed from the sealing resin 4. The end surface 193 is connected to both the main surface 191 and the back surface 192 and faces the second side y2 in the second direction y.

[0035] In each of the plurality of leads 19, a main surface 191 on which the semiconductor element 3 is supported may be plated with, for example, silver. Furthermore, a back surface 192 and an end surface 193 exposed from the sealing resin 4 may be plated with, for example, tin. Note that instead of tin plating, a plurality of metal platings, for example, nickel, palladium, and gold laminated in this order, may be used.

[0036] As shown in FIGS. 3 and 4, the lead 20 is arranged on the second side x2 in the first direction x of the semiconductor device A10. The lead 20 is also arranged in the second direction y, closer to the first side y1 in the second direction y. An electrical signal to be transmitted to, for example, a control circuit is input to the lead 20. The lead 20 has a main surface 201, a back surface 202, and an end surface 203. The main surface 201 faces the same side as the main surfaces 111 of the leads 11 to 14 in the thickness direction z and faces the semiconductor element 3. The main surface 201 is covered with the sealing resin 4. The semiconductor element 3 is supported by the main surface 201. The back surface 202 faces the side opposite to the main surface 201 (the second side z2 in the thickness direction z). The back surface 202 is exposed from the sealing resin 4. The end surface 203 is connected to both the main surface 201 and the back surface 202 and faces the second side x2 in the first direction x. The end face 203 is exposed from the sealing resin 4 .

[0037] The lead 20 may be plated with silver, for example, on the main surface 201 on which the semiconductor element 3 is supported. Furthermore, the back surface 202 and end surfaces 203 exposed from the sealing resin 4 may be plated with tin, for example. Note that instead of tin plating, multiple metal platings, for example, nickel, palladium, and gold layered in this order, may be used.

[0038] As shown in FIGS. 3 and 4, the multiple leads 21 are arranged on a first side y1 in the second direction y in the semiconductor device A10. The multiple leads 21 are arranged at intervals from one another in the first direction x. An electrical signal is input to each of the multiple leads 21 to be transmitted to, for example, a control circuit. As shown in FIGS. 3, 4, and 13, each of the multiple leads 21 has a main surface 211, a back surface 212, and an end surface 213. The main surface 211 faces the same side as the main surfaces 111 of the leads 11 to 14 in the thickness direction z and faces the semiconductor element 3. The main surface 211 is covered with a sealing resin 4. The semiconductor element 3 is supported by the main surface 211. The back surface 212 faces the opposite side to the main surface 211 (the second side z2 in the thickness direction z). The back surface 212 is exposed from the sealing resin 4. The end surface 213 is connected to both the main surface 211 and the back surface 212, and faces the first side y1 in the second direction y. The end surface 213 is exposed from the sealing resin 4.

[0039] In each of the plurality of leads 21, the main surface 211 on which the semiconductor element 3 is supported may be plated with, for example, silver. Furthermore, the back surface 212 and end surfaces 213 exposed from the sealing resin 4 may be plated with, for example, tin. Note that instead of tin plating, multiple metal platings may be employed, for example, in which nickel, palladium, and gold are layered in this order.

[0040] As shown in FIGS. 3 and 4, the lead 22 is arranged on a first side y1 in the second direction y in the semiconductor device A10. The lead 22 is also arranged closer to the first side x1 in the first direction x. An electrical signal to be transmitted to, for example, a control circuit is input to the lead 22. The lead 22 has a main surface 221, a back surface 222, and an end surface 223. The main surface 221 faces the same side as the main surfaces 111 of the leads 11 to 14 in the thickness direction z and faces the semiconductor element 3. The main surface 221 is covered with the sealing resin 4. The semiconductor element 3 is supported by the main surface 221. The back surface 222 faces the opposite side to the main surface 221 (a second side z2 in the thickness direction z). The back surface 222 is exposed from the sealing resin 4. The end surface 223 is connected to both the main surface 221 and the back surface 222 and faces the first side y1 in the second direction y. The end face 223 is exposed from the sealing resin 4 .

[0041] The lead 22 may be plated with silver, for example, on the main surface 221 on which the semiconductor element 3 is supported. Furthermore, the back surface 222 and the end surface 223 exposed from the sealing resin 4 may be plated with tin, for example. Note that instead of tin plating, multiple metal platings, for example, nickel, palladium, and gold stacked in this order, may be used.

[0042] As shown in FIGS. 3 and 4, the lead 23 is arranged on a first side x1 in the first direction x in the semiconductor device A10. The lead 23 is also arranged in the second direction y, closer to the first side y1 in the second direction y. An electrical signal to be transmitted to, for example, a control circuit is input to the lead 23. The lead 23 has a main surface 231, a back surface 232, and an end surface 233. The main surface 231 faces the same side as the main surfaces 111 of the leads 11 to 14 in the thickness direction z and faces the semiconductor element 3. The main surface 231 is covered with the sealing resin 4. The semiconductor element 3 is supported by the main surface 231. The back surface 232 faces the opposite side to the main surface 231 (a second side z2 in the thickness direction z). The back surface 232 is exposed from the sealing resin 4. The end surface 233 is connected to both the main surface 231 and the back surface 232 and faces the first side x1 in the first direction x. The end face 233 is exposed from the sealing resin 4 .

[0043] The lead 23 may be plated with silver, for example, on the main surface 231 on which the semiconductor element 3 is supported. Furthermore, the back surface 232 and end surface 233 exposed from the sealing resin 4 may be plated with tin, for example. Note that instead of tin plating, multiple metal platings, for example, nickel, palladium, and gold layered in this order, may be used.

[0044] As shown in FIGS. 3 and 4, each of the leads 25 is disposed at one of the four corners of the semiconductor device A10 when viewed in the thickness direction z (in a plan view). In this embodiment, three leads 25 are disposed. These three leads 25 are disposed at a corner of the semiconductor device A10 on a first side x1 in the first direction x and a first side y1 in the second direction y, a corner of a second side x2 in the first direction x and a first side y1 in the second direction y, and a corner of a second side x2 in the first direction x and a second side y2 in the second direction y. Each of the leads 25 is not electrically connected to the semiconductor element 3 and is a so-called dummy terminal. Each of the leads 25 has a main surface 251, a back surface 252, an end surface 253, and an end surface 254. The main surface 251 faces the same side as the main surfaces 111 of the leads 11 to 14 in the thickness direction z. The main surface 251 is covered with the sealing resin 4. The back surface 252 faces the opposite side to the main surface 251 (the second side z2 in the thickness direction z). The back surface 252 is exposed from the sealing resin 4. The end surface 253 is connected to both the main surface 251 and the back surface 252 and faces the first direction x. The end surface 254 is connected to both the main surface 251 and the back surface 252 and faces the second direction y. The end surfaces 253 and 254 are exposed from the sealing resin 4.

[0045] In each of the plurality of leads 25, the back surface 252, the end surface 253, and the end surface 254 exposed from the sealing resin 4 may be plated with, for example, tin. Note that instead of tin plating, a plurality of metal platings, for example, nickel, palladium, and gold laminated in this order, may be used.

[0046] 4, the multiple leads 21, the one lead 17 (on the first side y1 in the second direction y), and the lead 22 have their respective back surfaces 212, 172, and 222 aligned along the edge of the first side y1 in the second direction y of the bottom surface 42 of the sealing resin 4. The multiple leads 19, the other lead 17 (on the second side y2 in the second direction y), and the lead 18 have their respective back surfaces 192, 172, and 184 aligned along the edge of the second side y2 in the second direction y of the bottom surface 42. The leads 18, 12, 15, 16, 11, and 23 have their respective back surfaces 182, 112, 153, 162, 112, and 232 aligned along the edge of the first side x1 in the first direction x of the bottom surface 42. The back surfaces 112, 152, 162, 112, 202 of the leads 14, 15, 16, 13, and 20 are aligned along the edge of the second side x2 in the first direction x of the bottom surface 42. The leads 25 each have an end face 253 facing the first direction x and an end face 254 facing the second direction y. Each lead 25 is a dummy terminal that is not electrically connected to the semiconductor element 3. The lead 18 has an end face 186 facing the first direction x and an end face 187 facing the second direction y. The lead 18 is electrically connected to the semiconductor element 3.

[0047] There are no limitations on the arrangement, shape, and function of the leads 11 to 25. The conductive member 1 does not have to include all of the leads 11 to 25, and may include other leads. The layout of the conductive member 1 is designed as appropriate.

[0048] The sealing resin 4 covers a part of the conductive member 1 and the semiconductor element 3. The constituent material of the sealing resin 4 is an insulator, such as a black epoxy resin. The sealing resin 4 is rectangular when viewed in the thickness direction z. In this embodiment, the outer shape of the sealing resin 4 when viewed in the thickness direction z matches the outer shape of the semiconductor device A10. As shown in FIGS. 5 to 8 , the sealing resin 4 has a top surface 41, a bottom surface 42, a first side surface 431, a second side surface 432, a third side surface 433, and a fourth side surface 434.

[0049] 9 to 13, the top surface 41 faces the same side as the main surfaces 111 of the leads 11 to 14 in the thickness direction z (first side z1 in the thickness direction z). As shown in FIGS. 5 to 8, the bottom surface 42 faces the opposite side to the top surface 41 (second side z2 in the thickness direction z). The top surface 41 and the bottom surface 42 are rectangular. As shown in Figures 4 and 9 to 13, the back surfaces 112 and 113 of each of the multiple leads 11 to 14, the back surfaces 152 and 153 of lead 15, the back surface 162 of lead 16, the back surfaces 172 of each of the pair of leads 17, the back surfaces 182, 183 and 184 of lead 18, the back surfaces 192 of each of the multiple leads 19, the back surface 202 of lead 20, the back surface 212 of each of the multiple leads 21, the back surface 222 of lead 22, the back surface 232 of lead 23, and the back surface 252 of each of the multiple leads 25 are exposed from the bottom surface 42.

[0050] The first side surface 431, the second side surface 432, the third side surface 433, and the fourth side surface 434 are all connected to the top surface 41 and the bottom surface 42 and are perpendicular to the top surface 41 and the bottom surface 42. As shown in FIGS. 5 and 6, the first side surface 431 and the second side surface 432 are spaced apart from each other in the first direction x and face opposite each other. The first side surface 431 faces a first side x1 in the first direction x. The second side surface 432 faces a second side x2 in the first direction x. As shown in FIGS. 4, 7, 9 to 11, the end faces 115 of the leads 11 and 12, the end face 156 of the lead 15, the end face 164 of the lead 16, the end face 185 and the end face 186 of the lead 18, the end face 233 of the lead 23, and the end face 253 of the lead 25 are exposed from the first side surface 431 so as to be flush with the first side surface 431. As shown in Figures 4, 8, and 9 to 11, end faces 115 of leads 13 and 14, end face 155 of lead 15, end face 163 of lead 16, end face 203 of lead 20, and end faces 253 of each of the multiple leads 25 are exposed from second side face 432 so as to be flush with second side face 432.

[0051] The third side surface 433 and the fourth side surface 434 are each connected to both the first side surface 431 and the second side surface 432. As shown in FIGS. 7 and 8 , the third side surface 433 and the fourth side surface 434 are spaced apart in the second direction y and face opposite each other. The third side surface 433 faces a first side y1 in the second direction y. The fourth side surface 434 faces a second side y2 in the second direction y. As shown in FIGS. 4 , 6 , 12 , and 13 , the end face 173 of one lead 17, the end face 213 of each of the multiple leads 21, the end face 223 of each of the multiple leads 22, and the end face 254 of each of the multiple leads 25 are exposed from the third side surface 433 so as to be flush with the third side surface 433. As shown in Figures 4, 5, 12, and 13, the end face 173 of the other lead 17, the end face 187 and the end face 188 of the lead 18, the end face 193 of each of the multiple leads 19, and the end face 254 of the lead 25 are exposed from the fourth side face 434 so as to be flush with the fourth side face 434.

[0052] As shown in FIGS. 1 to 3 , the sealing resin 4 also has corners 45, 46, 47, and 48. Each of the corners 45, 46, 47, and 48 is located at one of the four corners of the top surface 41. The corners 45 and 46 are located on a first side x1 in the first direction x. More specifically, the corner 45 is located on the first side x1 in the first direction x and a first side y1 in the second direction y. The corner 46 is located on the first side x1 in the first direction x and a second side y2 in the second direction y. The corners 47 and 48 are located on a second side x2 in the first direction x. More specifically, the corner 47 is located on the second side x2 in the first direction x and the first side y1 in the second direction y. The corner 48 is located on the second side x2 in the first direction x and a second side y2 in the second direction y.

[0053] 3 and 9 to 13, the semiconductor element 3 is supported by a plurality of leads 11 to 14, a lead 15, a lead 16, a pair of leads 17, a lead 18, a plurality of leads 19, a lead 20, a plurality of leads 21, a lead 22, and a lead 23. The semiconductor element 3 is covered with a sealing resin 4. The semiconductor element 3 has a semiconductor substrate 31, a semiconductor layer 32, a plurality of electrodes 33, and a plurality of electrodes 34.

[0054] 9 to 13, semiconductor substrate 31 supports semiconductor layer 32, a plurality of electrodes 33, and a plurality of electrodes 34. The constituent material of semiconductor substrate 31 is, for example, Si (silicon) or silicon carbide (SiC).

[0055] The semiconductor layer 32 is laminated in the thickness direction z on the side of the semiconductor substrate 31 facing the main surfaces 111 of the leads 11 to 14. The semiconductor layer 32 includes multiple types of p-type and n-type semiconductors based on differences in the amount of doped elements. The semiconductor layer 32 includes a switching circuit and a control circuit connected to the switching circuit. The switching circuit is, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). In the example of the semiconductor device A10, the switching circuit is divided into two regions: a high-voltage region (upper arm circuit) and a low-voltage region (lower arm circuit). Each region is composed of one n-channel MOSFET. The control circuit includes a gate driver for driving the switching circuit and a bootstrap circuit corresponding to the high-voltage region of the switching circuit, and also performs control to operate the switching circuit normally. Note that a wiring layer (not shown) is further configured in the semiconductor layer 32. The wiring layer provides electrical continuity between the switching circuit and the control circuit.

[0056] 9 to 13, the plurality of electrodes 33 and the plurality of electrodes 34 are provided on the side of the semiconductor layer 32 facing the main surfaces 111 of the leads 11 to 14 in the thickness direction z. The plurality of electrodes 33 and the plurality of electrodes 34 are in contact with the semiconductor layer 32.

[0057] The plurality of electrodes 33 are electrically connected to the switching circuit of the semiconductor layer 32. Each of the plurality of electrodes 33 is electrically connected to one of the main surface 111 of each of the plurality of leads 11 to 14, the main surface 151 of lead 15, and the main surface 161 of lead 16. This allows the plurality of leads 11 to 14, lead 15, and lead 16 to be electrically connected to the switching circuit. In this embodiment, at least one electrode 33 overlaps with the back surface 113 of each of the plurality of leads 11 to 14 when viewed in the thickness direction z.

[0058] The plurality of electrodes 34 are electrically connected to a control circuit of the semiconductor layer 32. Each of the plurality of electrodes 34 is electrically connected to one of the main surfaces 171 of the pair of leads 17, the main surface 181 of the lead 18, the main surface 191 of the plurality of leads 19, the main surface 201 of the lead 20, the main surface 211 of the plurality of leads 21, the main surface 221 of the lead 22, and the main surface 231 of the lead 23. This electrically connects the pair of leads 17, the lead 18, the plurality of leads 19, the lead 20, the plurality of leads 21, the lead 22, and the lead 23 to the control circuit. The constituent material of the plurality of electrodes 33 and the plurality of electrodes 34 includes, for example, copper.

[0059] 2 and 3, the semiconductor element 3 has a rectangular shape when viewed in the thickness direction z. The semiconductor element 3 has an element main surface 305, an element back surface 306, and element side surfaces 301-304.

[0060] As shown in FIGS. 9 to 13, the element main surface 305 and the element back surface 306 face opposite each other in the thickness direction z. The element main surface 305 is the surface of the semiconductor layer 32 on which the plurality of electrodes 33 and the plurality of electrodes 34 are arranged. In this embodiment, the element main surface 305 faces the second side z2 and faces the main surfaces 111 of the leads 11 to 14. The element back surface 306 is the surface of the semiconductor substrate 31 opposite to the side on which the semiconductor layer 32 is stacked. In this embodiment, the element back surface 306 faces the first side z1. The element main surface 305 and the element back surface 306 are rectangular.

[0061] The element side surfaces 301 to 304 are all connected to the element main surface 305 and the element back surface 306, and are perpendicular to the element main surface 305 and the element back surface 306. As shown in FIGS. 2 and 3, the element side surfaces 301 and 302 are spaced apart and face in opposite directions. The element side surfaces 303 and 304 are each connected to both the element side surfaces 301 and 302. The element side surfaces 303 and 304 are spaced apart and face in opposite directions. In this embodiment, the outer peripheries of the semiconductor substrate 31 and the semiconductor layer 32, as viewed in the thickness direction z, form the element side surfaces 301 to 304.

[0062] In this embodiment, the rectangular semiconductor element 3 is not disposed parallel to the rectangular sealing resin 4 when viewed in the thickness direction, but is disposed at an incline. The element side surface 301 faces in a direction inclined from a first side x1 in the first direction x to a second side y2 in the second direction y. That is, the element side surface 301 is inclined with respect to a first side surface 431 of the sealing resin 4. The element side surface 302 faces in a direction inclined from a second side x2 in the first direction x to a first side y1 in the second direction y. That is, the element side surface 302 is inclined with respect to a second side surface 432 of the sealing resin 4. The element side surface 303 faces in a direction inclined from a first side y1 in the second direction y to a first side x1 in the first direction x. That is, the element side surface 303 is inclined with respect to a third side surface 433 of the sealing resin 4. The element side surface 304 faces in a direction inclined from a second side y2 in the second direction y to a second side x2 in the first direction x. In other words, the element side surface 304 is inclined with respect to the fourth side surface 434 of the sealing resin 4.

[0063] The relationship between the element principal surface 305 of the semiconductor element 3 and the top surface 41 of the sealing resin 4 will be described. As shown in FIG. 2 , as viewed in the thickness direction z, the side 305a of the element principal surface 305 connected to the element side surface 301 is inclined with respect to the side 41a connected to the first side surface 431 of the top surface 41. The inclination angle α of the side 305a with respect to the side 41a is greater than 0° and less than 90°. When the inclination angle α is greater than 45°, the inclination angle of the side 305a with respect to the side 41b connected to the fourth side surface 434 of the top surface 41 is less than 45°. In other words, as viewed in the thickness direction z, the inclination angle of any side of the element principal surface 305 with respect to any side of the top surface 41 is greater than 0° and equal to or less than 45°. In this embodiment, the inclination angle is 45° so that the distance between each corner 45, 46, 47, and 48 and the semiconductor element 3 is greatest as viewed in the thickness direction z. Note that the inclination angle α is not limited to 45°. It is desirable that the distance D1 between the corner 46 and the side 305a as viewed in the thickness direction z is 25% or more of the length D2 of the diagonal of the top surface 41 of the sealing resin 4. The same is true for the distances between the corners 45, 47, 48 as viewed in the thickness direction z and the sides closest to them.

[0064] Next, the effects of the semiconductor device A10 will be described.

[0065] According to this embodiment, in the semiconductor device A10, the side 305a of the element main surface 305 is inclined with respect to the side 41a of the top surface 41. As a result, the distance between the corners of the semiconductor device A10 and the semiconductor element 3 is longer when viewed in the thickness direction z, compared to when the side 305a is parallel to the side 41a (hereinafter referred to as "parallel arrangement"). Therefore, the semiconductor device A10 can improve the mounting reliability compared to when the side 305a is parallel to the side 41a.

[0066] Furthermore, in this embodiment, the inclination angle α of the side 305a with respect to the side 41a is 45°. This maximizes the distance between the corner of the semiconductor device A10 and the semiconductor element 3 when viewed in the thickness direction z. This further improves the mounting reliability of the semiconductor device A10.

[0067] <First Modification of First Embodiment> Fig. 14 shows a semiconductor device A11 according to a first modified example of the first embodiment. Fig. 14 is a plan view showing the semiconductor device A11, and corresponds to Fig. 2. In Fig. 14 and subsequent figures, elements that are the same as or similar to those in the semiconductor device A10 of the above embodiment are given the same reference numerals as in the above embodiment, and descriptions thereof will be omitted where appropriate.

[0068] In the semiconductor device A11 of this modification, the inclination angle α of the side 305a with respect to the side 41a is 15°. Compared to the semiconductor device A10 in which the inclination angle α is 45°, the distance D1 between the corner 46 and the side 305a as viewed in the thickness direction z is smaller. However, the distance D1 is still sufficiently larger than in the case of a parallel arrangement.

[0069] As described above, the inclination angle α is not limited as long as it is greater than 0° and less than 90°. The distance D1 is larger than in the case of a parallel arrangement (inclination angle α is 0°). However, if the inclination angle α is less than 5°, the distance D1 does not change much from the case of a parallel arrangement. Therefore, it is desirable that the inclination angle α be 5° or more.

[0070] Second Embodiment 15 and 16 show a semiconductor device A20 according to a second embodiment of the present disclosure. FIG. 15 is a plan view showing the semiconductor device A20 and corresponds to FIG. 3. FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 15 and corresponds to FIG. 9 and other figures. For ease of understanding, FIG. 15 shows the sealing resin 4 through a transparent view. In FIG. 15, the transparent sealing resin 4 is indicated by an imaginary line (two-dot chain line). The semiconductor device A20 of this embodiment differs from the first embodiment in the orientation of the semiconductor element 3 in the thickness direction z. The configuration and operation of other parts of this embodiment are similar to those of the first embodiment. The parts of the first embodiment and the modifications described above may be combined in any desired manner.

[0071] In the semiconductor device A20 of this embodiment, the conductive member 1 includes a lead 27 and a plurality of leads 26. The lead 27 includes a die pad 271 on which a semiconductor element 3 is mounted. The die pad 271 includes a main surface 271a facing a first side z1 in the thickness direction z and connected to terminals located at the four corners of the semiconductor device A20 as viewed in the thickness direction z. The main surface 271a of the die pad 271 is rectangular. As viewed in the thickness direction z, each side of the main surface 271a is parallel to one of the sides of the top surface 41 of the sealing resin 4. For example, a side 271b of the main surface 271a on the first side x1 in the first direction x is parallel to the side 41a of the top surface 41. The semiconductor element 3 is bonded to the main surface 271a of the die pad 271 with the element main surface 305 facing the first side z1 in the thickness direction z. Similar to the semiconductor device A10, the semiconductor element 3 is disposed such that a side 305a of the element main surface 305 is inclined relative to a side 41a of the top surface 41 when viewed in the thickness direction z. The plurality of leads 26 are disposed at both ends of the semiconductor device A20 in the first direction x and at both ends in the second direction y. Each electrode 33 of the semiconductor element 3 is electrically connected to one of the plurality of leads 26 by a wire 5.

[0072] In this embodiment, too, the side 305a of the element main surface 305 is inclined with respect to the side 41a of the top surface 41. As a result, the distance between the corners of the semiconductor device A20 and the semiconductor element 3 is longer when viewed in the thickness direction z compared to the parallel arrangement. Therefore, the semiconductor device A20 can improve the mounting reliability compared to the parallel arrangement. Furthermore, the semiconductor device A20 has a configuration in common with the semiconductor device A10, and thereby achieves the same effects as the semiconductor device A10.

[0073] <First Modification of Second Embodiment> Fig. 17 shows a semiconductor device A21 according to a first modified example of the second embodiment. Fig. 17 is a plan view showing the semiconductor device A21, and corresponds to Fig. 3. For ease of understanding, Fig. 17 shows the sealing resin 4 through which the sealing resin 4 is seen. In Fig. 17, the seen-through sealing resin 4 is shown by an imaginary line (two-dot chain line).

[0074] In the semiconductor device A21 of this modification, as viewed in the thickness direction z, each side of the main surface 271a of the die pad 271 is parallel to one of the sides of the element main surface 305 of the semiconductor element 3. For example, a side 271b of the main surface 271a on a first side x1 in the first direction x and a second side y2 in the second direction y is parallel to a side 305a of the element main surface 305.

[0075] <Second Modification of Second Embodiment> Fig. 18 shows a semiconductor device A22 according to a second modified example of the second embodiment. Fig. 18 is a plan view showing the semiconductor device A22, and corresponds to Fig. 3. For ease of understanding, Fig. 18 shows the sealing resin 4 through which the sealing resin 4 is seen. In Fig. 18, the seen-through sealing resin 4 is indicated by an imaginary line (two-dot chain line).

[0076] In the semiconductor device A22 of this modified example, the die pad 271 is not connected to each terminal portion located at the four corners of the semiconductor device A22, but is fixed by hanging leads exposed from the first side 431, the second side 432, the third side 433 and the fourth side 434 of the sealing resin 4.

[0077] As can be seen from these modified examples, regardless of the shape or configuration of the die pad 271, the semiconductor element 3 only needs to be mounted on the die pad 271 so that the side 305a of the element main surface 305 is inclined with respect to the side 41a of the top surface 41 when viewed in the thickness direction z. Furthermore, as can be seen from the second embodiment, the orientation of the semiconductor element 3 in the thickness direction z is irrelevant. The element main surface 305 may face either the first side z1 or the second side z2 in the thickness direction z.

[0078] In the first and second embodiments, the semiconductor device A10 (A11, A20, A21, A22) is packaged in a QFN format, but this is not limiting. The semiconductor device A10 (A11, A20, A21, A22) may be packaged in a QFP format in which leads protrude from a first side surface 431, a second side surface 432, a third side surface 433, and a fourth side surface 434.

[0079] Third Embodiment FIG. 19 shows a semiconductor device A30 according to a third embodiment of the present disclosure. FIG. 19 is a plan view showing the semiconductor device A30, and corresponds to FIG. 3. For ease of understanding, FIG. 19 shows the sealing resin 4 through a transparent view. In FIG. 19, the transparent sealing resin 4 is shown by an imaginary line (two-dot chain line). The semiconductor device A30 of this embodiment differs from the first embodiment in the package format. The configuration and operation of other parts of this embodiment are similar to those of the first embodiment. The parts of the first and second embodiments and their modified examples may be combined in any desired manner.

[0080] The semiconductor device A30 of this embodiment is a dual flat non-lead package (DFN) package, and does not include the leads 21, 22, 25, and 17 exposed from the third side surface 433 of the sealing resin 4, and the leads 19, 18, 25, and 17 exposed from the fourth side surface 434.

[0081] In this embodiment, too, the side 305a of the element main surface 305 is inclined with respect to the side 41a of the top surface 41. As a result, the distance between the corners of the semiconductor device A30 and the semiconductor element 3 is longer when viewed in the thickness direction z compared to the parallel arrangement. Therefore, the semiconductor device A30 can improve the mounting reliability compared to the parallel arrangement. Furthermore, by having a configuration in common with the semiconductor device A10, the semiconductor device A30 achieves the same effects as the semiconductor device A10.

[0082] In the third embodiment, the semiconductor device A30 is packaged in a DFN package, but this is not limiting. The semiconductor device A30 may also be packaged in a small outline package (SOP) with leads protruding from the first side surface 431 and the second side surface 432. In the third embodiment, the semiconductor element 3 is mounted so that the element main surface 305 faces the second side z2 in the thickness direction z, but this is not limiting. The semiconductor element 3 may also be mounted so that the element main surface 305 faces the first side z1 in the thickness direction z.

[0083] <Fourth embodiment> 20 and 21 show a semiconductor device A40 according to a fourth embodiment of the present disclosure. FIG. 20 is a plan view showing the semiconductor device A40, and corresponds to FIG. 2. FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 20, and corresponds to FIG. 9 and the like. The semiconductor device A40 of this embodiment differs from the first embodiment in terms of the package format. The configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that the parts of the first to third embodiments and their modified examples may be combined in any desired manner.

[0084] The semiconductor device A40 of this embodiment has a BGA (Ball Grid Array) package format. As shown in FIG. 21 , the semiconductor device A40 includes a wiring board 6 and a plurality of bumps 7 as the conductive member 1, instead of the leads 11 to 25. The wiring board 6 includes a base material 61, a wiring layer 62, and vias 63. The base material 61 is made of an insulator such as epoxy resin and includes a main surface 61a facing a first side z1 in the thickness direction z and a back surface 61b facing a second side z2. The wiring layers 62 are disposed on the main surface 61a and the back surface 61b, respectively. The vias 63 are through-holes that penetrate the base material 61 from the main surface 61a to the back surface 61b, and are made of a conductor such as copper and disposed in the through-holes, thereby electrically connecting the wiring layer 62 on the main surface 61a to the wiring layer 62 on the back surface 61b. The semiconductor element 3 is bonded to the main surface 61a of the base material 61, with the element main surface 305 facing the first side z1 in the thickness direction z. Similar to the semiconductor device A10, the semiconductor element 3 is disposed such that a side 305a of the element main surface 305 is inclined relative to a side 41a of the top surface 41 when viewed in the thickness direction z. Each electrode 33 of the semiconductor element 3 is electrically connected to a wiring layer 62 on the main surface 61a by a wire 5. The plurality of bumps 7 are, for example, spherical copper members, and are disposed on the wiring layer 62 on the back surface 61b.

[0085] In this embodiment, too, the side 305a of the element main surface 305 is inclined with respect to the side 41a of the top surface 41. As a result, the distance between the corners of the semiconductor device A40 and the semiconductor element 3 is longer when viewed in the thickness direction z compared to the parallel arrangement. Therefore, the semiconductor device A40 can improve the mounting reliability compared to the parallel arrangement. Furthermore, by having a configuration in common with the semiconductor device A10, the semiconductor device A40 achieves the same effects as the semiconductor device A10.

[0086] In the fourth embodiment, the semiconductor element 3 is mounted so that the element main surface 305 faces the first side z1 in the thickness direction z, but this is not limiting. The semiconductor element 3 may be mounted so that the element main surface 305 faces the second side z2 in the thickness direction z.

[0087] As can be seen from the third and fourth embodiments, the package format to which the present invention is applicable is not limited to QFN or QFP, and the present invention can be applied to various package formats.

[0088] In the first to fourth embodiments, the first side surface 431, the second side surface 432, the third side surface 433, and the fourth side surface 434 of the sealing resin 4 are all perpendicular to the top surface 41 and the bottom surface 42, but this is not limiting. At least one of the first side surface 431, the second side surface 432, the third side surface 433, and the fourth side surface 434 does not have to be perpendicular to the top surface 41 and the bottom surface 42. Furthermore, at least one of the first side surface 431, the second side surface 432, the third side surface 433, and the fourth side surface 434 is divided into a plurality of portions in the thickness direction z, and any of the portions does not have to be perpendicular to the top surface 41 and the bottom surface 42.

[0089] In addition, in the present embodiment, the semiconductor element 3 has been described as having all of the element side surfaces 301 to 304 perpendicular to the element main surface 305 and the element back surface 306, but this is not limiting. At least one of the element side surfaces 301 to 304 does not have to be perpendicular to the element main surface 305 and the element back surface 306.

[0090] The semiconductor device according to the present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the semiconductor device according to the present disclosure can be freely modified in various ways.

[0091] The present disclosure includes the embodiments described in the appendix below. [Appendix 1] a semiconductor element (3) having an element main surface (305) facing in the thickness direction (z) and on which an electrode (33) is arranged; a sealing resin (4) having a resin top surface (41) facing the first side (z1) in the thickness direction and covering the semiconductor element; Equipped with the element main surface and the resin top surface are rectangular; When viewed in the thickness direction, a first side (305a) of the element main surface is inclined with respect to a second side (41a) of the resin top surface. Semiconductor device. [Appendix 2] When viewed in the thickness direction, the inclination angle of the first side with respect to the second side is greater than 0° and equal to or less than 45°. 2. The semiconductor device according to claim 1. [Appendix 3] The inclination angle is 5° or more and 45° or less. 3. The semiconductor device according to claim 2. [Appendix 4] The tilt angle is 45°. 4. The semiconductor device according to claim 3. [Appendix 5] The resin top surface has a first corner portion (46) that is closest to the first side among the four corner portions, When viewed in the thickness direction, the distance (D1) between the first side and the first corner is 25% or more of the length (D2) of the diagonal of the resin top surface. 5. The semiconductor device according to any one of claims 1 to 4. [Appendix 6] Further provided is a conductive member (1) that is electrically connected to the semiconductor element, The semiconductor element has a main surface facing a second side (z2) in the thickness direction, The electrode is conductively joined to the conductive member. 6. The semiconductor device according to any one of appendices 1 to 5. [Appendix 7] a conductive member electrically connected to the semiconductor element; a connecting member (5) that electrically connects the semiconductor element and the conductive member; Furthermore, the semiconductor element has a main surface facing a first side in the thickness direction; the connecting member is electrically connected to the electrode and the conductive member; 6. The semiconductor device according to any one of appendices 1 to 5. [Appendix 8] The conductive member includes a plurality of leads (11 to 25), each having a lead main surface facing a first side in the thickness direction and a lead back surface facing a second side in the thickness direction. 8. The semiconductor device according to claim 6 or 7. [Appendix 9] the sealing resin has a resin bottom surface (42) facing the second side in the thickness direction, the back surfaces of the leads are all exposed from the resin bottom surface; 9. The semiconductor device according to claim 8. [Appendix 10] the plurality of leads includes a plurality of first leads (11, 22, 17) and a plurality of second leads (19, 17); the plurality of first leads are arranged such that the back surfaces of the leads are aligned along a first direction (x) parallel to the second side, the second leads are arranged along the first direction with the lead back surfaces spaced apart from the lead back surfaces of the first leads in a second direction (y) perpendicular to the thickness direction and the first direction; 10. The semiconductor device according to claim 9. [Appendix 11] the plurality of leads further includes a plurality of third leads (11, 12, 15, 16, 23); The plurality of third leads are arranged such that the back surfaces of the leads are aligned along the second direction. 11. The semiconductor device according to claim 10. [Appendix 12] the plurality of leads includes a fourth lead (25); the fourth lead has a first end surface (253) facing the first direction and exposed from the sealing resin, and a second end surface (254) facing the second direction and exposed from the sealing resin, and is not electrically connected to the semiconductor element; 12. The semiconductor device according to claim 10 or 11. [Appendix 13] the plurality of leads includes a fifth lead (18); the fifth lead has a third end surface (186) facing the first direction and exposed from the sealing resin, and a fourth end surface (187) facing the second direction and exposed from the sealing resin, and is electrically connected to the semiconductor element; 13. The semiconductor device according to any one of appendices 10 to 12. [Appendix 14, Second embodiment, Figure 15] The plurality of leads include a die pad (271) on which the semiconductor element is mounted, the die pad has a die pad main surface (271a) facing a first side in the thickness direction, the die pad main surface is rectangular, When viewed in the thickness direction, a third side (271b) of the die pad main surface is approximately parallel to the first side. 14. The semiconductor device according to any one of appendixes 8 to 13. [Appendix 15, First Modification of Second Embodiment, FIG. 17] the plurality of leads include a die pad on which the semiconductor element is mounted, the die pad has a die pad main surface facing a first side in the thickness direction, the die pad main surface is rectangular, When viewed in the thickness direction, a third side of the die pad main surface is approximately parallel to the second side. 14. The semiconductor device according to any one of appendixes 8 to 13. [Appendix 16, Fourth embodiment, Figs. 20 and 21] The device further includes a substrate (61) having a substrate main surface (61a) facing a first side in the thickness direction and a substrate back surface (61b) facing a second side in the thickness direction, The conductive member includes a conductive portion (63) disposed in a through hole that penetrates the base material in the thickness direction. 8. The semiconductor device according to claim 6 or 7. [Explanation of symbols]

[0092] A10, A11, A20, A21, A22, A30, A40: Semiconductor device 1: Conductive material 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 26, 27: Lead 271: Die pad 271a: Main surface 271b: Side 111,151,161,171,181,191,201,211,221,231,251,271a: Main surface 112,113,152,153,162,172,182,183,184,192,202,212,222,232,252: Back side 114,154: Concave 115,155,156,163,164,173,185,186,187,188,193,203,213,223,253,254: End face 3: Semiconductor elements 305: Main surface of element 305a: Side 306: Back side of element 301, 302, 303, 304: Side of element 31: Semiconductor substrate 32: Semiconductor layer 33,34: Electrode 4: Sealing resin 41:Top surface 41a, 41b: Side 42: Bottom 431 :1st side 432:Second side 433:Third side 434: 4th side 45, 46, 47, 48: Corners 5: Wire 6: Wiring board 61: Base material 61a: Main surface 61b: Back 62: Wiring layer 63: Beer 7: Bump

Claims

1. a semiconductor element having a main surface facing in the thickness direction and on which electrodes are arranged; a sealing resin having a resin top surface facing the first side in the thickness direction and covering the semiconductor element; Equipped with the element main surface and the resin top surface are rectangular; When viewed in the thickness direction, a first side of the element main surface is inclined with respect to a second side of the resin top surface. Semiconductor device.

2. When viewed in the thickness direction, an inclination angle of the first side with respect to the second side is greater than 0° and not more than 45°. The semiconductor device according to claim 1 .

3. The inclination angle is equal to or greater than 5° and equal to or less than 45°. The semiconductor device according to claim 2 .

4. The tilt angle is 45°. The semiconductor device according to claim 3 .

5. the resin top surface has a first corner portion that is closest to the first side among four corner portions, When viewed in the thickness direction, the distance between the first side and the first corner is 25% or more of the length of a diagonal line of the resin top surface. The semiconductor device according to claim 1 .

6. a conductive member electrically connected to the semiconductor element; the semiconductor element has a main surface facing a second side in the thickness direction; The electrode is conductively joined to the conductive member. The semiconductor device according to claim 1 .

7. a conductive member electrically connected to the semiconductor element; a connecting member that electrically connects the semiconductor element and the conductive member; Furthermore, the semiconductor element has a main surface facing a first side in the thickness direction; the connecting member is electrically connected to the electrode and the conductive member; The semiconductor device according to claim 1 .

8. The conductive member includes a plurality of leads, each having a lead main surface facing a first side in the thickness direction and a lead back surface facing a second side in the thickness direction.

8. The semiconductor device according to claim 6.

9. the sealing resin has a resin bottom surface facing the second side in the thickness direction, the back surfaces of the leads are all exposed from the resin bottom surface; The semiconductor device according to claim 8 .

10. the plurality of leads includes a plurality of first leads and a plurality of second leads; the plurality of first leads are arranged such that the back surfaces of the leads are aligned along a first direction parallel to the second side, the second leads are arranged along the first direction with the lead back surfaces spaced apart from the lead back surfaces of the first leads in a second direction perpendicular to the thickness direction and the first direction; The semiconductor device according to claim 9 .

11. the plurality of leads further includes a plurality of third leads; The plurality of third leads are arranged such that the back surfaces of the leads are aligned along the second direction. The semiconductor device according to claim 10.

12. the plurality of leads includes a fourth lead; the fourth lead has a first end surface facing the first direction and exposed from the sealing resin, and a second end surface facing the second direction and exposed from the sealing resin, and is not electrically connected to the semiconductor element; The semiconductor device according to claim 10.

13. the plurality of leads includes a fifth lead; the fifth lead has a third end surface facing the first direction and exposed from the sealing resin, and a fourth end surface facing the second direction and exposed from the sealing resin, and is electrically connected to the semiconductor element; The semiconductor device according to claim 10.

14. the plurality of leads include a die pad on which the semiconductor element is mounted, the die pad has a die pad main surface facing a first side in the thickness direction, the die pad main surface is rectangular, When viewed in the thickness direction, a third side of the die pad main surface is approximately parallel to the first side. The semiconductor device according to claim 8 .

15. the plurality of leads include a die pad on which the semiconductor element is mounted, the die pad has a die pad main surface facing a first side in the thickness direction, the die pad main surface is rectangular, When viewed in the thickness direction, a third side of the die pad main surface is approximately parallel to the second side. The semiconductor device according to claim 8 .

16. Further provided is a substrate having a substrate main surface facing a first side in the thickness direction and a substrate back surface facing a second side in the thickness direction, The conductive member includes a conductive portion disposed in a through hole that penetrates the base material in the thickness direction.

8. The semiconductor device according to claim 6.

Images