Semiconductor module

Abstract

To enable stable operation of a plurality of transistors connected in parallel.SOLUTION: A semiconductor module 10 includes a first transistor chip 20 including a first gate electrode pad 22, a second transistor chip 30 including a second gate electrode pad 32, a gate driver chip 40 including a fifth pad 45, a first gate connection part 160 used for electrically connecting the first gate electrode pad 22 and the fifth pad 45, and a second gate connection part 170 used for electrically connecting the second gate electrode pad 32 and the fifth pad 45. The first gate connection part 160 includes a first inductance component. The second gate connection part 170 includes a second inductance component. By the first inductance component and the second inductance component, a trans TR whose coupling coefficient becomes negative is formed.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor module. [Background technology]

[0002] Patent Document 1 discloses a switch device having transistors N1 and N2 connected in parallel with each other. The transistors N1 and N2 are configured to be turned on and off in response to a common gate signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2019 / 116737

[0004] [overview] It is desirable that multiple transistors connected in parallel operate stably.

[0005] a first transistor chip including a first gate electrode pad, a first source electrode pad, and a first drain electrode pad; a second transistor chip including a second gate electrode pad, a second source electrode pad, and a second drain electrode pad; a gate driver chip including a gate signal pad; a first gate connection portion used to electrically connect the first gate electrode pad and the gate signal pad; a second gate connection portion used to electrically connect the second gate electrode pad and the gate signal pad; and a source terminal and a drain terminal exposed to the outside, wherein the first source electrode pad, the second source electrode pad, and the source terminal are electrically connected to each other, the first drain electrode pad, the second drain electrode pad, and the drain terminal are electrically connected to each other, the first gate connection portion includes a first inductance component, and the second gate connection portion includes a second inductance component, and the first inductance component and the second inductance component form a transformer with a negative coupling coefficient. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic perspective view of an exemplary semiconductor module according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view of the interior of the semiconductor module of FIG. [Figure 3] FIG. 3 is a schematic rear view of the semiconductor module of FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view of the semiconductor module taken along line F4-F4 in FIG. [Figure 5] FIG. 5 is a schematic cross-sectional view of the semiconductor module taken along line F5-F5 in FIG. [Figure 6] FIG. 6 is a schematic plan view showing an enlarged portion of the inside of the first transistor chip of FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view of the first transistor chip taken along line F7-F7 in FIG. [Figure 8]FIG. 8 is a schematic plan view showing an enlarged view of the first gate connection portion, the second gate connection portion, and the periphery thereof in FIG. [Figure 9] FIG. 9 is a schematic circuit diagram of an exemplary semiconductor module according to the first embodiment. [Figure 10] FIG. 10 is a circuit diagram for explaining gate currents for the first transistor and the second transistor of FIG. [Figure 11] FIG. 11 is a circuit diagram for explaining gate currents for the first transistor and the second transistor of FIG. [Figure 12] FIG. 12 is a schematic plan view showing an enlarged view of the first transistor chip, the second transistor chip, and their surroundings in the interior of the semiconductor module according to the second embodiment. [Figure 13] FIG. 13 is a schematic plan view showing an enlarged view of the first transistor chip, the second transistor chip, and their surroundings in the interior of the exemplary semiconductor module according to the third embodiment. [Figure 14] FIG. 14 is a schematic plan view showing an enlarged view of the first gate connecting portion, the second gate connecting portion, and the periphery thereof in FIG. [Figure 15] FIG. 15 is a schematic plan view showing an enlarged view of the first gate connecting portion, the second gate connecting portion, and the surrounding areas in the semiconductor module of the modified example. [Figure 16] FIG. 16 is a schematic plan view showing an enlarged view of the first gate connecting portion, the second gate connecting portion, and the surrounding areas in the semiconductor module of the modified example. [Figure 17] FIG. 17 is a schematic plan view of the inside of a semiconductor module according to a modified example. [Figure 18] FIG. 18 is a schematic cross-sectional view of the first transistor chip according to the modified example.

[0007] [Detailed explanation] Hereinafter, several embodiments of the semiconductor module of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] The phrase "at least one" used in this disclosure means "one or more" of the desired options. As an example, the phrase "at least one" used in this disclosure means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" used in this disclosure means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0010] As used in this disclosure, "the dimensions (depth, width, length) of A are equal to the dimensions (depth, width, length) of B" or "the dimensions (depth, width, length) of A and the dimensions (depth, width, length) of B are equal to each other" also includes a relationship in which the difference between the dimensions (depth, width, length) of A and the dimensions (depth, width, length) of B is, for example, within 10% of the dimensions (depth, width, length) of A.

[0011] First Embodiment [Overall configuration of semiconductor module] The overall configuration of a semiconductor module 10 according to a first embodiment will be described with reference to FIGS. 1 to 5. FIG. 1 schematically shows a perspective view of the semiconductor module 10 according to the first embodiment. FIG. 2 schematically shows a plan view of the interior of the semiconductor module 10 of FIG. 1. FIG. 3 schematically shows a bottom view of the semiconductor module 10 of FIG. 1. FIG. 4 schematically shows a cross-sectional view of the semiconductor module 10 taken along line F4-F4 in FIG. 2. FIG. 5 schematically shows a cross-sectional view of the semiconductor module 10 taken along line F5-F5 in FIG. 2.

[0012] 1, the semiconductor module 10 includes a first transistor chip 20, a second transistor chip 30, a gate driver chip 40, a lead frame 50 that supports these chips 20, 30, and 40, and a sealing resin 120 that seals these chips 20, 30, and 40 and the lead frame 50. Here, the lead frame 50 is an example of a "lead metal layer."

[0013] The sealing resin 120 has a rectangular flat plate shape with the Z direction as its thickness direction. The sealing resin 120 forms the outer surface of the semiconductor module 10. Therefore, the Z direction can also be said to be the thickness direction of the semiconductor module 10. In addition, in this disclosure, two directions perpendicular to the Z direction that are perpendicular to each other are referred to as the "X direction" and the "Y direction." Furthermore, viewing the semiconductor module 10 from the Z direction is referred to as a "planar view." Here, the X direction is an example of a "second direction," and the Y direction is an example of a "first direction."

[0014] The sealing resin 120 includes a first sealing surface 121 and a second sealing surface 122 facing the opposite side to the first sealing surface 121. The first sealing surface 121 and the second sealing surface 122 are configured as flat surfaces perpendicular to the Z direction, for example. The first sealing surface 121 and the second sealing surface 122 are configured as rectangular surfaces with the X direction as the longitudinal direction and the Y direction as the lateral direction, for example. The sealing resin 120 includes first to fourth sealing side surfaces 123 to 126 as four sealing side surfaces connecting the first sealing surface 121 and the second sealing surface 122. The first sealing side surface 123 and the second sealing side surface 124 constitute both end surfaces of the sealing resin 120 in the X direction. The third sealing side surface 125 and the fourth sealing side surface 126 constitute both end surfaces of the sealing resin 120 in the Y direction.

[0015] 2, the lead frame 50 includes a first die pad 51 that supports the first transistor chip 20 and the second transistor chip 30, and a second die pad 52 that supports the gate driver chip 40. The lead frame 50 also includes a drain terminal 53, a source terminal 54, and a plurality of signal terminals 55 to 59 that constitute the external terminals of the semiconductor module 10. The lead frame 50 is made of a conductive material such as aluminum (Al) or copper (Cu).

[0016] 3, the first die pad 51, the drain terminal 53, the source terminal 54, and the plurality of signal terminals 55 to 59 are exposed from the second sealing surface 122 of the sealing resin 120. On the other hand, the second die pad 52 is not exposed from the second sealing surface 122. In other words, the first die pad 51, the drain terminal 53, the source terminal 54, and the plurality of signal terminals 55 to 59 are exposed to the outside of the semiconductor module 10. On the other hand, the second die pad 52 is not exposed to the outside of the semiconductor module 10.

[0017] The signal terminal 55 constitutes, for example, a logic input terminal. The signal terminal 56 constitutes, for example, a power terminal. The signal terminal 57 constitutes, for example, a ground terminal. The signal terminal 58 constitutes, for example, an enable terminal. The signal terminal 59 constitutes, for example, an input terminal for a low-side gate signal. In this way, the semiconductor module 10 constitutes, for example, a low-side switching element of an inverter circuit. The functions of the signal terminals 55 to 59 can be changed as desired.

[0018] As shown in FIG. 2, the first die pad 51 is disposed closer to the second sealing side-surface 124 in the X direction. Therefore, it can be said that the first transistor chip 20 and the second transistor chip 30 mounted on the first die pad 51 are disposed closer to the second sealing side-surface 124 in the X direction. The first die pad 51 is exposed from the second sealing side-surface 124. The first die pad 51 has a rectangular shape with the X direction as the longitudinal direction and the Y direction as the lateral direction in a plan view. In the example shown in FIG. 2, the longitudinal dimension (X direction) of the first die pad 51 is larger than half the longitudinal dimension (X direction) of the sealing resin 120. The first transistor chip 20 and the second transistor chip 30 are disposed at the same position relative to each other in the X direction and spaced apart from each other in the Y direction. Therefore, it can be said that the first transistor chip 20 and the second transistor chip 30 are disposed side by side in the lateral direction of the first die pad 51.

[0019] Drain terminals 53 and source terminals 54 are distributed on both sides of the first die pad 51 in the Y direction. It can also be said that the drain terminals 53 and source terminals 54 are distributed on both sides in the arrangement direction of the first transistor chip 20 and the second transistor chip 30.

[0020] The drain terminal 53 is disposed closer to the third sealing side surface 125 than the first die pad 51. The source terminal 54 is disposed closer to the fourth sealing side surface 126 than the first die pad 51. The drain terminal 53 and the source terminal 54 are strip-shaped extending in the X direction in a plan view. The drain terminal 53 is exposed from both the second sealing side surface 124 and the third sealing side surface 125. The source terminal 54 is exposed from both the second sealing side surface 124 and the fourth sealing side surface 126. In the example shown in FIG. 2 , the X-direction length of the drain terminal 53 and the X-direction length of the source terminal 54 are equal to each other. The X-direction lengths of both the drain terminal 53 and the source terminal 54 are equal to the X-direction length of the first die pad 51. Note that the X-direction lengths of the drain terminal 53 and the source terminal 54 can be changed as desired. In one example, the X-direction length of the drain terminal 53 and the source terminal 54 may be shorter than the X-direction length of the first die pad 51.

[0021] The first transistor chip 20 and the second transistor chip 30 are rectangular in shape with the X direction as the longitudinal direction and the Y direction as the lateral direction in a plan view. As shown in Fig. 4, the first transistor chip 20 is bonded to the first die pad 51 by a conductive bonding material SD. As shown in Fig. 5, the second transistor chip 30 is bonded to the first die pad 51 by a conductive bonding material SD. The conductive bonding material SD may be, for example, solder paste or silver (Ag) paste.

[0022] In one example, both the first transistor chip 20 and the second transistor chip 30 are made of a nitride semiconductor. An example of a nitride semiconductor is gallium nitride (GaN). In one example, both the first transistor chip 20 and the second transistor chip 30 are high electron mobility transistors (HEMTs) using nitride semiconductors.

[0023] As shown in FIG. 2, the second die pad 52 is disposed closer to the first sealing side surface 123 than the first die pad 51 and spaced apart from the first die pad 51 in a plan view. Furthermore, the second die pad 52 is disposed closer to the fourth sealing side surface 126 than the center of the sealing resin 120 in the Y direction in a plan view. Therefore, the gate driver chip 40 mounted on the second die pad 52 is disposed closer to the first sealing side surface 123 than the first transistor chip 20 and the second transistor chip 30 and closer to the fourth sealing side surface 126 than the center of the sealing resin 120 in the Y direction in a plan view. The gate driver chip 40 is disposed in a position overlapping the second transistor chip 30 in a plan view. As shown in FIG. 5, the gate driver chip 40 is bonded to the second die pad 52 by a conductive adhesive material SD.

[0024] As shown in FIG. 2, the multiple signal terminals 55 to 59 are arranged closer to the first sealing side surface 123 than the first die pad 51 in a plan view. The signal terminals 55 and 56 are arranged adjacent to the second die pad 52 in a plan view. The signal terminal 55 is arranged closer to the fourth sealing side surface 126 than the second die pad 52 in a plan view. The signal terminal 55 is exposed from the fourth sealing side surface 126. The signal terminal 56 is arranged closer to the first sealing side surface 123 than the second die pad 52 in a plan view. The signal terminals 57 to 59 are arranged closer to the third sealing side surface 125 than the second die pad 52 in a plan view. The signal terminals 57 and 58 are arranged at the same position as each other in the X direction and spaced apart from each other in the Y direction. The signal terminals 57 and 58 are exposed from the first sealing side surface 123. The signal terminal 59 is disposed closer to the third sealing side surface 125 than the signal terminals 57 and 58 in a plan view. The signal terminal 59 is exposed from the third sealing side surface 125.

[0025] A wiring portion 58A is connected to the signal terminal 58. The wiring portion 58A includes a first wiring portion extending in the X direction from the signal terminal 58 toward the second sealing side surface 124, and a second wiring portion extending in the Y direction from the first wiring portion toward the fourth sealing side surface 126. A connection portion 58B is provided at the tip of the second wiring portion on the opposite side to the first wiring portion. The dimension in the X direction of the connection portion 58B is larger than the dimension in the X direction (width dimension) of the second wiring portion. The wiring portion 58A and the connection portion 58B are not exposed from the second sealing surface 122 (see FIG. 3).

[0026] A wiring portion 59A is connected to the signal terminal 59. The wiring portion 59A extends in the Y direction from the signal terminal 59 toward the fourth sealing side surface 126. A connection portion 59B is provided at the tip of the wiring portion 59A opposite to the signal terminal 59. The connection portion 59B is arranged closer to the third sealing side surface 125 than the connection portion 58B. The dimension in the X direction of the connection portion 59B is larger than the dimension in the X direction (width dimension) of the wiring portion 59A.

[0027] The gate driver chip 40 includes a control circuit that controls the on / off of the first transistor chip 20 and the second transistor chip 30. The gate driver chip 40 includes a first chip surface 40S and a second chip surface 40R (see FIG. 5) opposite the first chip surface 40S. The second chip surface 40R is the surface that faces the second die pad 52 and is in contact with the conductive bonding material SD. The gate driver chip 40 includes first to sixth pads 41 to 46 exposed from the first chip surface 40S.

[0028] The first pad 41 is electrically connected to a signal terminal 55 via a wire W1. The second pad 42 is electrically connected to a signal terminal 56 via a wire W2. The third pad 43 is electrically connected to a signal terminal 57 via a wire W3. The fourth pad 44 is electrically connected to a signal terminal 58 via a wire W4. The wire W4 is connected to a connection portion 58B. The fifth pad 45 constitutes a gate signal pad. The fifth pad 45 is electrically connected to a first gate electrode pad 22 (described later) of the first transistor chip 20 and a second gate electrode pad 32 (described later) of the second transistor chip 30. The sixth pad 46 constitutes an output stage reference potential pad. The gate driver chip 40 includes an inverter circuit constituting the output stage. The inverter circuit includes an upper arm switching element and a lower arm switching element connected in series with each other. These switching elements may be, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs). The output stage reference potential pad is electrically connected to the source of the lower arm switching element. That is, the output stage reference potential is the source potential of the lower arm switching element. The sixth pad 46 is electrically connected to a first Kelvin source electrode pad 25 (described later) of the first transistor chip 20 and a second Kelvin source electrode pad 35 (described later) of the second transistor chip 30.

[0029] As shown in FIGS. 2 and 4, the first transistor chip 20 includes a first chip surface 20S and a second chip surface 20R opposite to the first chip surface 20S. The second chip surface 20R faces the first die pad 51 and is in contact with a conductive bonding material SD. The first transistor chip 20 includes first to fourth chip side surfaces 20A to 20D as four chip side surfaces connecting the first chip surface 20S and the second chip surface 20R. The first chip side surface 20A and the second chip side surface 20B constitute both end surfaces of the first transistor chip 20 in the longitudinal direction (X direction). The third chip side surface 20C and the fourth chip side surface 20D constitute both end surfaces of the first transistor chip 20 in the lateral direction (Y direction). The first transistor chip 20 includes first to fourth corner portions 21A to 21D. In a plan view, first corner portion 21A is composed of first chip side surface 20A and third chip side surface 20C. In a plan view, second corner portion 21B is composed of second chip side surface 20B and third chip side surface 20C. In a plan view, third corner portion 21C is composed of first chip side surface 20A and fourth chip side surface 20D. In a plan view, fourth corner portion 21D is composed of second chip side surface 20B and fourth chip side surface 20D.

[0030] The first transistor chip 20 includes a first gate electrode pad 22 exposed from the first chip surface 20S, a plurality of (three in FIG. 2) first source electrode pads 23, a plurality of (two in FIG. 2) first drain electrode pads 24, and a first Kelvin source electrode pad 25. The number of the first source electrode pads 23 and the number of the first drain electrode pads 24 can be changed arbitrarily.

[0031] The first gate electrode pad 22 is provided in the first corner portion 21A. The first Kelvin source electrode pad 25 is provided alongside the first gate electrode pad 22 in the Y direction. The first Kelvin source electrode pad 25 is arranged closer to the fourth chip side surface 20D than the first gate electrode pad 22 in the Y direction.

[0032] The plurality of first source electrode pads 23 and the plurality of first drain electrode pads 24 are arranged alternately one by one in the X direction. Adjacent first source electrode pads 23 and first drain electrode pads 24 are arranged spaced apart from each other.

[0033] The multiple first source electrode pads 23 are provided at an end closer to the first chip side surface 20A and an end closer to the second chip side surface 20B, respectively. The first source electrode pad 23 provided at the end closer to the first chip side surface 20A includes a recessed portion 23A provided to avoid the first gate electrode pad 22 and the first Kelvin source electrode pad 25. Both the first gate electrode pad 22 and the first Kelvin source electrode pad 25 are disposed within the recessed portion 23A in a plan view. The first source electrode pad 23 different from the first source electrode pad 23 provided at the end closer to the first chip side surface 20A has a rectangular shape with its short side in the X direction and its long side in the Y direction in a plan view.

[0034] The multiple first drain electrode pads 24 are rectangular in shape with the X direction as the short side direction and the Y direction as the long side direction in a plan view. The X direction dimension (width dimension) of the first drain electrode pad 24 is larger than the X direction dimension (width dimension) of the rectangular first source electrode pad 23. The Y direction dimension (length dimension) of the first drain electrode pad 24 is equal to the Y direction dimension (length dimension) of the first source electrode pad 23. The width and length dimensions of the first drain electrode pad 24 can be arbitrarily changed. The width and length dimensions of the first source electrode pad 23 can be arbitrarily changed. In one example, the width dimension of the first drain electrode pad 24 may be equal to the width dimension of the rectangular first source electrode pad 23. The width dimension of the first drain electrode pad 24 may be smaller than the width dimension of the rectangular first source electrode pad 23. The length dimension of the first drain electrode pad 24 may be different from the length dimension of the first source electrode pad 23.

[0035] As shown in FIGS. 2 and 5, the second transistor chip 30 includes a first chip surface 30S and a second chip surface 30R opposite the first chip surface 30S. The second chip surface 30R faces the first die pad 51 and is in contact with a conductive bonding material SD. The second transistor chip 30 includes first to fourth chip side surfaces 30A to 30D as four chip side surfaces connecting the first chip surface 30S and the second chip surface 30R. The first chip side surface 30A and the second chip side surface 30B constitute both end surfaces of the second transistor chip 30 in the longitudinal direction (X direction). The third chip side surface 30C and the fourth chip side surface 30D constitute both end surfaces of the second transistor chip 30 in the lateral direction (Y direction). The second transistor chip 30 includes first to fourth corner portions 31A to 31D. The first corner portion 31A is composed of the first chip side surface 30A and the third chip side surface 30C in a plan view. The second corner portion 31B is composed of the second chip side surface 30B and the third chip side surface 30C in a plan view. The third corner portion 31C is composed of the first chip side surface 30A and the fourth chip side surface 30D in a plan view. The fourth corner portion 31D is composed of the second chip side surface 30B and the fourth chip side surface 30D in a plan view. In the first embodiment, the second transistor chip 30 is arranged such that the third chip side surface 30C is closer to the first transistor chip 20.

[0036] The second transistor chip 30 includes a second gate electrode pad 32 exposed from the first chip surface 30S, a plurality of (three in FIG. 2 ) second source electrode pads 33, a plurality of (two in FIG. 2 ) second drain electrode pads 34, and a second Kelvin source electrode pad 35. In the first embodiment, the arrangement of the second gate electrode pad 32, the plurality of second source electrode pads 33, the plurality of second drain electrode pads 34, and the second Kelvin source electrode pad 35 of the second transistor chip 30 is the same as the arrangement of the first gate electrode pad 22, the plurality of first source electrode pads 23, the plurality of first drain electrode pads 24, and the first Kelvin source electrode pad 25 of the first transistor chip 20. In addition, the configurations of the second gate electrode pad 32, the plurality of second source electrode pads 33, the plurality of second drain electrode pads 34, and the second Kelvin source electrode pad 35 are the same as the configurations of the first gate electrode pad 22, the plurality of first source electrode pads 23, the plurality of first drain electrode pads 24, and the first Kelvin source electrode pad 25. The second source electrode pad 33 provided at the end closer to the second chip side surface 30B includes a recess 33A provided so as to avoid the second gate electrode pad 32 and the second Kelvin source electrode pad 35. The number of second source electrode pads 33 and the number of second drain electrode pads 34 can be changed as desired.

[0037] The first source electrode pads 23 of the first transistor chip 20, the second source electrode pads 33 of the second transistor chip 30, and the source terminal 54 are individually and electrically connected by source connection members 131-133. The source connection members 131-133 are, for example, clips. The source connection members 131-133 are made of a conductive material such as Al or Cu. Each of the source connection members 131-133 has a strip shape extending in the Y direction in a plan view. Here, the source connection members 131-133 are an example of a "large clip."

[0038] The source connection member 131 connects the first source electrode pad 23 having the recessed portion 23A, the second source electrode pad 33 having the recessed portion 33A, and the source terminal 54. The dimension (width) of the source connection member 131 in the X direction is smaller than the dimensions (width) of the source connection members 132 and 133 in the X direction. The source connection members 132 and 133 connect the first source electrode pad 23 not having the recessed portion 23A, the second source electrode pad 33 not having the recessed portion 33A, and the source terminal 54.

[0039] The first drain electrode pads 24 of the first transistor chip 20, the second drain electrode pads 34 of the second transistor chip 30, and the drain terminal 53 are individually and electrically connected by drain connection members 134, 135. Clips, for example, are used as the drain connection members 134, 135. The drain connection members 134, 135 are made of a conductive material such as Al or Cu. Each of the drain connection members 134, 135 has a strip shape extending in the Y direction in a plan view. In the example shown in FIG. 2, the X-direction dimension (width dimension) of the drain connection members 134, 135 is larger than the width dimension of the source connection members 132, 133. Here, the drain connection members 134, 135 are an example of a "second clip."

[0040] The widths of the source connection members 131 to 133 and the drain connection members 134 and 135 can be changed as desired. In one example, the widths of the source connection members 131 to 133 may be equal to each other. The widths of the drain connection members 134 and 135 may be equal to the widths of the source connection members 132 and 133.

[0041] [HEMT structure of transistor chip] The detailed configuration of the HEMT in the first transistor chip 20 and the second transistor chip 30 will be described with reference to Figures 6 and 7. Figure 6 schematically shows an enlarged planar structure of a portion of a semiconductor layer 210 (described later) of the first transistor chip 20. Figure 7 schematically shows a cross-sectional structure of the first transistor chip 20 taken along line F7-F7 in Figure 6. The HEMT in the second transistor chip 30 is similar to that in the first transistor chip 20, and therefore a detailed description thereof will be omitted.

[0042] As shown in FIG. 7, the first transistor chip 20 includes a semiconductor substrate 200 and a semiconductor layer 210 provided on the semiconductor substrate 200. The semiconductor substrate 200 may be made of silicon (Si), silicon carbide (SiC), GaN, sapphire, or other substrate materials. In one example, the semiconductor substrate 200 is a Si substrate. The thickness of the semiconductor substrate 200 may be, for example, 200 μm or more and 1500 μm or less. The Z direction corresponds to the thickness direction of the semiconductor substrate 200.

[0043] The semiconductor layer 210 includes a buffer layer 211 formed on the semiconductor substrate 200 , an electron transit layer 212 formed on the buffer layer 211 , and an electron supply layer 213 formed on the electron transit layer 212 .

[0044] The buffer layer 211 may be made of any material that can suppress wafer warpage and cracks due to mismatch in thermal expansion coefficients between the semiconductor substrate 200 and the electron transit layer 212. The buffer layer 211 may include one or more nitride semiconductor layers. The buffer layer 211 may include, for example, at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having a different aluminum (Al) composition. For example, the buffer layer 211 may be made of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure.

[0045] The electron transport layer 212 is composed of a nitride semiconductor. The electron transport layer 212 may be, for example, a GaN layer. The thickness of the electron transport layer 212 can be, for example, 0.1 μm or more and 2 μm or less. The electron transport layer 212 may include one or more nitride semiconductor layers. Also, in order to suppress the leakage current in the electron transport layer 212, impurities may be introduced into a part of the electron transport layer 212 to make the region other than the surface layer region of the electron transport layer 212 semi-insulating. In this case, the impurity is, for example, carbon (C). The impurity concentration of the carbon is, for example, 1×10 ,

[0047] , cm -3 or more.

[0046] The electron supply layer 213 is composed of a nitride semiconductor having a larger bandgap than the electron transport layer 212. The electron supply layer 213 may be, for example, an AlGaN layer. Since the larger the Al composition, the larger the bandgap, the electron supply layer 213 which is an AlGaN layer has a larger bandgap than the electron transport layer 212 which is a GaN layer. In one example, the electron supply layer 213 is composed of Al x Ga 1-x N. In this case, x satisfies 0.1 < x < 0.4, and more preferably, 0.1 < x < 0.3. The thickness of the electron supply layer 213 can be, for example, 5 nm or more and 20 nm or less.

[0047] The electron transit layer 212 and the electron supply layer 213 have different lattice constants in their bulk regions. Therefore, the nitride semiconductor (e.g., GaN) constituting the electron transit layer 212 and the nitride semiconductor (e.g., AlGaN) constituting the electron supply layer 213 form a lattice-mismatched heterojunction. Due to spontaneous polarization of the electron transit layer 212 and the electron supply layer 213 and piezoelectric polarization caused by compressive stress applied to the heterojunction of the electron transit layer 212, the energy level of the conduction band of the electron transit layer 212 near the heterojunction interface between the electron transit layer 212 and the electron supply layer 213 becomes lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 214 is formed in the electron transit layer 212 near the heterojunction interface between the electron transit layer 212 and the electron supply layer 213 (e.g., at a distance of about several nanometers from the interface).

[0048] The first transistor chip 20 includes a gate layer 220 formed on a portion of the electron supply layer 213 , and a gate electrode 230 formed on the gate layer 220 . The gate layer 220 is made of a nitride semiconductor. In one example, the gate layer 220 is made of a nitride semiconductor having a band gap smaller than that of the electron supply layer 213 and containing acceptor-type impurities. In one example, the gate layer 220 is GaN (p-type GaN layer) doped with acceptor-type impurities. The acceptor-type impurities may be at least one of magnesium (Mg), zinc (Zn), and C. The maximum concentration of the acceptor-type impurities in the gate layer 220 is, for example, 7×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0049] The gate electrode 230 includes one or more metal layers. In one example, the gate electrode 230 may be a titanium nitride (TiN) layer. In another example, the gate electrode 230 may be composed of a first metal layer composed of Ti and a second metal layer composed of TiN provided on the first metal layer. The gate electrode 230 may be composed of, for example, a material that forms a Schottky junction with the gate layer 220. One example of such a material is TiN. The thickness of the gate electrode 230 may be, for example, 50 nm to 200 nm.

[0050] The first transistor chip 20 includes a passivation layer 240. The passivation layer 240 covers the electron supply layer 213, the gate layer 220, and the gate electrode 230. The passivation layer 240 may be composed of one or any combination of silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), alumina (Al2O3), AlN, and aluminum oxynitride (AlON). The thickness of the passivation layer 240 may be, for example, 50 nm to 200 nm, preferably 80 nm to 150 nm. The passivation layer 240 includes a source opening 241 and a drain opening 242 that expose a portion of the upper surface 213A of the electron supply layer 213.

[0051] The first transistor chip 20 includes a source electrode 250 formed in the source opening 241 and a drain electrode 260 formed in the drain opening 242. The source electrode 250 includes a source contact portion 251 that contacts the electron supply layer 213 through the source opening 241. The drain electrode 260 includes a drain contact portion 261 that contacts the electron supply layer 213 through the drain opening 242.

[0052] The source electrode 250 and the drain electrode 260 include one or more metal layers. In one example, the source electrode 250 and the drain electrode 260 may be composed of one or any combination of Ti, TiN, Al, aluminum silicon copper (AlSiCu), and aluminum copper (AlCu). In one example, the source electrode 250 and the drain electrode 260 are composed of a first metal layer in contact with the electron supply layer 213, a second metal layer stacked on the second metal layer, a third metal layer stacked on the second metal layer, and a fourth metal layer stacked on the third metal layer. The first metal layer is, for example, a Ti layer, the second metal layer is, for example, an Al layer, the third metal layer is, for example, a Ti layer, and the fourth metal layer is, for example, a TiN layer.

[0053] A source contact portion 251 of the source electrode 250 is filled in the source opening 241. The source contact portion 251 is in ohmic contact with the 2DEG 214 directly below the electron supply layer 213 through the source opening 241. A drain contact portion 261 of the drain electrode 260 is filled in the drain opening 242. The drain contact portion 261 is in ohmic contact with the 2DEG 214 directly below the electron supply layer 213 through the drain opening 242. Although not shown in the figure, the semiconductor substrate 200 is electrically connected to the source electrode 250. As a result, a voltage having the same potential as that of the source electrode 250 is applied to the semiconductor substrate 200.

[0054] In a structure in which the gate layer 220 is formed of a nitride semiconductor containing acceptor-type impurities, the conduction path (channel) is blocked by depletion of the 2DEG 214 in the region directly below the gate layer 220 at zero bias when no voltage is applied to the gate electrode 230. This realizes a normally-off HEMT in which the gate threshold voltage is a positive value.

[0055] The gate layer 220 includes a ridge portion 221 and a source-side extension portion 222 and a drain-side extension portion 223 that are thinner than the ridge portion 221. The ridge portion 221 corresponds to a relatively thick portion of the gate layer 220. The gate electrode 230 is in contact with the ridge portion 221. The ridge portion 221 may have a rectangular or trapezoidal shape in a cross section along the XZ plane. The thickness of the ridge portion 221 may be, for example, 100 nm or more and 200 nm or less. The thickness of the ridge portion 221 can be defined by the distance in the Z direction between the upper surface 221A of the ridge portion 221 and the upper surface 213A of the electron supply layer 213. The thickness of the ridge portion 221 is determined in consideration of various parameters such as gate breakdown voltage.

[0056] The source-side extension portion 222 and the drain-side extension portion 223 extend in opposite directions relative to the ridge portion 221. More specifically, the source-side extension portion 222 extends from the ridge portion 221 toward the source opening 241 in the passivation layer 240. It can also be said that the source-side extension portion 222 extends from the ridge portion 221 toward the source electrode 250. The drain-side extension portion 223 extends from the ridge portion 221 toward the drain opening 242 in the passivation layer 240. It can also be said that the drain-side extension portion 223 extends from the ridge portion 221 toward the drain electrode 260.

[0057] The thickness of the source side extension 222 can be, for example, 60 nm or less. The thickness of the source side extension 222 can be, for example, 30 nm or less, 25 nm or less, 20 nm or less, or 15 nm or less. The thickness of the source side extension 222 can be, for example, 10 nm or more. The thickness of the drain side extension 223 can be, for example, 60 nm or less. The thickness of the drain side extension 223 can be, for example, 30 nm or less, 25 nm or less, 20 nm or less, or 15 nm or less. The thickness of the drain side extension 223 can be, for example, 10 nm or more. In one example, the thickness of the source side extension 222 and the thickness of the drain side extension 223 are equal to each other. Here, the thickness of the source side extension 222 can be defined as the distance in the Z direction between the upper surface 222A of the source side extension 222 and the upper surface 213A of the electron supply layer 213. The thickness of the drain-side extension 223 can be defined by the distance between the upper surface 223A of the drain-side extension 223 and the upper surface 213A of the electron supply layer 213 in the Z direction.

[0058] The first transistor chip 20 includes a field plate electrode 270 provided on the passivation layer 240. The field plate electrode 270 is electrically connected to the source electrode 250. In the example shown in FIG. 6, the field plate electrode 270 is formed integrally with the source electrode 250. That is, a part of the source electrode 250 is provided as the field plate electrode 270. Therefore, a voltage having the same potential as that of the source electrode 250 is applied to the field plate electrode 270. The field plate electrode 270 is also called a source field plate. The field plate electrode 270 covers the entire gate layer 220 in a plan view.

[0059] Field plate electrode 270 is spaced apart from drain electrode 260. Field plate electrode 270 includes an end 271 located between gate layer 220 and drain electrode 260 in a plan view. When a drain voltage is applied to drain electrode 260 in a zero bias state where no voltage is applied to gate electrode 230, field plate electrode 270 plays a role in alleviating electric field concentration near the end of gate electrode 230 and the end of gate layer 220.

[0060] Next, an exemplary planar layout of the HEMT structure (first transistor chip 20) will be described with reference to Fig. 6. For clarity, the passivation layer 240 is not shown in Fig. 6. Also, the source opening 241, the drain opening 242, the source electrode 250, and the field plate electrode 270 are depicted by dashed lines.

[0061] 6, the first transistor chip 20 includes, in an element region, a plurality of transistor elements each having a HEMT structure. Note that, although FIG. 6 shows only a plurality of transistor elements aligned in the X direction, in reality, the transistor elements may be aligned in both the X and Y directions.

[0062] A drain electrode 260 is provided for each transistor element. The drain electrode 260 extends in the Y-axis direction in a plan view. The source electrode 250 is provided, for example, to surround each drain electrode 260 in a plan view. As described with reference to FIG. 7 , the source electrode 250 includes a field plate electrode 270. The field plate electrode 270 formed integrally with the source electrode 250 extends toward the adjacent drain electrode 260 in a plan view. It can be said that the field plate electrode 270 is provided to surround the drain electrode 260 in a plan view. Note that in the example shown in FIG. 6 , the source electrode 250 and the field plate electrode 270 are formed continuously in the X direction across multiple transistor elements adjacent in the X direction, but they may also be separated into multiple portions in the X direction.

[0063] The gate layer 220 and the gate electrode 230 are provided for each transistor element. Each gate layer 220 and each gate electrode 230 is formed in a ring shape so as to surround one of the drain electrodes 260 in plan view.

[0064] The first transistor chip 20 includes a gate wiring 281, a source wiring 282, and a drain wiring 283. The gate wiring 281, the source wiring 282, and the drain wiring 283 are formed on a first interlayer insulating layer (not shown) that covers the source electrode 250 and the drain electrode 260. In the example shown in FIG. 6, the gate wiring 281, the source wiring 282, and the drain wiring 283 each extend in the X direction. The gate wiring 281, the source wiring 282, and the drain wiring 283 are arranged spaced apart from each other in the Y direction. The gate wiring 281 is arranged at a position different from the drain electrode 260, the source opening 241, and the drain opening 242 in the Y direction. The source wiring 282 and the drain wiring 283 are arranged at positions overlapping the drain electrode 260, the source opening 241, and the drain opening 242 in a plan view in the Y direction.

[0065] For example, the gate wiring 281 is connected to the gate electrode 230 by a gate connection conductor 284 that penetrates the first interlayer insulating layer and extends to the gate electrode 230. The source wiring 282 is connected to the source electrode 250 by a source connection conductor 285 that penetrates the first interlayer insulating layer. The drain wiring 283 is connected to the drain electrode 260 by a drain connection conductor 286 that penetrates the first interlayer insulating layer. Each of the gate connection conductors 284, source connection conductors 285, and drain connection conductors 286 is, for example, a via that penetrates the first interlayer insulating layer. The number of each of the gate connection conductors 284, source connection conductors 285, and drain connection conductors 286 can be changed as desired.

[0066] For example, the gate wiring 281, the source wiring 282, and the drain wiring 283 are covered with a second interlayer insulating layer (not shown). In one example, the first gate electrode pad 22, the first source electrode pad 23, the first drain electrode pad 24, and the first Kelvin source electrode pad 25 shown in FIG. 2 are formed on the second interlayer insulating layer.

[0067] For example, the gate wiring 281 is connected to the first gate electrode pad 22 by a gate connection conductor (not shown) that penetrates the second interlayer insulating layer and extends to the first gate electrode pad 22. The source wiring 282 is connected to the first source electrode pad 23 by a source connection conductor (not shown) that penetrates the second interlayer insulating layer. The drain wiring 283 is connected to the first drain electrode pad 24 by a drain connection conductor (not shown) that penetrates the second interlayer insulating layer.

[0068] [Gate connection structure] The electrical connection structure between the gate driver chip 40 and the first gate electrode pad 22 of the first transistor chip 20 and the second gate electrode pad 32 of the second transistor chip 30 will be described with reference to Fig. 8. Fig. 8 schematically shows an enlarged planar structure of the region between the gate driver chip 40 and the first gate electrode pad 22 and the second gate electrode pad 32 in Fig. 2.

[0069] The semiconductor module 10 includes a gate connection section 140 that electrically connects a fifth pad 45 (gate signal pad) of the gate driver chip 40 to the first gate electrode pad 22 and the second gate electrode pad 32.

[0070] The gate connection section 140 includes a driver side connection section 150 , a first gate connection section 160 , and a second gate connection section 170 . The driver-side connection unit 150 electrically connects the fifth pad 45 of the gate driver chip 40 to the first gate connection unit 160 and the second gate connection unit 170. The driver-side connection unit 150 includes an isolation region 151 in which the current path between the fifth pad 45 and the first gate electrode pad 22 and the second gate electrode pad 32 is isolated, and a resistor chip 180 arranged in the isolation region 151.

[0071] In one example, the isolation region 151 separates the current path between the first gate connection portion 160 and the second gate connection portion 170. The isolation region 151 is arranged closer to the third chip side surface 20C than the gate driver chip 40 in the Y direction. The isolation region 151 includes a portion that is located at the same position in the X direction as the fifth pad 45 in a plan view. The isolation region 151 includes a first isolated pattern 152 and a second isolated pattern 153. In one example, the first isolated pattern 152 and the second isolated pattern 153 are arranged spaced apart from each other in the Y direction in a plan view.

[0072] The first isolated pattern 152 is connected to both the first gate connection portion 160 and the second gate connection portion 170. The first isolated pattern 152 is arranged closer to the second transistor chip 30 than the first gate electrode pad 22 and the first Kelvin source electrode pad 25 of the first transistor chip 20 in a planar view. The first isolated pattern 152 is arranged closer to the third chip side surface 20C than the second transistor chip 30 in a planar view. In the example shown in FIG. 8 , the first isolated pattern 152 has a rectangular shape with the X direction as the longitudinal direction and the Y direction as the lateral direction in a planar view.

[0073] The second isolated pattern 153 is arranged closer to the gate driver chip 40 than the first isolated pattern 152. The second isolated pattern 153 is arranged closer to the third chip side surface 20C than the second gate electrode pad 32 of the second transistor chip 30. The second isolated pattern 153 is electrically connected to the fifth pad 45 of the gate driver chip 40. A portion of the second isolated pattern 153 closer to the gate driver chip 40 is arranged closer to the third chip side surface 20C than the second Kelvin source electrode pad 35. The second isolated pattern 153 is L-shaped in a plan view. The second isolated pattern 153 includes a first pattern portion extending in the X direction and a second pattern portion extending in the Y direction from an end of the first pattern portion closer to the first chip side surface 20A toward the gate driver chip 40.

[0074] The resistor chip 180 is provided in a current path between the fifth pad 45 of the gate driver chip 40 and the first wiring pattern 161 and the second wiring pattern 171. In one example, the resistor chip 180 is connected between the first isolated pattern 152 and the second isolated pattern 153. The resistor chip 180 includes a first terminal 181 and a second terminal 182. The first terminal 181 is bonded to the first isolated pattern 152 by a conductive bonding material (not shown). The second terminal 182 is bonded to the first pattern portion of the second isolated pattern 153 by a conductive bonding material (not shown).

[0075] The driver-side connection section 150 includes a first wire WA that connects the second isolated pattern 153 and a fifth pad 45 (a pad for gate signals). This electrically connects the second isolated pattern 153 to the fifth pad 45. In the example shown in FIG. 8, the first wire WA is connected to a second pattern portion of the second isolated pattern 153. The first wire WA is arranged closer to the gate driver chip 40 than the resistor chip 180 in a plan view. The first wire WA is, for example, a bonding wire, and is made of a conductive material such as Al, Cu, or Au. The first wire WA may also be connected to the second pattern portion of the second isolated pattern 153.

[0076] A wire WC is connected to the second separated pattern 153. In the example shown in Fig. 8, the wire WC is connected to the second pattern portion of the second separated pattern 153. The wire WC is connected to a connection portion 59B of a wiring portion 59A connected to the signal terminal 59. In this way, the second separated pattern 153 is electrically connected to the signal terminal 59. The wire WC is, for example, a bonding wire, and is made of a conductive material such as Al, Cu, or Au.

[0077] The first gate connection portion 160 is used to electrically connect the first gate electrode pad 22 and the fifth pad 45 of the gate driver chip 40. The first gate connection portion 160 includes a first wiring pattern 161. The first wiring pattern 161 includes a first portion 162.

[0078] The first portion 162 has an annular shape in plan view. More specifically, the first portion 162 has an annular shape extending in a first circumferential direction from a first end portion 152A of the first separated pattern 152. The first end portion 152A of the first separated pattern 152 is the end portion of the first separated pattern 152 in the X direction that is closer to the first chip side surface 20A. In the example shown in FIG. 8, the first circumferential direction is the clockwise direction in plan view. Also, in the example shown in FIG. 8, the first portion 162 has a rectangular annular shape in plan view.

[0079] The first portion 162 includes a first pattern portion P1 extending from the first end portion 152A toward the third chip side surface 20C, a second pattern portion P2 extending in the X direction from the first pattern portion P1 toward the first transistor chip 20, and a third pattern portion P3 extending in the Y direction from the second pattern portion P2 toward the first isolated pattern 152.

[0080] 8, the second pattern portion P2 is arranged closer to the third chip side surface 20C in the Y direction than the first Kelvin source electrode pad 25. The second pattern portion P2 is arranged closer to the third chip side surface 20C in the Y direction than the first gate electrode pad 22.

[0081] 8, the third pattern portion P3 is arranged closer to the first transistor chip 20 than the first isolated pattern 152 in the X direction. The third pattern portion P3 is arranged closer to the first transistor chip 20 than the fifth pad 45 of the gate driver chip 40 in the X direction. The third pattern portion P3 is arranged closer to the first transistor chip 20 than the gate driver chip 40 in the X direction.

[0082] The first portion 162 includes a wire connection portion extending in the X direction from the third pattern portion P3 toward the first chip side surface 20A. The wire connection portion constitutes a tip portion 163 of the first wiring pattern 161. The tip portion 163 is disposed closer to the first transistor chip 20 than the fifth pad 45 of the gate driver chip 40 in the X direction. The tip portion 163 is disposed closer to the first transistor chip 20 than the gate driver chip 40 in the X direction. The tip portion 163 is disposed closer to the third chip side surface 20C than the first isolated pattern 152 in the Y direction. The tip portion 163 is disposed closer to the first isolated pattern 152 than the first gate electrode pad 22 in the Y direction. The tip portion 163 is disposed closer to the first isolated pattern 152 than the first Kelvin source electrode pad 25 in the Y direction. Therefore, in the example shown in FIG. 8 , the tip portion 163 can be said to be disposed between the first isolated pattern 152 and the first Kelvin source electrode pad 25 in the Y direction.

[0083] The width dimension (dimension in the Y direction) of tip portion 163 is larger than the width dimensions of first to third pattern portions P1 to P3. Here, the width dimensions of first to third pattern portions P1 to P3 can be defined as the dimension in a direction perpendicular to the direction in which first to third pattern portions P1 to P3 extend in a plan view.

[0084] The first gate connection portion 160 includes a first gate wire WG1 that connects the first wiring pattern 161 and the first gate electrode pad 22. The first gate wire WG1 is connected to a tip portion 163 of the first wiring pattern 161. The first gate wire WG1 is, for example, a bonding wire, and is made of a conductive material such as Al, Cu, or Au.

[0085] The second gate connection portion 170 is used to electrically connect the second gate electrode pad 32 and the fifth pad 45 of the gate driver chip 40. The second gate connection portion 170 includes a second wiring pattern 171. The second wiring pattern 171 is provided at the same position as the first wiring pattern 161 in the Z direction. The second wiring pattern 171 includes a second portion 172.

[0086] The second portion 172 is arranged alongside the first portion 162. The second portion 172 has an annular shape that surrounds the first portion 162 and extends along the first portion 162 in a plan view. More specifically, the second portion 172 has an annular shape that extends in the second circumferential direction from the second end 152B of the first separated pattern 152. The second end 152B of the first separated pattern 152 is the end of the first separated pattern 152 in the X direction that is closer to the first transistor chip 20. In the example shown in FIG. 8, the second circumferential direction is the counterclockwise direction in a plan view. Therefore, the second portion 172 is configured so that a current flows in the opposite direction to the current flowing through the first portion 162. In the example shown in FIG. 8, the second portion 172 has a rectangular annular shape in a plan view. In this way, the first wiring pattern 161 and the second wiring pattern 171 extend from the first separated pattern 152 so as to branch off from each other into a current path.

[0087] The second portion 172 includes first to fifth pattern portions Q1 to Q5. The first pattern portion Q1 extends from the second end portion 152B toward the third chip side surface 20C. The first pattern portion Q1 is provided between the first isolated pattern 152 and the tip portion 163 of the first wiring pattern 161 in the Y direction. Therefore, it can be said that the first pattern portion Q1 extends from the second end portion 152B toward the tip portion 163 of the first wiring pattern 161.

[0088] The second pattern portion Q2 extends in the X direction from the first pattern portion Q1 toward the first transistor chip 20. The second pattern portion Q2 faces the tip portion 163 of the first wiring pattern 161 in the Y direction. The second pattern portion Q2 extends closer to the first transistor chip 20 than the tip portion 163 of the first wiring pattern 161 in the X direction.

[0089] The third pattern portion Q3 is disposed closer to the first transistor chip 20 in the X direction than the third pattern portion P3 of the first portion 162 of the first wiring pattern 161. The third pattern portion Q3 extends along the third pattern portion P3 of the first portion 162. In other words, the third pattern portion Q3 is parallel to the third pattern portion P3 in a plan view.

[0090] The fourth pattern portion Q4 extends in the X direction from the third pattern portion Q3 toward the first chip side surface 20A. The fourth pattern portion Q4 is disposed closer to the third chip side surface 20C than the second pattern portion P2 of the first portion 162. The fourth pattern portion Q4 extends along the second pattern portion P2 of the first portion 162. In other words, the fourth pattern portion Q4 is parallel to the second pattern portion P2 in a plan view.

[0091] The fifth pattern portion Q5 extends in the Y direction from the fourth pattern portion Q4 toward the gate driver chip 40. The fifth pattern portion Q5 is disposed closer to the first chip side surface 20A than the first pattern portion P1 of the first portion 162. The fifth pattern portion Q5 extends along the first pattern portion P1 of the first portion 162. In other words, the fifth pattern portion Q5 is parallel to the first pattern portion P1 in a plan view.

[0092] The first portion 162 of the first wiring pattern 161 includes a first inductance component LA. The second portion 172 of the second wiring pattern 171 includes a second inductance component LB. The first portion 162 and the second portion 172 form a transformer TR. In this way, it can be said that the first gate connection portion 160 includes the first inductance component LA, and the second gate connection portion 170 includes the second inductance component LB. In the first embodiment, the direction of the current flowing through the first portion 162 and the direction of the current flowing through the second portion 172 are opposite to each other, and therefore the transformer TR is configured so that the coupling coefficient is negative due to the first inductance component LA and the second inductance component LB. In one example, the first inductance component LA may be equal to the second inductance component LB.

[0093] The second wiring pattern 171 includes an extension pattern 173 that extends from the second portion 172 of the second wiring pattern 171 on the opposite side to the first separated pattern 152 in the Y direction. The extension pattern 173 extends in the Y direction from the fifth pattern portion Q5 of the second portion 172 toward the gate driver chip 40. In other words, the fifth pattern portion Q5 is a portion that extends in the Y direction from the fourth pattern portion Q4 to the first separated pattern 152. The extension pattern 173 is a portion of the second wiring pattern 171 that is closer to the gate driver chip 40 than the first separated pattern 152. Note that in FIG. 8, for convenience, the boundary between the fifth pattern portion Q5 and the extension pattern 173 is indicated by a two-dot chain line.

[0094] The extension pattern 173 extends across the Y direction between the second separated pattern 153 and the gate driver chip 40. The extension pattern 173 extends to surround the second separated pattern 153 in a plan view. More specifically, the extension pattern 173 includes first to fourth pattern portions R1 to R4. The first pattern portion R1 extends in the Y direction from the fifth pattern portion Q5 of the second portion 172. The first pattern portion R1 includes a portion that overlaps with the second separated pattern 153 when viewed in the X direction. The second pattern portion R2 extends in the X direction from the first pattern portion R1 toward the second separated pattern 153. The second pattern portion R2 is disposed closer to the first chip side surface 20A in the X direction than the second separated pattern 153. The third pattern portion R3 extends in the Y direction from the second pattern portion R2 toward the gate driver chip 40. The third pattern portion R3 includes a portion closer to the gate driver chip 40 in the Y direction than the second isolated pattern 153. The fourth pattern portion R4 extends in the X direction from the third pattern toward the second transistor chip 30. The fourth pattern portion R4 extends so as to cross between the second isolated pattern 153 and the gate driver chip 40 in the Y direction.

[0095] The first wire WA is provided so as to straddle the extension pattern 173 in plan view. More specifically, the first wire WA is provided so as to straddle the fourth pattern portion R4 of the extension pattern 173 in plan view.

[0096] The extension pattern 173 includes a wire connection portion extending in the Y direction from the fourth pattern portion R4 toward the second isolated pattern 153. The wire connection portion constitutes a tip portion 174 of the second wiring pattern 171. The tip portion 174 is arranged closer to the first transistor chip 20 than the fifth pad 45 of the gate driver chip 40 in the X direction. The tip portion 174 is arranged closer to the first transistor chip 20 than the gate driver chip 40 in the X direction. The tip portion 174 is provided at a position overlapping with the tip portion 163 of the first wiring pattern 161 when viewed from the Y direction. The tip portion 174 is arranged between the second isolated pattern 153 and the gate driver chip 40 in the Y direction. The tip portion 174 is arranged closer to the gate driver chip 40 than the second gate electrode pad 32 in the Y direction. The tip portion 174 is arranged closer to the second isolated pattern 153 than the second Kelvin source electrode pad 35 in the Y direction.

[0097] The width dimension (dimension in the X direction) of the tip portion 174 is larger than the width dimensions of the first to fourth patterns of the extension pattern 173. Here, the width dimensions of the first to fourth patterns can be defined as the dimension in a direction perpendicular to the direction in which the first to fourth patterns extend in a plan view.

[0098] The second gate connection portion 170 includes a second gate wire WG2 that connects the second wiring pattern 171 and the second gate electrode pad 32. The second gate wire WG2 is connected to a tip portion 174 of the extension pattern 173 (second wiring pattern 171). The second gate wire WG2 is, for example, a bonding wire, and is made of a conductive material such as Al, Cu, or Au.

[0099] The first isolated pattern 152, the second isolated pattern 153, the first wiring pattern 161, and the second wiring pattern 171 in the gate connection portion 140 are formed by the lead frame 50. That is, the first die pad 51, the second die pad 52, the drain terminal 53, the source terminal 54, the signal terminals 55 to 59, the first isolated pattern 152, the second isolated pattern 153, the first wiring pattern 161, and the second wiring pattern 171 are integrally provided.

[0100] [Kelvin connection structure] Referring to FIG. 8, the electrical connection structure between the gate driver chip 40 and the first Kelvin source electrode pad 25 of the first transistor chip 20 and the second Kelvin source electrode pad 35 of the second transistor chip 30 will be described.

[0101] As shown in FIG. 8, the semiconductor module 10 includes a Kelvin connection portion 190 that electrically connects the first Kelvin source electrode pad 25 and the second Kelvin source electrode pad 35 to a sixth pad 46 (output stage reference potential pad) of the gate driver chip 40.

[0102] The Kelvin connection 190 includes a Kelvin wiring pattern 191, a first Kelvin wire WK1, a second Kelvin wire WK2, and a second wire WB. The Kelvin wiring pattern 191 is arranged closer to the first transistor chip 20 than the isolation region 151. The Kelvin wiring pattern 191 is arranged closer to the first transistor chip 20 than the tip portion 174 of the extension pattern 173. The Kelvin wiring pattern 191 is arranged at a position overlapping the second pattern portion Q2 and the third pattern portion Q3 of the second portion 172 of the second wiring pattern 171 when viewed from the Y direction. The Kelvin wiring pattern 191 is arranged closer to the gate driver chip 40 than the first Kelvin source electrode pad 25 in the Y direction.

[0103] The Kelvin wiring pattern 191 extends in the Y direction. The Kelvin wiring pattern 191 includes a first connection portion 192, a second connection portion 193, and a third connection portion 194 that are arranged apart from each other in the Y direction.

[0104] The first connection portion 192 is provided at one of both ends of the Kelvin wiring pattern 191 in the Y direction that is closer to the first transistor chip 20. The first connection portion 192 is arranged at the same position in the Y direction as the third corner portion 21C of the first transistor chip 20. The first connection portion 192 is arranged at a position adjacent to the isolation region 151 in the X direction. In the example shown in FIG. 8, the first connection portion 192 is arranged closer to the first isolated pattern 152 than the second isolated pattern 153 in the Y direction. The first connection portion 192 is arranged at a position adjacent to the first isolated pattern 152 in the X direction.

[0105] The second connection portion 193 is provided at one of both ends in the Y direction of the Kelvin wiring pattern 191 that is closer to the gate driver chip 40. The second connection portion 193 is located at the same position in the Y direction as the third corner portion 31C of the second transistor chip 30.

[0106] The third connection portion 194 is disposed between the first connection portion 192 and the second connection portion 193 in the Y direction. The third connection portion 194 is disposed closer to the second connection portion 193 than the first connection portion 192 in the Y direction. The third connection portion 194 is disposed closer to the gate driver chip 40 than the second gate electrode pad 32 in the Y direction. The third connection portion 194 is disposed closer to the fourth chip side surface 20D than the second Kelvin source electrode pad 35 in the Y direction. The third connection portion 194 is disposed closer to the second connection portion 193 than the tip portion 174 of the extension pattern 173 in the Y direction. The second gate wire WG2 connected to the tip portion 174 of the extension pattern 173 is provided so as to straddle the Kelvin wiring pattern 191 in a plan view.

[0107] The first Kelvin wire WK1 connects the first Kelvin source electrode pad 25 and the Kelvin wiring pattern 191. The first Kelvin wire WK1 is connected to a first connection portion 192 of the Kelvin wiring pattern 191. The second Kelvin wire WK2 connects the second Kelvin source electrode pad 35 and the Kelvin wiring pattern 191. The second Kelvin wire WK2 is connected to a third connection portion 194 of the Kelvin wiring pattern 191. The second wire WB connects the second connection portion 193 and the sixth pad 46. Each of the first Kelvin wire WK1, the second Kelvin wire WK2, and the second wire WB is, for example, a bonding wire, and is made of a conductive material such as Al, Cu, or Au.

[0108] [Circuit configuration of semiconductor module] The circuit configuration of the semiconductor module 10 of the first embodiment will be described with reference to Fig. 9. Fig. 9 schematically shows the circuit configuration of the semiconductor module 10 of the first embodiment.

[0109] As shown in FIG. 9, the semiconductor module 10 includes a first transistor 20T, a second transistor 30T, and a gate driver circuit 40A. The first transistor 20T is a GaN HEMT provided on a first transistor chip 20. The first transistor 20T includes a gate electrode G1, a source electrode S1, a drain electrode D1, and a Kelvin source electrode K1. The gate electrode G1 corresponds to the first gate electrode pad 22 shown in FIG. 2, the source electrode S1 corresponds to the first source electrode pad 23 shown in FIG. 2, the drain electrode D1 corresponds to the first drain electrode pad 24 shown in FIG. 2, and the Kelvin source electrode K1 corresponds to the first Kelvin source electrode pad 25 shown in FIG. 2. The second transistor 30T is a GaN HEMT provided on a second transistor chip 30. The second transistor 30T includes a gate electrode G2, a source electrode S2, a drain electrode D2, and a Kelvin source electrode K2. 2, the source electrode S2 corresponds to the second source electrode pad 33 shown in Fig. 2, the drain electrode D2 corresponds to the second drain electrode pad 34 shown in Fig. 2, and the Kelvin source electrode K2 corresponds to the second Kelvin source electrode pad 35. The gate driver circuit 40A is provided in the gate driver chip 40.

[0110] The first transistor 20T and the second transistor 30T are connected in parallel to each other. More specifically, the drain electrode D1 of the first transistor 20T is electrically connected to the drain electrode D2 of the second transistor 30T, and the source electrode S1 of the first transistor 20T is electrically connected to the source electrode S2 of the second transistor 30T. The drain electrodes D1 and D2 are electrically connected to a drain terminal 53. The source electrodes S1 and S2 are electrically connected to a source terminal 54.

[0111] The first transistor 20T includes a Kelvin source electrode K1. The second transistor 30T includes a Kelvin source electrode K2. The Kelvin source electrodes K1 and K2 are electrically connected to each other and to the gate driver circuit 40A.

[0112] The gate electrode G1 of the first transistor 20T and the gate electrode G2 of the second transistor 30T are electrically connected to a current limiting resistor 180A. The current limiting resistor 180A is formed by a resistor chip 180. The gate electrodes G1 and G2 are electrically connected to the gate driver circuit 40A via the current limiting resistor 180A.

[0113] A transformer TR is interposed in the current path between the gate electrodes G1, G2 and the current-limiting resistor 180A. The transformer TR includes a first coil C1 and a second coil C2. The first coil C1 has a first inductance component LA of the first portion 162 of the first wiring pattern 161. The second coil C2 has a second inductance component LB of the second portion 172 of the second wiring pattern 171. The first coil C1 of the current path (first gate connection portion 160) between the gate electrode G1 and the current-limiting resistor 180A and the second coil C2 of the current path (second gate connection portion 170) between the gate electrode G2 and the current-limiting resistor 180A are wound in opposite directions. As a result, the first inductance component LA of the first coil C1 and the second inductance component LB of the second coil C2 form a transformer TR with a negative coupling coefficient.

[0114] [Operation of the first embodiment] The operation of the semiconductor module 10 of the first embodiment will be described with reference to Figures 6 to 8, 10, and 11. Figure 10 shows a case where the first transistor 20T and the second transistor 30T are simultaneously turned on and off. Figure 11 shows a case where a current loop is formed in the first transistor 20T and the second transistor 30T.

[0115] As shown in Figures 6 and 7, nitride semiconductor transistors (GaNHEMTs) are used for the first transistor 20T and the second transistor 30T. Nitride semiconductor transistors are used to operate at higher frequencies, such as several tens of megahertz, than SiMOSFETs. In addition, nitride semiconductor transistors have lower on-resistance than SiMOSFETs and allow for chip miniaturization, making them applicable to semiconductor modules that can be driven with large currents, such as several tens of amperes. However, supplying a large current to a nitride semiconductor transistor may generate heat that exceeds the operating temperature limit of the nitride semiconductor transistor. Therefore, to suppress heat generation, efforts are being made to reduce the amount of current flowing through a single nitride semiconductor transistor by connecting multiple nitride semiconductor transistors in parallel.

[0116] As described above, in a semiconductor module in which multiple nitride semiconductor transistors are connected in parallel, the timing of the on / off driving of the multiple nitride semiconductor transistors can become a problem. If the on / off driving timings of the multiple nitride semiconductor transistors are not synchronized, parallel oscillation may occur between the multiple nitride semiconductor transistors. Furthermore, if current is unevenly supplied to some of the multiple nitride semiconductor transistors, those nitride semiconductor transistors may generate excessive heat.

[0117] In particular, the magnitude of the parasitic capacitance Cgs between the gate and source of a nitride semiconductor transistor is between 1 / 10 and 1 / 5 of that of a SiMOSFET. As a result, in a nitride semiconductor transistor, the charging and discharging of the parasitic capacitance Cgs is completed in 1 nanosecond (nS) or less. Therefore, even a slight variation in the gate current supplied to the gate electrodes of multiple nitride semiconductor transistors can easily cause the parallel oscillation and excessive heat generation in some of the nitride semiconductor transistors.

[0118] In this regard, in the first embodiment, the magnitude of the gate current supplied to the gate electrode G1 of the first transistor 20T and the gate electrode G2 of the second transistor 30T is made uniform, thereby reducing the parallel oscillation and excessive heat generation in some of the nitride semiconductor transistors. The gate currents supplied to the first transistor 20T and the second transistor 30T will be described below.

[0119] As shown in FIG. 8 , for example, when the first transistor 20T and the second transistor 30T are turned on simultaneously, a gate current is supplied from the fifth pad 45 (gate signal pad) through the gate connection portion 140 to both the first gate electrode pad 22 of the first transistor chip 20 and the second gate electrode pad 32 of the second transistor chip 30. More specifically, the gate current flows through the first wire WA, the resistor chip 180, and the first isolation pattern 152 to the first portion 162 of the first wiring pattern 161 and the second portion 172 of the second wiring pattern 171. The gate current flows clockwise through the first wiring pattern 161 and is supplied to the first gate electrode pad 22 through the first gate wire WG1. The gate current flows counterclockwise through the second wiring pattern 171 and is supplied to the second gate electrode pad 32 through the second gate wire WG2. Thus, the gate current flowing through the first portion 162 and the gate current flowing through the second portion 172 are in opposite directions. In this way, the gate voltages of the gate electrodes G1, G2 rise due to the gate currents supplied to the first gate electrode pad 22 and the second gate electrode pad 32, respectively, and the first transistor 20T and the second transistor 30T in FIG. 10 are turned on.

[0120] As shown in FIG. 10, the gate current supplied from the current limiting resistor 180A to the gate electrode G1 of the first transistor 20T is referred to as the "first gate current Ig1," and the gate current supplied from the current limiting resistor 180A to the gate electrode G2 of the second transistor 30T is referred to as the "second gate current Ig2."

[0121] When the first gate current Ig1 is supplied to the first coil C1 formed by the first portion 162 and the second gate current Ig2 is supplied to the second coil C2 formed by the second portion 172, the transformer TR formed by the coils C1 and C2 acts to make the first gate current Ig1 and the second gate current Ig2 equal to each other. That is, when the first gate current Ig1 supplied to the first coil C1 is greater than the second gate current Ig2 supplied to the second coil C2, the first gate current Ig1 decreases while the second gate current Ig2 increases. As a result, the first gate current Ig1 flowing through the first coil C1 and the second gate current Ig2 flowing through the second coil C2 become equal to each other. Therefore, gate currents of the same magnitude are supplied to the gate electrode G1 of the first transistor 20T and the gate electrode G2 of the second transistor 30T. Therefore, the gate voltages of the first gate electrode G1 and the second gate electrode G2 rise at the same rate, so that the first transistor 20T and the second transistor 30T are turned on at the same time.

[0122] As shown in FIG. 11, when the first transistor 20T and the second transistor 30T are turned off, current flows from the gate electrodes G1 and G2 of the transistors 20T and 30T, and the gate voltages of the gate electrodes G1 and G2 decrease. The currents flowing from the gate electrodes G1 and G2 are equalized by the transformer TR, similar to the first gate current Ig1 and the second gate current Ig2. Therefore, the gate voltages of the gate electrodes G1 and G2 decrease in the same manner, and the first transistor 20T and the second transistor 30T are turned off at the same timing. In this way, the operation timings of the first transistor 20T and the second transistor 30T can be synchronized.

[0123] In a semiconductor module not including the transformer TR of the first embodiment, a current path may be formed in which a current flows in a loop through the source electrode S2 of the second transistor 30T, the Kelvin source electrode K1 of the first transistor 20T, the gate electrode G1 of the first transistor 20T, the first coil C1, the second coil C2, the gate electrode G2 of the second transistor 30T, and then back to the source electrode S2 of the second transistor 30T. For example, current flowing from the gate electrode G1 of the first transistor 20T flows toward the gate electrode G2 of the second transistor 30T, as indicated by the dashed arrow in FIG. 11 . This current may delay the turn-off timing of the second transistor 30T or turn the second transistor 30T on again. The same applies to the current flowing from the gate electrode G2 of the second transistor 30T toward the gate electrode G1 of the first transistor 20T. As a result, parallel oscillation may occur between the first transistor 20T and the second transistor 30T when the first transistor 20T and the second transistor 30T are switched on and off.

[0124] However, in the semiconductor module 10 of the first embodiment, when a first current flows through the first coil C1, a second current flows in the second coil C2 due to electromagnetic induction in the same direction, so that the first current flowing from the first coil C1 to the second coil C2 and the second current flowing in the opposite direction to the first current cancel each other out. As a result, the current flowing through the loop-shaped current path is reduced, thereby suppressing parallel oscillation between the first transistor 20T and the second transistor 30T.

[0125] [Effects of the first embodiment] According to the semiconductor module 10 of the first embodiment, the following effects can be obtained. (1-1) The semiconductor module 10 includes a first transistor chip 20 including a first gate electrode pad 22, a first source electrode pad 23, and a first drain electrode pad 24; a second transistor chip 30 including a second gate electrode pad 32, a second source electrode pad 33, and a second drain electrode pad 34; a gate driver chip 40 including a fifth pad 45 as a gate signal pad; a first gate connection portion 160 used to electrically connect the first gate electrode pad 22 and the fifth pad 45; a second gate connection portion 170 used to electrically connect the second gate electrode pad 32 and the fifth pad 45; and a source terminal 54 and a drain terminal 53 exposed to the outside. The first source electrode pad 23, the second source electrode pad 33, and the source terminal 54 are electrically connected to each other. The first drain electrode pad 24, the second drain electrode pad 34, and the drain terminal 53 are electrically connected to each other. The first gate connection portion 160 includes a first inductance component LA. The second gate connection portion 170 includes a second inductance component LB. The first inductance component LA and the second inductance component LB form a transformer TR whose coupling coefficient is negative.

[0126] According to this configuration, the magnitude of the current supplied by the transformer TR to the first gate electrode pad 22 through the first gate connection portion 160 and to the second gate electrode pad 32 through the second gate connection portion 170 can be made uniform. This makes it possible to synchronize the operation timing of the first transistor chip 20 and the operation timing of the second transistor chip 30. This makes it possible to suppress parallel oscillation between the first transistor chip 20 and the second transistor chip 30 connected in parallel and current flowing unevenly to one of the first transistor chip 20 and the second transistor chip 30. This makes it possible to stably operate the first transistor chip 20 and the second transistor chip 30 connected in parallel.

[0127] (1-2) The first gate connection portion 160 includes a first wiring pattern 161 including a first portion 162. The second gate connection portion 170 includes a second wiring pattern 171 including a second portion 172 arranged alongside the first portion 162. The first portion 162 includes a first inductance component LA. The second portion 172 includes a second inductance component LB. The first portion 162 and the second portion 172 form a transformer TR.

[0128] According to this configuration, the transformer TR is configured by the first wiring pattern 161 and the second wiring pattern 171, and therefore the transformer TR can be provided more easily than when the transformer TR is configured by a wire, for example.

[0129] (1-3) The first portion 162 has an annular shape in a plan view. The second portion 172 has an annular shape that surrounds the first portion 162 and extends along the first portion 162 in a plan view. According to this configuration, the transformer TR is formed by combining the annular first portion 162 and the annular second portion 172. This makes it possible to easily provide the transformer TR.

[0130] (1-4) The second portion 172 is configured so that a current flows through it in the opposite direction to the direction of the current flowing through the first portion 162. According to this configuration, the transformer TR having a negative coupling coefficient can be easily provided.

[0131] (1-5) The semiconductor module 10 includes an isolation region 151 in which a current path between the fifth pad 45 of the gate driver chip 40 and the first gate electrode pad 22 and the second gate electrode pad 32 is isolated, and a resistor chip 180 arranged in the isolation region 151.

[0132] According to this configuration, the resistor chip 180 is provided within the semiconductor module 10, and by adjusting the resistance value of this resistor chip 180, the switching speed of the first transistor chip 20 and the second transistor chip 30 can be adjusted during the manufacturing of the semiconductor module 10.

[0133] (1-6) The resistor chip 180 is provided in the current path between the fifth pad 45 of the gate driver chip 40 and the first gate electrode pad 22 and the second gate electrode pad 32, and in the current path between the fifth pad 45 and the first wiring pattern 161 and the second wiring pattern 171.

[0134] According to this configuration, the resistor chip 180 is provided in the current path before it branches into the first wiring pattern 161 and the second wiring pattern 171. This eliminates the need to provide a resistor chip 180 for each of the first wiring pattern 161 and the second wiring pattern 171. This prevents variations in the on / off timing of the first transistor chip 20 and the second transistor chip 30 caused by variations in the resistance values ​​among the multiple resistor chips 180.

[0135] In addition, when a current path is formed in which a current flows in a loop through the source electrode S2 of the second transistor 30T, the Kelvin source electrode K1 of the first transistor 20T, the gate electrode G1 of the first transistor 20T, the first coil C1, the second coil C2, and the gate electrode G2 of the second transistor 30T, and then back to the source electrode S2 of the second transistor 30T, the resistor chip 180 is provided at a position outside the current path. Therefore, the parasitic inductance of the resistor chip 180 no longer has an effect on the current path, and therefore, parallel oscillation between the first transistor chip 20 and the second transistor chip 30 can be suppressed.

[0136] (1-7) The first portion 162 has an annular shape extending in a first circumferential direction from a first end portion 152A of the first separated pattern 152 of the separation region 151. The second portion 172 has an annular shape extending in a second circumferential direction opposite to the first circumferential direction from a second end portion 152B of the first separated pattern 152 opposite to the first end portion 152A.

[0137] According to this configuration, by making the extension direction of the annular first portion 162 and the extension direction of the annular second portion 172 opposite to each other, it is possible to easily realize a configuration in which a current flows through the second portion 172 in the opposite direction to the current flowing through the first portion 162.

[0138] (1-8) The first gate connection portion 160 includes a first gate wire WG1 that connects the first wiring pattern 161 and the first gate electrode pad 22. The second gate connection portion 170 includes a second gate wire WG2 that connects the second wiring pattern 171 and the second gate electrode pad 32.

[0139] According to this configuration, the first gate connecting portion 160 is a combination of the first wiring pattern 161 and the first gate wire WG1, which improves the degree of freedom in the layout of the first gate connecting portion 160. The second gate connecting portion 170 is a combination of the second wiring pattern 171 and the second gate wire WG2, which improves the degree of freedom in the layout of the second gate connecting portion 170.

[0140] (1-9) The first gate wire WG1 is connected to the tip 163 of the first wiring pattern 161. The second gate wire WG2 is connected to the tip 174 of the second wiring pattern 171.

[0141] This configuration makes it possible to increase the lengths of the first portion 162 and the second portion 172 of the transformer TR, which are formed by the first wiring pattern 161 and the second wiring pattern 171. This increases the coupling coefficient of the transformer TR.

[0142] (1-10) The second wiring pattern 171 includes an extension pattern 173 that extends from the second portion 172 of the second wiring pattern 171 on the side opposite to the first separated pattern 152. The second separated pattern 153 is disposed closer to the gate driver chip 40 than the first separated pattern 152. The extension pattern 173 extends so as to cross between the second separated pattern 153 and the gate driver chip 40. The gate connection portion 140 includes a first wire WA that connects the second separated pattern 153 and a fifth pad 45 of the gate driver chip 40. The first wire WA is provided so as to straddle the extension pattern 173 in a plan view.

[0143] According to this configuration, the gate connection portion 140 is a combination of the first wire WA, the first separated pattern 152, and the second separated pattern 153. Furthermore, since the first wire WA is provided so as to straddle the extension pattern 173, it is possible to improve the degree of freedom in the layout of the gate connection portion 140 compared to when the first wire WA is configured as a wiring pattern.

[0144] (1-11) The first gate wire WG1 extends so as to straddle a part of the second portion 172 in plan view. According to this configuration, the degree of freedom in the layout of the first gate connecting portion 160 can be improved.

[0145] (1-12) The semiconductor module 10 includes a first die pad 51 on which a first transistor chip 20 and a second transistor chip 30 are mounted, and a second die pad 52 on which a gate driver chip 40 is mounted. The first die pad 51, the second die pad 52, the source terminal 54, the drain terminal 53, the first wiring pattern 161, and the second wiring pattern 171 are configured by a lead frame 50.

[0146] According to this configuration, the first die pad 51, the second die pad 52, the source terminal 54, the drain terminal 53, the first wiring pattern 161, and the second wiring pattern 171 are integrally formed by the lead frame 50. This makes it possible to easily form the second die pad 52, the source terminal 54, the drain terminal 53, the first wiring pattern 161, and the second wiring pattern 171.

[0147] (1-13) The first transistor chip 20 includes a first Kelvin source electrode pad 25. The second transistor chip 30 includes a second Kelvin source electrode pad 35. The gate driver chip 40 includes a sixth pad 46 as an output stage reference potential pad. The semiconductor module 10 includes a Kelvin connection portion 190 that electrically connects the first Kelvin source electrode pad 25 and the second Kelvin source electrode pad 35 to the sixth pad 46.

[0148] This configuration can avoid the influence of fluctuations in the gate-source voltage caused by changes in the potential of the first source electrode pad 23 and the second source electrode pad 33. Therefore, the on / off operations of the first transistor chip 20 and the second transistor chip 30 can be controlled with high precision.

[0149] (1-14) The Kelvin connection portion 190 includes a Kelvin wiring pattern 191, a first Kelvin wire WK1 connecting the first Kelvin source electrode pad 25 and the Kelvin wiring pattern 191, a second Kelvin wire WK2 connecting the second Kelvin source electrode pad 35 and the Kelvin wiring pattern 191, and a second wire WB connecting the Kelvin wiring pattern 191 and the sixth pad 46 of the gate driver chip 40.

[0150] According to this configuration, the Kelvin connection 190 is a combination of the Kelvin wiring pattern 191, the Kelvin wires WK1 and WK2, and the second wire WB, so that the degree of freedom in the layout of the Kelvin connection 190 can be improved.

[0151] (1-15) The second gate connecting portion 170 includes a second gate wire WG2 that connects the second wiring pattern 171 and the second gate electrode pad 32. The second gate wire WG2 is provided so as to straddle the Kelvin wiring pattern 191 in plan view. This configuration can improve the degree of freedom in the layout of the second gate connecting portion 170.

[0152] (1-16) Both the first transistor chip 20 and the second transistor chip 30 are made of nitride semiconductors. This configuration makes it possible to achieve high frequency operation and low on-resistance compared to, for example, a SiMOSFET.

[0153] (1-17) The semiconductor module 10 includes signal terminals 56 to 58 electrically connected to the gate driver chip 40. Both the first wiring pattern 161 and the second wiring pattern 171 are arranged closer to the first transistor chip 20 and the second transistor chip 30 than the signal terminals 56 to 58 in the X direction.

[0154] With this configuration, the lengths of the first gate connecting portion 160 and the second gate connecting portion 170, particularly the first gate wire WG1 and the second gate wire WG2, can be shortened compared to a configuration in which the first wiring pattern 161 and the second wiring pattern 171 are arranged on the side away from the first transistor chip 20 and the second transistor chip 30 with respect to the signal terminals 56 to 58. Therefore, the inductance of the first gate connecting portion 160 and the second gate connecting portion 170 can be reduced.

[0155] (1-18) The semiconductor module 10 includes a signal terminal 58 electrically connected to the gate driver chip 40, and a wiring portion 58A connected to the signal terminal 58 and extending toward the gate driver chip 40. The shortest distance between the first portion 162 and the second portion 172 is shorter than the shortest distance between the second portion 172 and the wiring portion 58A.

[0156] This configuration reduces the effect of the magnetic field generated by the current flowing through the wiring portion 58A on the second portion 172. Therefore, the first transistor chip 20 and the second transistor chip 30 connected in parallel can operate stably.

[0157] (1-19) The arrangement of the first gate electrode pad 22, the first source electrode pad 23, the first drain electrode pad 24, and the first Kelvin source electrode pad 25 in the first transistor chip 20 is the same as the arrangement of the second gate electrode pad 32, the second source electrode pad 33, the second drain electrode pad 34, and the second Kelvin source electrode pad 35 in the second transistor chip 30.

[0158] According to this configuration, a common transistor chip can be used for the first transistor chip 20 and the second transistor chip 30. Therefore, the manufacturing cost of the semiconductor module 10 can be reduced.

[0159] (1-20) The semiconductor module 10 includes source connection members 131 to 133 as first clips that electrically connect the first source electrode pad 23, the second source electrode pad 33, and the source terminal 54, and drain connection members 134, 135 as second clips that electrically connect the first drain electrode pad 24, the second drain electrode pad 34, and the drain terminal 53.

[0160] According to this configuration, since each of the source connection members 131 to 133 and the drain connection members 134, 135 is formed by a clip, the source connection members 131 to 133 and the drain connection members 134, 135 can have low resistance and have improved heat dissipation performance.

[0161] Second Embodiment A semiconductor module 10 of the second embodiment will be described with reference to Fig. 12. The semiconductor module 10 of the second embodiment differs from the semiconductor module 10 of the first embodiment mainly in the electrode configurations of both the first transistor chip 20 and the second transistor chip 30. In the following, components common to the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0162] 12 is a schematic diagram showing an enlarged planar structure of the first transistor chip 20, the second transistor chip 30, and their surroundings. In order to make the drawing easier to understand, dots are added to the first gate electrode pad 22, the second gate electrode pad 32, a third gate electrode pad 26 (described later), and a fourth gate electrode pad 36 (described later) in FIG.

[0163] The first transistor chip 20 and the second transistor chip 30 of the second embodiment are arranged such that the third chip side surface 20C of the first transistor chip 20 and the third chip side surface 30C of the second transistor chip 30 are adjacent to each other in the Y direction. Therefore, the arrangement posture of the first transistor chip 20 is different from that of the first embodiment. Specifically, both the first gate electrode pad 22 and the first Kelvin source electrode pad 25 are arranged closer to the second sealing side surface 124 (see FIG. 2) in the X direction. On the other hand, the arrangement posture of the second transistor chip 30 is the same as that of the first embodiment. Therefore, both the second gate electrode pad 32 and the second Kelvin source electrode pad 35 are arranged closer to the first sealing side surface 123 (see FIG. 2) in the X direction.

[0164] Of the multiple first source electrode pads 23 of the first transistor chip 20, the first source electrode pad 23 closest to the second chip side surface 20B includes a recessed portion 23B. The recessed portion 23B is recessed so as to expose the second chip side surface 20B and the third chip side surface 20C. Of the multiple second source electrode pads 33 of the second transistor chip 30, the second source electrode pad 33 closest to the second chip side surface 30B includes a recessed portion 33B. The recessed portion 33B is recessed so as to expose the second chip side surface 30B and the third chip side surface 30C.

[0165] The first transistor chip 20 includes a third gate electrode pad 26 and a third Kelvin source electrode pad 27. The third gate electrode pad 26 is electrically connected to the first gate electrode pad 22. The third Kelvin source electrode pad 27 is electrically connected to the first Kelvin source electrode pad 25. Both the third gate electrode pad 26 and the third Kelvin source electrode pad 27 are arranged in the second corner portion 21B. More specifically, the third gate electrode pad 26 and the third Kelvin source electrode pad 27 are arranged in a region surrounded by the second chip side surface 20B, the third chip side surface 20C, and the recessed portion 23B in a plan view.

[0166] The third Kelvin source electrode pad 27 is disposed adjacent to the third gate electrode pad 26 in the Y direction. The third Kelvin source electrode pad 27 is disposed closer to the third chip side surface 20C than the third gate electrode pad 26 in the Y direction. When viewed from the X direction, the third gate electrode pad 26 is disposed at a position overlapping with the first Kelvin source electrode pad 25. In the example shown in FIG. 12, the third gate electrode pad 26 is disposed at the same position as the first Kelvin source electrode pad 25 in the Y direction. When viewed from the X direction, the third Kelvin source electrode pad 27 is disposed at a position overlapping with the first gate electrode pad 22. In the example shown in FIG. 12, the third Kelvin source electrode pad 27 is disposed at the same position as the first gate electrode pad 22 in the Y direction.

[0167] 12, the first source electrode pads 23 provided at both ends of the first transistor chip 20 in the longitudinal direction (X direction) are line-symmetrical with respect to an imaginary line extending in the Y direction at the center of the longitudinal direction of the first transistor chip 20 in a plan view. More specifically, the plurality of first source electrode pads 23 and the plurality of first drain electrode pads 24 are line-symmetrical with respect to the imaginary line. Therefore, even when the first transistor chip 20 is rotated 180 degrees in a plan view, the positional relationship between the plurality of first source electrode pads 23 and the plurality of first drain electrode pads 24 remains the same. Therefore, even when the first transistor chip 20 is rotated 180 degrees in a plan view, the source connecting members 131 to 133 and the drain connecting members 134 and 135 can be connected to the plurality of first source electrode pads 23 and the plurality of first drain electrode pads 24 in the same manner as in the state before the first transistor chip 20 is rotated 180 degrees in a plan view.

[0168] The second transistor chip 30 includes a fourth gate electrode pad 36 and a fourth Kelvin source electrode pad 37. The fourth gate electrode pad 36 is electrically connected to the second gate electrode pad 32. The fourth Kelvin source electrode pad 37 is electrically connected to the second Kelvin source electrode pad 35. Both the fourth gate electrode pad 36 and the fourth Kelvin source electrode pad 37 are arranged in the second corner portion 31B. More specifically, the fourth gate electrode pad 36 and the fourth Kelvin source electrode pad 37 are arranged in a region surrounded by the second chip side surface 30B, the third chip side surface 30C, and the recessed portion 33B in a plan view. The fourth Kelvin source electrode pad 37 is arranged adjacent to the fourth gate electrode pad 36 in the Y direction.

[0169] The fourth Kelvin source electrode pad 37 is disposed closer to the third chip side surface 30C in the Y direction than the fourth gate electrode pad 36. When viewed from the X direction, the fourth gate electrode pad 36 is disposed at a position overlapping with the fourth Kelvin source electrode pad 37. In the example shown in FIG. 12 , the fourth gate electrode pad 36 is disposed at the same position as the fourth Kelvin source electrode pad 37 in the Y direction.

[0170] As shown in FIG. 12 , the arrangement of the first gate electrode pad 22, the first source electrode pad 23, the first drain electrode pad 24, the first Kelvin source electrode pad 25, the third gate electrode pad 26, and the third Kelvin source electrode pad 27 in the first transistor chip 20 is the same as the arrangement of the second gate electrode pad 32, the second source electrode pad 33, the second drain electrode pad 34, the second Kelvin source electrode pad 35, the fourth gate electrode pad 36, and the fourth Kelvin source electrode pad 37 in the second transistor chip 30.

[0171] In the first transistor chip 20, the first gate wire WG1 is connected to the third gate electrode pad 26. The first Kelvin wire WK1 is connected to the third Kelvin source electrode pad 27. In the second transistor chip 30, the second gate wire WG2 is connected to the second gate electrode pad 32. The second Kelvin wire WK2 is connected to the second Kelvin source electrode pad 35.

[0172] [Effects of the second embodiment] According to the semiconductor module 10 of the second embodiment, the following effects can be obtained. (2-1) The arrangement of the first gate electrode pad 22, the first source electrode pad 23, the first drain electrode pad 24, the first Kelvin source electrode pad 25, the third gate electrode pad 26, and the third Kelvin source electrode pad 27 in the first transistor chip 20 is the same as the arrangement of the second gate electrode pad 32, the second source electrode pad 33, the second drain electrode pad 34, the second Kelvin source electrode pad 35, the fourth gate electrode pad 36, and the fourth Kelvin source electrode pad 37 in the second transistor chip 30.

[0173] According to this configuration, a common transistor chip can be used for the first transistor chip 20 and the second transistor chip 30. Therefore, the manufacturing cost of the semiconductor module 10 can be reduced.

[0174] (2-2) The first transistor chip 20 and the second transistor chip 30 are arranged side by side in the Y direction. The first transistor chip 20 is rectangular in plan view and includes four corner portions 21A to 21D. The first transistor chip 20 includes a third gate electrode pad 26 electrically connected to the first gate electrode pad 22. The first gate electrode pad 22 is arranged in the first corner portion 21A of the four corner portions 21A to 21D in plan view. The third gate electrode pad 26 is arranged in the second corner portion 21B of the four corner portions 21A to 21D in plan view, which is at the same position in the Y direction as the first corner portion 21A but spaced apart in the X direction.

[0175] According to this configuration, when the third gate electrode pad 26 is disposed closer to the first wiring pattern 161 in the X direction, it is disposed closer to the second transistor chip 30 in the Y direction. This brings the tip 163 of the first wiring pattern 161 and the third gate electrode pad 26 into close proximity in the Y direction, allowing the length of the first gate wire WG1 to be shortened.

[0176] (2-3) The first transistor chip 20 includes a third Kelvin source electrode pad 27 electrically connected to the first Kelvin source electrode pad 25. The first Kelvin source electrode pad 25 is arranged at the first corner portion 21A of the four corner portions 21A to 21D in a planar view. The third Kelvin source electrode pad 27 is arranged at the second corner portion 21B, which is at the same position in the Y direction as the first corner portion 21A of the four corner portions 21A to 21D in a planar view and is spaced apart in the X direction.

[0177] According to this configuration, when the third Kelvin source electrode pad 27 is disposed closer to the Kelvin wiring pattern 191 in the X direction, it is disposed closer to the first connection portion 192 of the Kelvin wiring pattern 191 in the Y direction. This brings the first connection portion 192 and the third Kelvin source electrode pad 27 into close positions in the Y direction, thereby making it possible to shorten the length of the first Kelvin wire WK1.

[0178] Third Embodiment A semiconductor module 10 of the third embodiment will be described with reference to Figures 13 and 14. The semiconductor module 10 of the third embodiment differs from the semiconductor module 10 of the second embodiment mainly in the electrode configurations of both the first transistor chip 20 and the second transistor chip 30 and the configurations of the first gate connection portion 160 and the second gate connection portion 170. In the following, components common to the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0179] Fig. 13 is a schematic diagram showing an enlarged planar structure of the first transistor chip 20, the second transistor chip 30, and their surroundings. Fig. 14 is a schematic diagram showing an enlarged planar structure of the first gate connection portion 160, the second gate connection portion 170, and their surroundings in Fig. 13.

[0180] 13, the first transistor chip 20 of the third embodiment is different from the first transistor chip 20 of the second embodiment in the arrangement of the first gate electrode pad 22, the first Kelvin source electrode pad 25, the third gate electrode pad 26, and the third Kelvin source electrode pad 27. Specifically, the first gate electrode pad 22 is arranged closer to the third chip side surface 20C than the first Kelvin source electrode pad 25.

[0181] The second transistor chip 30 of the third embodiment is different from the second transistor chip 30 of the second embodiment in the arrangement of the second gate electrode pad 32, the second Kelvin source electrode pad 35, the fourth gate electrode pad 36, and the fourth Kelvin source electrode pad 37. Specifically, the fourth gate electrode pad 36 is arranged closer to the third chip side surface 20C than the fourth Kelvin source electrode pad 37.

[0182] As shown in FIG. 13 , the arrangement of the first gate electrode pad 22, the first source electrode pad 23, the first drain electrode pad 24, the first Kelvin source electrode pad 25, the third gate electrode pad 26, and the third Kelvin source electrode pad 27 in the first transistor chip 20 is the same as the arrangement of the second gate electrode pad 32, the second source electrode pad 33, the second drain electrode pad 34, the second Kelvin source electrode pad 35, the fourth gate electrode pad 36, and the fourth Kelvin source electrode pad 37 in the second transistor chip 30.

[0183] As shown in FIG. 14, in the third embodiment, the configurations of the first gate connection portion 160, the second gate connection portion 170, and the Kelvin connection portion 190 are different from those in the second embodiment. The Kelvin wiring pattern 191 in the Kelvin connection portion 190 extends closer to the third sealing side surface 125 than the isolation region 151. The first connection portion 192 of the Kelvin wiring pattern 191 is arranged closer to the third sealing side surface 125 in the Y direction than the first isolation pattern 152. The first connection portion 192 is arranged at the same position as the third Kelvin source electrode pad 27 of the first transistor chip 20 in the Y direction. The first connection portion 192 is arranged closer to the third sealing side surface 125 than the third gate electrode pad 26 in the Y direction.

[0184] As the Kelvin connection portion 190 extends closer to the third sealing side surface 125 than the first isolated pattern 152, the shape of the second portion 172 of the second wiring pattern 171 in the second gate connection portion 170 differs from that in the second embodiment. Specifically, the first pattern portion Q1 and the second pattern portion Q2 of the second portion 172 are provided so as to surround the first connection portion 192 in a plan view. The length of the first pattern portion Q1 in the Y direction is longer than in the second embodiment. Accordingly, the length of the third pattern portion Q3 in the Y direction is shorter.

[0185] Due to the changes in the first pattern portion Q1 and the third pattern portion Q3 of the second wiring pattern 171, the shape of the first portion 162 of the first wiring pattern 161 in the first gate connection portion 160 is different from that in the second embodiment. Specifically, the length in the Y direction of the third pattern portion P3 of the first portion 162 is shorter than that in the second embodiment. The first portion 162 further includes a fourth pattern portion P4 and a fifth pattern portion P5. The fourth pattern portion P4 extends in the X direction from the third pattern portion P3 toward the first pattern portion P1. The fourth pattern portion P4 is disposed adjacent to the second pattern portion Q2 of the second portion 172 of the second wiring pattern 171 in the Y direction. The fourth pattern portion P4 extends along the second pattern portion Q2 of the second portion 172. In other words, the fourth pattern portion P4 is parallel to the second pattern portion Q2 in a plan view. The fifth pattern portion P5 extends in the Y direction from the fourth pattern portion P4 toward the first separated pattern 152. The fifth pattern portion P5 is disposed adjacent to the first pattern portion Q1 and the second pattern portion Q2 of the second portion 172 in the X direction. The fifth pattern portion P5 extends along the first pattern portion Q1 of the second portion 172. In other words, the fifth pattern portion P5 is parallel to the first pattern portion Q1 in a plan view. The tip portion 163 of the first wiring pattern 161 extends in the Y direction from the fifth pattern portion P5 toward the first separated pattern 152. The width dimension (dimension in the X direction) of the tip portion 163 is larger than the width dimension (dimension in the X direction) of the fifth pattern portion P5. The tip portion 163 is disposed at a position overlapping with the first connection portion 192 of the Kelvin wiring pattern 191 when viewed from the X direction. The semiconductor module 10 of the third embodiment can achieve the same effects as the second embodiment.

[0186] <Example of change> The above-described embodiments can be modified as follows: Furthermore, the above-described embodiments and the following modifications can be combined with each other within the scope of technical compatibility.

[0187] In each embodiment, the shape of each of the first portion 162 of the first wiring pattern 161 in the first gate connection portion 160 and the second portion 172 of the second wiring pattern 171 in the second gate connection portion 170 in a plan view can be changed as desired. Examples of modifications of the first wiring pattern 161 and the second wiring pattern 171 include a first modification shown in Fig. 15 and a second modification shown in Fig. 16. Figs. 15 and 16 schematically show enlarged planar structures of the first gate connection portion 160, the second gate connection portion 170, and their surrounding areas.

[0188] In a first modified example shown in FIG. 15 , both the first portion 162 and the second portion 172 may be annular in plan view. In the example shown in FIG. 15 , the first portion 162 is annular in plan view with a gap. The second portion 172 is annular in plan view with a gap. The second portion 172 extends along the first portion 162 in plan view. In the example shown in FIG. 15 , the first portion 162 and the second portion 172 are concentric in plan view. Therefore, the distance between the first portion 162 and the second portion 172 is constant in the extension direction of the first portion 162 and the second portion 172 in plan view.

[0189] 15, the configuration of the extension pattern 173 of the second wiring pattern 171 is different. The extension pattern 173 is L-shaped in a plan view. The extension pattern 173 includes a first pattern portion R1 and a fourth pattern portion R4. The first pattern portion R1 is connected to the fourth pattern portion R4. The first pattern portion R1 extends from the second portion 172 to a position closer to the gate driver chip 40 than the second isolated pattern 153.

[0190] In a second modified example shown in FIG. 16, each of a first portion 162 of a first wiring pattern 161 and a second portion 172 of a second wiring pattern 171 may have a spiral shape in a plan view. The first portion 162 of the first wiring pattern 161 includes a fourth pattern portion P4 and a fifth pattern portion P5. The fourth pattern portion P4 extends in the X direction from the third pattern portion P3 toward the first sealing side surface 123 (see FIG. 2). The fifth pattern portion P5 extends in the Y direction from the fourth pattern portion P4 toward the second pattern portion P2. The tip portion 163 of the first wiring pattern 161 extends in the Y direction from the fifth pattern portion P5 toward the second pattern portion P2.

[0191] The second portion 172 of the second wiring pattern 171 is connected to a portion between the center and the first end portion 152A of the first separated pattern 152 in the X direction. The second portion 172 includes first to seventh pattern portions Q1 to Q7.

[0192] The first pattern portion Q1 of the second portion 172 is disposed at a position adjacent to the first pattern portion P1 of the first portion 162 in the X direction. The first pattern portion Q1 of the second portion 172 extends in the Y direction along the first pattern portion P1 of the first portion 162. In other words, the first pattern portion Q1 is parallel to the first pattern portion P1 in a plan view.

[0193] The second pattern portion Q2 of the second portion 172 extends in the X direction from the first pattern portion Q1 toward the tip portion 163 of the first wiring pattern 161. The second pattern portion Q2 of the second portion 172 extends along the second pattern portion P2 of the first portion 162. In other words, the second pattern portion Q2 is parallel to the second pattern portion P2 in a plan view.

[0194] The third pattern portion Q3 of the second portion 172 extends in the Y direction from the second pattern portion Q2 toward the first separated pattern 152. The third pattern portion Q3 of the second portion 172 is disposed in a position adjacent to the fifth pattern portion P5 of the first portion 162 in the X direction. The third pattern portion Q3 of the second portion 172 extends along the fifth pattern portion P5 of the first portion 162. In other words, the third pattern portion Q3 is parallel to the fifth pattern portion P5 in a plan view.

[0195] The fourth pattern portion Q4 of the second portion 172 extends in the X direction from the third pattern portion Q3 toward the first transistor chip 20. The fourth pattern portion Q4 of the second portion 172 is disposed at a position adjacent to the fourth pattern portion P4 of the first portion 162 in the Y direction. The fourth pattern portion Q4 of the second portion 172 extends in the X direction along the fourth pattern portion P4 of the first portion 162. In other words, the fourth pattern portion Q4 is parallel to the fourth pattern portion P4 in a plan view.

[0196] The fifth pattern portion Q5 of the second portion 172 extends in the Y direction from the fourth pattern portion Q4 of the second portion 172 toward the third sealing side surface 125 (see FIG. 2). The fifth pattern portion Q5 of the second portion 172 is disposed in a position adjacent to the third pattern portion P3 of the first portion 162 in the X direction. The fifth pattern portion Q5 extends in the Y direction along the third pattern portion P3 of the first portion 162. In other words, the fifth pattern portion Q5 is parallel to the third pattern portion P3 in a plan view.

[0197] The sixth pattern portion Q6 of the second portion 172 extends in the X direction from the fifth pattern portion Q5 toward the first sealing side surface 123 (see FIG. 2). The sixth pattern portion Q6 is disposed in a position adjacent to the second pattern portion P2 of the first portion 162 in the Y direction. The sixth pattern portion Q6 extends in the X direction along the second pattern portion P2 of the first portion 162. In other words, the sixth pattern portion Q6 is parallel to the second pattern portion P2 in a plan view.

[0198] The seventh pattern portion Q7 of the second portion 172 extends in the Y direction from the sixth pattern portion Q6 toward the gate driver chip 40. The seventh pattern portion Q7 is disposed in a position adjacent to the first pattern portion P1 of the first portion 162 in the X direction. The seventh pattern portion Q7 extends in the Y direction along the first pattern portion P1 of the first portion 162. In other words, the seventh pattern portion Q7 is parallel to the first pattern portion P1 in a plan view. The seventh pattern portion Q7 is connected to the extension pattern 173.

[0199] The width dimension of the second portion 172 is smaller than the width dimensions of the second to fourth pattern portions R2 to R4 of the extension pattern 173. In the example shown in FIG. 16, the width dimension of the second portion 172 is equal to the width dimension of the first portion 162. Here, the width dimension of the second portion 172 is the dimension in a direction perpendicular to the direction in which the second portion 172 extends in a plan view. The width dimensions of the second to fourth pattern portions R2 to R4 of the extension pattern 173 are the dimension in a direction perpendicular to the direction in which the second to fourth pattern portions R2 to R4 extend in a plan view. The width dimension of the first portion 162 is the dimension in a direction perpendicular to the direction in which the first portion 162 extends in a plan view.

[0200] In each embodiment, the positions of the signal terminals 55 to 59 can be changed as desired. For example, the signal terminal 55 may be arranged closer to the second transistor chip 30 than the gate driver chip 40 in the X direction. The signal terminal 55 may be arranged closer to the second transistor chip 30 than both the first wiring pattern 161 and the second wiring pattern 171 in the X direction. The signal terminal 59 may be arranged closer to the first transistor chip 20 than the gate driver chip 40 in the X direction. The signal terminal 59 may be arranged closer to the first transistor chip 20 than both the first wiring pattern 161 and the second wiring pattern 171 in the X direction.

[0201] In each embodiment, the position of the Kelvin wiring pattern 191 can be changed as desired. For example, the Kelvin wiring pattern 191 may be disposed at a position other than between the tip end 174 of the second wiring pattern 171 and the second transistor chip 30.

[0202] In each embodiment, the shortest distance between the first portion 162 and the second portion 172 of the first wiring pattern 161 may be equal to or greater than the shortest distance between the wiring portion 58A connected to the signal terminal 58 and the second portion 172 of the second wiring pattern 171.

[0203] In each embodiment, the configurations of the source connection members 131 to 133 and the drain connection members 134, 135 can be changed as desired. In one example, as shown in FIG. 17, each of the source connection members 131 to 133 may be a wire. Each of the drain connection members 134, 135 may be a wire. In one example, each of the source connection members 131 to 133 and the drain connection members 134, 135 is a bonding wire formed by a wire bonding apparatus. In the example shown in FIG. 17, a plurality of each of the source connection members 131 to 133 and the drain connection members 134, 135 is provided.

[0204] In each embodiment, the arrangement of the first separated pattern 152 and the second separated pattern 153 in the separation region 151 can be changed as desired. In one example, the first separated pattern 152 and the second separated pattern 153 may be arranged spaced apart from each other in the X direction. In this case, the first terminal 181 and the second terminal 182 of the resistor chip 180 are arranged in the X direction.

[0205] In each embodiment, the position of the isolation region 151 can be changed as desired, as long as the isolation region 151 is disposed at a predetermined position on the current path between the fifth pad 45 (gate signal pad) of the gate driver chip 40 and the first gate electrode pad 22 of the first transistor chip 20 and the second gate electrode pad 32 of the second transistor chip 30.

[0206] In each embodiment, the position of the resistor chip 180 can be changed as desired, as long as the resistor chip 180 is placed at a predetermined position on the current path between the fifth pad 45 (gate signal pad) of the gate driver chip 40 and the first gate electrode pad 22 of the first transistor chip 20 and the second gate electrode pad 32 of the second transistor chip 30.

[0207] In each embodiment, the positional relationship between the second isolated pattern 153 of the isolation region 151 and the extension pattern 173 of the second wiring pattern 171 can be changed as desired. The extension pattern 173 may be disposed closer to the first isolated pattern 152 than the second isolated pattern 153. In other words, the extension pattern 173 does not have to cross the Y-direction between the second isolated pattern 153 and the gate driver chip 40. As a result, the first wire WA connected to the fifth pad 45 does not have to cross the extension pattern 173.

[0208] In each embodiment, the first die pad 51, the second die pad 52, the source terminal 54, the drain terminal 53, the first wiring pattern 161, and the second wiring pattern 171 are configured by the lead frame 50, but this is not limited to this. It is sufficient that at least one of the first die pad 51, the second die pad 52, the source terminal 54, the drain terminal 53, the first wiring pattern 161, and the second wiring pattern 171 is configured by the lead frame 50.

[0209] In the first embodiment, the first Kelvin source electrode pad 25 may be omitted from the first transistor chip 20. In the second and third embodiments, at least one of the first Kelvin source electrode pad 25 and the third Kelvin source electrode pad 27 may be omitted from the first transistor chip 20.

[0210] In the first embodiment, the second Kelvin source electrode pad 35 may be omitted from the second transistor chip 30. In the second and third embodiments, at least one of the second Kelvin source electrode pad 35 and the fourth Kelvin source electrode pad 37 may be omitted from the second transistor chip 30.

[0211] In the first embodiment, the arrangement of the first gate electrode pad 22, the first source electrode pad 23, the first drain electrode pad 24, and the first Kelvin source electrode pad 25 of the first transistor chip 20 may be different from the arrangement of the second gate electrode pad 32, the second source electrode pad 33, the second drain electrode pad 34, and the second Kelvin source electrode pad 35 of the second transistor chip 30.

[0212] In the second and third embodiments, the arrangement of the first gate electrode pad 22, the first source electrode pad 23, the first drain electrode pad 24, the first Kelvin source electrode pad 25, the third gate electrode pad 26, and the third Kelvin source electrode pad 27 of the first transistor chip 20 may be different from the arrangement of the second gate electrode pad 32, the second source electrode pad 33, the second drain electrode pad 34, the second Kelvin source electrode pad 35, the fourth gate electrode pad 36, and the fourth Kelvin source electrode pad 37 of the second transistor chip 30.

[0213] In the second and third embodiments, the positions of the third gate electrode pad 26 and the third Kelvin source electrode pad 27 can be changed as desired. For example, the third gate electrode pad 26 and the third Kelvin source electrode pad 27 may be disposed in the fourth corner portion 21D.

[0214] In the second and third embodiments, the positions of the fourth gate electrode pad 36 and the fourth Kelvin source electrode pad 37 can be changed as desired. For example, the fourth gate electrode pad 36 and the fourth Kelvin source electrode pad 37 may be disposed in the fourth corner portion 31D.

[0215] In each embodiment, the relative positions of the first transistor chip 20, the second transistor chip 30, the gate driver chip 40, the first wiring pattern 161, and the second wiring pattern 171 can be changed as desired. For example, the first wiring pattern 161 and the second wiring pattern 171 may be disposed in the same position as the second transistor chip 30 in the Y direction, and the gate driver chip 40 may be disposed in a position overlapping the first transistor chip 20 when viewed from the X direction. Alternatively, both the first wiring pattern 161 and the second wiring pattern 171 may be disposed in positions different from both the first transistor chip 20 and the second transistor chip 30 in the Y direction.

[0216] In each embodiment, the sealing resin 120 may be omitted from the semiconductor module 10. In each embodiment, the HEMT structure of the first transistor chip 20 can be modified as desired. FIG. 18 shows a modified example of the configuration of the nitride transistor of the first transistor chip 20. FIG. 18 schematically shows a cross-sectional structure of the first transistor chip 20. As shown in FIG. 18, the first transistor chip 20 of the modified example has a different configuration of the gate layer 220. Specifically, the gate layer 220 has a configuration in which the source side extension portion 222 and the drain side extension portion 223 are omitted from the gate layer 220 of each embodiment. Therefore, the gate layer 220 has a rectangular shape in the cross-sectional view of FIG. 18. The HEMT structure of the second transistor chip 30 may also be modified in a similar manner.

[0217] In each embodiment, at least one of the first transistor chip 20 and the second transistor chip 30 may be configured as either a SiMOSFET or a SiCMOSFET.

[0218] One or more of the various examples described in the present disclosure may be combined to the extent that they are not technically inconsistent. The term "on" as used in this disclosure includes the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" means that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0219] The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" of the Z direction described in this disclosure being "up" and "down" of the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0220] <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the above embodiment. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0221] [Appendix 1] a first transistor chip (20) including a first gate electrode pad (22), a first source electrode pad (23), and a first drain electrode pad (24); a second transistor chip (30) including a second gate electrode pad (32), a second source electrode pad (33), and a second drain electrode pad (34); a gate driver chip (40) including gate signal pads (45); a first gate connection portion (160) used to electrically connect the first gate electrode pad (22) and the gate signal pad (45); a second gate connection portion (170) used to electrically connect the second gate electrode pad (32) and the gate signal pad (45); an externally exposed source terminal (54) and drain terminal (53); Including, the first source electrode pad (23), the second source electrode pad (33), and the source terminal (54) are electrically connected to each other; the first drain electrode pad (24), the second drain electrode pad (34), and the drain terminal (53) are electrically connected to each other; The first gate connection portion (160) includes a first inductance component (LA), The second gate connection portion (170) includes a second inductance component (LB), The first inductance component (LA) and the second inductance component (LB) form a transformer (TR) whose coupling coefficient is negative. A semiconductor module (10).

[0222] [Appendix 2] The first gate connection portion (160) includes a first wiring pattern (161) including a first portion (162), the second gate connection portion (170) includes a second wiring pattern (171) including a second portion (172) arranged alongside the first portion (162); The first portion (162) includes the first inductance component (LA), The second portion (172) includes the second inductance component (LB), The first portion (162) and the second portion (172) constitute the transformer (TR). 2. The semiconductor module of claim 1.

[0223] [Appendix 3] The first portion (162) is annular in plan view, The second portion (172) is annular in shape and surrounds the first portion (162) in a plan view, and extends along the first portion (162). 3. The semiconductor module according to claim 2.

[0224] [Appendix 4] The second portion (172) is configured so that a current flows in a direction opposite to that of the current flowing in the first portion (162). 4. The semiconductor module according to claim 2 or 3.

[0225] [Appendix 5] an isolation region (151) in which a current path is isolated between the gate signal pad (45) and the first gate electrode pad (22) and the second gate electrode pad (32); a resistor chip (180) disposed in the isolation region (151); Contains 5. The semiconductor module according to any one of claims 2 to 4.

[0226] [Appendix 6] The resistor chip (180) is provided in the current path between the gate signal pad (45) and the first wiring pattern (161) and the second wiring pattern (171). 6. The semiconductor module according to claim 5.

[0227] [Appendix 7] The separation region (151) is a first separation pattern (152) to which both the first wiring pattern (161) and the second wiring pattern (171) are connected; a second isolation pattern (153) electrically connected to the gate signal pad (45) and spaced apart from the first isolation pattern (152); Including, the first wiring pattern (161) and the second wiring pattern (171) extend from the first separation pattern (152) so as to branch off the current path, The resistor chip (180) is connected between the first isolated pattern (152) and the second isolated pattern (153). 7. The semiconductor module according to claim 6.

[0228] [Appendix 8] the first portion (162) is annular and extends in a first circumferential direction from a first end (152A) of the first separation pattern (152); The second portion (172) has an annular shape extending from a second end (152B) of the first separated pattern (152) opposite to the first end (152A) in a second circumferential direction opposite to the first circumferential direction. 8. The semiconductor module of claim 7.

[0229] [Appendix 9] the first gate connection part (160) includes a first gate wire (WG1) connecting the first wiring pattern (161) and the first gate electrode pad (22); The second gate connection part (170) includes a second gate wire (WG2) that connects the second wiring pattern (171) and the second gate electrode pad (32). 9. The semiconductor module according to claim 8.

[0230] [Appendix 10] the first gate wire (WG1) is connected to the tip (163) of the first wiring pattern (161); The second gate wire (WG2) is connected to the tip (174) of the second wiring pattern (171). 10. The semiconductor module according to claim 9.

[0231] [Appendix 11] The second wiring pattern (171) includes an extension pattern (173) extending from the second portion (172) of the second wiring pattern (171) on the opposite side to the first separation pattern (152), the second isolated pattern (153) is disposed closer to the gate driver chip (40) than the first isolated pattern (152); The extension pattern (173) extends across the second isolation pattern (153) and the gate driver chip (40), a first wire (WA) connecting the second isolation pattern (153) and the gate signal pad (45); The first wire (WA) is provided so as to straddle the extension pattern (173) in a plan view. 11. The semiconductor module of claim 10.

[0232] [Appendix 12] The first gate wire (WG1) extends so as to straddle a part of the second portion (172) in a plan view. 12. The semiconductor module according to any one of claims 9 to 11.

[0233] [Appendix 13] a first die pad (51) on which the first transistor chip (20) and the second transistor chip (30) are mounted, and a second die pad (52) on which the gate driver chip (40) is mounted, At least one of the first die pad (51), the second die pad (52), the source terminal (54), the drain terminal (53), the first wiring pattern (161), and the second wiring pattern (171) is formed of a lead metal layer (50). 13. The semiconductor module according to any one of claims 2 to 12.

[0234] [Appendix 14] The first transistor chip (20) includes a first Kelvin source electrode pad (25); the second transistor chip (30) includes a second Kelvin source electrode pad (35); The gate driver chip (40) includes an output stage reference potential pad (46), and a Kelvin connection portion (190) that electrically connects the first Kelvin source electrode pad (25) and the second Kelvin source electrode pad (35) to the output stage reference potential pad (46). 14. The semiconductor module according to any one of claims 2 to 13.

[0235] [Appendix 15] The Kelvin connection (190) Kelvin wiring pattern (191) and a first Kelvin wire (WK1) connecting the first Kelvin source electrode pad (25) and the Kelvin wiring pattern (191); a second Kelvin wire (WK2) connecting the second Kelvin source electrode pad (35) and the Kelvin wiring pattern (191); a second wire (WB) connecting the Kelvin wiring pattern (191) and the output stage reference potential pad (46); Contains 15. The semiconductor module of claim 14.

[0236] [Appendix 16] the second gate connection portion (170) includes a second gate wire (WG2) connecting the second wiring pattern (171) and the second gate electrode pad (32); The second gate wire (WG2) is provided so as to straddle the Kelvin wiring pattern (191) in a plan view. 16. The semiconductor module of claim 15.

[0237] [Appendix 17] The arrangement of the first gate electrode pad (22), the first source electrode pad (23), the first drain electrode pad (24), and the first Kelvin source electrode pad (25) in the first transistor chip (20) is the same as the arrangement of the second gate electrode pad (32), the second source electrode pad (33), the second drain electrode pad (34), and the second Kelvin source electrode pad (35) in the second transistor chip (30). 17. The semiconductor module according to any one of claims 14 to 16.

[0238] [Appendix 18] the first transistor chip (20) and the second transistor chip (30) are arranged side by side in a first direction (Y); The first transistor chip (20) has a rectangular shape in a plan view and includes four corner portions (21A to 21D), the first transistor chip (20) includes a third gate electrode pad (26) electrically connected to the first gate electrode pad (22); the first gate electrode pad (22) is arranged in a first corner portion (21A) of the four corner portions (21A to 21D) in a plan view, The third gate electrode pad (26) is disposed in a second corner portion (21B) that is located at the same position in the first direction (Y) as the first corner portion (21A) of the four corner portions (21A to 21D) in a plan view and that is spaced apart in a second direction (X) perpendicular to the first direction (Y) in a plan view. 18. The semiconductor module of claim 17.

[0239] [Appendix 19] a first clip (131-133) that electrically connects the first source electrode pad (23), the second source electrode pad (33), and the source terminal (54); second clips (134, 135) that electrically connect the first drain electrode pad (24), the second drain electrode pad (34), and the drain terminal (53); Contains 19. A semiconductor module according to any one of appendices 1 to 18.

[0240] [Appendix 20] Both the first transistor chip (20) and the second transistor chip (30) are made of nitride semiconductors. 20. The semiconductor module according to any one of claims 1 to 19.

[0241] [Appendix 21] The first transistor chip (20) a third gate electrode pad (26) electrically connected to the first gate electrode pad (22); a first Kelvin source electrode pad (25); a third Kelvin source electrode pad (27) electrically connected to the first Kelvin source electrode pad (25); Including, The second transistor chip (30) a fourth gate electrode pad (36) electrically connected to the second gate electrode pad (32); a second Kelvin source electrode pad (35); a fourth Kelvin source electrode pad (37) electrically connected to the second Kelvin source electrode pad (35); Contains 21. The semiconductor module according to any one of claims 1 to 20.

[0242] [Appendix 22] The arrangement of the first gate electrode pad (22), the first source electrode pad (23), the first drain electrode pad (24), the first Kelvin source electrode pad (25), the third gate electrode pad (26), and the third Kelvin source electrode pad (27) in the first transistor chip (20) is the same as the arrangement of the second gate electrode pad (32), the second source electrode pad (33), the second drain electrode pad (34), the second Kelvin source electrode pad (35), the fourth gate electrode pad (36), and the fourth Kelvin source electrode pad (37) in the second transistor chip (30). 22. The semiconductor module of claim 21.

[0243] [Appendix 23] the first transistor chip (20) and the second transistor chip (30) are arranged side by side in a first direction (Y); The first transistor chip (20) has a rectangular shape in a plan view and includes four corner portions (21A to 21D), the first gate electrode pad (22) and the first Kelvin source electrode pad (25) are arranged in a first corner portion (21A) of the four corner portions (21A to 21D) of the first transistor chip (20) that is closer to the second transistor chip (30) in a plan view; The third gate electrode pad (26) and the third Kelvin source electrode pad (27) are arranged in a second corner portion (21B) that is located at the same position in the first direction (Y) as the first corner portion (21A) of the four corner portions (21A to 21D) of the first transistor chip (20) in a plan view and that is spaced apart in a second direction (X) perpendicular to the first direction (Y) in a plan view. 23. The semiconductor module according to claim 21 or 22.

[0244] [Appendix 24] the first gate electrode pad (22) and the first Kelvin source electrode pad (25) are arranged side by side in the first direction (Y) at the first corner portion (21A); the third gate electrode pad (26) and the third Kelvin source electrode pad (27) are arranged side by side in the first direction (Y) in the second corner portion (21B); When viewed from the second direction (X), the first gate electrode pad (22) is disposed at a position overlapping the third Kelvin source electrode pad (27), When viewed from the second direction (X), the third gate electrode pad (26) is disposed at a position overlapping the first Kelvin source electrode pad (25). 24. The semiconductor module of claim 23.

[0245] [Appendix 25] the first gate electrode pad (22) and the first Kelvin source electrode pad (25) are arranged side by side in the first direction (Y) at the first corner portion (21A); the third gate electrode pad (26) and the third Kelvin source electrode pad (27) are arranged side by side in the first direction (Y) in the second corner portion (21B); When viewed from the second direction (X), the first gate electrode pad (22) is disposed at a position overlapping the third gate electrode pad (26), When viewed from the second direction (X), the first Kelvin source electrode pad (25) is disposed at a position overlapping the third Kelvin source electrode pad (27). 24. The semiconductor module of claim 23.

[0246] [Appendix 26] The first transistor chip (20) and the second transistor chip (30) are arranged such that chip side surfaces (20C / 30C) between the first corner portion (21A / 31A) and the second corner portion (21B / 31B) face each other. 26. The semiconductor module according to any one of appendices 23 to 25.

[0247] [Appendix 27] Both the first portion (162) and the second portion (172) are annular in plan view. 19. The semiconductor module according to any one of appendixes 2 to 18.

[0248] [Appendix 28] the first transistor chip (20) and the second transistor chip (30) are arranged side by side in a first direction (Y); the first wiring pattern (161), the second wiring pattern (171), and the gate driver chip (40) are arranged at a distance from the first transistor chip (20) and the second transistor chip (30) in a second direction (X) perpendicular to the first direction (Y) in a plan view; the first wiring pattern (161) and the second wiring pattern (171) are disposed apart from the gate driver chip (40) in the first direction (Y), and are disposed at the same position as the first transistor chip (20) in the first direction (Y); The gate driver chip (40) is disposed at a position overlapping the second transistor chip (30) when viewed from the second direction (X). 19. The semiconductor module according to any one of appendixes 2 to 18.

[0249] [Appendix 29] signal terminals (56-58) electrically connected to the gate driver chip (40); Both the first wiring pattern (161) and the second wiring pattern (171) are disposed closer to the first transistor chip (20) and the second transistor chip (30) than the signal terminals (56 to 58) in the second direction (X). 29. The semiconductor module of claim 28.

[0250] [Appendix 30] the first transistor chip (20) and the second transistor chip (30) are arranged side by side in a first direction (Y); The Kelvin wiring pattern (191) extends in the first direction (Y) and is disposed between the tip end (174) of the second wiring pattern (171) and the second transistor chip (30). 17. The semiconductor module according to claim 15 or 16.

[0251] [Appendix 31] a signal terminal (58) electrically connected to the gate driver chip (40); a wiring portion (58A) connected to the signal terminal (58) and extending toward the gate driver chip (40); Including, The shortest distance between the first portion (162) and the second portion (172) is shorter than the shortest distance between the second portion (172) and the wiring portion (58A). 19. The semiconductor module according to any one of appendixes 2 to 18.

[0252] [Appendix 32] a sealing resin (120) that seals the first transistor chip (20), the second transistor chip (30), the gate driver chip (40), the first gate connection portion (160), the second gate connection portion (170), the source terminal (54), and the drain terminal (53); The source terminal (54) and the drain terminal (53) include portions exposed from the sealing resin (120). 32. The semiconductor module according to any one of claims 1 to 31.

[0253] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0254] 10...Semiconductor module 20...First transistor chip 20S...First chip side 20R...Second chip surface 20A to 20D: 1st to 4th chip sides 20T...first transistor 21A~21D...1st to 4th corners 22...First gate electrode pad 23...First source electrode pad 23A...recess 24...First drain electrode pad 25...First Kelvin source electrode pad 26...Third gate electrode pad 27...Third Kelvin source electrode pad 30...Second transistor chip 30S...First chip side 30R...Second chip surface 30T...Second transistor 30A to 30D: 1st to 4th chip sides 31A~31D...1st to 4th corners 32...Second gate electrode pad 33...Second source electrode pad 34...Second drain electrode pad 35...Second Kelvin source electrode pad 36...Fourth gate electrode pad 37...4th Kelvin source electrode pad 40...Gate driver chip 40A...Gate driver circuit 40S...First chip side 40R...Second chip surface 41...First pad 42...Second pad 43...Third pad 44...4th pad 45...5th pad (gate signal pad) 46...6th pad (output stage reference potential pad) 50...Lead frame 51...First die pad 52...Second die pad 53...Drain terminal 54...Source terminal 55~59...Signal terminals 58A, 59A...Wiring section 58B, 59B...Connection 60...Gate connection 70...First gate connection 71...First wiring pattern 72...First gate wire 80...Second gate connection 81...Second wiring pattern 82...Second gate wire 90...Separation area 91...First separation pattern 92...Second separation pattern 120…Sealing resin 121...first sealing surface 122…Second sealing surface 123~126...1st~4th sealing side 131 to 134...Source connection members 135, 136...Drain connection members 140...Gate connection 150...Driver side connection part 151…Separation area 152...First separation pattern 152A…First end 152B…Second end 153...Second separation pattern 160...First gate connection 161...First wiring pattern 162…Part 1 163...Tip 170...Second gate connection 171...Second wiring pattern 172…Second part 173...extension pattern 174...Tip 180...Resistor chip 180A...Current limiting resistor 181...1st terminal 182…Second terminal 190...Kelvin connection 191...Kelvin wiring pattern 192...First connection part 193...Second connection part 194...Third connection part 200...Semiconductor substrate 210...Semiconductor layer 211...Buffer layer 212...Electron transit layer 213…electron supply layer 213A…Top surface 214...Two-dimensional electron gas (2DEG) 220...Gate layer 221...Ridge 221A…Top surface 222…Source side extension part 222A…Top surface 223...Drain side extension 223A…Top surface 230...Gate electrode 240...passivation layer 241...Source opening 242...Drain opening 250...Source electrode 251...Source contact part 260...Drain electrode 261...Drain contact part 270...Field plate electrode 271...End 281...Gate wiring 282...Source wiring 283...Drain wiring 284...Gate connecting conductor 285...Source connecting conductor 286...Drain connecting conductor C1: First coil C2: Second coil D1, D2...Drain electrodes G1, G2...gate electrodes S1, S2...Source electrodes K1, K2...Kelvin source electrodes P1 to P5: 1st to 5th pattern portions of the 1st part Q1 to Q7: 1st to 7th pattern sections of the second section R1 to R4: 1st to 4th pattern parts of the extension pattern TR...transformer W1~W4...Wires WA...First wire WB: Second wire WC…Wire WG1: First gate wire WG2: Second gate wire WK1...1st Kelvin wire WK2...Second Kelvin wire LA: First inductance component LB: Second inductance component

Claims

1. a first transistor chip including a first gate electrode pad, a first source electrode pad, and a first drain electrode pad; a second transistor chip including a second gate electrode pad, a second source electrode pad, and a second drain electrode pad; a gate driver chip including gate signal pads; a first gate connection portion used to electrically connect the first gate electrode pad and the gate signal pad; a second gate connection portion used to electrically connect the second gate electrode pad and the gate signal pad; a source terminal and a drain terminal exposed to the outside; Including, the first source electrode pad, the second source electrode pad, and the source terminal are electrically connected to each other; the first drain electrode pad, the second drain electrode pad, and the drain terminal are electrically connected to each other; the first gate connection portion includes a first inductance component; the second gate connection portion includes a second inductance component; The first inductance component and the second inductance component form a transformer with a negative coupling coefficient. Semiconductor module.

2. the first gate connection portion includes a first wiring pattern including a first portion; the second gate connection portion includes a second wiring pattern including a second portion arranged alongside the first portion; the first portion includes the first inductance component, the second portion includes the second inductance component, The first part and the second part constitute the transformer. The semiconductor module according to claim 1 .

3. the first portion is annular in plan view, The second portion is annular in shape and surrounds the first portion in a plan view and extends along the first portion. The semiconductor module according to claim 2 .

4. The second portion is configured so that a current flows in a direction opposite to that of the current flowing in the first portion. The semiconductor module according to claim 2 .

5. an isolation region in which a current path between the gate signal pad and the first gate electrode pad and the second gate electrode pad is isolated; a resistor chip disposed in the isolation region; Contains The semiconductor module according to claim 2 .

6. The resistor chip is provided in the current path between the gate signal pad and the first wiring pattern and the second wiring pattern. The semiconductor module according to claim 5 .

7. The separation region is a first isolated pattern to which both the first wiring pattern and the second wiring pattern are connected; a second isolation pattern electrically connected to the gate signal pad and spaced apart from the first isolation pattern; Including, the first wiring pattern and the second wiring pattern extend from the first isolated pattern so as to branch off the current path, The resistor chip is connected between the first isolated pattern and the second isolated pattern. The semiconductor module according to claim 6 .

8. the first portion is annular and extends in a first circumferential direction from a first end of the first separated pattern; The second portion has an annular shape extending from a second end portion of the first separated pattern opposite to the first end portion in a second circumferential direction opposite to the first circumferential direction. The semiconductor module according to claim 7 .

9. the first gate connection portion includes a first gate wire connecting the first wiring pattern and the first gate electrode pad; The second gate connection portion includes a second gate wire that connects the second wiring pattern and the second gate electrode pad. The semiconductor module according to claim 8 .

10. the first gate wire is connected to a tip end of the first wiring pattern, The second gate wire is connected to a tip of the second wiring pattern. The semiconductor module according to claim 9 .

11. the second wiring pattern includes an extension pattern extending from a side of the second wiring pattern opposite to the first separation pattern with respect to the second portion, the second isolated pattern is disposed closer to the gate driver chip than the first isolated pattern, the extension pattern extends across the second isolation pattern and the gate driver chip; a first wire connecting the second isolation pattern and the gate signal pad; The first wire is provided so as to straddle the extension pattern in a plan view. The semiconductor module according to claim 10.

12. The first gate wire extends so as to straddle a part of the second portion in a plan view. The semiconductor module according to claim 9 .

13. a first die pad on which the first transistor chip and the second transistor chip are mounted, and a second die pad on which the gate driver chip is mounted, At least one of the first die pad, the second die pad, the source terminal, the drain terminal, the first wiring pattern, and the second wiring pattern is formed of a lead metal layer. The semiconductor module according to claim 2 .

14. the first transistor chip includes a first Kelvin source electrode pad; the second transistor chip includes a second Kelvin source electrode pad; the gate driver chip includes an output stage reference potential pad; a Kelvin connection portion electrically connecting the first Kelvin source electrode pad and the second Kelvin source electrode pad to the output stage reference potential pad; The semiconductor module according to claim 2 .

15. The Kelvin connection Kelvin wiring pattern, a first Kelvin wire connecting the first Kelvin source electrode pad and the Kelvin wiring pattern; a second Kelvin wire connecting the second Kelvin source electrode pad and the Kelvin wiring pattern; a second wire connecting the Kelvin wiring pattern and the output stage reference potential pad; Contains The semiconductor module according to claim 14.

16. the second gate connection portion includes a second gate wire connecting the second wiring pattern and the second gate electrode pad; The second gate wire is provided so as to straddle the Kelvin wiring pattern in a plan view. The semiconductor module according to claim 15.

17. The arrangement of the first gate electrode pad, the first source electrode pad, the first drain electrode pad, and the first Kelvin source electrode pad in the first transistor chip is the same as the arrangement of the second gate electrode pad, the second source electrode pad, the second drain electrode pad, and the second Kelvin source electrode pad in the second transistor chip. The semiconductor module according to claim 14.

18. the first transistor chip and the second transistor chip are arranged side by side in a first direction, the first transistor chip has a rectangular shape in a plan view and includes four corner portions; the first transistor chip includes a third gate electrode pad electrically connected to the first gate electrode pad; the first gate electrode pad is disposed in a first corner portion of the four corner portions in a plan view, The third gate electrode pad is disposed at a second corner portion of the four corner portions, which is located at the same position in the first direction as the first corner portion in a plan view and is spaced apart in a second direction perpendicular to the first direction in a plan view. The semiconductor module according to claim 17.

19. a first clip electrically connecting the first source electrode pad, the second source electrode pad, and the source terminal; a second clip electrically connecting the first drain electrode pad, the second drain electrode pad, and the drain terminal; Contains The semiconductor module according to claim 1 .

20. Both the first transistor chip and the second transistor chip are made of nitride semiconductor. The semiconductor module according to any one of claims 1 to 19.

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