Display device, mother board, and manufacturing method for display device

Abstract

To suppress the decrease in reliability.SOLUTION: According to an embodiment, a display device includes a substrate, an inorganic insulating layer disposed over the substrate in a display region to display images and a peripheral region outside the display region, a display element disposed in the display region, a first sealing layer formed of an inorganic insulating material and covering the display element, a plurality of peripheral partition walls disposed in the peripheral region, and a second sealing layer formed of the inorganic insulating material and disposed in the display region and the peripheral region. Each of the peripheral partition walls includes a first lower part disposed on the inorganic insulating layer and a first upper part disposed on the first lower part, and is covered with the second sealing layer.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a display device, a motherboard, and a method for manufacturing the display device. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put to practical use. These display elements include a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. In addition to the light-emitting layer, the organic layer includes functional layers such as a hole transport layer and an electron transport layer. In the process of manufacturing such display elements, a technique for suppressing deterioration in reliability is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device, a motherboard, and a method for manufacturing a display device that can suppress a decrease in reliability. [Means for solving the problem]

[0005] According to one embodiment, the display device comprises: The display device comprises a substrate, an inorganic insulating layer disposed above the substrate over a display area for displaying an image and a peripheral area outside the display area, a display element disposed in the display area, a first sealing layer formed of an inorganic insulating material and covering the display element, a plurality of peripheral partitions disposed in the peripheral area, and a second sealing layer formed of an inorganic insulating material and disposed over the display area and the peripheral area, wherein each of the plurality of peripheral partitions has a first lower portion disposed on the inorganic insulating layer and a first upper portion disposed on the first lower portion, and is covered with the second sealing layer.

[0006] According to one embodiment, the motherboard comprises: The display device comprises a panel portion having a display area for displaying an image and a peripheral area outside the display area, a margin portion outside the panel portion, an inorganic insulating layer arranged across the panel portion and the margin portion, a display element arranged in the display area, a first sealing layer formed of an inorganic insulating material and covering the display element, a plurality of peripheral partitions arranged in the margin portion, and a second sealing layer formed of an inorganic insulating material and arranged across the panel portion and the margin portion, wherein each of the plurality of peripheral partitions has a first lower portion arranged on the inorganic insulating layer and a first upper portion arranged on the first lower portion, and is covered with the second sealing layer.

[0007] According to one embodiment, a method for manufacturing a display device includes the steps of: A processing substrate is prepared, which includes an inorganic insulating layer that extends over a display area that displays an image and a peripheral area outside the display area, a display element located in the display area, a plurality of peripheral partitions located in the peripheral area, and a first sealing layer that covers the display element and exposes the peripheral partitions.A second sealing layer is formed of an inorganic insulating material that extends over the display area and the peripheral area, and each of the plurality of peripheral partitions has a first lower portion located on the inorganic insulating layer and a first upper portion located on the first lower portion, and is covered with the second sealing layer. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device DSP. [Figure 2] FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line AB in FIG. [Figure 4] FIG. 4 is a plan view showing an example of the motherboard 100. As shown in FIG. [Figure 5] FIG. 5 is a plan view showing an example of the configuration of the region 100A and the region 100B shown in FIG. [Figure 6] FIG. 6 is a cross-sectional view of the peripheral partition wall 7 taken along line CD in FIG. [Figure 7] FIG. 7 is a plan view showing another example of the configuration of the region 100A and the region 100B shown in FIG. [Figure 8] FIG. 8 is a cross-sectional view of the peripheral partition wall 7A and the peripheral partition wall 7B taken along the line EF in FIG. [Figure 9] FIG. 9 is a plan view showing another example of the configuration of the region 100A and the region 100B shown in FIG. [Figure 10] FIG. 10 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 11] FIG. 11 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 12] FIG. 12 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 13] FIG. 13 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 14] FIG. 14 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 15] FIG. 15 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 16] FIG. 16 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 17] FIG. 17 is a diagram for explaining a method of manufacturing the display device DSP. [Figure 18] FIG. 18 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 19] FIG. 19 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 20] FIG. 20 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 21] FIG. 21 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 22] FIG. 22 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 23] FIG. 23 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 24] FIG. 24 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 25] FIG. 25 is a diagram for explaining a manufacturing method of the display device DSP. DETAILED DESCRIPTION OF THE INVENTION

[0009] An embodiment will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0010] In the drawings, mutually perpendicular X, Y, and Z axes are shown as necessary to facilitate understanding. The direction along the X axis is referred to as the first direction X, the direction along the Y axis is referred to as the second direction Y, and the direction along the Z axis is referred to as the third direction Z. Viewing various elements parallel to the third direction Z is referred to as a planar view.

[0011] The display device according to this embodiment is an organic electroluminescence display device having organic light-emitting diodes (OLEDs) as display elements, and can be installed in televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and the like.

[0012] FIG. 1 is a diagram showing an example of the configuration of a display device DSP.

[0013] The display device DSP includes a display panel PNL having a display area DA for displaying an image and a peripheral area SA outside the display area DA, on an insulating substrate 10. The substrate 10 may be made of glass or a flexible resin film.

[0014] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to rectangular, and may be other shapes such as square, circle, or ellipse.

[0015] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes a plurality of subpixels SP. In one example, the pixel PX includes a subpixel SP1 of a first color, a subpixel SP2 of a second color, and a subpixel SP3 of a third color. The first color, second color, and third color are different from each other. Note that the pixel PX may include subpixels SP of another color, such as white, in addition to the subpixels SP1, SP2, and SP3, or instead of any of the subpixels SP1, SP2, and SP3.

[0016] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0017] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element DE.

[0018] The configuration of the pixel circuit 1 is not limited to the example shown in the figure. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0019] The display element DE is an organic light-emitting diode (OLED) as a light-emitting element, and may be called an organic EL element.

[0020] The peripheral area SA has a plurality of terminals TE arranged in one direction. In the illustrated example, the plurality of terminals TE are arranged along a first direction X. Each of the terminals TE extends in a second direction Y, but this is not limiting. Such a plurality of terminals TE are electrically connected to, for example, a flexible printed circuit board or an IC chip.

[0021] FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3.

[0022] In the illustrated example, the subpixels SP2 and SP3 are aligned in the second direction Y. The subpixels SP1 and SP2 are aligned in the first direction X, and the subpixels SP1 and SP3 are aligned in the first direction X.

[0023] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with a column in which the subpixels SP2 and the subpixels SP3 are alternately arranged in the second direction Y, and a column in which multiple subpixels SP1 are arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0024] The layout of the subpixels SP1, SP2, and SP3 is not limited to the example in Fig. 2. As another example, the subpixels SP1, SP2, and SP3 in each pixel PX may be arranged in order in the first direction X.

[0025] In the display area DA, an inorganic insulating layer 5 and partition walls 6 are arranged. The inorganic insulating layer 5 has openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. The inorganic insulating layer 5 having these openings AP1, AP2, and AP3 may be referred to as a rib.

[0026] The partition wall 6 overlaps with the inorganic insulating layer 5 in a plan view. The partition wall 6 is formed in a lattice shape surrounding the openings AP1, AP2, and AP3. It can also be said that the partition wall 6 has openings in the subpixels SP1, SP2, and SP3, similar to the inorganic insulating layer 5. The partition wall 6 is conductive and electrically connected to the terminal TE of the common potential among the multiple terminals TE shown in FIG. 1 .

[0027] The subpixels SP1, SP2, and SP3 include display elements DE1, DE2, and DE3, respectively, as the display element DE.

[0028] The display element DE1 of the subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, each overlapping with the aperture AP1. The peripheral portion of the lower electrode LE1 is covered with an inorganic insulating layer 5. The lower electrode LE1, the organic layer OR1, and the upper electrode UE1 that constitute the display element DE1 are surrounded by a partition wall 6 in a planar view. The peripheral portions of the organic layer OR1 and the upper electrode UE1 overlap with the inorganic insulating layer 5 in a planar view. The organic layer OR1 includes a light-emitting layer that emits light in, for example, a blue wavelength region.

[0029] The display element DE2 of the subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, each of which overlaps with the opening AP2. The peripheral portion of the lower electrode LE2 is covered with an inorganic insulating layer 5. The lower electrode LE2, the organic layer OR2, and the upper electrode UE2 that constitute the display element DE2 are surrounded by a partition wall 6 in a planar view. The peripheral portions of the organic layer OR2 and the upper electrode UE2 each overlap with the inorganic insulating layer 5 in a planar view. The organic layer OR2 includes a light-emitting layer that emits light in, for example, a green wavelength region.

[0030] The display element DE3 of the subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, each overlapping with the opening AP3. The periphery of the lower electrode LE3 is covered with an inorganic insulating layer 5. The lower electrode LE3, the organic layer OR3, and the upper electrode UE3 that constitute the display element DE3 are surrounded by a partition wall 6 in a planar view. The peripheries of the organic layer OR3 and the upper electrode UE3 overlap with the inorganic insulating layer 5 in a planar view. The organic layer OR3 includes a light-emitting layer that emits light in the red wavelength range, for example.

[0031] In the illustrated example, the outlines of the lower electrodes LE1, LE2, and LE3 are indicated by dotted lines, and the outlines of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are indicated by dashed lines. Note that the outlines of the illustrated lower electrodes, organic layers, and upper electrodes do not necessarily reflect their exact shapes.

[0032] The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anodes of the display elements, and the upper electrodes UE1, UE2, and UE3 correspond to the cathodes of the display elements or common electrodes, and are in contact with the partition walls 6.

[0033] The lower electrode LE1 is electrically connected to the pixel circuit 1 of the subpixel SP1 (see FIG. 1). The lower electrode LE2 is electrically connected to the pixel circuit 1 of the subpixel SP2. The lower electrode LE3 is electrically connected to the pixel circuit 1 of the subpixel SP3.

[0034] In the illustrated example, the areas of openings AP1, AP2, and AP3 are different from one another. The area of ​​opening AP1 is larger than the area of ​​opening AP2, and the area of ​​opening AP2 is larger than the area of ​​opening AP3. In other words, the area of ​​the lower electrode LE1 exposed through opening AP1 is larger than the area of ​​the lower electrode LE2 exposed through opening AP2, and the area of ​​the lower electrode LE2 exposed through opening AP2 is larger than the area of ​​the lower electrode LE3 exposed through opening AP3.

[0035] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line AB in FIG.

[0036] The circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes various circuits such as the pixel circuit 1 shown in FIG. 1 and various wirings such as the scanning line GL, the signal line SL, and the power supply line PL. The circuit layer 11 is covered with an insulating layer 12. The insulating layer 12 is an organic insulating layer that flattens unevenness caused by the circuit layer 11.

[0037] The lower electrodes LE1, LE2, and LE3 are disposed on the insulating layer 12 and spaced apart from one another. The inorganic insulating layer 5 is disposed on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. An opening AP1 in the inorganic insulating layer 5 overlaps the lower electrode LE1, an opening AP2 overlaps the lower electrode LE2, and an opening AP3 overlaps the lower electrode LE3. The peripheries of the lower electrodes LE1, LE2, and LE3 are covered with the inorganic insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively, through contact holes provided in the insulating layer 12. Note that the contact holes in the insulating layer 12 are omitted from FIG. 3 .

[0038] The partition wall 6 has a conductive lower portion 61 disposed on the inorganic insulating layer 5 and an upper portion 62 disposed on the lower portion 61 .

[0039] In the illustrated example, the lower part 61 has a bottom layer 63 disposed on the inorganic insulating layer 5 and an axial layer 64 disposed between the bottom layer 63 and the upper part 62. The bottom layer 63 is thinner than the axial layer 64. The bottom layer 63 has a width greater than that of the axial layer 64. Both ends of the bottom layer 63 protrude from the side surfaces of the axial layer 64. The upper part 62 has a thin film 65 disposed on the axial layer 64 and a thin film 66 disposed on the thin film 65. The upper part 62 has a width greater than that of the axial layer 64. Both ends of the upper part 62 protrude from the side surfaces of the axial layer 64. In this specification, the side surfaces of the axial layer 64 refer to the surfaces of the axial layer 64 that extend between the bottom layer 63 and the upper part 62. In the illustrated example, the upper portion 62 has a width greater than that of the bottom layer 63. The bottom layer 63 may have a width greater than that of the upper portion 62.

[0040] The organic layer OR1 is in contact with the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed from the opening AP1, and has its peripheral edge located on the inorganic insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and is in contact with the lower part 61.

[0041] The organic layer OR2 is in contact with the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed from the opening AP2, and has its peripheral edge located on the inorganic insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and is in contact with the lower part 61.

[0042] The organic layer OR3 is in contact with the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed from the opening AP3, and has its peripheral edge located on the inorganic insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and is in contact with the lower part 61.

[0043] Note that contact between each of the upper electrodes UE1, UE2, UE3 and the lower portion 61 includes a case where each of the upper electrodes UE1, UE2, UE3 is in direct contact with the upper surface of the bottom layer 63, and a case where each of the upper electrodes UE1, UE2, UE3 is in direct contact with the upper surface of the bottom layer 63 and also in direct contact with the side surface of the axial layer 64. In this specification, the upper surface of the bottom layer 63 includes the surface of the bottom layer 63 that is in direct contact with the axial layer 64 and the surface that protrudes from the axial layer 64 and faces the upper portion 62.

[0044] In the illustrated example, subpixel SP1 has a cap layer CP1 and a sealing layer SE1, subpixel SP2 has a cap layer CP2 and a sealing layer SE2, and subpixel SP3 has a cap layer CP3 and a sealing layer SE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively. Note that the cap layers CP1, CP2, and CP3 may be omitted.

[0045] The cap layer CP1 is disposed on the upper electrode UE1. The cap layer CP2 is disposed on the upper electrode UE2. The cap layer CP3 is disposed on the upper electrode UE3.

[0046] The sealing layer SE1 is disposed on the cap layer CP1, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP1. That is, the sealing layer SE1 is in contact with the axis layer 64 and the upper portion 62 of the partition wall 6 that surrounds the display element DE1. The sealing layer SE2 is disposed on the cap layer CP2, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP2. That is, the sealing layer SE2 is in contact with the axis layer 64 and the upper portion 62 of the partition wall 6 that surrounds the display element DE2. The sealing layer SE3 is disposed on the cap layer CP3, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP3. That is, the sealing layer SE3 is in contact with the axis layer 64 and the upper portion 62 of the partition wall 6 that surrounds the display element DE3.

[0047] In the following description, the multilayer structure including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as the laminate film FL1, the multilayer structure including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as the laminate film FL2, and the multilayer structure including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as the laminate film FL3.

[0048] In the illustrated example, a part of the laminated film FL1 is located on the partition wall 6 around the subpixel SP1, and is spaced apart from the laminated film FL1 (the part that constitutes the display element DE1) located in the aperture AP1. Similarly, a part of the laminated film FL2 is located on the partition wall 6 around the subpixel SP2, and is spaced apart from the laminated film FL2 (the part that constitutes the display element DE2) located in the aperture AP2. Similarly, a part of the laminated film FL3 is located on the partition wall 6 around the subpixel SP3, and is spaced apart from the laminated film FL3 (the part that constitutes the display element DE3) located in the aperture AP3. The stacked films FL1, FL2, and FL3 on the partition wall 6 may be omitted. In this case, a cavity is formed between the partition wall 6 and the sealing layers SE1, SE2, and SE3.

[0049] Ends of the sealing layers SE1, SE2, and SE3 are each located on the partition wall 6. In the example shown, the stacked film FL1 and the sealing layer SE1 on the partition wall 6 between the subpixels SP1 and SP2 are spaced apart from the stacked film FL2 and the sealing layer SE2 on the partition wall 6. In addition, the stacked film FL1 and the sealing layer SE1 on the partition wall 6 between the subpixels SP1 and SP3 are spaced apart from the stacked film FL3 and the sealing layer SE3 on the partition wall 6.

[0050] The partition wall 6 and the sealing layers SE1, SE2, and SE3 are covered with a resin layer 13. If cavities are formed between the sealing layers SE1, SE2, and SE3 and the partition wall 6, the resin layer 13 fills these cavities. The resin layer 13 is covered with a sealing layer 14. The wiring TL is disposed on the sealing layer 14 and is located, for example, directly above the partition wall 6. Such wiring TL functions, for example, as sensor wiring for detecting an object approaching the display device DSP. The sealing layer 14 and the wiring TL are covered with a resin layer 15.

[0051] The inorganic insulating layer 5, the sealing layers SE1, SE2, SE3, and the sealing layer 14 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0052] The lower portion 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The bottom layer 63 is formed of a titanium-based material such as titanium or a titanium compound. The shaft layer 64 is formed of a material different from the bottom layer 63 and the upper portion 62, and is formed of an aluminum-based material such as aluminum or an aluminum compound.

[0053] The upper portion 62 of the partition wall 6 is formed of, for example, a conductive material, but may also be formed of an insulating material. The upper portion 62 is formed of a material different from that of the lower portion 61. The thin film 65 is formed of, for example, a titanium-based material such as titanium or a titanium compound. The thin film 66 is formed of, for example, an oxide conductive material such as indium tin oxide (ITO).

[0054] The lower electrodes LE1, LE2, and LE3 are multilayer structures including a transparent layer made of an oxide conductive material such as indium tin oxide (ITO) and a reflective layer made of a metal material such as silver. In one example, the lower electrodes LE1, LE2, and LE3 are multilayer structures including a reflective layer between a pair of transparent layers.

[0055] The organic layer OR1 includes an emitting layer EM1. The organic layer OR2 includes an emitting layer EM2. The organic layer OR3 includes an emitting layer EM3. The emitting layers EM1, EM2, and EM3 are formed of different materials. In one example, the emitting layer EM1 is formed of a material that emits light in the blue wavelength range, the emitting layer EM2 is formed of a material that emits light in the green wavelength range, and the emitting layer EM3 is formed of a material that emits light in the red wavelength range. Each of the organic layers OR1, OR2, and OR3 includes a plurality of functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0056] The upper electrodes UE1, UE2, and UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg).

[0057] The cap layers CP1, CP2, and CP3 are multilayer structures made up of multiple thin films, all of which are transparent and have different refractive indices.

[0058] The wiring TL is formed of a metal material such as aluminum, titanium, molybdenum, etc. In one example, the wiring TL is a multilayer body including an aluminum layer between a pair of titanium layers.

[0059] The illustrated circuit layer 11, insulating layer 12, and inorganic insulating layer 5 are disposed across the display area DA and the peripheral area SA.

[0060] Next, a mother substrate 100 for a display device (hereinafter simply referred to as a mother substrate) for collectively manufacturing a plurality of display device DSPs will be described.

[0061] FIG. 4 is a plan view showing an example of the motherboard 100. As shown in FIG.

[0062] The mother substrate 100 comprises a plurality of panel portions PP and blank portions MP outside the panel portions PP on a large substrate 10. The large substrate 10 is formed, for example, in a rectangular shape. Each of the plurality of panel portions PP is extracted by cutting the mother substrate 100 along a cutting line.

[0063] Each of the extracted panel portions PP corresponds to the display panel PNL shown in Fig. 1 and includes a display area DA and a peripheral area SA. The peripheral area SA has a terminal area TA in which the plurality of terminals TE shown in Fig. 1 are arranged. Each of the plurality of wirings TL is arranged in the display area DA, drawn out to the peripheral area SA, and electrically connected to the terminals TE included in the terminal area TA.

[0064] In the drawing, an area 100A is a part of the surrounding area SA, and an area 100B is a part of the blank space MP.

[0065] FIG. 5 is a plan view showing an example of the configuration of the region 100A and the region 100B shown in FIG.

[0066] A plurality of peripheral partition walls 7 are arranged in the region 100A and the region 100B. Each of the plurality of peripheral partition walls 7 is formed in a lattice pattern in a plan view. In one example, the peripheral partition walls 7 are formed in the same pattern as the lattice-shaped partition walls 6 shown in FIG. 2. The plurality of peripheral partition walls 7 are aligned in the first direction X and the second direction Y and spaced apart from one another. The plurality of peripheral partition walls 7 are covered with a sealing layer 14. Note that the planar shape of the peripheral partition walls 7 is not limited to the lattice shape as shown in the figure, and may be linear, L-shaped, arc-shaped, or the like.

[0067] FIG. 6 is a cross-sectional view of the peripheral partition wall 7 taken along line CD in FIG.

[0068] The peripheral partition wall 7 has a lower portion 71 disposed on the inorganic insulating layer 5 and an upper portion 72 disposed on the lower portion 71. The lower portion 71 has a bottom layer 73 disposed on the inorganic insulating layer 5 and an axial layer 74 disposed between the bottom layer 73 and the upper portion 72. The upper portion 72 has a thin film 75 disposed on the axial layer and a thin film 76 disposed on the thin film 75.

[0069] The bottom layer 73 is thinner than the shaft layer 74. The bottom layer 73 has a width greater than the shaft layer 74. Both ends of the bottom layer 73 protrude from the side surfaces of the shaft layer 74. The upper part 72 has a width greater than the shaft layer 74. Both ends of the upper part 72 protrude from the side surfaces of the shaft layer 74. In the illustrated example, the upper part 72 has a width greater than the bottom layer 73, but the bottom layer 73 may also have a width greater than the upper part 72.

[0070] The peripheral partition wall 7 can be formed in the same process as the partition wall 6. In this case, the bottom layer 73 is formed of the same material as the bottom layer 63, the axial layer 74 is formed of the same material as the axial layer 64, the thin film 75 is formed of the same material as the thin film 65, and the thin film 76 is formed of the same material as the thin film 66.

[0071] The sealing layer 14 is in contact with the bottom layer 73, the shaft layer 74, and the upper portion 72. In this way, the sealing layer 14 covers the peripheral partition wall 7, and thereby unevenness caused by the cross-sectional shape of the peripheral partition wall 7 is reduced compared to before the sealing layer 14 is formed.

[0072] The resin layer 13 and the resin layer 15 shown in FIG. 3 are disposed in the display area DA, but do not overlap the peripheral partition wall 7.

[0073] FIG. 7 is a plan view showing another example of the configuration of the region 100A and the region 100B shown in FIG.

[0074] The configuration example shown in FIG. 7 differs from the configuration example shown in FIG. 5 in that the sealing layer 14 is segmented. In the illustrated example, each segment of the sealing layer 14 is formed to cover four peripheral partition walls 7. A gap of, for example, about 5 to 10 μm is formed between adjacent sealing layers 14. The peripheral partition wall 7A and the peripheral partition wall 7B in the drawing are spaced apart from each other and aligned in the first direction X. The portion of the sealing layer 14 that covers the peripheral partition wall 7A is spaced apart from the portion that covers the peripheral partition wall 7B.

[0075] FIG. 8 is a cross-sectional view of the peripheral partition wall 7A and the peripheral partition wall 7B taken along the line EF in FIG.

[0076] The sealing layer 14 is in contact with the bottom layer 73, the shaft layer 74, and the upper portion 72 of the peripheral partition wall 7A. The sealing layer 14 is also in contact with the bottom layer 73, the shaft layer 74, and the upper portion 72 of the peripheral partition wall 7B. The sealing layer 14 has a missing portion between the portion covering the peripheral partition wall 7A and the portion covering the peripheral partition wall 7B. Therefore, the inorganic insulating layer 5 is exposed from the sealing layer 14 between the peripheral partition wall 7A and the peripheral partition wall 7B.

[0077] As in the configuration examples shown in Figures 7 and 8, by dividing the sealing layer 14 into smaller pieces, the stress acting on the sealing layer 14 is alleviated, and separation of the sealing layer 14 from the inorganic insulating layer 5 can be suppressed.

[0078] FIG. 9 is a plan view showing another example of the configuration of the region 100A and the region 100B shown in FIG.

[0079] The configuration example shown in Fig. 9 differs from the configuration example shown in Fig. 7 in that the sealing layer 14 is further divided into smaller parts. In the illustrated example, each of the divided parts of the sealing layer 14 is formed so as to cover one peripheral partition wall 7. In the sealing layer 14, the parts that cover the peripheral partition wall 7 are spaced apart from each other. Between adjacent parts of the sealing layer 14, the inorganic insulating layer 5 is exposed from the sealing layer 14, as shown in Fig. 8.

[0080] Next, a manufacturing method of the display device DSP will be described. Note that in each drawing for explaining the manufacturing method, illustration of the part below the insulating layer 12 is omitted. In Figures 10 to 17 referred to in the following description, the cross section corresponding to the display area DA on the left side corresponds to the cross section along line AB in Figure 2, and the cross section corresponding to the peripheral area SA and margin part MP on the right side corresponds to the cross section along line EF in Figure 7.

[0081] 10, a process substrate SUB is prepared which includes lower electrodes LE1, LE2, and LE3, an inorganic insulating layer 5, a partition wall 6, and a peripheral partition wall 7. The process of preparing the process substrate SUB includes the following steps.

[0082] That is, the circuit layer 11 and the insulating layer 12 are formed across the display area DA, the peripheral area SA, and the marginal area MP on the substrate 10. Then, in the display area DA, the lower electrode LE1 of the subpixel SP1, the lower electrode LE2 of the subpixel SP2, and the lower electrode LE3 of the subpixel SP3 are formed on the insulating layer 12.

[0083] Thereafter, an inorganic insulating layer 5 is formed over the display area DA, the peripheral area SA, and the marginal area MP. The inorganic insulating layer 5 covers the periphery of each of the lower electrodes LE1, LE2, and LE3, and has openings AP1, AP2, and AP3 that overlap the lower electrodes LE1, LE2, and LE3, respectively. The inorganic insulating layer 5 is formed of, for example, silicon oxynitride.

[0084] Thereafter, a partition wall 6 is formed, which has a lower portion 61 located on the inorganic insulating layer 5 and an upper portion 62 located on the lower portion 61. Simultaneously with the formation of the partition wall 6, a peripheral partition wall 7 is formed, which has a lower portion 71 located on the inorganic insulating layer 5 and an upper portion 72 located on the lower portion 71. The bottom layer 63 and upper portion 62 of the lower portion 61 protrude from the side surface of the shaft layer 64 of the lower portion 61. Similarly, the bottom layer 73 and upper portion 72 of the lower portion 71 protrude from the side surface of the shaft layer 74 of the lower portion 71. The bottom layers 63 and 73 are formed of a titanium-based material, and the shaft layers 64 and 74 are formed of an aluminum-based material.

[0085] The step of forming the openings AP1, AP2, and AP3 in the inorganic insulating layer 5 may be performed before or after the partition walls 6 and peripheral partition walls 7 are formed.

[0086] Next, the display element DE1 is formed.

[0087] First, as shown in FIG. 11, a laminated film FL1 including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 is formed. The process of forming the laminated film FL1 includes the steps of forming the organic layer OR1 on the lower electrode LE1 in the opening AP1, forming the upper electrode UE1 covering the organic layer OR1 and in contact with the lower portion 61 of the partition wall 6, and forming the cap layer CP1 on the upper electrode UE1. The process of forming the organic layer OR1 includes the steps of forming a hole injection layer, a hole transport layer, an electron blocking layer, an emitting layer EM1, a hole blocking layer, an electron transport layer, an electron injection layer, etc. The upper electrode UE1 is formed from a mixture of magnesium and silver.

[0088] The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are each formed by vapor deposition using the partition wall 6 as a mask. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are successively formed while maintaining a vacuum environment.

[0089] The laminated film FL1 is formed on the lower electrodes LE2 and LE3 in the display area DA, and is also formed in the peripheral area SA and marginal portion MP. Such laminated film FL1 is divided into multiple parts by overhanging partition walls 6 and peripheral partition walls 7. In particular, in the peripheral area SA and marginal portion MP, the laminated film FL1 is divided by the peripheral partition walls 7, thereby dividing the laminated film FL1 into smaller parts. This reduces the stress acting on the laminated film FL1 during the manufacturing process, and makes it possible to prevent the laminated film FL1 from separating from the inorganic insulating layer 5.

[0090] Thereafter, an inorganic insulating material is deposited to form a sealing layer SE1 on the laminated film FL1. The sealing layer SE1 is formed over the display area DA, the peripheral area SA, and the marginal portion MP by CVD (Chemical Vapor Deposition). The sealing layer SE1 continuously covers each divided portion of the laminated film FL1, the partition walls 6, and the peripheral partition walls 7. The sealing layer SE1 is formed of, for example, silicon nitride.

[0091] 12, a resist RS patterned into a predetermined shape is formed on the sealing layer SE1 in the display area DA. The resist RS overlaps the subpixel SP1 and part of the partition wall 6 around it. The resist RS is not disposed in the peripheral area SA or the marginal portion MP.

[0092] Next, as shown in FIG. 13, etching is performed using the resist RS as a mask to pattern the stacked film FL1 and the sealing layer SE1. That is, dry etching is performed using the resist RS as a mask to remove the sealing layer SE1 exposed from the resist RS. Then, the stacked film FL1 exposed from the resist RS is removed. At this time, in the stacked film FL1, the cap layer CP1, the upper electrode UE1, and the organic layer OR1 are removed in this order. As a result, the stacked film FL1 covered with the resist RS remains in the subpixel SP1. In addition, a part of the upper part 62 of the partition 6 is exposed, and the lower electrode LE2 and the lower electrode LE3 are also exposed. Furthermore, in the peripheral region SA and the margin MP, the peripheral partition 7 is exposed. Thereafter, the resist RS is removed, thereby forming the display element DE1 in the subpixel SP1.

[0093] In the process of removing the sealing layer SE1 and the stacked film FL1 and then removing the resist RS, the stacked film FL1 located on the upper portion 62 of the partition wall 6 may be removed. In this case, a cavity is formed between the upper portion 62 and the sealing layer SE1.

[0094] Next, as shown in FIG. 14, a display element DE2 is formed. The procedure for forming the display element DE2 is the same as that for forming the display element DE1. That is, an organic layer OR2 including an emitting layer EM2, an upper electrode UE2, and a cap layer CP2 are formed in this order on the lower electrode LE2 to form a stacked film FL2. Then, a sealing layer SE2 is formed on the stacked film FL2. Then, a resist is formed on the sealing layer SE2, and the sealing layer SE2, the cap layer CP2, the upper electrode UE2, and the organic layer OR2 are patterned by etching using this resist as a mask. After this patterning, the resist is removed. As a result, a display element DE2 is formed in the subpixel SP2, and the lower electrode LE3 of the subpixel SP3 is exposed.

[0095] It should be noted that, in the process of removing the sealing layer SE2 and the stacked film FL2 and then removing the resist, the stacked film FL2 located on the upper portion 62 of the partition wall 6 may be removed. In this case, a cavity is formed between the upper portion 62 and the sealing layer SE2.

[0096] The laminated film FL2 does not remain on the peripheral partition wall 7, and the peripheral partition wall 7 is not covered with the sealing layer SE2.

[0097] Next, as shown in FIG. 15, a display element DE3 is formed. The procedure for forming the display element DE3 is the same as that for forming the display element DE1. That is, an organic layer OR3 including an emitting layer EM3, an upper electrode UE3, and a cap layer CP3 are formed in this order on the lower electrode LE3 to form a stacked film FL3. Then, a sealing layer SE3 is formed on the stacked film FL3. Then, a resist is formed on the sealing layer SE3, and the sealing layer SE3, the cap layer CP3, the upper electrode UE3, and the organic layer OR3 are patterned by etching using this resist as a mask. After this patterning, the resist is removed. This forms a display element DE3 in the subpixel SP3.

[0098] It should be noted that, in the process of removing the sealing layer SE3 and the stacked film FL3 and then removing the resist, the stacked film FL3 located on the upper portion 62 of the partition wall 6 may be removed. In this case, a cavity is formed between the upper portion 62 and the sealing layer SE3.

[0099] The laminated film FL3 does not remain on the peripheral partition wall 7, and the peripheral partition wall 7 is not covered with the sealing layer SE3.

[0100] In the above manufacturing process, it is assumed that display element DE1 is formed first, then display element DE2 is formed, and finally display element DE3 is formed, but the order in which display elements DE1, DE2, and DE3 are formed is not limited to this example.

[0101] Next, as shown in FIG. 16, a resin layer 13 is formed in the display area DA, located on the sealing layers SE1, SE2, and SE3. The display area DA is surrounded by protruding bodies, which will not be described in detail. The resin layer 13 is applied to the inside of the protruding bodies. Therefore, the resin layer 13 is not disposed in the peripheral area SA or marginal portion MP, and does not overlap the peripheral partition wall 7.

[0102] Next, as shown in FIG. 17, an inorganic insulating material is deposited to form the sealing layer 14. The sealing layer 14 is formed by CVD across the display area DA, the peripheral area SA, and the margin area MP. The sealing layer 14 is disposed on the resin layer 13 in the display area DA, and continuously covers the peripheral partition wall 7 in the peripheral area SA and the margin area MP. In other words, the bottom layer 73 of the lower portion 71, the axis layer 74, and the upper portion 72 are directly covered by the sealing layer 14. The sealing layer 14 is formed of, for example, silicon nitride.

[0103] Subsequently, the inorganic insulating layer 5 and the sealing layer 14 are patterned. FIG. 18 is a cross-sectional view showing the terminal area TA. Here, the terminal area TA, which is part of the peripheral area SA, is shown. The marginal area MP has a terminal area where the inspection terminals are arranged, although this will not be described in detail. The terminal area of ​​the marginal area MP also has a cross section similar to that shown in FIG.

[0104] As shown on the left side of Fig. 18, the terminal TE is formed in the process of forming the circuit layer 11. The insulating layer 12 covers the peripheral edge of the terminal TE. The inorganic insulating layer 5 covers the insulating layer 12 in the terminal region TA and also covers the terminal TE. As described with reference to Fig. 17, the sealing layer 14 is also formed in the peripheral region SA and covers the inorganic insulating layer 5 in the terminal region TA.

[0105] Thereafter, as shown on the right side of FIG. 18, the inorganic insulating layer 5 and the sealing layer 14 are patterned, and in the terminal region TA, through-holes TH are formed that penetrate the inorganic insulating layer 5 and the sealing layer 14, exposing the terminals TE.

[0106] Subsequently, as shown in FIG. 19, the sealing layer 14 is patterned. In the peripheral region SA and the marginal portion MP, the sealing layer 14 covering the peripheral partition wall 7 is divided into smaller parts. In the terminal region TA, the sealing layer 14 around the terminals TE is removed, and the step at the through hole TH is reduced.

[0107] Next, as shown in FIG. 20, the conductive layer 20 is formed. The conductive layer 20 is a multilayer body in which, for example, a titanium layer, an aluminum layer, and another titanium layer are laminated in this order. In the peripheral area SA and the marginal portion MP, the conductive layer 20 is disposed on the sealing layer 14 and also on the inorganic insulating layer 5. In the terminal area TA, the conductive layer 20 is disposed on the inorganic insulating layer 5 and also on the terminals TE in the through holes TH. In the display area DA, the conductive layer 20 is disposed on the sealing layer 14.

[0108] 21, a resist RS1 is applied onto the conductive layer 20. At this time, in the peripheral region SA and the marginal portion MP, the sealing layer 14 reduces the unevenness of the peripheral partition wall 7 in the vicinity of the peripheral partition wall 7, thereby suppressing the formation of undesired gaps between the resist RS1 and the peripheral partition wall 7. In addition, the surface of the resist RS1 can be flattened. Therefore, the formation of locally thick regions and regions in the shadow of the peripheral partition wall 7 in the resist RS1 is suppressed. Such a resist RS1 is, for example, a positive type that becomes soluble in a developer when irradiated with light.

[0109] 22, the resist RS1 is patterned. By this patterning, the resist RS1 is formed so as to overlap the terminals TE in the terminal region TA, and also so as to overlap the partition walls 6 in the display region DA. In the peripheral region SA and the margin portion MP, almost the entire area of ​​the resist RS1 is exposed, so no residue of the resist RS1 is left.

[0110] 23, the conductive layer 20 is patterned using the resist RS1 as a mask. In the peripheral area SA and the marginal portion MP, the resist RS1 has been removed, so no residue of the conductive layer 20 remains. In the terminal area TA and the display area DA, the conductive layer 20 exposed from the resist RS1 is removed.

[0111] Subsequently, the resist RS1 is removed as shown in Fig. 24. As a result, the wiring TL is formed from the display area DA to the terminal area TA, and in the terminal area TA, the wiring TL is connected to the terminal TE.

[0112] 25, a resin layer 15 is formed in the display area DA, on the sealing layer 14 and the wiring TL. Although not described in detail, the resin layer 15 is applied to the inside of the protrusions surrounding the display area DA. Therefore, the resin layer 15 is not disposed in the terminal area TA, the peripheral area SA, or the margin MP, and does not overlap the peripheral partition wall 7.

[0113] As described above, since the peripheral partition wall 7 is covered with the sealing layer 14, the peripheral partition wall 7 is protected by the sealing layer 14 when the conductive layer 20 is patterned in the process of forming the wiring TL. This prevents the peripheral partition wall 7 from being undesirably scraped off. In addition, the generation of conductive particles caused by the detachment of a portion of the peripheral partition wall 7 is prevented.

[0114] Furthermore, when patterning the conductive layer 20, the formation of voids between the resist RS1 and the peripheral partition wall 7 and the local thickening of the resist RS1 are suppressed. This suppresses the generation of undesired residues of the resist RS1 around the peripheral partition wall 7. This suppresses the generation of undesired residues of the conductive layer 20.

[0115] Although the resist RS1 applied in patterning the conductive layer 20 has been described in particular here, the formation of voids and local thickening of the resist are also suppressed when applying the resists applied in patterning the inorganic insulating layer 5 and the sealing layer 14 described with reference to Fig. 18 and patterning the sealing layer 14 described with reference to Fig. 19. This suppresses the generation of undesired resist residues.

[0116] As described above, according to the present embodiment, it is possible to provide a display device, a mother substrate for a display device, and a method for manufacturing a display device that are capable of suppressing a decrease in reliability.

[0117] In the above embodiment, for example, the sealing layers SE1, SE2, and SE3 correspond to the first sealing layer, and the sealing layer 14 corresponds to the second sealing layer. The resin layer 13 corresponds to the first resin layer, and the resin layer 15 corresponds to the second resin layer. In the peripheral partition wall 7, the lower portion 71 corresponds to the first lower portion, the upper portion 72 corresponds to the second upper portion, the bottom layer 73 corresponds to the first bottom layer, and the axial layer 74 corresponds to the first axial layer. The peripheral partition wall 7A corresponds to the first peripheral partition wall, and the peripheral partition wall 7B corresponds to the second peripheral partition wall. In the partition wall 6, the lower portion 61 corresponds to the second lower portion, the upper portion 62 corresponds to the second upper portion, the bottom layer 63 corresponds to the second bottom layer, and the axial layer 64 corresponds to the second axial layer.

[0118] All display devices, motherboards, and display device manufacturing methods that can be implemented by a person skilled in the art by making appropriate design modifications based on the display devices, motherboards, and display device manufacturing methods described above as embodiments of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0119] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of the above-described embodiment, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0120] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0121] DSP...display device 10...substrate 100...motherboard 5...Inorganic insulating layer AP1, AP2, AP3...Openings 6...Partition wall 61...Lower part 62...Upper part 63...Bottom layer 64...Axial layer 7...Peripheral partition 71...Lower part 72...Upper part 73...Bottom layer 74...Axial layer SP1, SP2, SP3...subpixels DE1, DE2, DE3...Display element (organic EL element) LE1, LE2, LE3…lower electrode UE1, UE2, UE3...upper electrode OR1, OR2, OR3…Organic layer CP1, CP2, CP3...cap layer SE1, SE2, SE3...Sealing layer 13...resin layer 14...sealing layer 15...resin layer DA...Display area SA...Peripheral area TA...Terminal area TE...Terminal PP: Panel section MP: Margin section SUB...Processing board TL...Wiring

Claims

1. A substrate; an inorganic insulating layer disposed above the substrate across a display area where an image is displayed and a peripheral area outside the display area; a display element disposed in the display area; a first sealing layer formed of an inorganic insulating material and covering the display element; a plurality of peripheral partition walls disposed in the peripheral region; a second sealing layer formed of an inorganic insulating material and disposed across the display area and the peripheral area; each of the plurality of peripheral partition walls has a first lower portion disposed on the inorganic insulating layer and a first upper portion disposed on the first lower portion, and is covered with the second sealing layer; Display device.

2. The first lower part has a first bottom layer disposed on the inorganic insulating layer and a first axial layer disposed between the first bottom layer and the first upper part, The first bottom layer and the first top layer protrude from a side surface of the first axial layer, the second sealing layer contacts the first bottom layer, the first axial layer, and the first top layer; The display device according to claim 1 .

3. the plurality of peripheral partition walls include a first peripheral partition wall and a second peripheral partition wall spaced apart from the first peripheral partition wall; a portion of the second sealing layer that covers the first peripheral partition wall is spaced apart from a portion that covers the second peripheral partition wall; the inorganic insulating layer is exposed from the second sealing layer between the first peripheral partition wall and the second peripheral partition wall; The display device according to claim 1 .

4. further comprising wiring disposed on the second sealing layer in the display region and drawn out to the peripheral region. The display device according to claim 1 .

5. a first resin layer disposed between the first sealing layer and the second sealing layer in the display region; a second resin layer disposed on the second sealing layer in the display region; the first resin layer and the second resin layer do not overlap the peripheral partition wall; The display device according to claim 1 .

6. Further, a partition wall surrounding the display element is provided, the partition wall has a second lower portion disposed on the inorganic insulating layer and having conductivity, and a second upper portion disposed on the second lower portion, The second lower portion has a second bottom layer disposed on the inorganic insulating layer and formed of the same material as the first bottom layer, and a second axial layer disposed between the second bottom layer and the second upper portion and formed of the same material as the first axial layer, The second bottom layer and the second top layer protrude from a side surface of the second axial layer, the first sealing layer contacts the second axial layer and the second top portion; The display device according to claim 2 .

7. The display element is a lower electrode having a periphery covered with the inorganic insulating layer; an organic layer including a light-emitting layer disposed on the lower electrode; an upper electrode disposed on the organic layer and in contact with the second lower portion; the partition wall surrounds the organic layer and the upper electrode; The display device according to claim 6.

8. further comprising a cap layer disposed between the upper electrode and the first sealing layer. The display device according to claim 7 .

9. a panel unit having a display area for displaying an image and a peripheral area outside the display area; a margin portion outside the panel portion; an inorganic insulating layer disposed across the panel portion and the marginal portion; a display element disposed in the display area; a first sealing layer formed of an inorganic insulating material and covering the display element; a plurality of peripheral partition walls arranged in the marginal portion; a second sealing layer formed of an inorganic insulating material and disposed across the panel portion and the marginal portion; each of the plurality of peripheral partition walls has a first lower portion disposed on the inorganic insulating layer and a first upper portion disposed on the first lower portion, and is covered with the second sealing layer; Motherboard.

10. The first lower part has a first bottom layer disposed on the inorganic insulating layer and a first axial layer disposed between the first bottom layer and the first upper part, The first bottom layer and the first top layer protrude from a side surface of the first axial layer, the second sealing layer contacts the first bottom layer, the first axial layer, and the first top layer; The motherboard according to claim 9 .

11. the plurality of peripheral partition walls include a first peripheral partition wall and a second peripheral partition wall spaced apart from the first peripheral partition wall; the second sealing layer covering the first peripheral partition wall is spaced apart from the second sealing layer covering the second peripheral partition wall; the inorganic insulating layer is exposed from the second sealing layer between the first peripheral partition wall and the second peripheral partition wall; The motherboard according to claim 9 .

12. further comprising wiring disposed on the second sealing layer in the display region and drawn out to the peripheral region. The motherboard according to claim 9 .

13. a first resin layer disposed between the first sealing layer and the second sealing layer in the display region; a second resin layer disposed on the second sealing layer in the display region; the first resin layer and the second resin layer do not overlap the peripheral partition wall; The motherboard according to claim 9 .

14. a processing substrate including: an inorganic insulating layer extending over a display area for displaying an image and a peripheral area outside the display area; a display element located in the display area; a plurality of peripheral partition walls located in the peripheral area; and a first sealing layer covering the display element and exposing the peripheral partition walls; forming a second sealing layer that is made of an inorganic insulating material and that extends across the display area and the peripheral area; each of the plurality of peripheral partition walls has a first lower portion disposed on the inorganic insulating layer and a first upper portion disposed on the first lower portion, and is covered with the second sealing layer; A method for manufacturing a display device.

15. The first lower part has a first bottom layer disposed on the inorganic insulating layer and a first axial layer disposed between the first bottom layer and the first upper part, The first bottom layer and the first top layer protrude from a side surface of the first axial layer, The second sealing layer is formed to contact the first bottom layer, the first axial layer, and the first top layer. The method for manufacturing a display device according to claim 14 .

16. the processing substrate includes terminals in the peripheral region; After forming the second sealing layer, forming a through hole that penetrates the inorganic insulating layer and the second sealing layer and exposes the terminal; patterning the second encapsulation layer; The method for manufacturing a display device according to claim 14 .

17. the plurality of peripheral partition walls include a first peripheral partition wall and a second peripheral partition wall spaced apart from the first peripheral partition wall; the second sealing layer is patterned such that a portion covering the first peripheral partition wall is spaced from a portion covering the second peripheral partition wall, and the inorganic insulating layer is exposed between the first peripheral partition wall and the second peripheral partition wall. The method for manufacturing a display device according to claim 16.

18. Furthermore, after forming the second sealing layer, forming a conductive layer; forming a resist on the conductive layer; removing the conductive layer using the resist as a mask to form wiring located on the second sealing layer in the display region and drawn out to the peripheral region; The method for manufacturing a display device according to claim 14 .

19. Furthermore, before forming the second sealing layer, a first resin layer is formed on the first sealing layer in the display region; After forming the wiring, a second resin layer is formed in the display region, the second resin layer being located on the second sealing layer and the wiring; the first resin layer and the second resin layer do not overlap the peripheral partition wall; The method for manufacturing a display device according to claim 18.

20. The display element is forming a lower electrode located in the display area; the inorganic insulating layer covers a peripheral portion of the lower electrode; forming a laminated film including an organic layer including a light-emitting layer and an upper electrode located on the organic layer on the lower electrode; The first sealing layer is formed by patterning the laminated film. The method for manufacturing a display device according to claim 14 .

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