Display device, mother board, and manufacturing method for display device

Abstract

To suppress the decrease in reliability.SOLUTION: According to an embodiment, a display device includes a substrate, a first inorganic insulating layer disposed over the substrate in a display region to display images and a peripheral region outside the display region, an organic insulating layer disposed on the first inorganic insulating layer, a second inorganic insulating layer disposed on the organic insulating layer, a display element disposed in the display region, a first sealing layer formed of an inorganic insulating material and covering the display element, a plurality of peripheral partition walls disposed in the peripheral region, and a second sealing layer formed of the inorganic insulating material and disposed in the display region and the peripheral region. The inorganic insulating layer includes a first penetration part in the peripheral region. Each of the peripheral partition walls includes a first lower part disposed in the first penetration part and a first upper part disposed on the first lower part, and is covered with the second sealing layer.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a display device, a motherboard, and a method for manufacturing the display device. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put to practical use. These display elements include a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. In addition to the light-emitting layer, the organic layer includes functional layers such as a hole transport layer and an electron transport layer. In the process of manufacturing such display elements, a technique for suppressing deterioration in reliability is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device, a motherboard, and a method for manufacturing a display device that can suppress a decrease in reliability. [Means for solving the problem]

[0005] According to one embodiment, the display device comprises: The display device comprises a substrate, a first inorganic insulating layer arranged above the substrate, spanning a display area for displaying an image and a peripheral area outside the display area, an organic insulating layer arranged on the first inorganic insulating layer, a second inorganic insulating layer arranged on the organic insulating layer, a display element arranged in the display area, a first sealing layer formed of an inorganic insulating material and covering the display element, a plurality of peripheral partitions arranged in the peripheral area, and a second sealing layer formed of an inorganic insulating material and arranged across the display area and the peripheral area, wherein the organic insulating layer has a first penetration portion in the peripheral area, and each of the plurality of peripheral partitions has a first lower portion arranged in the first penetration portion and a first upper portion arranged on the first lower portion, and is covered with the second sealing layer.

[0006] According to one embodiment, the motherboard comprises: The display device comprises a panel portion having a display area for displaying an image and a peripheral area outside the display area, a margin area outside the panel portion, a first inorganic insulating layer arranged across the panel portion and the margin area, an organic insulating layer arranged on the first inorganic insulating layer, a second inorganic insulating layer arranged on the organic insulating layer, a display element arranged in the display area, a first sealing layer formed of an inorganic insulating material and covering the display element, a plurality of peripheral partitions arranged in the margin area, and a second sealing layer formed of an inorganic insulating material and arranged across the panel portion and the margin area, wherein the organic insulating layer has a first penetration portion in the margin area, and each of the plurality of peripheral partitions has a first lower portion arranged in the first penetration portion and a first upper portion arranged on the first lower portion, and is covered with the second sealing layer.

[0007] According to one embodiment, a method for manufacturing a display device includes the steps of: A processing substrate is prepared, the processing substrate comprising: a first inorganic insulating layer extending over a display area for displaying an image and a peripheral area outside the display area; an organic insulating layer positioned on the first inorganic insulating layer; a second inorganic insulating layer positioned on the organic insulating layer; a display element positioned in the display area; a plurality of peripheral partitions positioned in the peripheral area; and a first sealing layer covering the display element and exposing the peripheral partitions; a second sealing layer formed of an inorganic insulating material extending over the display area and the peripheral area; patterning when forming the organic insulating layer includes a step of forming a first penetration portion in the peripheral area; each of the plurality of peripheral partitions having a first lower portion positioned in the first penetration portion and a first upper portion positioned on the first lower portion, and covered with the second sealing layer. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device DSP. [Figure 2] FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line AB in FIG. [Figure 4] FIG. 4 is a plan view showing an example of the shape of the insulating layer 12 in the display device DSP. [Figure 5] FIG. 5 is a plan view showing an example of the shape of the sealing layer 14 in the display device DSP. [Figure 6] FIG. 6 is a plan view showing an example of the motherboard 100. As shown in FIG. [Figure 7] FIG. 7 is a plan view showing an example of the motherboard 100. As shown in FIG. [Figure 8] FIG. 8 is a plan view showing an example of the configuration of the pad PD. [Figure 9] FIG. 9 is a schematic cross-sectional view of the motherboard 100 taken along line GH in FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view of the display panel PNL taken along line CD in FIG. [Figure 11]FIG. 11 is a cross-sectional view showing an example of the configuration of each of the regions 100A of the mother substrate 100 shown in FIG. 9 and the display panel PNL shown in FIG. [Figure 12] FIG. 12 is a cross-sectional view showing another example of the configuration of each of the regions 100A of the mother substrate 100 shown in FIG. 9 and the display panel PNL shown in FIG. [Figure 13] FIG. 13 is a cross-sectional view showing an example of the configuration of another region of the mother substrate 100 shown in FIG. 9 and the display panel PNL shown in FIG. [Figure 14] FIG. 14 is a cross-sectional view showing an example of the configuration of the pad PD taken along the line EF in FIG. [Figure 15] FIG. 15 is a cross-sectional view showing another example of the configuration of the pad PD taken along the line EF in FIG. [Figure 16] FIG. 16 is a plan view showing an example of the configuration of the peripheral partition wall 7 in the through-hole portion 12T. [Figure 17] FIG. 17 is a cross-sectional view showing an example of the configuration of the peripheral partition wall 7A and the peripheral partition wall 7B taken along line IJ in FIG. [Figure 18] FIG. 18 is a cross-sectional view showing another example of the configuration of the peripheral partition wall 7A and the peripheral partition wall 7B taken along the line IJ in FIG. [Figure 19] FIG. 19 is a plan view showing another example of the configuration of the peripheral partition wall 7 in the through-hole portion 12T. [Figure 20] FIG. 20 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 21] FIG. 21 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 22] FIG. 22 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 23] FIG. 23 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 24] FIG. 24 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 25] FIG. 25 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 26]FIG. 26 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 27] FIG. 27 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 28] FIG. 28 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 29] FIG. 29 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 30] FIG. 30 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 31] FIG. 31 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 32] FIG. 32 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 33] FIG. 33 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 34] FIG. 34 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 35] FIG. 35 is a diagram for explaining a manufacturing method of the display device DSP. DETAILED DESCRIPTION OF THE INVENTION

[0009] An embodiment will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0010] In the drawings, mutually perpendicular X, Y, and Z axes are shown as necessary to facilitate understanding. The direction along the X axis is referred to as the first direction X, the direction along the Y axis is referred to as the second direction Y, and the direction along the Z axis is referred to as the third direction Z. Viewing various elements parallel to the third direction Z is referred to as a planar view.

[0011] The display device according to this embodiment is an organic electroluminescence display device having organic light-emitting diodes (OLEDs) as display elements, and can be installed in televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and the like.

[0012] FIG. 1 is a diagram showing an example of the configuration of a display device DSP.

[0013] The display device DSP includes a display panel PNL having a display area DA for displaying an image and a peripheral area SA outside the display area DA, on an insulating substrate 10. The substrate 10 may be made of glass or a flexible resin film.

[0014] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to rectangular, and may be other shapes such as square, circle, or ellipse.

[0015] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes a plurality of subpixels SP. In one example, the pixel PX includes a subpixel SP1 of a first color, a subpixel SP2 of a second color, and a subpixel SP3 of a third color. The first color, second color, and third color are different from each other. Note that the pixel PX may include subpixels SP of another color, such as white, in addition to the subpixels SP1, SP2, and SP3, or instead of any of the subpixels SP1, SP2, and SP3.

[0016] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0017] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element DE.

[0018] The configuration of the pixel circuit 1 is not limited to the example shown in the figure. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0019] The display element DE is an organic light-emitting diode (OLED) as a light-emitting element, and may be called an organic EL element.

[0020] The peripheral area SA has a terminal area TA. The terminal area TA has a plurality of terminals TE and pads PD arranged in one direction. In the illustrated example, the plurality of terminals TE are arranged along a first direction X. Each of the terminals TE extends in a second direction Y, but this is not limited thereto. Such a plurality of terminals TE are electrically connected to, for example, a flexible printed circuit board or an IC chip. The pads PD are electrically connected to, for example, an inspection device. Note that the pads PD may be omitted in the display device DSP.

[0021] FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3.

[0022] In the illustrated example, the subpixels SP2 and SP3 are aligned in the second direction Y. The subpixels SP1 and SP2 are aligned in the first direction X, and the subpixels SP1 and SP3 are aligned in the first direction X.

[0023] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with a column in which the subpixels SP2 and the subpixels SP3 are alternately arranged in the second direction Y, and a column in which multiple subpixels SP1 are arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0024] The layout of the subpixels SP1, SP2, and SP3 is not limited to the example in Fig. 2. As another example, the subpixels SP1, SP2, and SP3 in each pixel PX may be arranged in order in the first direction X.

[0025] In the display area DA, an inorganic insulating layer 5 and partition walls 6 are arranged. The inorganic insulating layer 5 has openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. The inorganic insulating layer 5 having these openings AP1, AP2, and AP3 may be referred to as a rib.

[0026] The partition wall 6 overlaps with the inorganic insulating layer 5 in a plan view. The partition wall 6 is formed in a lattice shape surrounding the openings AP1, AP2, and AP3. It can also be said that the partition wall 6 has openings in the subpixels SP1, SP2, and SP3, similar to the inorganic insulating layer 5. The partition wall 6 is conductive and electrically connected to the terminal TE of the common potential among the multiple terminals TE shown in FIG. 1 .

[0027] The subpixels SP1, SP2, and SP3 include display elements DE1, DE2, and DE3, respectively, as the display element DE.

[0028] The display element DE1 of the subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, each overlapping with the aperture AP1. The peripheral portion of the lower electrode LE1 is covered with an inorganic insulating layer 5. The lower electrode LE1, the organic layer OR1, and the upper electrode UE1 that constitute the display element DE1 are surrounded by a partition wall 6 in a planar view. The peripheral portions of the organic layer OR1 and the upper electrode UE1 overlap with the inorganic insulating layer 5 in a planar view. The organic layer OR1 includes a light-emitting layer that emits light in, for example, a blue wavelength region.

[0029] The display element DE2 of the subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, each of which overlaps with the opening AP2. The peripheral portion of the lower electrode LE2 is covered with an inorganic insulating layer 5. The lower electrode LE2, the organic layer OR2, and the upper electrode UE2 that constitute the display element DE2 are surrounded by a partition wall 6 in a planar view. The peripheral portions of the organic layer OR2 and the upper electrode UE2 each overlap with the inorganic insulating layer 5 in a planar view. The organic layer OR2 includes a light-emitting layer that emits light in, for example, a green wavelength region.

[0030] The display element DE3 of the subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, each overlapping with the opening AP3. The periphery of the lower electrode LE3 is covered with an inorganic insulating layer 5. The lower electrode LE3, the organic layer OR3, and the upper electrode UE3 that constitute the display element DE3 are surrounded by a partition wall 6 in a planar view. The peripheries of the organic layer OR3 and the upper electrode UE3 overlap with the inorganic insulating layer 5 in a planar view. The organic layer OR3 includes a light-emitting layer that emits light in the red wavelength range, for example.

[0031] In the illustrated example, the outlines of the lower electrodes LE1, LE2, and LE3 are indicated by dotted lines, and the outlines of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are indicated by dashed lines. Note that the outlines of the illustrated lower electrodes, organic layers, and upper electrodes do not necessarily reflect their exact shapes.

[0032] The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anodes of the display elements, and the upper electrodes UE1, UE2, and UE3 correspond to the cathodes of the display elements or common electrodes, and are in contact with the partition walls 6.

[0033] The lower electrode LE1 is electrically connected to the pixel circuit 1 of the subpixel SP1 (see FIG. 1). The lower electrode LE2 is electrically connected to the pixel circuit 1 of the subpixel SP2. The lower electrode LE3 is electrically connected to the pixel circuit 1 of the subpixel SP3.

[0034] In the illustrated example, the areas of openings AP1, AP2, and AP3 are different from one another. The area of ​​opening AP1 is larger than the area of ​​opening AP2, and the area of ​​opening AP2 is larger than the area of ​​opening AP3. In other words, the area of ​​the lower electrode LE1 exposed through opening AP1 is larger than the area of ​​the lower electrode LE2 exposed through opening AP2, and the area of ​​the lower electrode LE2 exposed through opening AP2 is larger than the area of ​​the lower electrode LE3 exposed through opening AP3.

[0035] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line AB in FIG.

[0036] The circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes various circuits such as the pixel circuit 1 shown in FIG. 1 and various wirings such as the scanning line GL, the signal line SL, and the power supply line PL. The inorganic insulating layer 111 included in the circuit layer 11 is covered with the insulating layer 12. The insulating layer 12 is an organic insulating layer that flattens out any irregularities caused by the circuit layer 11.

[0037] The lower electrodes LE1, LE2, and LE3 are disposed on the insulating layer 12 and spaced apart from one another. The inorganic insulating layer 5 is disposed on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. An opening AP1 in the inorganic insulating layer 5 overlaps the lower electrode LE1, an opening AP2 overlaps the lower electrode LE2, and an opening AP3 overlaps the lower electrode LE3. The peripheries of the lower electrodes LE1, LE2, and LE3 are covered with the inorganic insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively, through contact holes provided in the insulating layer 12. Note that the contact holes in the insulating layer 12 are omitted from FIG. 3 .

[0038] The partition wall 6 has a conductive lower portion 61 disposed on the inorganic insulating layer 5 and an upper portion 62 disposed on the lower portion 61 .

[0039] In the illustrated example, the lower part 61 has a bottom layer 63 disposed on the inorganic insulating layer 5 and an axial layer 64 disposed between the bottom layer 63 and the upper part 62. The bottom layer 63 is thinner than the axial layer 64. The bottom layer 63 has a width greater than that of the axial layer 64. Both ends of the bottom layer 63 protrude from the side surfaces of the axial layer 64. The upper part 62 has a thin film 65 disposed on the axial layer 64 and a thin film 66 disposed on the thin film 65. The upper part 62 has a width greater than that of the axial layer 64. Both ends of the upper part 62 protrude from the side surfaces of the axial layer 64. In this specification, the side surfaces of the axial layer 64 refer to the surfaces of the axial layer 64 that extend between the bottom layer 63 and the upper part 62. In the illustrated example, the upper portion 62 has a width greater than that of the bottom layer 63. The bottom layer 63 may have a width greater than that of the upper portion 62.

[0040] The organic layer OR1 is in contact with the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed from the opening AP1, and has its peripheral edge located on the inorganic insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and is in contact with the lower part 61.

[0041] The organic layer OR2 is in contact with the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed from the opening AP2, and has its peripheral edge located on the inorganic insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and is in contact with the lower part 61.

[0042] The organic layer OR3 is in contact with the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed from the opening AP3, and has its peripheral edge located on the inorganic insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and is in contact with the lower part 61.

[0043] Note that contact between each of the upper electrodes UE1, UE2, UE3 and the lower portion 61 includes a case where each of the upper electrodes UE1, UE2, UE3 is in direct contact with the upper surface of the bottom layer 63, and a case where each of the upper electrodes UE1, UE2, UE3 is in direct contact with the upper surface of the bottom layer 63 and also in direct contact with the side surface of the axial layer 64. In this specification, the upper surface of the bottom layer 63 includes the surface of the bottom layer 63 that is in direct contact with the axial layer 64 and the surface that protrudes from the axial layer 64 and faces the upper portion 62.

[0044] In the illustrated example, subpixel SP1 has a cap layer CP1 and a sealing layer SE1, subpixel SP2 has a cap layer CP2 and a sealing layer SE2, and subpixel SP3 has a cap layer CP3 and a sealing layer SE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively. Note that the cap layers CP1, CP2, and CP3 may be omitted.

[0045] The cap layer CP1 is disposed on the upper electrode UE1. The cap layer CP2 is disposed on the upper electrode UE2. The cap layer CP3 is disposed on the upper electrode UE3.

[0046] The sealing layer SE1 is disposed on the cap layer CP1, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP1. That is, the sealing layer SE1 is in contact with the axis layer 64 and the upper portion 62 of the partition wall 6 that surrounds the display element DE1. The sealing layer SE2 is disposed on the cap layer CP2, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP2. That is, the sealing layer SE2 is in contact with the axis layer 64 and the upper portion 62 of the partition wall 6 that surrounds the display element DE2. The sealing layer SE3 is disposed on the cap layer CP3, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP3. That is, the sealing layer SE3 is in contact with the axis layer 64 and the upper portion 62 of the partition wall 6 that surrounds the display element DE3.

[0047] In the following description, the multilayer structure including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as the laminate film FL1, the multilayer structure including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as the laminate film FL2, and the multilayer structure including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as the laminate film FL3.

[0048] In the illustrated example, a part of the laminated film FL1 is located on the partition wall 6 around the subpixel SP1, and is spaced apart from the laminated film FL1 (the part that constitutes the display element DE1) located in the aperture AP1. Similarly, a part of the laminated film FL2 is located on the partition wall 6 around the subpixel SP2, and is spaced apart from the laminated film FL2 (the part that constitutes the display element DE2) located in the aperture AP2. Similarly, a part of the laminated film FL3 is located on the partition wall 6 around the subpixel SP3, and is spaced apart from the laminated film FL3 (the part that constitutes the display element DE3) located in the aperture AP3. The stacked films FL1, FL2, and FL3 on the partition wall 6 may be omitted. In this case, a cavity is formed between the partition wall 6 and the sealing layers SE1, SE2, and SE3.

[0049] Ends of the sealing layers SE1, SE2, and SE3 are each located on the partition wall 6. In the example shown, the stacked film FL1 and the sealing layer SE1 on the partition wall 6 between the subpixels SP1 and SP2 are spaced apart from the stacked film FL2 and the sealing layer SE2 on the partition wall 6. In addition, the stacked film FL1 and the sealing layer SE1 on the partition wall 6 between the subpixels SP1 and SP3 are spaced apart from the stacked film FL3 and the sealing layer SE3 on the partition wall 6.

[0050] The partition wall 6 and the sealing layers SE1, SE2, and SE3 are covered with a resin layer 13. If cavities are formed between the sealing layers SE1, SE2, and SE3 and the partition wall 6, the resin layer 13 fills these cavities. The resin layer 13 is covered with a sealing layer 14. The wiring TL is disposed on the sealing layer 14 and is located, for example, directly above the partition wall 6. Such wiring TL functions, for example, as sensor wiring for detecting an object approaching the display device DSP. The sealing layer 14 and the wiring TL are covered with a resin layer 15.

[0051] The inorganic insulating layer 111, the inorganic insulating layer 5, the sealing layers SE1, SE2, SE3, and the sealing layer 14 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0052] The lower portion 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The bottom layer 63 is formed of a titanium-based material such as titanium or a titanium compound. The shaft layer 64 is formed of a material different from the bottom layer 63 and the upper portion 62, and is formed of an aluminum-based material such as aluminum or an aluminum compound.

[0053] The upper portion 62 of the partition wall 6 is formed of, for example, a conductive material, but may also be formed of an insulating material. The upper portion 62 is formed of a material different from that of the lower portion 61. The thin film 65 is formed of, for example, a titanium-based material such as titanium or a titanium compound. The thin film 66 is formed of, for example, an oxide conductive material such as indium tin oxide (ITO).

[0054] The lower electrodes LE1, LE2, and LE3 are multilayer structures including a transparent layer made of an oxide conductive material such as indium tin oxide (ITO) and a reflective layer made of a metal material such as silver. In one example, the lower electrodes LE1, LE2, and LE3 are multilayer structures including a reflective layer between a pair of transparent layers.

[0055] The organic layer OR1 includes an emitting layer EM1. The organic layer OR2 includes an emitting layer EM2. The organic layer OR3 includes an emitting layer EM3. The emitting layers EM1, EM2, and EM3 are formed of different materials. In one example, the emitting layer EM1 is formed of a material that emits light in the blue wavelength range, the emitting layer EM2 is formed of a material that emits light in the green wavelength range, and the emitting layer EM3 is formed of a material that emits light in the red wavelength range. Each of the organic layers OR1, OR2, and OR3 includes a plurality of functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0056] The upper electrodes UE1, UE2, and UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg).

[0057] The cap layers CP1, CP2, and CP3 are multilayer structures made up of multiple thin films, all of which are transparent and have different refractive indices.

[0058] The wiring TL is formed of a metal material such as aluminum, titanium, molybdenum, etc. In one example, the wiring TL is a multilayer body including an aluminum layer between a pair of titanium layers.

[0059] The illustrated circuit layer 11, insulating layer 12, and inorganic insulating layer 5 are disposed across the display area DA and the peripheral area SA.

[0060] Fig. 4 is a plan view showing an example of the shape of the insulating layer 12 in the display device DSP. In Fig. 4, the configuration necessary for explanation is shown, and the details of the terminal area TA are omitted.

[0061] The insulating layer 12 overlaps the display area DA and extends into the peripheral area SA. The insulating layer 12 has a through-hole 12T that penetrates the insulating layer 12 in the peripheral area SA to expose its underlying layer. The through-hole 12T is formed in a loop shape along the end 10E.

[0062] The multiple dam portions DM are insulating layers formed from the same material as the insulating layer 12, and may be a single layer body or a multi-layer body of multiple insulating layers. The multiple dam portions DM are arranged in the peripheral area SA and are formed in a loop shape surrounding the insulating layer 12. In the illustrated example, there are two dam portions DM, but there may be three or more dam portions DM.

[0063] In the illustrated example, each of the through portion 12T and the dam portion DM is formed in a rectangular frame shape, but may be formed in any other polygonal, circular, or elliptical shape.

[0064] The dam portion (inner dam portion) DM adjacent to the insulating layer 12 is spaced apart from the insulating layer 12. The multiple dam portions DM are arranged at intervals. The through portion 12T includes the regions between the insulating layer 12 and the inner dam portion DM, between adjacent dam portions DM, and between the outermost dam portion (outer dam portion) DM and the edge 10E of the substrate 10.

[0065] Fig. 5 is a plan view showing an example of the shape of the sealing layer 14 in the display device DSP. In Fig. 5, the configuration necessary for explanation is shown, and the details of the terminal area TA are omitted.

[0066] The sealing layer 14 is disposed across the display area DA and the peripheral area SA. The sealing layer 14 has through-holes 14T that penetrate the sealing layer 14 in the peripheral area SA to expose its underlying layer. The through-holes 14T are formed in a loop shape that surrounds the display area DA. In the illustrated example, the through-holes 14T are located between the outer dam portion DM and the edge 10E of the substrate 10, and overlap the outer dam portion DM and the outermost through-holes 12T in plan view. Meanwhile, the sealing layer 14 overlaps the insulating layer 12, the region between the insulating layer 12 and the inner dam portion DM, and the region between adjacent dam portions DM.

[0067] In the illustrated example, the through portion 14T is formed in a rectangular frame shape, but may be formed in any other polygonal, circular, or elliptical shape.

[0068] Next, a mother substrate 100 for a display device (hereinafter simply referred to as a mother substrate) for collectively manufacturing a plurality of display device DSPs will be described.

[0069] FIG. 6 is a plan view showing an example of the motherboard 100. As shown in FIG.

[0070] The mother substrate 100 comprises a plurality of panel portions PP and blank portions MP outside the panel portions PP on a large substrate 10. The large substrate 10 is formed, for example, in a rectangular shape. Each of the plurality of panel portions PP is extracted by cutting the mother substrate 100 along a cutting line.

[0071] Each of the extracted panel sections PP corresponds to, for example, the display panel PNL shown in Fig. 1 and includes a display area DA and a peripheral area SA. The peripheral area SA has a terminal area TA in which the multiple terminals TE and pads PD shown in Fig. 1 are arranged. Each of the multiple wirings TL is arranged in the display area DA, drawn out to the peripheral area SA, and electrically connected to the terminals TE included in the terminal area TA.

[0072] The blank area MP has, for example, a plurality of pads PD electrically connected to a test element group or the like.

[0073] FIG. 7 is a plan view showing an example of the motherboard 100. As shown in FIG.

[0074] The cut lines CL for removing the panel portions PP are indicated by dashed lines in the drawing. The through holes 12T are formed in each of the panel portions PP between the insulating layer 12 and the dam portions DM and between adjacent dam portions. The through holes 12T are positioned across the panel portions PP and the blank portions MP, and are formed in loops that surround each of the panel portions PP and overlap the cut lines CL.

[0075] 8 is a plan view showing an example of the configuration of the pads PD. The pads PD shown in the figure correspond to the pads PD in the peripheral area SA shown in FIG. 1 or the pads PD in the marginal portion MP shown in FIG.

[0076] The metal layer MT indicated by the dashed dotted line corresponds to the electrode of the pad PD. The metal layer MT overlaps the opening 5AP in the inorganic insulating layer 5, the through portion 12T in the insulating layer 12, and the through portion 14T in the sealing layer 14, and is exposed from the opening 5AP. A portion of the sealing layer 14 is located between the edge of the opening 5AP and the edge of the through portion 12T.

[0077] FIG. 9 is a schematic cross-sectional view of the motherboard 100 taken along line GH in FIG.

[0078] The inorganic insulating layer 111 included in the circuit layer 11 is disposed across the panel portion PP and the blank portion MP. The insulating layer 12 and the dam portion DM are disposed on the inorganic insulating layer 111. The inorganic insulating layer 5 is disposed across the panel portion PP and the blank portion MP, and covers the insulating layer 12 and the dam portion DM. At the through portion 12T, the inorganic insulating layer 5 is in contact with the inorganic insulating layer 111.

[0079] Although the partition walls 6 are shown in a simplified form, they are disposed on the inorganic insulating layer 5 in the display area DA. Although the multiple peripheral partition walls 7 are shown in a simplified form, they are disposed on the inorganic insulating layer 5 in the peripheral area SA and the marginal area MP of the panel section PP. Some of the multiple peripheral partition walls 7 are disposed in the through-holes 12T. For example, in the vicinity of the cut line CL, the peripheral partition walls 7 are disposed in the through-holes 12T in the peripheral area SA and also in the through-holes 12T in the marginal area MP.

[0080] The sealing layer SE1 is disposed on the partition wall 6 in the display area DA. Although not shown in Fig. 9, other sealing layers SE2 and SE3 are also disposed in the display area DA in the same manner. Details of the sealing layers SE1, SE2, and SE3 are as described with reference to Fig. 3.

[0081] The resin layer 13 is disposed in the display area DA and also in the peripheral area SA, and has an end portion near the dam portion DM.

[0082] The sealing layer 14 is disposed across the panel portion PP and the margin portion MP. The sealing layer 14 covers the resin layer 13 in the panel portion PP and contacts the inorganic insulating layer 5 in the through portion 12T. In the illustrated example, the sealing layer 14 contacts the inorganic insulating layer 5 between adjacent dam portions DM as part of the through portion 12T. In other words, a multilayer body is formed in which the inorganic insulating layer 111, the inorganic insulating layer 5, and the sealing layer 14 are stacked in this order, with no organic insulating material interposed between them. This multilayer body is formed to surround the display area DA. This multilayer body forms a moisture-blocking region that blocks the path of moisture that can penetrate from the outside through the organic insulating material.

[0083] The through portion 14T of the sealing layer 14 is located in the peripheral region SA, is formed closer to the cut line CL than the moisture blocking region, and exposes the inorganic insulating layer 5. In the illustrated example, the through portion 14T overlaps the slope of the dam portion DM. The sealing layer 14 further covers the peripheral partition wall 7 in the peripheral region SA and the margin portion MP.

[0084] The wiring TL is disposed on the sealing layer 14 in the display area DA. The resin layer 15 is disposed in the panel portion PP, covers the sealing layer 14 and the wiring TL, and has an end portion outside the resin layer 13. In the illustrated example, the resin layer 15 is also disposed in the margin portion MP beyond the cut line CL, and has an end portion in the through portion 12T. In the through portion 14T, the resin layer 15 is in contact with the inorganic insulating layer 5. The resin layer 15 also overlaps the peripheral partition wall 7 located in the through portion 12T. Note that when the resin layer 15 has an end portion near the cut line CL, the resin layer 15 does not overlap the peripheral partition wall 7 located on the margin portion MP side of the cut line CL.

[0085] According to this configuration example, even if a crack occurs in the sealing layer 14 near the cut line CL when the mother substrate 100 is cut along the cut line CL, the crack can be prevented from spreading in the through portion 14T. This prevents the crack from spreading to the moisture-blocking region formed in the through portion 12T between the through portion 14T and the display area DA. This prevents moisture from penetrating into the display area DA, thereby preventing a decrease in reliability.

[0086] FIG. 10 is a schematic cross-sectional view of the display panel PNL taken along line CD in FIG.

[0087] The edge 10E of the substrate 10 in the figure corresponds to the position of the cut line CL of the mother substrate 100 shown in FIG. 9. The through portion 12T is formed in the peripheral area SA. The inorganic insulating layer 5 is in contact with the inorganic insulating layer 111 at the through portion 12T. The peripheral partition wall 7 is disposed on the inorganic insulating layer 5 at the through portion 12T. The sealing layer 14 is in contact with the inorganic insulating layer 5 and covers the peripheral partition wall 7 at the through portion 12T. The through portion 14T of the sealing layer 14 is located in the peripheral area SA, overlaps the slope of the dam portion DM, and exposes the inorganic insulating layer 5. A moisture-blocking region, which is a multilayer body of the inorganic insulating layer 111, the inorganic insulating layer 5, and the sealing layer 14, is formed in the through portion 12T between the through portion 14T and the display area DA. The resin layer 15 is in contact with the inorganic insulating layer 5 at the through portion 14T.

[0088] FIG. 11 is a cross-sectional view showing an example of the configuration of each of the regions 100A of the mother substrate 100 shown in FIG. 9 and the display panel PNL shown in FIG.

[0089] The peripheral partition wall 7 has a lower portion 71 disposed on the inorganic insulating layer 5 at the through portion 12T, and an upper portion 72 disposed on the lower portion 71. The lower portion 71 has a bottom layer 73 disposed on the inorganic insulating layer 5, and an axial layer 74 disposed between the bottom layer 73 and the upper portion 72. The upper portion 72 has a thin film 75 disposed on the axial layer, and a thin film 76 disposed on the thin film 75.

[0090] The bottom layer 73 is thinner than the shaft layer 74. The bottom layer 73 has a width greater than the shaft layer 74. Both ends of the bottom layer 73 protrude from the side surfaces of the shaft layer 74. The upper part 72 has a width greater than the shaft layer 74. Both ends of the upper part 72 protrude from the side surfaces of the shaft layer 74. In the illustrated example, the upper part 72 has a width greater than the bottom layer 73, but the bottom layer 73 may also have a width greater than the upper part 72.

[0091] The peripheral partition wall 7 can be formed in the same process as the partition wall 6. In this case, the bottom layer 73 is formed of the same material as the bottom layer 63, the axial layer 74 is formed of the same material as the axial layer 64, the thin film 75 is formed of the same material as the thin film 65, and the thin film 76 is formed of the same material as the thin film 66.

[0092] The sealing layer 14 is in contact with the bottom layer 73, the shaft layer 74, and the upper portion 72, and covers the entire peripheral partition wall 7. In this way, by the sealing layer 14 covering the peripheral partition wall 7, the unevenness caused by the cross-sectional shape of the peripheral partition wall 7 is reduced compared to before the sealing layer 14 is formed.

[0093] Furthermore, since the through portion 14T of the sealing layer 14 overlaps the steep slope of the dam portion DM, the stress acting on the sealing layer 14 near the slope is alleviated, thereby preventing the sealing layer 14 from separating from the inorganic insulating layer 5.

[0094] FIG. 12 is a cross-sectional view showing another example of the configuration of each of the regions 100A of the mother substrate 100 shown in FIG. 9 and the display panel PNL shown in FIG.

[0095] The configuration example shown in FIG. 12 differs from the configuration example shown in FIG. 11 in that the inorganic insulating layer 5 has a through portion 5T. The through portion 5T overlaps the through portion 14T. Therefore, the inorganic insulating layer 5 exposes the slope of the dam portion DM at the through portion 5T. Furthermore, the through portion 5T overlaps the through portion 12T. Therefore, the inorganic insulating layer 5 exposes the inorganic insulating layer 111 at the through portion 5T. The resin layer 15 is in contact with the dam portion DM at the through portion 5T, and is also in contact with the inorganic insulating layer 111.

[0096] In this configuration example, similarly to the configuration example shown in FIG. 11, the peripheral partition wall 7 is covered with the sealing layer 14, so that the unevenness caused by the cross-sectional shape of the peripheral partition wall 7 is reduced. Furthermore, since the through portion 5T of the inorganic insulating layer 5 overlaps the steep slope of the dam portion DM, the stress acting on the inorganic insulating layer 5 in the vicinity of the slope is alleviated, thereby preventing the inorganic insulating layer 5 and the sealing layer 14 from separating from the dam portion DM and the inorganic insulating layer 111.

[0097] FIG. 13 is a cross-sectional view showing an example of the configuration of another region of the mother substrate 100 shown in FIG. 9 and the display panel PNL shown in FIG.

[0098] The insulating layer 12 has a stepped cross section in which the thickness decreases toward the through portion 12T. The insulating layer 12 here may be a single layer or a multilayer structure of multiple insulating layers. When the insulating layer 12 has a stepped cross section as shown in the figure, the slope is gentler than the slope of the dam portion DM shown in FIG. 11 . However, for example, a relatively large stress is likely to occur near the intersection between the slope of the insulating layer 12 and the inorganic insulating layer 111. Therefore, by overlapping the through portion 5T of the inorganic insulating layer 5 and the through portion 14T of the sealing layer 14 with the slope of the insulating layer 12, separation of the inorganic insulating layer 5 and the sealing layer 14 starting near the intersection can be suppressed.

[0099] FIG. 14 is a cross-sectional view showing an example of the configuration of the pad PD taken along the line EF in FIG.

[0100] The metal layer MT is disposed on the inorganic insulating layer 111. The insulating layer 12 overlaps the peripheral edge of the metal layer MT and is also disposed on the inorganic insulating layer 111. A through portion 12T of the insulating layer 12 overlaps the metal layer MT. The inorganic insulating layer 5 covers the insulating layer 12 and is in contact with the metal layer MT at the through portion 12T. The inorganic insulating layer 5 also has an opening 5AP that exposes the metal layer MT.

[0101] The peripheral partition wall 7 is disposed on the inorganic insulating layer 5 at the through portion 12T. The sealing layer 14 is in contact with the bottom layer 73, the axis layer 74, and the upper portion 72, and covers the entire peripheral partition wall 7. The through portion 14T of the sealing layer 14 overlaps the slope of the insulating layer 12, exposing the inorganic insulating layer 5.

[0102] In this configuration example, the peripheral partition wall 7 is covered with the sealing layer 14, so that the unevenness caused by the cross-sectional shape of the peripheral partition wall 7 is reduced. Furthermore, since the through portion 14T of the sealing layer 14 overlaps the steep slope of the insulating layer 12, the stress acting on the sealing layer 14 near the slope is alleviated, thereby preventing the sealing layer 14 from separating from the inorganic insulating layer 5.

[0103] FIG. 15 is a cross-sectional view showing another example of the configuration of the pad PD taken along the line EF in FIG.

[0104] The configuration example shown in FIG. 15 differs from the configuration example shown in FIG. 14 in that the inorganic insulating layer 5 has a through portion 5T. The through portion 5T overlaps the through portion 14T. Therefore, the inorganic insulating layer 5 exposes the slope of the insulating layer 12 at the through portion 5T. Furthermore, the through portion 5T overlaps the through portion 12T. Therefore, the inorganic insulating layer 5 exposes the inorganic insulating layer 111 at the through portion 5T. In this configuration example, similarly to the configuration example shown in FIG. 14, the peripheral partition wall 7 is covered with the sealing layer 14, so that the unevenness caused by the cross-sectional shape of the peripheral partition wall 7 is reduced. Furthermore, since the through portion 5T of the inorganic insulating layer 5 overlaps the steep slope of the insulating layer 12, the stress acting on the inorganic insulating layer 5 near the slope is alleviated, and separation of the inorganic insulating layer 5 and the sealing layer 14 from the insulating layer 12 and the inorganic insulating layer 111 can be suppressed.

[0105] FIG. 16 is a plan view showing an example of the configuration of the peripheral partition wall 7 in the through-hole portion 12T.

[0106] Each of the peripheral partition walls 7 is formed in a lattice shape in a plan view. In one example, the peripheral partition walls 7 are formed in the same pattern as the lattice-shaped partition walls 6 shown in FIG. 2. The peripheral partition walls 7 are aligned in the first direction X and the second direction Y and spaced apart from one another. The peripheral partition walls 7 are covered with a sealing layer 14. The planar shape of the peripheral partition walls 7 is not limited to the lattice shape shown in the drawing, and may be linear, L-shaped, arc-shaped, or the like.

[0107] In the illustrated example, the sealing layer 14 is divided into segments, and each segment of the divided sealing layer 14 is formed to cover four peripheral partition walls 7. A gap of, for example, about 5 to 10 μm is formed between adjacent sealing layers 14. The peripheral partition wall 7A and the peripheral partition wall 7B in the drawing are spaced apart from each other and aligned in the first direction X. The portion of the sealing layer 14 that covers the peripheral partition wall 7A is spaced apart from the portion that covers the peripheral partition wall 7B.

[0108] FIG. 17 is a cross-sectional view showing an example of the configuration of the peripheral partition wall 7A and the peripheral partition wall 7B taken along line IJ in FIG.

[0109] The sealing layer 14 is in contact with the bottom layer 73, the shaft layer 74, and the upper portion 72 of the peripheral partition wall 7A. The sealing layer 14 is also in contact with the bottom layer 73, the shaft layer 74, and the upper portion 72 of the peripheral partition wall 7B. The sealing layer 14 has a through portion 14T between the portion covering the peripheral partition wall 7A and the portion covering the peripheral partition wall 7B. Therefore, the inorganic insulating layer 5 is exposed from the sealing layer 14 between the peripheral partition wall 7A and the peripheral partition wall 7B.

[0110] As in the configuration examples shown in Figures 16 and 17, by dividing the sealing layer 14 into smaller pieces, the stress acting on the sealing layer 14 is alleviated, and separation of the sealing layer 14 from the inorganic insulating layer 5 can be suppressed.

[0111] FIG. 18 is a cross-sectional view showing another example of the configuration of the peripheral partition wall 7A and the peripheral partition wall 7B taken along the line IJ in FIG.

[0112] 18 differs from the configuration example shown in Fig. 17 in that the inorganic insulating layer 5 has a through portion 5T. The through portion 5T overlaps the through portion 14T. Therefore, the inorganic insulating layer 5 exposes the inorganic insulating layer 111 at the through portion 5T.

[0113] FIG. 19 is a plan view showing another example of the configuration of the peripheral partition wall 7 in the through-hole portion 12T.

[0114] The configuration example shown in FIG. 19 differs from the configuration example shown in FIG. 16 in that the sealing layer 14 is further subdivided. In the illustrated example, each of the subdivided sealing layer 14 portions is formed so as to cover one peripheral partition wall 7. In the sealing layer 14, the portions that cover the peripheral partition wall 7 are spaced apart from one another. Between adjacent portions of the sealing layer 14, the inorganic insulating layer 5 is exposed from the sealing layer 14, as shown in FIG. 17. Alternatively, between adjacent portions of the sealing layer 14, the inorganic insulating layer 111 is exposed from the sealing layer 14 and the inorganic insulating layer 5, as shown in FIG. 18.

[0115] Next, a manufacturing method of the display device DSP will be described. Note that in each drawing for explaining the manufacturing method, illustration of the part below the inorganic insulating layer 111 is omitted. In Figures 20 to 27 referred to in the following description, the cross section corresponding to the display area DA on the left side corresponds to the cross section along line AB in Figure 2, and the cross section corresponding to the through portion 12T on the right side corresponds to the cross section along line IJ in Figure 16.

[0116] 20, a process substrate SUB is prepared which includes lower electrodes LE1, LE2, and LE3, an inorganic insulating layer 5, a partition wall 6, and a peripheral partition wall 7. The process of preparing the process substrate SUB includes the following steps.

[0117] That is, on the substrate 10, a circuit layer 11 including an inorganic insulating layer 111 is formed across the display area DA, the peripheral area SA, and the marginal area MP. Then, an insulating layer 12 is formed on the inorganic insulating layer 111. In the patterning process for forming the insulating layer 12, through-holes 12T are formed in necessary locations in the peripheral area SA and the marginal area MP. This forms the insulating layer 12 overlapping the display area DA and multiple dam areas DM.

[0118] Thereafter, in the display region DA, on the insulating layer 12, the lower electrode LE1 of the subpixel SP1, the lower electrode LE2 of the subpixel SP2, and the lower electrode LE3 of the subpixel SP3 are formed.

[0119] Thereafter, an inorganic insulating layer 5 is formed across the display area DA, the peripheral area SA, and the margin area MP. The inorganic insulating layer 5 covers the periphery of each of the lower electrodes LE1, LE2, and LE3, and has openings AP1, AP2, and AP3 that overlap the lower electrodes LE1, LE2, and LE3, respectively. In the through portion 12T, the inorganic insulating layer 5 is formed on the inorganic insulating layer 111. The inorganic insulating layer 5 is formed of, for example, silicon oxynitride.

[0120] Thereafter, a partition wall 6 is formed, which has a lower portion 61 located on the inorganic insulating layer 5 and an upper portion 62 located on the lower portion 61. Simultaneously with the formation of the partition wall 6, a peripheral partition wall 7 is formed in the through portion 12T, which has a lower portion 71 located on the inorganic insulating layer 5 and an upper portion 72 located on the lower portion 71. The bottom layer 63 and upper portion 62 of the lower portion 61 protrude from the side surface of the shaft layer 64 of the lower portion 61. Similarly, the bottom layer 73 and upper portion 72 of the lower portion 71 protrude from the side surface of the shaft layer 74 of the lower portion 71. The bottom layers 63 and 73 are formed of a titanium-based material, and the shaft layers 64 and 74 are formed of an aluminum-based material.

[0121] The step of forming the openings AP1, AP2, and AP3 in the inorganic insulating layer 5 may be performed before or after the partition walls 6 and peripheral partition walls 7 are formed.

[0122] Next, the display element DE1 is formed.

[0123] First, as shown in FIG. 21, a laminated film FL1 including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 is formed. The process of forming the laminated film FL1 includes the steps of forming the organic layer OR1 on the lower electrode LE1 in the opening AP1, forming the upper electrode UE1 covering the organic layer OR1 and in contact with the lower portion 61 of the partition wall 6, and forming the cap layer CP1 on the upper electrode UE1. The process of forming the organic layer OR1 includes the steps of forming a hole injection layer, a hole transport layer, an electron blocking layer, an emitting layer EM1, a hole blocking layer, an electron transport layer, an electron injection layer, etc. The upper electrode UE1 is formed from a mixture of magnesium and silver.

[0124] The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are each formed by vapor deposition using the partition wall 6 as a mask. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are successively formed while maintaining a vacuum environment.

[0125] The laminated film FL1 is formed on the lower electrodes LE2 and LE3 in the display area DA, and is also formed in the peripheral area SA and marginal portion MP. Such laminated film FL1 is divided into multiple parts by overhanging partition walls 6 and peripheral partition walls 7. In particular, in the peripheral area SA and marginal portion MP, the laminated film FL1 is divided by the peripheral partition walls 7, thereby dividing the laminated film FL1 into smaller parts. This reduces the stress acting on the laminated film FL1 during the manufacturing process, and makes it possible to prevent the laminated film FL1 from separating from the inorganic insulating layer 5.

[0126] Thereafter, an inorganic insulating material is deposited to form a sealing layer SE1 on the laminated film FL1. The sealing layer SE1 is formed over the display area DA, the peripheral area SA, and the marginal portion MP by CVD (Chemical Vapor Deposition). The sealing layer SE1 continuously covers each divided portion of the laminated film FL1, the partition walls 6, and the peripheral partition walls 7. The sealing layer SE1 is formed of, for example, silicon nitride.

[0127] 22, a resist RS patterned into a predetermined shape is formed on the sealing layer SE1 in the display area DA. The resist RS overlaps the subpixel SP1 and part of the partition wall 6 around it. The resist RS is not disposed in the peripheral area SA or the marginal portion MP.

[0128] Next, as shown in FIG. 23, etching is performed using the resist RS as a mask to pattern the stacked film FL1 and the sealing layer SE1. That is, dry etching is performed using the resist RS as a mask to remove the sealing layer SE1 exposed from the resist RS. Then, the stacked film FL1 exposed from the resist RS is removed. At this time, in the stacked film FL1, the cap layer CP1, the upper electrode UE1, and the organic layer OR1 are removed in this order. As a result, the stacked film FL1 covered with the resist RS remains in the subpixel SP1. In addition, a part of the upper part 62 of the partition 6 is exposed, and the lower electrode LE2 and the lower electrode LE3 are also exposed. Furthermore, in the peripheral region SA and the margin MP, the peripheral partition 7 is exposed. Thereafter, the resist RS is removed, thereby forming the display element DE1 in the subpixel SP1.

[0129] In the process of removing the sealing layer SE1 and the stacked film FL1 and then removing the resist RS, the stacked film FL1 located on the upper portion 62 of the partition wall 6 may be removed. In this case, a cavity is formed between the upper portion 62 and the sealing layer SE1.

[0130] Next, as shown in FIG. 24, a display element DE2 is formed. The procedure for forming the display element DE2 is the same as that for forming the display element DE1. That is, an organic layer OR2 including an emitting layer EM2, an upper electrode UE2, and a cap layer CP2 are formed in this order on the lower electrode LE2 to form a stacked film FL2. Then, a sealing layer SE2 is formed on the stacked film FL2. Then, a resist is formed on the sealing layer SE2, and the sealing layer SE2, the cap layer CP2, the upper electrode UE2, and the organic layer OR2 are patterned by etching using this resist as a mask. After this patterning, the resist is removed. As a result, a display element DE2 is formed in the subpixel SP2, and the lower electrode LE3 of the subpixel SP3 is exposed.

[0131] It should be noted that, in the process of removing the sealing layer SE2 and the stacked film FL2 and then removing the resist, the stacked film FL2 located on the upper portion 62 of the partition wall 6 may be removed. In this case, a cavity is formed between the upper portion 62 and the sealing layer SE2.

[0132] The laminated film FL2 does not remain on the peripheral partition wall 7, and the peripheral partition wall 7 is not covered with the sealing layer SE2.

[0133] Next, as shown in FIG. 25, a display element DE3 is formed. The procedure for forming the display element DE3 is the same as that for forming the display element DE1. That is, an organic layer OR3 including an emitting layer EM3, an upper electrode UE3, and a cap layer CP3 are formed in this order on the lower electrode LE3 to form a stacked film FL3. Then, a sealing layer SE3 is formed on the stacked film FL3. Then, a resist is formed on the sealing layer SE3, and the sealing layer SE3, the cap layer CP3, the upper electrode UE3, and the organic layer OR3 are patterned by etching using this resist as a mask. After this patterning, the resist is removed. This forms a display element DE3 in the subpixel SP3.

[0134] It should be noted that, in the process of removing the sealing layer SE3 and the stacked film FL3 and then removing the resist, the stacked film FL3 located on the upper portion 62 of the partition wall 6 may be removed. In this case, a cavity is formed between the upper portion 62 and the sealing layer SE3.

[0135] The laminated film FL3 does not remain on the peripheral partition wall 7, and the peripheral partition wall 7 is not covered with the sealing layer SE3.

[0136] In the above manufacturing process, it is assumed that display element DE1 is formed first, then display element DE2 is formed, and finally display element DE3 is formed, but the order in which display elements DE1, DE2, and DE3 are formed is not limited to this example.

[0137] 26, a resin layer 13 is formed in the display area DA, located on the sealing layers SE1, SE2, and SE3. When the resin material for forming the resin layer 13 is applied, the resin material is blocked by the multiple dam portions DM shown in FIG. 9 and is not disposed in the through portions 12T shown in the drawing.

[0138] Next, as shown in FIG. 27, an inorganic insulating material is deposited to form the sealing layer 14. The sealing layer 14 is formed by CVD across the display area DA, peripheral area SA, and margin area MP. The sealing layer 14 is disposed on the resin layer 13 in the display area DA, and continuously covers the peripheral partition wall 7 in the peripheral area SA and margin area MP. In other words, the bottom layer 73 of the lower portion 71, the axis layer 74, and the upper portion 72 are directly covered by the sealing layer 14. The sealing layer 14 is formed of, for example, silicon nitride.

[0139] Subsequently, the inorganic insulating layer 5 and the sealing layer 14 are patterned at the same time. FIG. 28 is a cross-sectional view showing the terminal area TA. Here, the terminal area TA, which is a part of the peripheral area SA, is shown.

[0140] As shown on the left side of FIG. 28, the terminal TE is formed in the process of forming the circuit layer 11. For example, the terminal TE is formed on an inorganic insulating layer 111. The insulating layer 12 covers the peripheral edge of the terminal TE. The inorganic insulating layer 5 covers the insulating layer 12 in the terminal region TA and also covers the terminal TE. As described with reference to FIG. 27, the sealing layer 14 is also formed in the peripheral region SA and covers the inorganic insulating layer 5 in the terminal region TA.

[0141] 28, the inorganic insulating layer 5 and the sealing layer 14 are patterned together, and in the terminal region TA, through holes TH are formed that penetrate the inorganic insulating layer 5 and the sealing layer 14, exposing the terminals TE. The through portions 5T and through portions 14T described with reference to FIGS. 12, 13, 15, and 18 can be formed by the above-described collective patterning of the inorganic insulating layer 5 and the sealing layer 14. As a result, in the peripheral region SA and the marginal region MP, the inorganic insulating layer 5 and the sealing layer 14 are subdivided by the through portions 5T and through portions 14T.

[0142] Subsequently, as shown in FIG. 29, the sealing layer 14 is patterned. In the terminal region TA, the sealing layer 14 around the terminal TE is removed, and the step at the through hole TH is reduced. The through portion 14T described with reference to FIGS. 11, 14, and 17 can be formed by patterning the sealing layer 14 described herein. The left side of FIG. 29 shows a through portion 14T similar to that shown in FIG. 17. As a result, in the peripheral region SA and the margin portion MP, the sealing layer 14 is subdivided by the through portion 14T.

[0143] That is, the through portion 14T may be formed by simultaneous patterning of the inorganic insulating layer 5 and the sealing layer 14 as described with reference to FIG. 28, or may be formed by patterning the sealing layer 14 as described with reference to FIG. 29.

[0144] Next, as shown in FIG. 30, the conductive layer 20 is formed. The conductive layer 20 is a multilayer body in which, for example, a titanium layer, an aluminum layer, and another titanium layer are laminated in this order. In the peripheral area SA and the marginal portion MP, the conductive layer 20 is disposed on the sealing layer 14 and also on the inorganic insulating layer 5. In the terminal area TA, the conductive layer 20 is disposed on the inorganic insulating layer 5 and also on the terminals TE in the through holes TH. In the display area DA, the conductive layer 20 is disposed on the sealing layer 14.

[0145] Next, as shown in FIG. 31 , a resist RS1 is applied onto the conductive layer 20. At this time, in the peripheral region SA and the marginal portion MP, the unevenness of the peripheral partition wall 7 is reduced by the sealing layer 14 in the vicinity of the peripheral partition wall 7, so that the formation of undesired gaps between the resist RS1 and the peripheral partition wall 7 is suppressed. In addition, the surface of the resist RS1 can be flattened. Therefore, the formation of locally thickened regions and regions in the shadow of the peripheral partition wall 7 in the resist RS1 is suppressed. Such a resist RS1 is, for example, a positive type that becomes soluble in a developer when irradiated with light.

[0146] 32, the resist RS1 is patterned. By this patterning, the resist RS1 is formed so as to overlap the terminals TE in the terminal region TA, and also so as to overlap the partition walls 6 in the display region DA. In the peripheral region SA and the margin portion MP, almost the entire area of ​​the resist RS1 is exposed, so no residue of the resist RS1 is left.

[0147] 33, the conductive layer 20 is patterned using the resist RS1 as a mask. In the peripheral area SA and the marginal portion MP, the resist RS1 has been removed, so no residue of the conductive layer 20 remains. In the terminal area TA and the display area DA, the conductive layer 20 exposed from the resist RS1 is removed.

[0148] Subsequently, the resist RS1 is removed as shown in Fig. 34. As a result, the wiring TL is formed from the display area DA to the terminal area TA, and in the terminal area TA, the wiring TL is connected to the terminal TE.

[0149] 35, a resin layer 15 is formed in the display area DA, located on the sealing layer 14 and the wiring TL. When the resin material for forming the resin layer 15 is applied, the resin material is blocked by the multiple dam portions DM shown in FIG. 9, etc. For this reason, the resin layer 15 is not disposed in the terminal area TA, peripheral area SA, and margin portion MP shown in the figure.

[0150] As described above, since the peripheral partition wall 7 is covered with the sealing layer 14, the peripheral partition wall 7 is protected by the sealing layer 14 when the conductive layer 20 is patterned in the process of forming the wiring TL. This prevents the peripheral partition wall 7 from being undesirably scraped off. In addition, the generation of conductive particles caused by the detachment of a portion of the peripheral partition wall 7 is prevented.

[0151] Furthermore, when patterning the conductive layer 20, the formation of voids between the resist RS1 and the peripheral partition wall 7 and the local thickening of the resist RS1 are suppressed. This suppresses the generation of undesired residues of the resist RS1 around the peripheral partition wall 7. This suppresses the generation of undesired residues of the conductive layer 20.

[0152] Although the resist RS1 applied in patterning the conductive layer 20 has been described in particular here, the formation of voids and local thickening of the resist are also suppressed when applying the resists applied in patterning the inorganic insulating layer 5 and the sealing layer 14 described with reference to Fig. 28 and patterning the sealing layer 14 described with reference to Fig. 29. This suppresses the generation of undesired resist residues.

[0153] As described above, according to the present embodiment, it is possible to provide a display device, a mother substrate for a display device, and a method for manufacturing a display device that are capable of suppressing a decrease in reliability.

[0154] In the above embodiment, for example, the sealing layers SE1, SE2, and SE3 correspond to the first sealing layer, and the sealing layer 14 corresponds to the second sealing layer. The resin layer 13 corresponds to the first resin layer, and the resin layer 15 corresponds to the second resin layer. In the peripheral partition wall 7, the lower portion 71 corresponds to the first lower portion, the upper portion 72 corresponds to the second upper portion, the bottom layer 73 corresponds to the first bottom layer, and the axial layer 74 corresponds to the first axial layer. The peripheral partition wall 7A corresponds to the first peripheral partition wall, and the peripheral partition wall 7B corresponds to the second peripheral partition wall. In the partition wall 6, the lower portion 61 corresponds to the second lower portion, the upper portion 62 corresponds to the second upper portion, the bottom layer 63 corresponds to the second bottom layer, and the axial layer 64 corresponds to the second axial layer. The inorganic insulating layer 111 corresponds to the first inorganic insulating layer, and the inorganic insulating layer 5 corresponds to the second inorganic insulating layer. The through portion 12T corresponds to the first through portion, the through portion 14T corresponds to the second through portion, and the through portion 5T corresponds to the third through portion.

[0155] All display devices, motherboards, and display device manufacturing methods that can be implemented by a person skilled in the art by making appropriate design modifications based on the display devices, motherboards, and display device manufacturing methods described above as embodiments of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0156] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of the above-described embodiment, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0157] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0158] DSP...display device 10...substrate 100...motherboard 111... inorganic insulating layer 12... insulating layer (organic insulating layer) 12T... penetration portion 5...Inorganic insulating layer AP1, AP2, AP3...Openings 5T...Penetration 6...Partition wall 61...Lower part 62...Upper part 63...Bottom layer 64...Axial layer 7...Peripheral partition 71...Lower part 72...Upper part 73...Bottom layer 74...Axial layer SP1, SP2, SP3...subpixels DE1, DE2, DE3...Display element (organic EL element) LE1, LE2, LE3…lower electrode UE1, UE2, UE3...upper electrode OR1, OR2, OR3…Organic layer CP1, CP2, CP3...cap layer SE1, SE2, SE3...Sealing layer 13...resin layer 15...resin layer 14...Sealing layer 14T...Penetration part DA: Display area SA: Surrounding area TA...Terminal area TE...Terminal PD: Pad MT: Metal layer PP: Panel section MP: Margin section SUB...Processing board TL...Wiring

Claims

1. A substrate; a first inorganic insulating layer disposed above the substrate across a display area for displaying an image and a peripheral area outside the display area; an organic insulating layer disposed on the first inorganic insulating layer; a second inorganic insulating layer disposed on the organic insulating layer; a display element disposed in the display area; a first sealing layer formed of an inorganic insulating material and covering the display element; a plurality of peripheral partition walls disposed in the peripheral region; a second sealing layer formed of an inorganic insulating material and disposed across the display area and the peripheral area; the organic insulating layer has a first penetrating portion in the peripheral region, each of the plurality of peripheral partition walls has a first lower portion disposed in the first penetration portion and a first upper portion disposed on the first lower portion, and is covered with the second sealing layer; Display device.

2. the first penetrating portion is formed in a loop shape along an edge of the substrate, In the first penetrating portion, the second inorganic insulating layer is in contact with the first inorganic insulating layer. The display device according to claim 1 .

3. further comprising a metal layer disposed on the first inorganic insulating layer; the first penetration portion overlaps the metal layer; In the first penetrating portion, the second inorganic insulating layer is in contact with the metal layer. The display device according to claim 1 .

4. the second sealing layer has a second penetrating portion in the peripheral region; The display device according to claim 1 .

5. The second through-portion is formed in a loop shape surrounding the display area in a plan view. The display device according to claim 4 .

6. The insulating film further includes a dam portion disposed on the first inorganic insulating layer and formed in a loop shape surrounding the organic insulating layer, The second penetration portion overlaps the slope of the dam portion. The display device according to claim 5 .

7. the second inorganic insulating layer has a third penetration portion overlapping the second penetration portion, and the inclined surface is exposed; The display device according to claim 6.

8. a first resin layer disposed between the first sealing layer and the second sealing layer in the display region; a second resin layer disposed on the second sealing layer in the display region; the second sealing layer has a second penetration portion and is in contact with the second inorganic insulating layer at the first penetration portion between the second penetration portion and the display area; The display device according to claim 1 .

9. the plurality of peripheral partition walls include a first peripheral partition wall and a second peripheral partition wall spaced apart from the first peripheral partition wall; the second sealing layer has a second penetration portion between a portion covering the first peripheral partition wall and a portion covering the second peripheral partition wall; The display device according to claim 1 .

10. further comprising wiring disposed on the second sealing layer in the display region and drawn out to the peripheral region. The display device according to claim 1 .

11. The first lower portion has a first bottom layer disposed on the second inorganic insulating layer and a first axial layer disposed between the first bottom layer and the first upper portion, The first bottom layer and the first top layer protrude from a side surface of the first axial layer, the second sealing layer contacts the first bottom layer, the first axial layer, and the first top layer; The display device according to claim 1 .

12. Further, a partition wall surrounding the display element is provided, the partition wall has a second lower portion disposed on the second inorganic insulating layer and having conductivity, and a second upper portion disposed on the second lower portion, The second lower portion has a second bottom layer disposed on the second inorganic insulating layer and formed of the same material as the first bottom layer, and a second axial layer disposed between the second bottom layer and the second upper portion and formed of the same material as the first axial layer, The second bottom layer and the second top layer protrude from a side surface of the second axial layer, the first sealing layer contacts the second axial layer and the second top portion; The display device according to claim 11.

13. The display element is a lower electrode having a periphery covered with the second inorganic insulating layer; an organic layer including a light-emitting layer disposed on the lower electrode; an upper electrode disposed on the organic layer and in contact with the second lower portion; the partition wall surrounds the organic layer and the upper electrode; The display device according to claim 12.

14. a panel unit having a display area for displaying an image and a peripheral area outside the display area; a margin portion outside the panel portion; a first inorganic insulating layer disposed across the panel portion and the marginal portion; an organic insulating layer disposed on the first inorganic insulating layer; a second inorganic insulating layer disposed on the organic insulating layer; a display element disposed in the display area; a first sealing layer formed of an inorganic insulating material and covering the display element; a plurality of peripheral partition walls arranged in the marginal portion; a second sealing layer formed of an inorganic insulating material and disposed across the panel portion and the marginal portion; the organic insulating layer has a first penetrating portion in the marginal portion, each of the plurality of peripheral partition walls has a first lower portion disposed in the first penetration portion and a first upper portion disposed on the first lower portion, and is covered with the second sealing layer; Motherboard.

15. The first penetration portion is formed in a loop shape surrounding the panel portion, In the first penetrating portion, the second inorganic insulating layer is in contact with the first inorganic insulating layer. The motherboard according to claim 14.

16. further comprising a metal layer disposed on the first inorganic insulating layer; the first penetration portion overlaps the metal layer; In the first penetrating portion, the second inorganic insulating layer is in contact with the metal layer. The motherboard according to claim 14.

17. the second sealing layer has a second penetrating portion in the peripheral region; The motherboard according to claim 14.

18. The second through-portion is formed in a loop shape surrounding the display area in a plan view. The motherboard according to claim 17.

19. The panel unit further includes a dam portion disposed on the first inorganic insulating layer and formed in a loop shape surrounding the organic insulating layer, The second penetration portion overlaps the slope of the dam portion. The motherboard according to claim 18.

20. the second inorganic insulating layer has a third penetration portion overlapping the second penetration portion, and the inclined surface is exposed; 20. The motherboard according to claim 19.

21. a first resin layer disposed between the first sealing layer and the second sealing layer in the display region; a second resin layer disposed on the second sealing layer in the display region; the second sealing layer has a second penetration portion and is in contact with the second inorganic insulating layer at the first penetration portion between the second penetration portion and the display area; The motherboard according to claim 14.

22. the plurality of peripheral partition walls include a first peripheral partition wall and a second peripheral partition wall spaced apart from the first peripheral partition wall; the second sealing layer has a second penetration portion between a portion covering the first peripheral partition wall and a portion covering the second peripheral partition wall; The motherboard according to claim 14.

23. further comprising wiring disposed on the second sealing layer in the display region and drawn out to the peripheral region. The motherboard according to claim 14.

24. a processing substrate including: a first inorganic insulating layer extending over a display area for displaying an image and a peripheral area outside the display area; an organic insulating layer positioned on the first inorganic insulating layer; a second inorganic insulating layer positioned on the organic insulating layer; a display element positioned in the display area; a plurality of peripheral partition walls positioned in the peripheral area; and a first sealing layer covering the display element and exposing the peripheral partition walls; forming a second sealing layer that is made of an inorganic insulating material and that extends across the display area and the peripheral area; the patterning step for forming the organic insulating layer includes a step of forming a first penetrating portion in the peripheral region; each of the plurality of peripheral partition walls has a first lower portion disposed in the first penetration portion and a first upper portion disposed on the first lower portion, and is covered with the second sealing layer; A method for manufacturing a display device.

25. Furthermore, after forming the second sealing layer, The second inorganic insulating layer and the second sealing layer are patterned together; patterning the second sealing layer; The method for manufacturing the display device according to claim 24.

26. In the simultaneous patterning of the second inorganic insulating layer and the second sealing layer or the patterning of the second sealing layer, a second penetrating portion is formed in the second sealing layer located in the peripheral region. The method for manufacturing the display device according to claim 25.

27. the patterning when forming the organic insulating layer includes a step of forming a loop-shaped dam portion located on the first inorganic insulating layer and surrounding the organic insulating layer; In patterning the second sealing layer, a second penetrating portion that penetrates the second sealing layer is formed at a position overlapping the slope of the dam portion. The method for manufacturing the display device according to claim 25.

28. the patterning when forming the organic insulating layer includes a step of forming a loop-shaped dam portion located on the first inorganic insulating layer and surrounding the organic insulating layer; In the simultaneous patterning of the second inorganic insulating layer and the second sealing layer, a second penetration portion that penetrates the second sealing layer is formed at a position overlapping the slope of the dam portion, and a third penetration portion that penetrates the second inorganic insulating layer and exposes the slope is formed at a position overlapping the second penetration portion. The method for manufacturing the display device according to claim 25.

29. Furthermore, after forming the second sealing layer, forming a conductive layer; forming a resist on the conductive layer; patterning the conductive layer using the resist as a mask to form wiring located on the second sealing layer in the display region and drawn out to the peripheral region; The method for manufacturing the display device according to claim 24.

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