3D die stack redistribution layer for topside power delivery to backside die metallization in multichip composite devices

Abstract

To provide microelectronic devices, assemblies, and systems.SOLUTION: A microelectronic device 100 includes a multichip architecture having one or more integrated circuit dies 101 over and bonded to a base die 102, and a metallization network 107 over the integrated circuit dies 101. A backside metallization 134 of the integrated circuit dies is proximal to the metallization network 107, and a frontside metallization 136 of the integrated circuit dies 101 is opposite from the backside metallization with respect to a device layer 135. A backside via 143 extends from an interconnect layer 138 to the backside metallization 134. The backside via 143 may be made of any appropriate conductive material, such as copper.SELECTED DRAWING: Figure 4

Description

[Background technology]

[0001] Higher performance, lower cost, increased miniaturization, greater packaging density, and increased product flexibility of integrated circuit devices are ongoing goals of the electronics industry. In particular, heterogeneous integrated semiconductor devices are expanding in both power and computational bandwidth demands. Power levels in data center central processing units (CPUs) and graphics processing units (GPUs) are approaching 1000W, and the need for increased computational performance demands increasing bandwidth and input / output (IO) routing problems.

[0002] Current package architectures may not meet future needs for CPU and GPU power and IO demands. In connection with these and other considerations, this improvement has been needed. Such improvements may become important as the desire for improved computing device performance and the corresponding need to remove heat from such devices becomes even more prevalent. [Brief explanation of the drawings]

[0003] The subject matter described herein is by way of example only and is not limited in the accompanying drawings. For simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Furthermore, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or similar elements. The drawings are as follows:

[0004] [Figure 1] 1 illustrates a cross-sectional side view of a multi-chip composite device including a topside metallization network that provides a power route to the backside of an integrated circuit die, according to some embodiments. [Figure 2]1 illustrates a cross-sectional side view of electrical routing in a multi-chip composite device according to some embodiments. [Figure 3] 2 illustrates an enlarged cross-sectional side view of a region of the multi-chip composite device of FIG. 1 according to some embodiments. [Figure 4] FIG. 1 illustrates another enlarged cross-sectional side view of a multi-chip composite device having an inverted base die according to some embodiments. [Figure 5] 1 illustrates a cross-sectional side view of an IC die showing further details of the device layer, front-side metallization, and back-side metallization according to some embodiments. [Figure 6] 1 illustrates a cross-sectional side view of a metallization die showing further details of the metallization network according to some embodiments. [Figure 7] 1 illustrates a cross-sectional side view of electrical routing in a multi-chip composite device according to some embodiments. [Figure 8] 1 illustrates a cross-sectional side view of electrical routing in a multi-chip composite device having multiple integrated circuit dies according to some embodiments. [Figure 9] 1 illustrates a cross-sectional side view of electrical routing in a multi-chip composite device having multiple base dies according to some embodiments. [Figure 10] FIG. 1 illustrates a cross-sectional side view of a multi-chip composite device including an upper metallization network fabricated from one or more directly applied metallization levels to provide a power route to the backside of an integrated circuit die, according to some embodiments. [Figure 11] FIG. 1 illustrates a cross-sectional side view of a multi-chip composite device including a second integrated circuit die level on an upper metallization network according to some embodiments. [Figure 12] 1 illustrates a cross-sectional side view of a multi-chip composite device having components within the thickness of the top metallization network according to some embodiments. [Figure 13]1 illustrates a cross-sectional side view of a multi-chip composite device having a bond wire upper metallization network according to some embodiments. [Figure 14] FIG. 1 is a flow diagram illustrating a method for forming a multi-chip composite device including a topside metallization network that provides a power route to the backside of an integrated circuit die, according to some embodiments. [Figure 15] 15 is a cross-sectional side view of an integrated circuit (IC) device structure that develops as the method of FIG. 14 is performed, according to some embodiments. [Figure 16] 15 is a cross-sectional side view of an integrated circuit (IC) device structure that develops as the method of FIG. 14 is performed, according to some embodiments. [Figure 17] 15 is a cross-sectional side view of an integrated circuit (IC) device structure that develops as the method of FIG. 14 is performed, according to some embodiments. [Figure 18] 15 is a cross-sectional side view of an integrated circuit (IC) device structure that develops as the method of FIG. 14 is performed, according to some embodiments. [Figure 19] 15 is a cross-sectional side view of an integrated circuit (IC) device structure that develops as the method of FIG. 14 is performed, according to some embodiments. [Figure 20] 15 is a cross-sectional side view of an integrated circuit (IC) device structure that develops as the method of FIG. 14 is performed, according to some embodiments. [Figure 21] 15 is a cross-sectional side view of an integrated circuit (IC) device structure that develops as the method of FIG. 14 is performed, according to some embodiments. [Figure 22] 15 is a cross-sectional side view of an integrated circuit (IC) device structure that develops as the method of FIG. 14 is performed, according to some embodiments. [Figure 23] 15 is a cross-sectional side view of an integrated circuit (IC) device structure that develops as the method of FIG. 14 is performed, according to some embodiments. [Figure 24] 15 is a cross-sectional side view of an integrated circuit (IC) device structure that develops as the method of FIG. 14 is performed, according to some embodiments. [Figure 25] 15 is a cross-sectional side view of an integrated circuit (IC) device structure that develops as the method of FIG. 14 is performed, according to some embodiments. [Figure 26] 15 is a cross-sectional side view of an integrated circuit (IC) device structure that develops as the method of FIG. 14 is performed, according to some embodiments. [Figure 27] 15 is a cross-sectional side view of an integrated circuit (IC) device structure that develops as the method of FIG. 14 is performed, according to some embodiments. [Figure 28] 15 is a cross-sectional side view of an integrated circuit (IC) device structure that develops as the method of FIG. 14 is performed, according to some embodiments. [Figure 29] 15 is a cross-sectional side view of an integrated circuit (IC) device structure that develops as the method of FIG. 14 is performed, according to some embodiments. [Figure 30] 15 is a cross-sectional side view of an integrated circuit (IC) device structure that develops as the method of FIG. 14 is performed, according to some embodiments. [Figure 31] 1 illustrates an exemplary microelectronic device assembly including a multi-chip composite device having a topside metallization network that provides a power route to the backside of an integrated circuit die, according to some embodiments. [Figure 32]1 illustrates an exemplary system using an IC assembly including a multi-chip composite device having a topside metallization network that provides a power route to the backside of an integrated circuit die, according to some embodiments. [Figure 33] FIG. 1 is a functional block diagram of an electronic computing device according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0005] One or more embodiments will be described with reference to the accompanying drawings. While specific configurations and arrangements are shown and discussed in detail, it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the description. Those skilled in the art will appreciate that the techniques and / or arrangements described herein can be used in a variety of other systems and applications other than those specifically described herein.

[0006] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. It is to be understood that other embodiments may be utilized and structural and / or logical changes may be made without departing from the scope of the claimed subject matter. It should also be noted that directions and references, such as up, down, upper, bottom, etc., may be used merely to facilitate description of features within the drawings. Therefore, the following detailed description is not intended to be limiting, and the scope of the claimed subject matter is defined solely by the appended claims and their equivalents.

[0007] The following description sets forth many details. However, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention. References throughout this specification to "one embodiment" or "one embodiment" mean that a particular feature, structure, function, or characteristic described in connection with that embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in one embodiment" in various places throughout this specification do not necessarily refer to the same embodiment of the present invention. Furthermore, particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment whenever particular features, structures, functions, or characteristics associated with the first and second embodiments are not mutually exclusive.

[0008] As used in the description of this invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or," as used herein, refers to and includes any and all possible combinations of one or more of the associated listed items.

[0009] The terms "coupled" and "connected," along with their derivatives, may be used herein to describe a functional or structural relationship between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" may be used to indicate that two or more elements are in physical or electrical contact with each other, either directly or indirectly (with other intervening elements between them), and / or that two or more elements cooperate or interact with each other (e.g., in a causal relationship).

[0010] As used herein, the terms "above," "below," "between," "on," and / or the like refer to the relative location of a layer of material or component with respect to another layer or component. For example, a layer disposed above or below another layer may be in direct contact with the other layer or may have one or more intervening layers. Furthermore, a layer disposed between two layers may be in direct contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in direct contact with the second layer. Similarly, unless expressly stated otherwise, a feature disposed between two features may be in direct contact with the adjacent feature or may have one or more intervening features. The term "directly adjacent" indicates that such features are in direct contact. Furthermore, terms such as "substantially," "approximately," "approximately," "near," and "about" generally refer to within ±10% of a target value.

[0011] As used herein, the term layer and similar terms such as metallization or dielectric may include a single material or multiple materials or a single component or multiple components. The term metallization generally refers to a metal layer (including metal lines or traces and vias) that provides routing for the delivery of power, ground, IO, etc. The metal layer is generally patterned to form metal structures such as traces and vias. The metallization structures are separated by a dielectric material, or simply a dielectric, which generally refers to any number of non-conductive materials. As used throughout this specification and in the claims, a list of items connected by the terms “at least one of” or “one or more of” may refer to any combination of the listed terms. For example, the phrase “at least one of A, B, or C” may mean A; B; C; A and B; A and C; B and C; or A, B, and C. The terms “laterally,” “laterally adjacent,” and similar terms indicate that two or more components are aligned along a plane perpendicular to the vertical direction of the overall structure. The terms "vertical," "vertically aligned," and similar terms indicate that two or more components are aligned along a vertical direction, typically in the build-up direction of a device structure. As used herein, the term primarily indicates a predominant component (i.e., greater than 50% is the largest percentage component in a layer or material). The term substantially pure indicates that a component is 99% or more of the material. The term pure indicates that a component is 99.5% or more of the material, and the term completely pure indicates that a component is 99.9% or more of the material. As used herein, the terms "monolithic," "monolithically integrated," and similar terms indicate that the components of a monolithic overall structure form an inseparable whole that is not reasonably capable of being separated.

[0012] As discussed, heterogeneous integrated semiconductor devices are expanding in both power and computational bandwidth demands. To meet these demands, evolved package architectures will continue to develop. In particular, in integrated circuit (IC) devices, front-side and back-side metallization are being introduced. In such IC dies, a device layer (e.g., a layer containing transistors) resides between a set of front-side metallization layers and a set of back-side metallization layers. The inclusion of a back-side metallization layer in addition to the traditional front-side metallization layers provides various advantages. For example, power can be supplied from the backside, thereby making the front-side metallization layer available for additional IO routing. By routing around the periphery of the base die, vias can be removed from the base die, reducing its size or providing additional compute on the base die. Furthermore, the back-side metallization can be thicker and have more direct routes to the device layer, thereby providing less power loss and other advantages. For example, the introduction of front-side and back-side metallization improves end-to-end power efficiency, removes routing constraints, and reduces IO routing and memory utilization. 2 This allows for a higher computation density per processor, which brings other benefits.

[0013] In current 3D package architectures, an interposer or base die may be mounted on a package substrate, and a compute die may be mounted above the interposer or base die. In such architectures, both power and IO are provided to a second-level die (e.g., the compute die) through, for example, the interposer or base die. This drives base die area and IO routing constraints, limiting overall power delivery and end-to-end power efficiency. While isolating the package voltage regulator and improving the interconnect system can improve power delivery, IO and power routing constraints and other issues remain.

[0014] In some embodiments, power routing from the package substrate through the base die to the second-level die (e.g., compute die) is eliminated. The structures and architectures discussed herein route power (and optionally IO) to a thick metal redistribution layer on top of the second-level die (e.g., compute die). Power can be routed to the thick metal redistribution layer through an isolated voltage regulator (VR), power can be connected directly to the thick metal redistribution layer, or power can be delivered to the thick metal redistribution layer on top of the second-level die (e.g., compute die) through alternative power delivery network components. Other routing to the thick metal redistribution layer can be used. This architecture utilizes the previously discussed IC die including a front-side metallization layer and a back-side metallization layer, such that the front-side metallization layer is adjacent to the interposer or base die and the back-side metallization layer (on the opposite side of the device layer from the front-side metallization layer) is on top of the second-level die (e.g., compute die). Such structures and architectures provide a highly efficient interface for the second level die (e.g., compute die) and the overall system. For example, the upper power architecture and routing discussed herein reduces IR drop due to reduced routing lengths, removes via and routing limitations through the base die, reduces base die area requirements (e.g., due to the elimination of voltage regulators and vias for power delivery), thereby reducing die size and cost, and allows additional intellectual property (IP) to be moved to the base die, freeing up compute area for cores / compute blocks and increasing efficiency. Other advantages will become apparent based on the disclosure below.

[0015] In some embodiments, a microelectronic device includes a multi-chip composite architecture including a base die and one or more integrated circuit (IC) dies attached to the base die. As used herein, the term microelectronic device refers to a device including one or more integrated circuits for providing one or more functions. A microelectronic device may be at any level, such as a packaged device, an assembly, an assembled motherboard, or a consumer product. The term multi-chip composite device refers to a device having several chips or dies integrated and formed into a semi-monolithic structure. For example, a semi-monolithic structure may have a semi-monolithic hierarchical integration of IC dies, such as a base die, IC dies, or chiplets, that combine to form a composite structure of a processing system. In particular, the term composite indicates that a structure has multiple components, such as an active die and dielectric material on and between the active dies. As used herein, the terms base die, IC die, and chiplet refer to dies or chips that are passive or have active circuitry (i.e., circuitry that provides electronic or device functionality during operation). For example, the base die, IC die, and chiplet may include processor circuitry, memory circuitry, control circuitry, signal and power routing circuitry, etc. The term IC die may be used generically, and the term base die refers to an IC die deployed as a bottom or base layer die of a multi-chip composite device. The term chiplet may be expanded to refer to a top or mid-level IC die of a multi-chip composite device, although such die may be referred to simply as an IC die.

[0016] In particular, higher-level IC dies or dies typically include functional circuitry, while the base die may or may not include functional circuitry (and may include only integrated metallization routing). Such IC dies may include a device layer between the front-side and back-side metallization of the IC die. In some embodiments, a multi-chip composite device or architecture includes an IC die above and coupled to a base die. The IC die has a device layer between first and second stacks of metallization layers, with the first being proximal to the base die. The first stack of metallization layers provides signal routing for signals received through the base die up to the device layer. The second stack of metallization layers provides power routing (e.g., power and ground routing) up to the device layer, with the second stack typically having thicker and fewer metal lines for these purposes, as discussed further herein below.

[0017] The multi-chip composite device or architecture further includes a metallization network above the IC die and coupled to the second stack of metallization layers. The metallization network includes one or more thick metallization layers (e.g., each having a thickness greater than or equal to five times, or even ten times, the thickness of either the first or second stack of metallization layers). A via is adjacent to the base die and coupled to the metallization network and an external interconnect such that a power route is provided to the second stack of metallization layers on the top side of the IC die. The power route may include the external interconnect, the via, and a portion of the metallization network. The metallization network may be formed using any of the techniques discussed herein below.

[0018] Additionally, a multi-chip composite device may include one or more dielectric materials laterally adjacent to one or more IC dies or chiplets, above a region of a base die, and / or laterally adjacent to the base die. For example, a dielectric material may be formed over or around a die, embedding some or all of the die in the dielectric material. In some embodiments, the dielectric material includes one or more inorganic dielectric materials. As used herein, the term inorganic dielectric material refers to a material that does not have carbon-hydrogen bonds and is characterized as an electrical insulator. For example, an inorganic dielectric material may have a resistivity similar to that of silicon dioxide. Although carbon may not be a fundamental component of an inorganic dielectric material, an inorganic dielectric material may include carbon, for example, as a dopant. In some embodiments, the dielectric material includes one or more organic dielectric materials. As used herein, the term organic dielectric material refers to a material that has carbon-hydrogen bonds and carbon chains, and the material is characterized as an electrical insulator. FIG. 1 shows a cross-sectional side view of a multichip composite device 100 including an upper metallization network 107 that provides a power route to a backside 119 of an integrated circuit die 101, arranged in accordance with some embodiments. Region 130 of multichip composite device 100 is shown in more detail in FIG. 3 herein below. For example, multichip composite device 100 may be deployed in any microelectronic device. Multichip composite device 100 may include any number of IC dies 101 (which may be characterized as chiplets) coupled to the upper surface of any number of base dies 102. Additionally, multichip composite device 100 may include any number of chiplets or components that are laterally disposed relative to IC dies 101 and / or base die 102, such as voltage regulator (VR) die 103. While shown with VR die 103, which may be a silicon substrate-based voltage regulator and / or power delivery network, multichip composite device 100 may omit VR die 103 and use direct pass-through power delivery. Although two levels of die are shown in the example of FIG. 2, multi-chip composite device 100 may include any number of levels of die, such as three or more levels of die.

[0019] The base die 102 includes through vias 125 (e.g., through silicon vias (TSVs)). As discussed, the terms IC die and chiplet refer to active circuit devices (i.e., circuits that, during operation, provide computing functionality). For example, an IC die or chiplet may contain circuitry that performs a defined subset of functionality, such as a memory chip, a microprocessor, a microcontroller, or a commodity IC (e.g., a chip used for repetitive processing routines, simple tasks, application-specific ICs, etc.). The term base die also refers to an active circuit device, which may also be characterized as an IC die. For example, IC dies, such as chiplets and base dies, may be individual dies connected to create the functionality of a monolithic IC. As shown, the base die 102 is at the lowest or base layer of the multi-chip composite device 100. Furthermore, the base die 102 may be interconnected to the microelectronic substrate 104 via interconnects 111. For example, the interconnects 111 may be package-level interconnects that couple to the microelectronic substrate 104, such as a package substrate, board, or motherboard. The interconnects 111 may be interconnect posts or pads, solder bumps or balls, interconnects formed from conductive films or conductive pastes, or the like.

[0020] The IC die 101 can be bonded to the base die or die 102 using any suitable technique or techniques, such as hybrid bonding, to form the die-level interconnect 112. In some embodiments, surfaces including metallization, interspersed between dielectric materials, can be formed on each of the IC die 101 and the base die or die 102. In some embodiments, patterning of the surfaces mates metal-to-metal and dielectric-to-dielectric for the hybrid bond. The surfaces are then brought together, optionally under pressure and / or heat, to fuse the metals to form the die-level interconnect 112 and, optionally, to fuse the dielectric materials to form the hybrid bond. As shown with respect to a close-up view, in some embodiments, the die-level interconnect 112 can include a misalignment 117 indicative of a hybrid bond. The misalignment 117 includes, for example, a first sidewall 114 that is misaligned with a second sidewall 116 such that there is a lateral offset 115 (i.e., measured in the x-dimension) therebetween. In some embodiments, lateral offset 113 is in the range of 10 to 200 nm. While any thickness can be used, in some embodiments, base die or die 102 and IC die 101 can have a thickness between 20 and 150 microns, and IC die 101 can have a thickness between 20 and 50 microns. While shown with respect to die-level interconnect 112 being a hybrid-bonded interconnect, any interconnect can be deployed, such as a solder ball or solder feature.

[0021] As described in more detail below, IC die 101 has a backside 119 and a frontside 120. Such terms are used in accordance with common knowledge in the art and refer to the build-up direction of the fabrication of IC die 101. In particular, the terms frontside and backside may be oriented so that either side faces up in the assembly or other structure of multi-chip composite device 100. For example, a device layer may be formed on the frontside above a substrate such that the frontside metallization is on or above the device layer, and the backside is opposite the frontside of the device layer. The device layer of IC die 101 and / or base die 102 may include any suitable devices, such as transistors, capacitors, resistors, etc. The backside metallization may be formed opposite the frontside metallization for the device layer using any suitable technique or techniques, such as attachment to a carrier wafer, backside grinding to expose the device layer (and buried through vias), and metallization fabrication processing (such as dual damascene processing) as known in the art. In the context of the multi-chip composite device 100 , the metallization die 106 includes a substrate 108 and a metallization network 107 .

[0022] Metallization network 107 may be constructed on substrate 108, and metallization network 107 may include any number of relatively thick metallization levels 131, including metal lines or routes, such that metallization levels 131 are interconnected by via levels 132 (e.g., via layers). Metallization levels 131 are thicker than the metal layers of the front-side metallization and back-side metallization of IC die 101. For example, each of metallization levels 131 may have a thickness five times or more than the thickness of any of the metal layers of the front-side metallization and back-side metallization of IC die 101. In some embodiments, metallization network 107 may be characterized as a redistribution layer, and metallization die 106 may be characterized as a redistribution die or substrate. While shown as having three metallization levels 131, metallization network 107 may include any number, such as a single metal layer 131, two metallization levels 131, four metallization levels 131, or more. In some embodiments, metallization network 107 includes several metallization levels 131 formed on substrate 108 and coupled to IC die 101 and / or VR die 103 by interconnects 109. While shown with interconnects 109 being solder balls or solder features, any interconnects may be used, such as hybrid-bonded interconnects. In some embodiments, metallization network 107 includes several wire bonds or bond wires formed between IC die 101 and / or VR die 103. In some embodiments, metallization network 107 includes several thick metal layers fabricated directly on or above IC die 101 and / or VR die 103.

[0023] As shown, the metallization network 107 is coupled to the microelectronic substrate 104 by one or more vias 110, which may be embedded in an inorganic dielectric material 128. The inorganic dielectric material 128 may be any suitable material, such as silicon oxide, silicon nitride, silicon oxynitride, carbon-doped silicon oxide, or the like. For example, the vias 110 may be characterized as through-dielectric vias (TDVs) or pillars, such as copper pillars. The vias 110 are laterally adjacent to the base die 102 and couple to interconnects 111 for electrical attachment to the microelectronic substrate 104. As used herein, the term laterally adjacent indicates that at least a portion of the components are aligned in the xy plane (i.e., orthogonal to the vertical build-up direction discussed). The vias 110 may be made of any suitable conductive material or materials, such as copper, silver, nickel, gold, and aluminum, and alloys thereof. In the context of multi-chip composite device 100, interconnects 111, vias 110, VR die 103 (if deployed), and metallization network 107, as applicable, provide power routing (and optional IO routing) to backside 119 of IC die 101, while interconnects 111 and base die 102, as applicable, provide IO routing to frontside 120. As used herein, power refers to the power supply for operating the device (and includes power and ground), while IO refers to the signals under which the device is operating.

[0024] The IC die 101, the base die 102, and the metallization die 106 may include any suitable substrate and associated device components. In some embodiments, the IC die 101 and / or the base die 102 are semiconductor dies having device layers and metallization layers fabricated using known semiconductor manufacturing processes. In some embodiments, the substrate of any of the IC die 101, the base die 102, and the metallization die 106 is a substantially single-crystalline semiconductor, such as silicon or germanium, although other material systems may be developed. In some embodiments, the substrate 108 of the metallization die 106 is a silicon substrate, and the substrate 108 acts as a heat spreader to remove heat from the IC die 101. For example, the substrate 108 and / or the metallization network 107 may act as a heat spreader to remove heat from the IC die 101. In some embodiments, the substrate 108 is or includes a material that facilitates heat removal. In some embodiments, substrate 108 is or includes silicon, aluminum, nitride, aluminum, copper, or other thermally conductive material. In such a context, substrate 108 may be characterized as a passive integrated heat spreader. In some embodiments, metallization network 107 may be fabricated over an active heat removal device, such as a heat pipe, a thermoelectric cooler, or the like. In such a context, the underlying device (on which metallization network 107 is fabricated) may be characterized as an active integrated heat spreader.

[0025] In some embodiments, the substrate 108 is a glass substrate. The glass substrate can have any suitable properties. In some embodiments, the glass substrate is or includes a layer of glass (e.g., a glass core). In some embodiments, the glass substrate is an amorphous solid glass layer. In some embodiments, the glass substrate is or includes a layer of glass, for example, one of aluminosilicon, borosilicon, alumino-borosilicon, silica, and quartz glass. The glass layer can include one or more additives including Al2O3, BO3, MgO, CaO, SrO, BaO, SnO2, Na2O, KO, PO3, ZrO2, Li2O, Ti, or Zn. For example, the glass layer can include additives including one or more of aluminum, boron, magnesium, calcium, strontium, barium, tin, sodium, potassium, phosphorus, zirconium, lithium, titanium, or zinc. In some embodiments, the glass layer may include silicon and oxygen and one or more of aluminum, boron, magnesium, calcium, strontium, barium, tin, sodium, potassium, phosphorus, zirconium, lithium, titanium, and zinc. In some embodiments, the glass layer includes at least 23 weight percent silicon and at least 26 weight percent oxygen, and further includes at least 5 weight percent aluminum. In some embodiments, the glass layer is rectangular in plan view; however, other shapes may be used. In some embodiments, the glass substrate is free of any organic adhesives or other organic materials.

[0026] As shown, the base die 102 is coupled to the microelectronic substrate 104 by interconnects 111. The microelectronic substrate 104 can be any suitable structure or carrier. In some embodiments, the microelectronic substrate 104 includes a dielectric material layer, which may include a build-up film and / or a solder resist layer, and may be composed of any suitable dielectric material, including, but not limited to, bismaleimide triazine resin, flame-retardant grade 4 material, polyimide material, silica-filled epoxy material, glass-reinforced epoxy material, and low-temperature co-fired ceramic material, as well as low-k and ultra-low-k dielectrics (dielectric constants less than about 3.6), including, but not limited to, carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymer dielectrics, and fluoropolymers. The microelectronic substrate 104 may further include conductive paths or metallization extending through the microelectronic substrate 104, such that the conductive paths can be a combination of conductive traces and conductive vias extending through the dielectric material layer, similar to other metallization layers discussed herein. The conductive traces and conductive vias may be made of any suitable conductive material or materials, including, but not limited to, metals such as copper, silver, nickel, gold, and aluminum, and alloys thereof. The microelectronic substrate 104 may be a cored or coreless substrate. In some embodiments, components, such as passive components 118, may be deployed on the backside of the microelectronic substrate 104.

[0027] As shown, microelectronic substrate 104 includes external interconnects 105 for coupling to external devices (not shown). In some embodiments, external interconnects 105 may be provided on bond pads on the opposite surface of microelectronic substrate 104 to that of interconnects 111. External interconnects 105 may be any suitable conductive material, including, but not limited to, metal-filled epoxies and solders, such as tin, lead / tin alloys (e.g., 63% tin / 37% lead solder), and high-tin alloys (e.g., 90% or more tin, e.g., tin / bismuth, eutectic tin / silver, ternary tin / silver / copper, eutectic tin / copper, and similar alloys). External interconnects 105 may be used to attach microelectronic substrate 104 to an external substrate (not shown), such as a motherboard.

[0028] FIG. 2 illustrates a side cross-sectional view of electrical routing 200 in a multi-chip composite device 100 arranged according to some embodiments. As shown, in some embodiments, power routing 121 is provided on the top side of one or more IC dies 101, including the backside 119 and corresponding backside metallization of the IC dies 101. In FIG. 2, power routing 121 is illustrated using two double-headed arrows with darker shading compared to that of IO routing 122. As discussed, power or power routing refers to the routing of power (including power and ground) for operating the device, such that power routing 121 includes any conductive vias, paths, metallization, and any intervening devices between the power and device layers of one or more IC dies 101. In the context of FIG. 2, power routing 121 includes one or more interconnects 111, vias 110, VR die 103, and metallization network 107, and die-level interconnect 112. However, in some embodiments, power routing 121 does not include VR die 103. For example, voltage regulation may be provided by components embedded within metallization network 107 (and mounted to substrate 108), by components mounted to microelectronic substrate 104, or by components otherwise deployed in multi-chip composite device 100.

[0029] 2 further illustrates signal or IO routing 122, including conductive vias, routes, metallization, and any intervening devices, etc., for providing signal routing to one or more IC dies 101. As shown, IO routing 122 is provided on the bottom side of one or more IC dies 101, including front side 120 and corresponding front side metallization of IC die 101. IO routing 122 is again illustrated using two double-headed arrows, and IO routing 122 provides signals for devices operating below it. IO routing 122 includes any conductive vias, routes, metallization, and any intervening devices between external signal routes and device layers of one or more IC dies 101. In the context of FIG. 2, IO routing 122 includes one or more interconnects 111, base die 102 (using through vias 125), and die-level interconnects 112.

[0030] Removing power routing 121 from the same path and physical space used by IO routing 122 provides the discussed advantages, such as freeing up the front-side metallization layers and through-vias 125 of IC die 101 for additional IO routing, having a thicker power delivery path by expanding top-side metallization network 107, and having a more direct route down to the device layer.

[0031] 3 illustrates an enlarged cross-sectional side view 300 of region 130 of multi-chip composite device 100, arranged in accordance with some embodiments. As shown in FIG. 3 , multi-chip composite device 100 includes metallization network 107 overlying IC die 101 and coupled thereto by interconnects 109. For example, interconnects 109 may be part of interconnect layer 133. IC die 101 overlies base die 102 and is coupled thereto by die-level interconnects 112. For example, die-level interconnects 112 may be part of die-level interconnect layer 138. As shown, IC die 101 includes device layer 135 between front-side metallization 136 and back-side metallization 134.

[0032] As discussed, front-side metallization 136 may be formed above the front side of device layer 135, after which back-side metallization 134 may be formed opposite front-side metallization 136 on device layer 135 (by carrier wafer attachment, back-side grinding, and metallization). Furthermore, metallization network 107 provides power delivery through back-side metallization 134, while base die 102 provides IO routing through front-side metallization 136. In some embodiments, back-side metallization 134 includes thicker metallization (e.g., metal lines or layers having a greater thickness in the z-dimension) than that of front-side metallization 136. Furthermore, metallization 136 may have fewer metallization layers (e.g., layers of metal lines) than front-side metallization 136. For example, thicker metallization may provide more efficient power delivery, while more metallization layers are required due to the complexity of IO signaling.

[0033] The metallization network 107 may include any number of metallization levels 131 and intervening via levels 132. The term metallization level refers to a network of substantially coplanar metal lines or conductive paths. A via level includes a network of substantially coplanar metal vias or conductive plugs that interconnect the metallization levels. In the example shown, the metallization network 107 has four metallization levels (M0, M1, M2, M3) and three intervening via levels (V1, V2, V3). However, any number of metallization levels and via levels may be used. In some embodiments, a single metallization level is deployed. Similarly, the backside metallization 134 and the frontside metallization 136 each include several metallization levels and intervening via levels. Individual metallization levels and intervening via levels of the backside metallization 134 and the frontside metallization 136 are described further herein below.

[0034] In some embodiments, each metallization level of the backside metallization 134 has a thickness Tbs, which may be the same for each metallization level of the backside metallization 134, or the thickness Tbs of each level may increase as one moves away from the device layer (i.e., in the positive z-direction). Similarly, each metallization level of the frontside metallization 136 has a thickness Tfs, which again may be the same for each metallization level of the frontside metallization 136, or the thickness Tfs of each level may increase as one moves away from the device layer (i.e., in the negative z-direction). As also shown, the metallization levels of the metallization network 107 have a thickness Tn. As with the other metallization layers, each metallization level of the metallization network 107 may have the same thickness, or the thickness Tn of each level may increase as one moves away from the IC die 101 (i.e., in the positive z-direction).

[0035] In some embodiments, each metallization level of the backside metallization 134 is thicker than all metallization levels of the frontside metallization 136. That is, the thickest metallization level of the frontside metallization 136 may have a thickness Tfs that is less than the thickness Tbs of the thinnest metallization level of the backside metallization 134. In some embodiments, each metallization level of the backside metallization 134 is at least as thick as all metallization levels of the frontside metallization 136. For example, the thickest metallization level of the frontside metallization 136 may have a thickness Tfs that is less than or equal to the thickness Tbs of the thinnest metallization level of the backside metallization 134.

[0036] Additionally, the backside metallization 134 may have fewer metallization levels than the number of metallization levels of the frontside metallization 136. In some embodiments, the number of metallization levels of the backside metallization 134 is fewer than the number of metallization levels of the frontside metallization 136. In some embodiments, the difference between the number of metallization levels of the frontside metallization 136 and the number of metallization levels of the backside metallization 134 is 3 or more. In some embodiments, the difference between the number of metallization levels of the frontside metallization 136 and the number of metallization levels of the backside metallization 134 is 4 or more or more.

[0037] Each metallization level 131 of the metallization network 107 is much thicker than all of the metallization levels of the front side metallization 136 and the back side metallization 134. In some embodiments, the thickness Tn of the thinnest metallization level of the metallization network 107 is a multiple of or an order of magnitude greater than the thickness Tbs of the thickest metallization level of the front side metallization 136 and the back side metallization 134. In some embodiments, the thickness Tn of the thinnest metallization level of the metallization network 107 is five times or more greater than the thickness Tbs of the thickest metallization level of the front side metallization 136 and the back side metallization 134. In some embodiments, the thickness Tn of the thinnest metallization level of the metallization network 107 is ten times or more greater than the thickness Tbs of the thickest metallization level of the front side metallization 136 and the back side metallization 134. In some embodiments, the thickness Tn of the thinnest metallization level of the metallization network 107 is 25 times or more the thickness Tbs of the thickest metallization level of the front side metallization 136 and the back side metallization 134. In some embodiments, the thickness Tn of the thinnest metallization level of the metallization network 107 is 50 times or more the thickness Tbs of the thickest metallization level of the front side metallization 136 and the back side metallization 134. In some embodiments, the thickness Tn of the thinnest metallization level of the metallization network 107 is 100 times or more the thickness Tbs of the thickest metallization level of the front side metallization 136 and the back side metallization 134.

[0038] In some embodiments, the metallization levels 131 of the metallization network 107 are thicker than the metallization levels of the backside metallization 134, which are thicker than the metallization levels of the frontside metallization 136. In some embodiments, the thickness Tfs of each of the metallization levels of the frontside metallization 136 is 1 micron thick or less. In some embodiments, the thickness Tfs of each of the metallization levels of the frontside metallization 136 is 500 nm thick or less. In some embodiments, the thickness Tbs of each of the metallization levels of the backside metallization 134 is on the order of 1 micron thick. In some embodiments, the thickness Tbs of each of the metallization levels of the backside metallization 134 is 1.5 microns thick or less. In some embodiments, the thickness Tbs of each of the metallization levels of the backside metallization 134 is 1.0 micron thick or less.

[0039] In contrast, the metallization levels 131 of the metallization network 107 are several orders of magnitude larger. In some embodiments, the thickness Tn of each of the metallization levels 131 of the metallization network 107 is 10 microns thick or greater. In some embodiments, the thickness Tn of each of the metallization levels 131 of the metallization network 107 is 25 microns thick or greater. In some embodiments, the thickness Tn of each of the metallization levels 131 of the metallization network 107 is 50 microns thick or greater. In some embodiments, the thickness Tn of each of the metallization levels 131 of the metallization network 107 is in the range of 10 to 100 microns thick. The metallization network 107 further has a total thickness Tnt (total network thickness). As discussed herein below, components may be embedded within the total thickness Tnt of the metallization network 107.

[0040] That is, the thickest metallization level of the front-side metallization 136 may have a thickness Tfs that is less than the thickness Tbs of the thinnest metallization level of the back-side metallization 134. In some embodiments, each metallization level of the back-side metallization 134 has a thickness at least as thick as all metallization levels of the front-side metallization 136. For example, the thickest metallization level of the front-side metallization 136 may have a thickness Tfs that is less than or equal to the thickness Tbs of the thinnest metallization level of the back-side metallization 134.

[0041] In some embodiments, IC die 101 further includes substrate layer 137, which includes through via 144. Via 144 extends from die-level interconnect layer 138 to front-side metallization 136, and via 144 may be made of any suitable conductive material, such as copper. In some embodiments, IC die 101 includes back-side via 143, which extends from interconnect layer 138 to back-side metallization 134. Back-side via 143 may also be any suitable conductive material, such as copper. Via 144 and back-side via 143 may be formed using any suitable technique or techniques and may extend through substrate layer 137, thereby providing structural support during manufacturing. In some embodiments, one or both of via 144 and back-side via 143 are unexpanded.

[0042] As also shown, the base die 102 may include a device layer 141 between a front side metallization 140 and a back side metallization 139. In some embodiments, the base die 102 does not include such a layer, and instead includes only through vias 125. In some embodiments, the base die 102 further includes vias 145 and front side vias 143. The device layer 141, front side metallization 140, back side metallization 139, vias 145, and front side vias 143 may have any of the characteristics discussed above with respect to the device layer 135, front side metallization 136, back side metallization 134, vias 144, and back side vias 143. Notably, in the context of FIG. 3 , the front side metallization 136 and the back side metallization 139 are proximate to one another.

[0043] FIG. 4 illustrates an enlarged cross-sectional side view 400 of region 130 of a multichip composite device 100 having an inverted base die 102 arranged in accordance with some embodiments. As illustrated in FIG. 4, the base die 102 may be positioned relative to the multichip composite device 100 of FIG. 3 such that front-side metallization 136 and front-side metallization 140 are proximate to one another. In other variations, the components of the multichip composite device 100 may have any of the characteristics discussed herein. Note also that the base die 102 may not include the device layer 141, such that it provides only redistribution, and the base die 102 may be characterized as an interposer. In other examples, the base die 102 may include only the front-side metallization 140 (e.g., the base die 102 may not have the back-side metallization 139). Other base die 102 architectures may be used.

[0044] 5 illustrates a cross-sectional side view 500 of IC die 101 showing further details of device layer 135, front-side metallization 136, and back-side metallization 134 arranged according to some embodiments. Front-side metallization 136 and back-side metallization 134 may be formed using any suitable technique or techniques, such as dual damascene, single damascene, or subtractive metallization patterning techniques. As discussed, interconnectivity, signal routing, IO routing, and the like may be provided by front-side metallization 136. Front-side metallization 136 includes any number of metallization and via levels 501, with via levels between and interconnecting the metallization levels. For example, metal routes or lines 503 in metallization levels are interconnected by vias, such as via 504.

[0045] As shown, in some embodiments, front-side metallization 136 is formed over one side of device layer 135, which may include transistor structure 160. In the context of FIG. 5 , transistor structure 160 is a gate-all-around field effect transistor (GAA-FET), but transistor structure 160 may be any suitable device, such as a planar FET or FinFET, or device layer 135 may include other functional device structures. In the illustrated example, front-side metallization 136 includes M0, V0, M1, M2 / V1, M3 / V2, M4 / V3, M5 / V4, M6 / V5, M7 / V6, and M8 / V7. However, M4 / V3 may include any number of metallization levels and corresponding via levels, e.g., 6, 8, or more metallization layers.

[0046] Similarly, the backside metallization 134 may include any number of thicker metallization and via levels 502 (as discussed above). For example, the metallization and via levels 502 may include backside metallization level 0 (BM0), backside via level 0 (BV0), backside metallization level 1 (BM1), backside via level 1 (BV1), and backside metallization level 2 (BM2), etc. As shown, interconnect 109 may contact the backside metallization level of the backside metallization 134 for interconnection to the metallization network 107. The backside metallization 134 is formed above and directly adjacent to the device layer 135, and opposite the frontside metallization 136 of the device layer 135. In the illustrated example, the metallization levels of the backside metallization 134 include BM0, BM1, and BM2, along with intervening via layers. However, the backside metallization 134 may include any number of metallization levels, for example, four, five, or more metallization layers.

[0047] FIG. 6 shows a cross-sectional side view 600 of a metallization die 106, illustrating further details of the metallization network 107, arranged according to some embodiments. The metallization network 107 may be formed using any suitable technique or techniques, such as dual damascene, single damascene, or subtractive metallization patterning techniques. In the illustrated example, the metallization network 107 is fabricated on a substrate 108 as part of the metallization die 106. However, in other contexts, the metallization network 107 may be formed directly on the IC die 101 or from wirebond techniques, as discussed further herein below. The metallization network 107 provides topside power routing to the IC die 101 via connections through interconnects 109. In some embodiments, the metallization network 107 may further provide optional IO routing, as discussed further herein below.

[0048] Metallization network 107 may include any number of thicker metallization levels 131 and via levels 132. For example, metallization levels 131 and via levels 132 may include power network metallization level 0 (NM0), power network via level 0 (NV0), power network metallization level 1 (NM1), power network via level 1 (NV1), and power network metallization level 2 (NM2), etc. As shown, interconnect 109 may contact a backside or via metallization level of metallization network 107 for interconnection to IC die 101 using interconnect 109. In some embodiments, metallization network 107 is formed above or on substrate 108. In the illustrated example, metallization network 107 includes three metallization levels 131 and two intervening via levels 132. However, metallization network 107 may include any number of metallization layers, for example, 1, 2, 4, 5, or more metallization layers.

[0049] 7 illustrates a side cross-sectional view of electrical routing 700 in multi-chip composite device 100 arranged according to some embodiments. As discussed with respect to FIG. 2, in some embodiments, power routing 121 is provided on the top side of IC die 101 and couples directly to the backside metallization of IC die 101, and signal or IO routing 122 is routed through base die 102 to the frontside metallization of IC die 101.

[0050] 7 , in some embodiments, signal or IO routing 122 includes a first routing 704 from the microelectronic substrate 104 through the interconnects 111 to the base die 102, and a second routing 703 from the base die 102 through the die-level interconnects 112 to the IC die 101. For example, the base die 102 may passively route the IO routing 122 from the microelectronic substrate 104 to the IC die 101 (e.g., using through vias 125), or the base die 102 may handle the signals as part of the IO routing 122. As also shown in FIG. 7 , power may be provided to the base die 102 through power routing 701. In some embodiments, the power routing 701 is from the microelectronic substrate 104 through the interconnects 111 to the base die 102.

[0051] 8 illustrates a side cross-sectional view of electrical routing 800 in a multi-chip composite device 100 having multiple integrated circuit dies 101 arranged according to some embodiments. As shown in FIG. 8 , power routing 121 can be provided on the top side of any number of IC dies 101 through metallization network 107. Additionally, in some embodiments, signal or IO routing 122 can further include third routing 801 from the base die 102 to another IC die 101 through die-level interconnect 112. The base die 102 can passively provide second routing 703 and third routing 801, or the base die 102 can manipulate signals as part of the IO routing 122.

[0052] 8 , metallization network 107 can be used to provide signal or IO routing 802 between IC dies 101 in addition to power routing 121. For example, signal or IO routing 802 can extend from the front-side metallization of a first one of the IC dies 101, through a particular one of the interconnects 109, through metallization network 107, through one of the interconnects 109, and to a second one of the IC dies 101. For example, metallization network 107 can provide additional routing and architectural flexibility in addition to that provided by moving power routing 121 to metallization network 107. In some embodiments, signal or IO routing 802 can be characterized as an IO bridge, and signal or IO routing 802 can relieve the base die from some of the IO routing.

[0053] 9 illustrates a side cross-sectional view of electrical routing 900 in a multi-chip composite device 100 having multiple base dies 102 arranged according to some embodiments. As shown in FIG. 9 , power routing 121 is provided on the top side of the IC die 101 and is directly coupled to the backside metallization of the IC die 101. Additionally, electrical routing 900 includes multiple IO routings 122, each including a first routing 704 from the microelectronic substrate 104 to one of the base dies 102 through interconnects 111, and a second routing 703 from each of the base dies 102 to the IC die 101 through die-level interconnects 112. The base die 102 may passively route the IO routing 122, or the base die 102 may manipulate signals as part of the IO routing 122.

[0054] 10 shows a cross-sectional side view of a multi-chip composite device 1000 including an upper metallization network 107 fabricated from one or more directly applied metallization levels 1001 to provide a power route to the backside 119 of an integrated circuit die 101, arranged in accordance with some embodiments. As discussed, in some embodiments, the upper metallization network 107 may be formed on a substrate 108 as part of a metallization die 106, which may be bonded to the backside 119 of the IC die 101.

[0055] In other embodiments, metallization network 107 may be formed above the IC die, such as on the surface of interconnect layer 133. For example, the top surface of interconnect layer 133 may include exposed portions of interconnects 109 that are substantially coplanar with dielectric material 1002. Metallization network 107 may then be formed on the surface using any suitable technique or techniques. In some embodiments, metallization network 107 is formed using an additive processing technique. In some embodiments, metallization network 107 is formed using a screen printing technique. Any number of metallization levels (i.e., one or more) and intervening via levels (if multiple metallization levels are deployed) may be fabricated, and metallization network 107 (substrate 108 is not present) may have any of the properties discussed elsewhere herein.

[0056] 11 illustrates a cross-sectional side view of a multichip composite device 1100 including a second integrated circuit die level on an upper metallization network 107, arranged according to some embodiments. For example, multichip composite device 1100 is similar to multichip composite device 1000 after attachment of IC die 1101 to metallization network 107 and formation of dielectric material 1102. In some embodiments, metallization network 107 is fabricated using additive techniques, as discussed with respect to FIG. 10, such that a top surface of metallization network 107 is exposed for attachment of IC die 1101. In other embodiments, substrate 108 may be removed to expose metallization network 107 for attachment of IC die 1101. For example, substrate 108 may be removed using grinding techniques, etching techniques, or a combination thereof.

[0057] IC die 1101 may have any of the characteristics discussed herein with respect to IC die 101, such that IC die 1101 includes backside metallization on backside 119 and frontside metallization on frontside 120. The backside metallization on backside 119 is opposite the frontside metallization on frontside 120 of the device layer (see FIG. 5 ). In particular, backsides 119 of both IC die 101 and IC die 1101 are proximal to metallization network 107 for direct power delivery to the backside metallization layers of IC die 101 and IC die 1101. Signal and IO routing may be provided to IC die 1101 through metallization network 107 and IC die 101, or through alternative routing laterally adjacent to metallization network 107, IC die 101, and base die 102.

[0058] FIG. 12 illustrates a cross-sectional side view of a multichip composite device 1200 having a component 1201 positioned within the thickness of an upper metallization network 107, according to some embodiments. As illustrated with respect to FIGS. 3, 4, and 6, the metallization network 107 has a total thickness Tnt. In some embodiments, the total thickness Tnt of the metallization network 107 is in the range of about 25 to 500 microns. In some embodiments, such a total thickness of the metallization network 107 allows the component 1201 to be inserted completely within the total thickness Tnt of the metallization network 107. For example, opposing sides of the component 1201 orthogonal to the z-direction can be completely within the total thickness Tnt of the metallization network 107.

[0059] Component 1201 can be any suitable active or passive component, such as an IC die, a voltage regulator, a capacitor, an inductor, or a circuit including such a device. In some embodiments, component 1201 is attached to a surface of substrate 108, and metallization network 107, including metallization level 131, via level 132, and dielectric material 128, is built up adjacent to component 1201. In some embodiments, component 1201 is an inductor attached directly to the surface of substrate 108 such that metallization network 107 is on the same surface of substrate 108. In some embodiments, a component, such as an inductor, is deployed on microelectronic substrate 104.

[0060] 13 shows a cross-sectional side view of a multichip composite device 1300 having an upper metallization network 107 of bond wires 1301 arranged in accordance with some embodiments. As discussed herein, the metallization network 107 may include several metallization levels 131 with via levels 132 therebetween, such that the metallization levels 131 include substantially planar metallization features, such as conductive paths or metal lines (see FIG. 4 ). In some embodiments, the metallization network 107 instead includes several bond wires 1301 embedded in a molding material 1302.

[0061] Bond wires 1301 may be formed using any suitable technique or techniques to couple bond pads between IC die 101 and VR die 103. In some embodiments, bond wires 1301 form an inductor between IC die 101 and VR die 103. For example, molding material 1302 may be a magnetic material. Bond wires 1301 may have any thickness discussed herein with respect to metallization level 131 to form an efficient metallization network 107. In some embodiments, the thickness of each of bond wires 1301 may be the diameter or width of bond wire 1301 orthogonal to the respective length dimension of bond wire 1301.

[0062] In some embodiments, the width of each of the bond wires 1301 of the metallization network 107 is five times or more the thickness Tbs of the thickest metallization level of the front side metallization 136 and the back side metallization 134 . In some embodiments, the width of each of the bond wires 1301 of the metallization network 107 is 10 times or more the thickness Tbs of the thickest metallization level of the front side metallization 136 and the back side metallization 134 . In some embodiments, the width of each of the bond wires 1301 of the metallization network 107 is 25 times or greater than the thickness Tbs of the thickest metallization level of the front side metallization 136 and the back side metallization 134 . In some embodiments, the width of each of the bond wires 1301 of the metallization network 107 is 50 times or greater than the thickness Tbs of the thickest metallization level of the front side metallization 136 and the back side metallization 134 . In some embodiments, the width of each of the bond wires 1301 of the metallization network 107 is 100 times or more the thickness Tbs of the thickest metallization level of the front side metallization 136 and the back side metallization 134 .

[0063] 14 is a flow diagram 1400 illustrating a method for forming a multichip composite device including an upper metallization network for providing a power route to the backside of an integrated circuit die, arranged in accordance with at least some implementations of the present disclosure. Figures 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, and 30 are cross-sectional side views of integrated circuit (IC) device structures, arranged in accordance with some embodiments of the present disclosure, that develop as method 1400 is performed.

[0064] Method 1400 begins with input operation 1401, where a workpiece is received for processing. For example, fully or partially fabricated IC die, base die, VR die, metallization die, and other components may be received for processing. The received die may be part of a substrate structure, or they may be diced from a substrate. In some embodiments, the discussed multi-chip composite devices may be fabricated on a reconstructed wafer using die-to-wafer bonding, such that an IC die is bonded to a base die (as a reconstructed base die wafer) or a base die is bonded to an IC die (as a reconstructed IC die wafer). In some embodiments, wafer-to-wafer bonding techniques are used. Additionally, either before or after attachment, other components, such as through-dielectric vias adjacent to the base die or a metallization network above the IC die, may be fabricated. For example, method 1400 includes exemplary fabrication methods that may be performed out of sequence or using other techniques for fabricating the multi-chip composite devices discussed herein.

[0065] Processing continues at operations 1402 and 1404. At operation 1402, the diced or singulated IC die are tested, and those that pass the test are attached to a carrier wafer with their front-side metallization facing up (i.e., away from the carrier wafer). Testing may be performed using any suitable technique or techniques, such as bonding probe pins to conductive pads on the IC die and probing various paths of the IC die (using test circuitry). Those that pass the test are attached to the carrier wafer using any suitable technique or techniques, such as die-to-wafer bonding using adhesives, laminates, tape, etc. Similarly, at operation 1404, the diced or singulated base die is tested, and again is attached to the carrier wafer with their front-side metallization facing up (i.e., away from the carrier wafer). Testing may be performed using any suitable technique or techniques, such as those discussed with respect to operation 1402.

[0066] 15 shows a side cross-sectional view of an integrated circuit die 101 under test 1500. The IC die 101 includes or is attached to a substrate 1501. The IC die 101 further includes a front-side metallization 136, a device layer 135, a back-side metallization 134, and an optional substrate layer 137. As shown, the IC die 101 may be attached or mounted to a thermal head 1502, which provides temperature control and optional thermal stress during testing. Probe pins 1503 are coupled to the back-side metallization 134 and are used to test various components of the IC die 101, such as active or test components of the device layer 135.

[0067] FIG. 16 shows a cross-sectional side view of a device structure 1600 including several IC dies 101 attached to a carrier wafer 1601 with the backside metallization 134 proximal to the carrier wafer 1601 and the frontside metallization 136 facing up and away from the carrier wafer 1601 (i.e., the frontside metallization 136 is distal from the carrier wafer 1601). The carrier wafer 1601 can be of any suitable material in any suitable format. For example, the carrier wafer 1601 can be a monocrystalline silicon wafer. Although discussed in terms of a wafer format, any carrier format, such as a panel, can be used. The IC dies 101 can be attached to the carrier wafer 1601 using adhesives, laminates, tapes, etc., as known in the art.

[0068] 14 , processing continues from operation 1402 to operation 1403, where a dielectric or molding compound is formed around the attached IC die and above the carrier substrate. A backside grind is then performed to remove the substrate from above the front-side metallization and provide a flat surface for the dielectric or molding compound. Alternatively, the substrate can be removed, a dielectric or molding compound can be formed, and a planarization operation can be performed. The IC die and carrier wafer are then singulated so that each IC die now has its front-side metallization exposed and is ready for bonding to the base die, as discussed further herein below.

[0069] 17 shows a cross-sectional side view of a device structure 1700 similar to device structure 1600, having a dielectric material 1701 formed over and around IC die 101 such that IC die 101 is embedded in dielectric material 1701. Dielectric material 1701 can be any suitable dielectric material, such as an inorganic or organic dielectric material. In some embodiments, dielectric material 1701 is or includes one or more of silicon dioxide, silicon nitride, and silicon carbon nitride. In some embodiments, dielectric material 1701 is or includes a polymeric material. In some embodiments, dielectric material 1701 is a molding material. Dielectric material 1701 can be formed using any suitable deposition technique or techniques.

[0070] FIG. 18 shows a cross-sectional side view of a device structure 1800 similar to device structure 1700 after a backside material operation that removes substrate 1501 and a portion of dielectric material 1701. Such backside material operations may include any suitable technique, such as a backside grinding operation, a chemical removal or etching operation, a planarization operation, etc. As discussed, in some embodiments, dielectric material 1701 is applied after removal of substrate 1501, followed by planarization. As shown, a substantially flat surface 1802 of each of IC die 101 is exposed for die attach. In the embodiment shown, optional substrate layer 137 is left exposed, while in some embodiments, front-side metallization 136 is exposed. Additionally, device structure 1800 shows exemplary dicing or scribe lines 1801 along which IC die 101 is diced or segmented from carrier wafer 1601. Such diced IC die 101 may then be attached to a base die as discussed herein below with respect to FIG.

[0071] Referring to FIG. 14, as discussed, in operation 1404, the diced or singulated base die is tested and attached to a carrier wafer with the front side metallization facing up (i.e., away from the carrier wafer).

[0072] 19 shows a side cross-sectional view of a base die 102 under test 1900. The base die 102 includes or is attached to a substrate 1901, and the base die 102 may further include a front-side metallization 140, a device layer 141, a back-side metallization 139, and an optional substrate layer 142. As discussed herein, in some embodiments, the base die 102 does not include the device layer 141 and instead includes IO routing. In such a context, device testing is not required, but routing testing may still be performed. The base die 102 may be attached or mounted to a thermal head 1502 and may be tested using probe pins 1503 that couple to the back-side metallization 139.

[0073] 20 shows a side cross-sectional view of a device structure 2000 including a base die 102 attached to a carrier wafer 2001. Although shown with a single base die 102 attached to the carrier wafer 2001, any number of base dies may be attached to the carrier wafer 2001 for processing. As shown, the backside metallization 139 is proximal to the carrier wafer 2001 and the frontside metallization 140 faces up and away from the carrier wafer 2001. The carrier wafer 2001 may be of any suitable material in any suitable format, such as those discussed with respect to the carrier wafer 1601. The base die may be attached to the carrier wafer 2001 using an adhesive, a laminate, tape, or the like.

[0074] 14 , processing continues from operation 1404 to operation 1405, where a dielectric or molding material is formed around the attached base die and above the carrier substrate. A backside grinding is then performed to remove the substrate from above the front-side metallization and provide a flat surface for the dielectric or molding material. Alternatively, the substrate can be removed, a dielectric or molding material can be formed, and a planarization operation can be performed. A through-dielectric via is then fabricated adjacent to the base die such that the via is laterally adjacent to the base die and extends through the entire thickness of the base die. The fabricated via becomes part of the power routing to the backside metallization of one or more IC dies, as discussed herein.

[0075] 21 shows a side cross-sectional view of a device structure 2100 similar to device structure 2000 after removal of substrate 1901 and after formation of dielectric material 2101 laterally adjacent to base die 102. For example, dielectric material 2101 may be formed over and around base die 102 such that base die 102 is embedded in dielectric material 2101, and a backside material operation may be performed to remove substrate 1901 and portions of dielectric material 2101. Alternatively, dielectric material 2101 may be applied after removal of substrate 1901, followed by a planarization operation. Dielectric material 2101 may be any of the materials discussed with respect to dielectric material 1701. As shown, a substantially flat surface 2102 of device structure 2100 is exposed for die attach. In the embodiment shown, optional substrate layer 142 is left exposed, although in some embodiments, front-side metallization 140 is exposed.

[0076] FIG. 22 shows a cross-sectional side view of a device structure 2200, similar to device structure 2100, after fabrication of a via 110, which may be characterized as a through-dielectric via. The via 110 may be fabricated using any suitable technique or techniques. In some embodiments, an opening or hole is formed in the dielectric material 2101 using lithography and etching techniques, laser drilling techniques, or other patterning techniques. The resulting opening or hole is then filled with a conductive material using deposition and / or plating techniques, followed by a planarization operation to restore the substantially flat surface 2102. As shown, the via 110 is laterally adjacent to the base die 102 (i.e., in the x-y plane) and extends vertically (i.e., in the z-direction) through the entire thickness of the base die 102. Power routing may thereby bypass the base die 102 using the via 110.

[0077] 14 , processing continues from operations 1403 and 1405 to operation 1406, where the IC die formed in operation 1403 is mounted to the reconstructed base die wafer formed in operation 1405. While discussed with respect to an IC die being mounted to a reconstructed base die wafer, method 1400 may be used to form a diced base die (including adjacent dielectric material and through-dielectric vias) mounted to a reconstructed IC die wafer. In other embodiments, wafer-to-wafer bonding may be used. In operation 1405, the singulated IC die may be mounted to the reconstructed base die wafer using any suitable technique or techniques, such as a hybrid bonding technique.

[0078] For example, the surfaces of the metal patterning on the IC die and base wafer are matched metal-to-metal and dielectric-to-dielectric for hybrid bonding. The surfaces are then brought together, optionally under pressure and / or heat, to fuse the metals and optionally the dielectric material to form the hybrid bond. Although hybrid bonding for die-level interconnects is discussed, other interconnect technologies and structures may be used, such as solder bonds using solder balls or similar features.

[0079] FIG. 23 shows a cross-sectional side view of a device structure 2300 similar to device structure 2200 after bonding several IC die 101 and VR die to a substantially flat surface 2102. As discussed, such bonding may be performed using any suitable technique or techniques, such as hybrid bonding, solder interconnects, etc. Such die-level interconnects are not shown in detail in FIG. 23 for clarity of presentation. By mounting the IC die 101 and VR die to the substantially flat surface 2102, any number of multi-chip composite devices 100 or die composites may be formed above the carrier wafer 2001. Additional manufacturing operations may be performed, and such multi-chip composite devices 100 or die composites may then be diced or singulated from the carrier wafer 2001. Notably, in device structure 2300, backside metallization 134 is exposed on the top of device structure 2300 for bonding to a metallization network.

[0080] Returning to FIG. 14 , processing continues at operation 1407, where a metallization network is formed above the IC die mounted in operation 1406. In some embodiments, the metallization network is formed on a separate metallization die or dies, which are mounted to the exposed backside metallization of the mounted IC die. In some embodiments, the metallization network is formed directly on the exposed backside metallization of the mounted IC die. For example, the metallization network may be formed using a screen printing technique or other additive metallization techniques discussed with respect to FIG. 10 . In some embodiments, the metallization network is formed by wire bonds between the IC die and adjacent ones of the IC dies and / or adjacent VR dies or components. In some embodiments, such wire bonds may be used to fabricate inductors by embedding wire bonds in a magnetic material, such as a magnetic molding compound. For example, the metallization network may be formed with wire bonds embedded in a dielectric or magnetic material, such as a magnetic molding compound, as discussed with respect to FIG. 13 .

[0081] 24 shows a side cross-sectional view of a device structure 2400 similar to device structure 2300 after removal of the remaining portions of carrier wafer 1601 and after formation of a dielectric material 2401 laterally adjacent to IC die 101 and VR die 103. For example, dielectric material 2401 can be formed above and around IC die 101 and VR die 103 such that IC die 101 and VR die 103 are embedded in dielectric material 2401, and a backside material operation can be performed to remove the remaining portions of carrier wafer 1601 and a portion of dielectric material 2401. Alternatively, dielectric material 2401 can be applied after removal of the remaining portions of carrier wafer 1601, followed by a planarization operation. Dielectric material 2401 can be any of the materials discussed with respect to dielectric material 1701. As shown, a substantially flat surface 2402 of device structure 2400 is exposed for formation of a metallization network. In particular, the backside metallization 134 of the IC die 101 is exposed so that a metallization network can be formed proximate to the backside metallization 134 .

[0082] 25 illustrates a cross-sectional side view of fabrication 2500 of a metallization die 106. The metallization die 106 includes a substrate 108, over which a metallization level 131, a via level 132, and a dielectric material 128 are formed using any suitable technique or techniques. In some embodiments, the metallization level 131, the via level 132, and the dielectric material 128 are formed using a damascene or dual damascene approach. In some embodiments, the metallization level 131, the via level 132, and the dielectric material 128 are formed using an additive bulk metallization process followed by patterning. As shown, interconnects 109 can be formed on or above the metallization network 107.

[0083] FIG. 26 illustrates a cross-sectional side view of a device structure 2600 similar to device structure 2400 after bonding several metallization die 106 to a substantially flat surface 2402. Such bonding may be performed using any suitable technique or techniques, such as solder interconnects, hybrid bonding, etc. In the context of FIG. 26 , a metallization network 107 is formed across the several metallization die 106. In some embodiments, one or more of the metallization die 106 are interconnected across the IC die 101 and the VR die 103 (i.e., interconnecting separate die), and one or more of the metallization die 106 are interconnected between individual ones of the IC die 101 and the VR die 103. In some embodiments, the metallization network 107 is formed by providing a single metallization die 106 per multi-chip composite device 100 or die composite, as illustrated herein above (see FIG. 1 ). In some embodiments, a single metallization die 106 may span (e.g., in the xy plane) each of the VR die 103 and the IC die 101 for coupling to each of the VR die 103 and the IC die 101. In some embodiments, a single metallization die 106 may span the entire lateral area covered by the metallization die 106, or even larger laterally, for example, the entire area shown in FIG.

[0084] Device structure 2600 illustrates the formation of metallization network 107 using one or more metallization die 106, such that metallization network 107, or a portion thereof, is formed on a separate metallization die 106, which is mounted above the exposed backside metallization 134 of IC die 101. In some embodiments, metallization network 107 is formed directly on the exposed backside metallization 134 of IC die 101. Referring to FIG. 10 , metallization network 107 may be formed using a screen printing technique or other additive metallization technique to apply metallization network 107 directly to substantially flat surface 2402. In some embodiments, metallization network 107 is formed with wire bonds by a wire bonding process. Referring to FIG. 13, metallization network 107 may be formed of bond wires 1301 fabricated using any suitable technique or techniques for interconnecting IC die 101 and VR die 103 above a substantially flat surface 2402.

[0085] Additionally, device structure 2600 shows vias 110 laterally adjacent to base die 102 and extending vertically across the thickness of base die 102 to VR die 103. In some embodiments, VR die 103 is not used, and in such contexts, vias 110 are laterally adjacent (i.e., in the xy plane) to base die 102 and IC die 101 and extend vertically (i.e., in the z direction) across the entire thickness established by base die 102 and IC die 101. Power routing can thereby bypass base die 102 and IC die 101 and couple directly to metallization network 107. Such vias can be formed in device structure 2400, for example, as discussed with respect to FIG. 22 . In some embodiments, openings or holes are formed in dielectric material 2401 and dielectric material 2101 using lithography and etching techniques, laser drilling techniques, or other patterning techniques, and the openings or holes are filled with a conductive material using deposition and / or plating techniques, followed by a planarization operation to restore a substantially flat surface 2402.

[0086] FIG. 27 shows a cross-sectional side view of a device structure 2700 similar to device structure 2600 after the formation of a dielectric material 2701 laterally adjacent to the metallization die 106. For example, the dielectric material 2701 may be formed over and around the metallization die 106 such that the metallization die 106 is embedded in the dielectric material 2701, and a backside material operation may be performed to remove a portion of the dielectric material 2701 and form a substantially planar surface 2702. In some embodiments, all or a portion of the substrate 108 may be removed. For example, the backside material operation may also remove remaining portions of the substrate 108. Alternatively, the dielectric material 2701 may be applied after removal of the substrate 108, followed by a planarization operation. The dielectric material 2701 may be any of the materials discussed for the dielectric material 1701. The substantially planar surface 2702 of the device structure 2700 may be used to mount a heat removal device, as described herein.

[0087] Returning to FIG. 14 , processing continues at operation 1408, where the carrier wafer hosting the base die, IC die, and / or VR die and the metallization network are removed to form package-level interconnects. In some embodiments, the die composite structure provides sufficient structural support for the package-level interconnects, and unfolding of a separate carrier wafer or support substrate is not required during such processing. However, an additional carrier wafer proximate to the metallization network may be used. The carrier wafer may be removed using any suitable technique or techniques, such as UV or heat if a UV or heat-release adhesive is used, grinding, or chemical removal operations. The package-level interconnects are then formed using any suitable technique or techniques, such as pick and place and reflow of solder balls or similar operations. While shown with respect to solder-based package-level interconnects, any suitable interconnects, such as copper posts, may be used.

[0088] 28 shows a cross-sectional side view of a device structure 2800, similar to device structure 2700, after removal of carrier wafer 2001 and after formation of interconnects 111. Notably, device structure 2800 is inverted relative to device structure 2700. As discussed, carrier wafer 2001 may be removed by application of UV light and / or heat radiation, mechanical actions such as grinding, and / or chemical removal actions, etc. Interconnects 111 are then formed on or above vias 110 and front-side metallization 140 using any suitable technique or techniques, such as solder formation, bond pad and solder formation, etc. In some embodiments, particularly in embodiments in which substrate 108 has been removed, there is a carrier wafer or panel (not shown) below substantially flat surface 2702 for additional support.

[0089] Returning to FIG. 14 , the process continues at operation 1409, where the fabricated multi-chip composite device or die composite is singulated, tested, and packaged. Such testing may be performed before or after singulation, and testing of such multi-chip composite devices or die composites may be performed using any suitable technique or techniques, such as bonding probe pins to conductive pads, probing (using test circuitry) of various paths and components of the multi-chip composite device or die composite. Those that pass testing are passed on for continued processing, as known in the art. Such processing may include dicing, packaging, assembly, etc. The resulting device (e.g., the packaged multi-chip composite device or die composite) may then be implemented in any suitable form factor device, such as a laptop, netbook, notebook, ultrabook, smartphone, tablet, personal digital assistant, ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, digital video recorder, etc.

[0090] 29 shows a side cross-sectional view of a multi-chip composite device 100 under test 2900. The IC die 101 includes or is attached to a substrate 1501. The IC die 101 further includes a front-side metallization 136, a device layer 135, a back-side metallization 134, and an optional substrate layer 137. As shown, the IC die 101 may be attached or mounted to a thermal head 1502, which provides temperature control and optional thermal stress during testing. Probe pins 1503 are coupled to the back-side metallization 134 and are used to test various components of the IC die 101, such as active or test components of the device layer 135.

[0091] 30 shows a cross-sectional side view of a device structure 3000 similar to device structure 2800 after singulation or dicing to separate the multichip composite device 100 and after mounting the multichip composite device 100 to the microelectronic substrate 104. The multichip composite device 100 may be mounted and electrically coupled to the microelectronic substrate 104 using any suitable technique or techniques, such as a controlled collapse chip attach process. An underfill material 3001 may be formed around the interconnects 111 to protect them from moisture and to provide structural support.

[0092] The multi-chip composite devices discussed herein offer advantages in power delivery, IO routing efficiency, and other aspects. Note that the thermal performance of the discussed multi-chip composite devices may be comparable to previous structures or architectures or may have improvements based on improved efficiency of power delivery. Other advantages will become apparent based on this disclosure.

[0093] FIG. 31 illustrates an exemplary microelectronic device assembly 3100 including a multichip composite device 100 having an upper metallization network 107 for providing a power route to the backside 119 of the integrated circuit die 101, according to some embodiments. In the illustrative example of FIG. 31, a multichip composite device 100 is depicted. However, any multichip composite device, microelectronic device, or any other structure or architecture discussed herein may be deployed in the microelectronic device assembly 3100. As shown, the microelectronic device assembly 3100 includes a base die 102 attached to a microelectronic substrate 104 via interconnects 111. The microelectronic device assembly 3100 further includes an IC die 101 and a VR die 103 above the base die 102 and coupled thereto by die-level interconnects 112, and a metallization network 107 for providing upper power (and optionally additional IO) routing from the microelectronic substrate 104 and through vias 110 to the IC die 101. As discussed, in some embodiments, VR die 103 is not expanded, and direct connection to metallization network 107 is made by vias 110. Additionally, base die 102 provides IO routing to IC die 101, such that IO routing is through the front-side metallization of IC die 101, and top-side power (and optionally additional IO) routing is provided through the back-side metallization of IC die 101. In some embodiments, power routing can be sourced from a power supply, which can include a battery, a voltage converter, a power delivery circuit, etc., as shown in FIG.

[0094] The microelectronic device assembly 3100 further includes a thermal interface material (TIM) 3101 disposed on, for example, the top surface of the substrate 108. In such an embodiment, the substrate 108 may act as an integrated heat spreader (IHS) for the multi-chip composite device 100. In other embodiments, the TIM 3101 may be on a molding compound or dielectric, including, for example, bond wires or thick metallization. The TIM 3101 may include any suitable thermal interface material and may be characterized as TIM1. An integrated heat spreader 3102 having a surface on the TIM 3101 extends above the multi-chip composite device 100 and is mounted to the microelectronic substrate 104. As discussed, the microelectronic substrate 104 may include any suitable substrate, such as a package substrate, a motherboard, an interposer, etc. Additionally or alternatively, the microelectronic substrate 104 may be mounted to a motherboard. The microelectronic device assembly 3100 further includes a TIM 3103 disposed on top of the integrated heat spreader 3102. The TIM 3103 may include any suitable thermal interface material and may be characterized as TIM2. The TIM 3101 and TIM 3103 may be the same material, or they may be different. A heat sink 3104 (e.g., an exemplary heat dissipation device or thermal solution) resides on the TIM 3103 and dissipates heat generated by the multi-chip composite device 100. While illustrated with respect to the microelectronic device assembly 3100, the various multi-chip composite devices discussed herein may be deployed in any suitable architecture and form factor. For example, the microelectronic device assembly 3100 may be used in desktop and server form factors. In other contexts, a thermal solution such as a heat pipe, heat spreader, or thermoelectric cooler may be mounted directly on the TIM 3101, or the substrate 108 may be replaced with a solution such as a heat pipe or thermoelectric cooler. Such an assembly can be used in smaller form factor devices.

[0095] FIG. 32 illustrates an exemplary system using an IC assembly including a multichip composite device having an upper metallization network for power delivery to the backside of the integrated circuit die, according to some embodiments. The system may be, for example, a mobile computing platform 3205 and / or a data server machine 3206. Either may use a component assembly including a multichip composite device having an upper metallization network for power delivery to the backside of the IC die, as described elsewhere herein. The server machine 3206 may be any commercial server including, for example, any number of high-performance computing platforms networked together in a rack for electronic data processing, which in an exemplary embodiment includes an IC die assembly 3250 including a multichip composite device having an upper metallization network for power delivery to the backside of the IC die, as described elsewhere herein. The mobile computing platform 3205 may be any portable device configured for electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, the mobile computing platform 3205 may be a tablet, smartphone, laptop, etc., and may include a display screen (e.g., a capacitive, floating, resistive, or optical touch screen), a chip-level or package-level integrated system 3210, and a battery 3215. While illustrated with respect to a mobile computing platform 3205, in other examples, the chip-level or package-level integrated system 3210 and battery 3215 may be implemented in a desktop computing platform, an automotive computing platform, an Internet of Things platform, etc. As discussed below, in some examples, the disclosed system may include a subsystem 3260, such as a system on a chip (SOC) or an integrated system of multiple ICs, which is illustrated with respect to a mobile computing platform 3205.

[0096] Whether provided within the integrated system 3210 shown in enlarged view 3220 or as a standalone packaged device within the data server machine 3206, the subsystem 3260 may include a memory circuit and / or processor circuit 3240 (e.g., RAM, a microprocessor, a multi-core microprocessor, a graphics processor, etc.), a power management integrated circuit (PMIC) 3230, a controller 3235, and a radio frequency integrated circuit (RFIC) 3225 (e.g., including a wideband RF transmitter and / or receiver (TX / RX)). As shown, one or more IC dies, such as the memory circuit and / or processor circuit 3240, may be assembled and implemented to have a multi-chip composite device, one or more having a topside metallization network for power delivery to the backside of the IC die as described herein. In some embodiments, the RFIC 3225 includes a digital baseband and analog front-end module further including a power amplifier on the transmit path and a low-noise amplifier on the receive path. Functionally, the PMIC 3230 may perform battery power conditioning, DC-to-DC conversion, etc., and therefore has an input coupled to the battery 3215, and an output that provides a current supply to other functional modules.32 , in an exemplary embodiment, RFIC 3225 has an output coupled to an antenna (not shown) to implement any of several wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols designated as 3G, 4G, 5G, and beyond. Memory and / or processor circuit 3240 may provide memory functionality, high-level control, data processing, and the like for subsystem 3260. In an alternative implementation, each of the SOC modules may be integrated on a separate IC and coupled to a package substrate, interposer, or board.

[0097] FIG. 33 is a functional block diagram of an electronic computing device 3300 according to some embodiments. For example, the device 3300 may employ a multi-chip composite device having a top-side metallization network for power delivery to the backside of the IC die according to any embodiment described elsewhere herein through any suitable components therein. The device 3300 further includes a motherboard or package substrate 3302 that hosts several components, such as, but not limited to, a processor 3304 (e.g., an application processor). The processor 3304 may be physically and / or electrically coupled to the package substrate 3302. In some examples, the processor 3304 is within an IC assembly that includes a multi-chip composite device having a top-side metallization network for power delivery to the backside of the IC die, as described elsewhere herein. In general, the terms “processor” or “microprocessor” may refer to any device, or portion of a device, that processes electronic data from a plurality of registers and / or memory and converts the electronic data into other electronic data that may be further stored in a plurality of registers and / or memory.

[0098] In various examples, one or more communications chips 3306 may also be physically and / or electrically coupled to the package substrate 3302. In further implementations, the communications chip 3306 may be part of the processor 3304. The computing device 3300 may include other components that may or may not be physically and electrically coupled to the package substrate 3302, depending on its application. These other components include, but are not limited to, volatile memory (e.g., DRAM 3332), non-volatile memory (e.g., ROM 3335), flash memory (e.g., NAND or NOR), magnetic memory (MRAM 3330), graphics processor 3322, digital signal processor, cryptoprocessor, chipset 3312, antenna 3325, touchscreen screen 3315, touchscreen controller 3365, battery 3316, audio codec, power amplifier 3321, global positioning system (GPS) device 3340, compass 3345, accelerometer, gyroscope, speaker 3320, camera 3341, and storage device (e.g., hard disk drive, solid-state drive (SSD), compact disk (CD), digital versatile disk (DVD), etc., or the like).

[0099] The communications chip 3306 enables wireless communication for data transfer to and from the computing device 3300. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated device is completely wire-free, although in some embodiments this may not be the case. The communications chip 3306 may implement any of several wireless standards or protocols, including but not limited to those described elsewhere herein. As discussed, the computing device 3300 may include multiple communications chips 3306. For example, a first communications chip may be dedicated to short-range wireless communications such as Wi-Fi® and Bluetooth®, and a second communications chip may be dedicated to long-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX®, LTE, Ev-DO, and others.

[0100] While certain features described herein have been described with reference to various implementations, this description is not intended to be construed in a limiting sense. Accordingly, various modifications of the implementations described herein and other implementations that may be apparent to those skilled in the art to which this disclosure pertains are deemed to be within the spirit and scope of the present disclosure.

[0101] It is to be appreciated that the invention is not limited to the embodiments so described, and that modifications and variations may be made without departing from the scope of the appended claims. For example, the above-described embodiments may comprise particular combinations of features as further described below.

[0102] The following relates to an exemplary embodiment.

[0103] In one or more first embodiments, an apparatus comprises: an integrated circuit die above and coupled to a base die; the integrated circuit die having a device layer between a first stack of metallization layers and a second stack of metallization layers, the first stack of metallization layers proximate the base die and having more metallization layers than the second stack of metallization layers; a metallization network above the integrated circuit die and coupled to the second stack of metallization layers, the metallization network having one or more metallization layers each having a thickness greater than or equal to five times a thickness of either the first or second stack of metallization layers; and vias laterally adjacent to the base die, the vias coupled to the metallization network.

[0104] In one or more second embodiments, further to the first embodiment, the device further comprises a metallization die having a substrate and the metallization network, the substrate comprising silicon, and the metallization network comprising metal traces embedded in an inorganic dielectric material.

[0105] In one or more third embodiments, in addition to the first or second embodiment, the apparatus further comprises a voltage regulator between the via and the metallization network.

[0106] In one or more fourth embodiments, in addition to the first to third embodiments, the base die has a plurality of through vias, the vias, the voltage regulator, and the metallization network have power routes to the second stack of metallization layers, and the through vias have input / output routes to the first stack of metallization layers.

[0107] In one or more fifth embodiments, further to the first through fourth embodiments, the apparatus further comprises a second integrated circuit die above and coupled to the base die, the second integrated circuit die being laterally adjacent to the integrated circuit die, and a metallization network having signal paths between the integrated circuit die and the second integrated circuit die.

[0108] In one or more sixth embodiments, further to the first through fifth embodiments, the apparatus further comprises a second integrated circuit die directly coupled to the metallization network, wherein the second integrated circuit die has a second device layer between a third stack of metallization layers and a fourth stack of metallization layers, the third stack of metallization layers being adjacent to the metallization network and having fewer metallization layers than the fourth stack of metallization layers.

[0109] In one or more seventh embodiments, further to the first to sixth embodiments, the metallization network has a total thickness, and the device further comprises a component in contact with and within the total thickness of the metallization network.

[0110] In one or more eighth embodiments, further to the first to seventh embodiments, the metallization network comprises one of a plurality of substantially planar metal lines or a plurality of wire bonds.

[0111] In one or more ninth embodiments, further to the first to eighth embodiments, the thickest metallization layer of the first stack of metallization layers has a first thickness that is less than a second thickness of the thinnest metallization layer of the second stack of metallization layers.

[0112] In one or more tenth embodiments, further to the first to ninth embodiments, each metallization layer of the metallization network has a thickness that is 10 times or greater than the thickness of either the first or second stack of metallization layers.

[0113] In one or more eleventh embodiments, in addition to the first to tenth embodiments, the apparatus further comprises a microelectronic board, wherein the vias and the base die are mounted to the microelectronic board.

[0114] In one or more twelfth embodiments, a system comprises an integrated circuit package according to any of the apparatus of the first through tenth embodiments, and a microelectronic board coupled to the integrated circuit package.

[0115] In one or more thirteenth embodiments, an apparatus comprises an integrated circuit die above and coupled to a base die, the integrated circuit die having a device layer between a front side metallization and a back side metallization, the front side metallization being proximal to the base die, a metallization network above the integrated circuit die and coupled to the back side metallization, and a via laterally adjacent to the base die, the via coupled to the metallization network and extending to an external interconnect.

[0116] In one or more fourteenth embodiments, further to the thirteenth embodiment, the device further comprises a metallization die having a substrate and the metallization network, the substrate comprising silicon, and the metallization network comprising metal traces embedded in an inorganic dielectric material.

[0117] In one or more fifteenth embodiments, further to the thirteenth or fourteenth embodiments, the device further comprises a voltage regulator between the via and the metallization network, the base die includes a plurality of through vias, the vias, the voltage regulator, and the metallization network include power routes to the backside metallization, and the through vias include input / output routes to the frontside metallization.

[0118] In one or more sixteenth embodiments, further to the thirteenth to fifteenth embodiments, the apparatus further comprises a second integrated circuit die directly coupled to the metallization network, wherein the second integrated circuit die has a second device layer between a third stack of metallization layers and a fourth stack of metallization layers, the third stack of metallization layers being adjacent to the metallization network and having fewer metallization layers than the fourth stack of metallization layers.

[0119] In one or more seventeenth embodiments, in addition to the thirteenth to sixteenth embodiments, the apparatus further comprises a microelectronic board, wherein the vias and the base die are mounted to the microelectronic board.

[0120] In one or more eighteenth embodiments, a system comprises an integrated circuit package according to any of the apparatus of the thirteenth to sixteenth embodiments, and a microelectronic board coupled to the integrated circuit package.

[0121] In one or more nineteenth embodiments, a method comprises mounting a first die to a second die, the first die having a device layer between a front side metallization layer and a back side metallization layer, the front side metallization layer of the first die being mounted proximate to the second die, forming a via laterally adjacent to the second die, and forming a metallization network above and proximate to the back side metallization layer of the first die, the metallization network being coupled to the via, the metallization network having one or more metallization layers each having a thickness greater than or equal to five times the thickness of any one of the front side metallization layer and the back side metallization layer.

[0122] In one or more twentieth embodiments, further to the nineteenth embodiment, the step of mounting the first die to the second die comprises one of placing the first die on a first reconstructed wafer including the second die, or placing the second die on a second reconstructed wafer including the first die.

[0123] In one or more twenty-first embodiments, in addition to the nineteenth or twentieth embodiment, the step of forming the metallization network includes one of wire-bonding the second die to an adjacent third die, applying the metallization network directly to the second die, or placing a metallization die including a substrate and the metallization network on the second die.

[0124] In one or more twenty-second embodiments, further to the nineteenth to twenty-first embodiments, the step of mounting the first die to the second die comprises hybrid bonding the first die to the second die, and the step of forming the metallization network comprises solder bump bonding a metallization die including a substrate and the metallization network to the second die.

[0125] However, the above embodiments are not limited in this respect, and in various implementations, the above embodiments may include implementing only a subset of such features, implementing a different order of such features, implementing a different combination of such features, and / or implementing additional features other than those expressly recited. The scope of the present invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. Other possible items [Item 1] an integrated circuit die above and bonded to a base die, the integrated circuit die having a device layer between a first stack of metallization layers and a second stack of metallization layers, the first stack of metallization layers being proximal to the base die and having more metallization layers than the second stack of metallization layers; a metallization network overlying the integrated circuit die and coupled to the second stack of metallization layers, the metallization network having one or more metallization layers each having a thickness greater than or equal to five times the thickness of either the first or second stack of metallization layers; and a via laterally adjacent the base die, the via coupled to the metallization network; An apparatus comprising: [Item 2] Further comprising a metallization die having a substrate and the metallization network, the substrate comprising silicon and the metallization network comprising metal traces embedded in an inorganic dielectric material. Item 1. The device according to item 1. [Item 3] and a voltage regulator between the via and the metallization network. 3. The device according to items 1 to 2. [Item 4] 4. The device of claim 3, wherein the base die has a plurality of through vias, the vias, the voltage regulator, and the metallization network have power routes to the second stack of metallization layers, and the through vias have input / output routes to the first stack of metallization layers. [Item 5] a second integrated circuit die above and coupled to the base die, the second integrated circuit die being laterally adjacent to the base die, and a metallization network providing signal paths between the integrated circuit die and the second integrated circuit die; 5. The device of any one of items 1 to 4, further comprising: [Item 6] a second integrated circuit die directly coupled to the metallization network, the second integrated circuit die having a second device layer between a third stack of metallization layers and a fourth stack of metallization layers, the third stack of metallization layers being adjacent to the metallization network and having fewer metallization layers than the fourth stack of metallization layers; 6. The device of any one of items 1 to 5, further comprising: [Item 7] the metallization network having a total thickness, and the device comprising: a component in contact with the metallization network and within the entire thickness of the metallization network 7. The device of any one of items 1 to 6, further comprising: [Item 8] 8. The device of any one of items 1 to 7, wherein the metallization network comprises one of a plurality of substantially planar metal lines or a plurality of wire bonds. [Item 9] 9. The device of any one of items 1 to 8, wherein a thickest metallization layer of the first stack of metallization layers has a first thickness that is less than a second thickness of a thinnest metallization layer of the second stack of metallization layers. [Item 10] Item 10. The apparatus of item 9, wherein each metallization layer of the metallization network has a thickness that is 10 times or greater than the thickness of either the first or second stack of metallization layers. [Item 11] a microelectronic board, wherein the vias and the base die are mounted on the microelectronic board. 11. The device of any one of items 1 to 10, further comprising: [Item 12] an integrated circuit die above and bonded to a base die, the integrated circuit die having a device layer between a front side metallization and a back side metallization, the front side metallization being proximal to the base die; a metallization network overlying the integrated circuit die and coupled to the backside metallization; and a via laterally adjacent the base die, the via coupled to the metallization network and extending to an external interconnect; An apparatus comprising: [Item 13] a metallization die having a substrate and the metallization network, the substrate comprising silicon and the metallization network comprising metal traces embedded in an inorganic dielectric material; Item 13. The device of item 12, further comprising: [Item 14] a voltage regulator between the via and the metallization network, wherein the base die includes a plurality of through vias, the vias, the voltage regulator, and the metallization network include power routes to the backside metallization, and the through vias include input / output routes to the frontside metallization. Item 14. The device of item 12 or 13, further comprising: [Item 15] a second integrated circuit die directly coupled to the metallization network, the second integrated circuit die having a second device layer between a third stack of metallization layers and a fourth stack of metallization layers, the third stack of metallization layers being adjacent to the metallization network and having fewer metallization layers than the fourth stack of metallization layers; 15. The device of any one of items 12 to 14, further comprising: [Item 16] a second integrated circuit die above and coupled to the base die, the second integrated circuit die being laterally adjacent to the base die, and a metallization network providing signal paths between the integrated circuit die and the second integrated circuit die; 16. The device of any one of items 12 to 15, further comprising: [Item 17] a third integrated circuit die directly coupled to the metallization network, the third integrated circuit die having a second device layer between a second front side metallization and a second back side metallization; 17. The device of any one of items 12 to 16, further comprising: [Item 18] the metallization network having a total thickness, and the device comprising: a component in contact with the metallization network and within the entire thickness of the metallization network 18. The device of any one of items 12 to 17, further comprising: [Item 19] Item 19. The device of any one of items 12 to 18, wherein the metallization network comprises one of a plurality of substantially planar metal lines or a plurality of wire bonds. [Item 20] 20. The device of any one of items 12 to 19, wherein the thickest metallization layer of the front side metallization has a first thickness that is less than a second thickness of the thinnest metallization layer of the back side metallization. [Item 21] a microelectronic board, wherein the vias and the base die are mounted on the microelectronic board. 21. The device of any one of items 12 to 20, further comprising: [Item 22] mounting a first die to a second die, the first die having a device layer between a front side metallization layer and a back side metallization layer, the front side metallization layer of the first die being mounted proximate to the second die; forming a via laterally adjacent to the second die; and forming a metallization network over and proximate to the backside metallization layer of the first die, the metallization network coupled to the vias, the metallization network having one or more metallization layers each having a thickness greater than or equal to five times the thickness of any one of the frontside metallization layer and the backside metallization layer. A method comprising: [Item 23] 23. The method of claim 22, wherein the step of mounting the first die to the second die comprises one of placing the first die on a first reconstructed wafer that includes the second die, or placing the second die on a second reconstructed wafer that includes the first die. [Item 24] 24. The method of claim 22 or 23, wherein forming the metallization network comprises one of wire-bonding the second die to an adjacent third die, applying the metallization network directly to the second die, or placing a metallization die including a substrate and the metallization network on the second die. [Item 25] 25. The method of any one of items 22 to 24, wherein the step of mounting the first die to the second die comprises hybrid bonding the first die to the second die, and the step of forming the metallization network comprises solder bump bonding a metallization die including a substrate and the metallization network to the second die.

Claims

1. an integrated circuit die above and bonded to a base die, the integrated circuit die having a device layer between a first stack of metallization layers and a second stack of metallization layers, the first stack of metallization layers being proximal to the base die and having more metallization layers than the second stack of metallization layers; a metallization network overlying the integrated circuit die and coupled to the second stack of metallization layers, the metallization network having one or more metallization layers each having a thickness greater than or equal to five times the thickness of either the first or second stack of metallization layers; and a via laterally adjacent the base die, the via coupled to the metallization network; An apparatus comprising:

2. Further comprising a metallization die having a substrate and the metallization network, the substrate comprising silicon and the metallization network comprising metal traces embedded in an inorganic dielectric material.

10. The apparatus of claim 1.

3. and a voltage regulator between the via and the metallization network.

10. The apparatus of claim 1.

4. 4. The device of claim 3, wherein the base die has a plurality of through vias, the vias, the voltage regulator, and the metallization network having power routes to the second stack of metallization layers, and the plurality of through vias having input / output routes to the first stack of metallization layers.

5. a second integrated circuit die above and coupled to the base die, the second integrated circuit die being laterally adjacent to the base die, and a metallization network providing signal paths between the integrated circuit die and the second integrated circuit die; The apparatus of claim 1 further comprising:

6. a third integrated circuit die directly coupled to the metallization network, the third integrated circuit die having a second device layer between a third stack of metallization layers and a fourth stack of metallization layers, the third stack of metallization layers being adjacent to the metallization network and having fewer metallization layers than the fourth stack of metallization layers; The apparatus of claim 1 further comprising:

7. the metallization network having a total thickness, and the device comprising: a component in contact with the metallization network and within the entire thickness of the metallization network The apparatus of claim 1 further comprising:

8. The device of claim 1 , wherein the metallization network comprises one of a plurality of substantially planar metal lines or a plurality of wire bonds.

9. 2. The apparatus of claim 1, wherein a thickest metallization layer of the first stack of metallization layers has a first thickness that is less than a second thickness of a thinnest metallization layer of the second stack of metallization layers.

10. 10. The apparatus of claim 9, wherein each metallization layer of the metallization network has a thickness that is at least 10 times the thickness of either the first or second stack of metallization layers.

11. a microelectronic board, wherein the vias and the base die are mounted on the microelectronic board. The apparatus of claim 1 , further comprising:

12. an integrated circuit die above and bonded to a base die, the integrated circuit die having a device layer between a front side metallization and a back side metallization, the front side metallization being proximal to the base die; a metallization network overlying the integrated circuit die and coupled to the backside metallization; and a via laterally adjacent the base die, the via coupled to the metallization network and extending to an external interconnect; An apparatus comprising:

13. Further comprising a metallization die having a substrate and the metallization network, the substrate comprising silicon and the metallization network comprising metal traces embedded in an inorganic dielectric material.

13. The apparatus of claim 12.

14. a voltage regulator between the via and the metallization network; The apparatus of claim 12 further comprising:

15. 15. The apparatus of claim 14, wherein the base die includes a plurality of through vias, the vias, the voltage regulator, and the metallization network include power routes to the backside metallization, and the plurality of through vias include input / output routes to the frontside metallization.

16. a second integrated circuit die above and coupled to the base die, the second integrated circuit die being laterally adjacent to the base die, and a metallization network providing signal paths between the integrated circuit die and the second integrated circuit die; The apparatus of claim 12 further comprising:

17. a third integrated circuit die directly coupled to the metallization network, the third integrated circuit die having a second device layer between a second front side metallization and a second back side metallization; The apparatus of claim 12 further comprising:

18. the metallization network having a total thickness, and the device comprising: a component in contact with the metallization network and within the entire thickness of the metallization network The apparatus of claim 12 further comprising:

19. The apparatus of claim 12 , wherein the metallization network comprises one of a plurality of substantially planar metal lines or a plurality of wire bonds.

20. 13. The apparatus of claim 12, wherein a thickest metallization layer of the front side metallization has a first thickness that is less than a second thickness of a thinnest metallization layer of the back side metallization.

21. a microelectronic board, wherein the vias and the base die are mounted on the microelectronic board.

21. The apparatus of claim 12, further comprising:

22. mounting a first die to a second die, the first die having a device layer between a front side metallization layer and a back side metallization layer, the front side metallization layer of the first die being mounted proximate to the second die; forming a via laterally adjacent to the second die; and forming a metallization network over and proximate to the backside metallization layer of the first die, the metallization network coupled to the vias, the metallization network having one or more metallization layers each having a thickness greater than or equal to five times the thickness of any one of the frontside metallization layer and the backside metallization layer. A method comprising:

23. 23. The method of claim 22, wherein the mounting the first die to the second die comprises one of placing the first die on a first reconstructed wafer that includes the second die, or placing the second die on a second reconstructed wafer that includes the first die.

24. 23. The method of claim 22, wherein forming the metallization network comprises one of wire-bonding the second die to an adjacent third die, applying the metallization network directly to the second die, or placing a metallization die including a substrate and the metallization network on the second die.

25. 25. The method of claim 22, wherein the step of mounting the first die to the second die comprises hybrid bonding the first die to the second die, and the step of forming the metallization network comprises solder bump bonding a metallization die including a substrate and the metallization network to the second die.

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