Semiconductor device

Abstract

To provide a semiconductor device capable of improving heat dissipation.SOLUTION: A semiconductor device has a buffer layer containing iron atoms and exhibiting nitrogen polarity on its upper surface, a barrier layer in which the upper surface exhibits nitrogen polarity and which is formed above the buffer layer, and a channel layer in which the upper surface exhibits nitrogen polarity and which is formed above the barrier layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] High electron mobility transistors (HEMTs) using nitride semiconductors have been proposed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2017 / 002317 Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, the amount of heat generated by semiconductor devices has increased with the increase in operating speed, and there is an increasing demand for improved heat dissipation.

[0005] An object of the present disclosure is to provide a semiconductor device that can improve heat dissipation. [Means for solving the problem]

[0006] The semiconductor device of the present disclosure includes a buffer layer containing iron atoms and having a nitrogen polarity on its upper surface, a barrier layer having a nitrogen polarity on the buffer layer, and a channel layer having a nitrogen polarity on its upper surface on the barrier layer. [Effects of the Invention]

[0007] According to the present disclosure, heat dissipation can be improved. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a cross-sectional view (part 1) illustrating the method for manufacturing a semiconductor device according to the embodiment. [Figure 3] FIG. 3 is a cross-sectional view (part 2) showing the method for manufacturing the semiconductor device according to the embodiment. [Figure 4] FIG. 4 is a cross-sectional view (part 3) showing the method for manufacturing a semiconductor device according to the embodiment. [Figure 5] FIG. 5 is a cross-sectional view (part 4) illustrating the method for manufacturing a semiconductor device according to the embodiment. [Figure 6] FIG. 6 is a cross-sectional view (part 5) showing the method for manufacturing a semiconductor device according to the embodiment. [Figure 7] FIG. 7 is a cross-sectional view (part 6) showing the method for manufacturing a semiconductor device according to the embodiment. [Figure 8] FIG. 8 is a cross-sectional view showing a semiconductor device according to a modified example of the embodiment. [Figure 9] FIG. 9 is a diagram showing the relationship between the polarity of the upper surface of the nitride semiconductor layer and the distribution of the concentration of Fe atoms. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] [1] A semiconductor device according to one embodiment of the present disclosure includes a buffer layer containing iron atoms and having a nitrogen (N) polarity on an upper surface thereof, a barrier layer having a nitrogen polarity on the buffer layer, and a channel layer having a nitrogen polarity on the barrier layer.

[0011] Because the buffer layer contains iron atoms as a dopant, the buffer layer can have high resistance, making it easier to achieve high output power and high-frequency characteristics. Furthermore, the inventors of the present invention discovered that when the upper surfaces of the buffer layer, barrier layer, and channel layer have nitrogen polarity, diffusion of iron atoms doped in the buffer layer from the buffer layer to the channel layer is less likely than when they have gallium (Ga) polarity. Iron atoms in the channel layer degrade the electron mobility of the two-dimensional electron gas (2DEG) in the channel layer. Iron is generally not doped into the channel layer. In this semiconductor device, because the upper surfaces of the buffer layer, barrier layer, and channel layer have nitrogen polarity, diffusion of iron atoms from the buffer layer to the channel layer and reduction in electron mobility due to iron atoms diffused into the channel layer are less likely to occur. This semiconductor device generates heat due to the movement of electrons in the channel layer. Therefore, by reducing the distance between the buffer layer and the channel layer, high electron mobility can be achieved while improving heat dissipation (thermal conduction) from the channel layer to the substrate.

[0012] [2] In [1], the thickness of the barrier layer may be 1 nm or more and 50 nm or less. By making the thickness of the barrier layer 1 nm or more and 50 nm or less, it is possible to easily improve thermal conductivity while making it difficult for a decrease in electron mobility and diffusion of iron atoms from the buffer layer to the channel layer to occur.

[0013] [3] In [1], the distance (gap) between the upper surface of the buffer layer and the lower surface of the channel layer may be 1 nm or more and 50 nm or less. By setting the distance (gap) between the upper surface of the buffer layer and the lower surface of the channel layer to 1 nm or more and 50 nm or less, it is possible to improve thermal conduction in the vertical direction described below while making it difficult for a decrease in electron mobility and diffusion of iron atoms into the channel layer to occur.

[0014] [4] In any one of [1] to [3], the average concentration of iron atoms in the channel layer is 2×10 16 cm -3 The average concentration of iron atoms in the channel layer may be 2×10 or less.16 cm -3 or less, high electron mobility can be easily obtained in the channel region.

[0015] [5] In any one of [1] to [4], the average concentration of the iron atoms in the buffer layer is 5×10 17 cm -3 The average concentration of iron atoms in the buffer layer may be 5×10 or more. 17 cm -3 As a result, the buffer layer can have a high resistance.

[0016] [6] In [1], the thickness of the barrier layer is 1 nm or more and 50 nm or less, and the average concentration of iron atoms in the channel layer is 2×10 16 cm -3 the average concentration of iron atoms in the buffer layer is 5×10 or less 17 cm -3 The thickness of the barrier layer is 1 nm or more and 50 nm or less, which makes it possible to improve the thermal conduction from the channel layer to the substrate while making it difficult for the electron mobility to decrease and for the diffusion of iron atoms from the buffer layer to the channel layer to occur. The average concentration of iron atoms in the channel layer is 2 × 10 16 cm -3 When the average concentration of iron atoms in the buffer layer is 5×10 or less, it is easy to obtain high electron mobility in the channel region. 17 cm -3 With the above, the buffer layer can have a high resistance.

[0017] [7] In any one of [1] to [6], the buffer layer may be a gallium nitride layer, the barrier layer may be an aluminum gallium nitride layer, and the channel layer may be a gallium nitride layer. In this case, the buffer layer, the barrier layer, and the channel layer can be easily and stably formed.

[0018] [Details of the embodiments of the present disclosure] Hereinafter, embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto. In this specification and drawings, components having substantially the same functional configurations may be designated by the same reference numerals to avoid redundant description. In this disclosure, the term "planar view" refers to viewing an object from above in a direction perpendicular to the top surface of a substrate (vertical direction).

[0019] The embodiment relates to a semiconductor device including a GaN-based high electron mobility transistor (HEMT). Fig. 1 is a cross-sectional view showing a semiconductor device according to the embodiment.

[0020] As shown in FIG. 1, the semiconductor device 1 according to the embodiment mainly includes a substrate 10, a nitride semiconductor layer 20, a dielectric film 31, a passivation film 50, a regrown layer 41S, a regrown layer 41D, a gate electrode 43, a source electrode 42S, and a drain electrode 42D.

[0021] The substrate 10 is, for example, a semi-insulating silicon carbide (SiC) substrate. When the substrate 10 is a SiC substrate, the upper surface of the substrate 10 is a carbon (C) polarity plane. When the surface of the substrate 10 is a C polarity plane, the nitride semiconductor layer 20 can grow as a crystal with the nitrogen (N) polarity plane as the growth plane.

[0022] The nitride semiconductor layer 20 includes a buffer layer 21, a barrier layer 22, a channel layer 23, and a cap layer 24. The nitride semiconductor layer 20 may include a nucleation layer between the substrate 10 and the buffer layer 21.

[0023] The buffer layer 21 is on the substrate 10. The buffer layer 21 contains iron (Fe) atoms. Iron is doped into the buffer layer 21 as an impurity (dopant). The buffer layer 21 is, for example, a gallium nitride (GaN) layer containing iron (Fe). That is, the buffer layer 21 is an iron-doped GaN layer. The thickness of the buffer layer 21 is, for example, not less than 10 nm and not more than 1000 nm. For example, the buffer layer 21 has a resistivity of not less than 1 MΩ·m.

[0024] The barrier layer 22 is on the buffer layer 21. The barrier layer 22 is, for example, an aluminum gallium nitride (AlGaN) layer. The band gap of the barrier layer 22 is larger than the band gap of the channel layer 23. The thickness of the barrier layer 22 is, for example, 1 nm or more and 50 nm or less. The composition of the barrier layer 22 is, for example, Al Y Ga 1-Y N (0.15≦Y≦0.55). The conductivity type of the barrier layer 22 is, for example, n-type or undoped (i-type). Even if the barrier layer 22 is not doped with iron, the barrier layer 22 may contain Fe atoms diffused from the iron-doped buffer layer 21. Instead of the AlGaN layer, a scandium aluminum nitride (ScAlN), an indium aluminum nitride (InAlN) layer, or an indium aluminum gallium nitride (InAlGaN) layer may be used. If the composition of the barrier layer 22 is Al Y Ga 1-Y In the case of N, the proportion of Al in the group III elements in the barrier layer 22 is Y×100%.

[0025] The channel layer 23 is located on the barrier layer 22. The channel layer 23 is, for example, a GaN layer. The band gap of the channel layer 23 is smaller than that of the barrier layer 22. The thickness of the channel layer 23 is, for example, 1 nm to 50 nm. Strain occurs between the channel layer 23 and the barrier layer 22 due to the difference in lattice constants between them. This strain induces piezoelectric charges at the interface between them. This generates a two-dimensional electron gas (2DEG) in the channel layer 23 near the surface facing the barrier layer 22, forming a channel region 26. The conductivity type of the channel layer 23 is, for example, n-type or undoped (i-type). Iron is usually not doped into the channel layer 23. Even in this case, the channel layer 23 may contain iron atoms that diffuse from the buffer layer 21 through the barrier layer 22. In this case, the average concentration of Fe atoms in the channel layer 23 is smaller than the average concentration of Fe atoms in the barrier layer 22, and the average concentration of Fe atoms in the barrier layer 22 is smaller than the average concentration of Fe atoms in the buffer layer 21.

[0026] The cap layer 24 is on the channel layer 23. The cap layer 24 is, for example, an AlGaN layer. The thickness of the cap layer 24 is, for example, not less than 0.2 nm and not more than 10 nm.

[0027] On the C-polarity surface of the SiC substrate, the buffer layer 21, the barrier layer 22, the channel layer 23, and the cap layer 24 undergo crystal growth with the N-polarity surface as the growth surface. Therefore, the upper surfaces 21A, 22A, 23A, and 24A of the buffer layer 21, the barrier layer 22, the channel layer 23, and the cap layer 24, respectively, have N-polarity. In addition, the lower surfaces 21B, 22B, 23B, and 24B of the buffer layer 21, the barrier layer 22, the channel layer 23, and the cap layer 24, respectively, have gallium (Ga) polarity or aluminum (Al) polarity.

[0028] A recess 40S for a source and a recess 40D for a drain are formed in the nitride semiconductor layer 20. The bottom of the recess 40S and the bottom of the recess 40D are closer to the lower surface of the nitride semiconductor layer 20 than to the upper surface 23A of the channel layer 23. In other words, the recess 40S and the recess 40D are formed deeper than the upper surface 23A of the channel layer 23. The bottom of the recess 40S and the bottom of the recess 40D may be in the channel layer 23 or in the barrier layer 22.

[0029] The dielectric film 31 is on the nitride semiconductor layer 20. The dielectric film 31 is in contact with the upper surface 24A of the cap layer 24. For example, the dielectric constant of the dielectric film 31 is higher than that of silicon dioxide (SiO2). The dielectric film 31 may be a high-dielectric-constant film. The dielectric film 31 is, for example, a silicon nitride (SiN) film. The dielectric film 31 may be a dielectric oxide film or a dielectric oxynitride film. The dielectric oxide film or the dielectric oxynitride film may contain at least one selected from the group consisting of hafnium (Hf), lanthanum (La), and zirconium (Zr). The dielectric oxide film or the dielectric oxynitride film may also contain at least one selected from the group consisting of silicon (Si) and aluminum (Al). For example, the dielectric film 31 may be hafnium silicate (HfSiO x) film, hafnium aluminate (HfAlO x The dielectric film 31 may be a silicon oxynitride (HfSiON) film, a hafnium silicon oxynitride (HfSiON) film, or a hafnium aluminum oxynitride (HfAlON) film. The thickness of the dielectric film 31 is, for example, 1 nm or more and 30 nm or less. An opening 31S for a source and an opening 31D for a drain are formed in the dielectric film 31. The opening 31S is connected to the recess 40S, and the opening 31D is connected to the recess 40D.

[0030] The regrown layer 41S is located on the channel layer 23 or the barrier layer 22 within the recess 40S. The regrown layer 41D is located on the channel layer 23 or the barrier layer 22 within the recess 40D. The regrown layer 41S and the regrown layer 41D are, for example, n-type GaN layers. The regrown layer 41S and the regrown layer 41D contain germanium (Ge) or Si as an n-type impurity. The electrical resistance of the regrown layer 41S and the regrown layer 41D is lower than the electrical resistance of the channel layer 23. For example, the regrown layer 41S and the regrown layer 41D are formed by regrowth of an n-type GaN layer after the recess 40S and the recess 40D are formed in the nitride semiconductor layer 20.

[0031] The source electrode 42S is on the regrown layer 41S, and the drain electrode 42D is on the regrown layer 41D. The source electrode 42S contacts the regrown layer 41S, and the drain electrode 42D contacts the regrown layer 41D. The source electrode 42S makes ohmic contact with the regrown layer 41S, and the drain electrode 42D makes ohmic contact with the regrown layer 41D.

[0032] The passivation film 50 covers the dielectric film 31, the regrown layer 41S, the regrown layer 41D, the source electrode 42S, and the drain electrode 42D. The passivation film 50 is, for example, a SiN film. The thickness of the passivation film 50 is, for example, 5 nm to 50 nm in the uniform portion on the dielectric film 31. The passivation film 50 has a source opening 50S, a drain opening 50D, and a gate opening 50G formed therein. The opening 50S reaches the source electrode 42S, and the opening 50D reaches the drain electrode 42D. In a plan view, the opening 50G is located between the openings 50S and 50D. The opening 50G reaches the dielectric film 31.

[0033] In plan view, the gate electrode 43 is located between the source electrode 42S and the drain electrode 42D. The gate electrode 43 is located on the passivation film 50 and the dielectric film 31, and contacts the dielectric film 31 through an opening 50G.

[0034] Next, a method for manufacturing the semiconductor device 1 according to the embodiment will be described. Figures 2 to 7 are cross-sectional views showing a method for manufacturing the semiconductor device 1 according to the embodiment.

[0035] 2, a nitride semiconductor layer 20 is formed on a substrate 10 by, for example, metal organic chemical vapor deposition (MOCVD). In forming the nitride semiconductor layer 20, a buffer layer 21, a barrier layer 22, a channel layer 23, and a cap layer 24 are formed in this order. In this formation process, iron is doped into the buffer layer 21, but not into the barrier layer 22 and the channel layer 23.

[0036] When forming the buffer layer 21, the temperature in the chamber is set to 1000°C or higher and 1100°C or lower, the pressure in the chamber is set to 10 kPa or higher and 15 kPa or lower, and the V / III ratio is set to 1000 or higher and 1100 or lower. The V / III ratio is the ratio of the amount (moles) of Group V elements supplied per unit time to the amount (moles) of Group III elements supplied per unit time.

[0037] Next, as shown in FIG. 3, a dielectric film 31 is formed on the nitride semiconductor layer 20.

[0038] 4, a source opening 31S and a drain opening 31D are formed in the dielectric film 31, and a source recess 40S and a drain recess 40D are formed in the nitride semiconductor layer 20. The bottoms of the recesses 40S and 40D may be closer to the lower surface of the nitride semiconductor layer 20 than to the upper surface 23A of the channel layer 23. That is, the recesses 40S and 40D may be formed deeper than the upper surface 23A of the channel layer 23. The bottoms of the recesses 40S and 40D may be in the channel layer 23 or in the barrier layer 22. The openings 31S, 31D, recesses 40S, and recesses 40D can be formed by, for example, reactive ion etching (RIE) using a mask (not shown).

[0039] 5, a regrown layer 41S is formed on the channel layer 23 or the barrier layer 22 in the recess 40S, and a regrown layer 41D is formed on the channel layer 23 or the barrier layer 22 in the recess 40D. The regrown layer 41S and the regrown layer 41D can be formed by, for example, evaporation, sputtering, physical vapor deposition (PVD) such as molecular beam epitaxy (MBE), or metalorganic chemical vapor deposition (MOCVD).

[0040] Next, as shown in FIG. 6, a source electrode 42S is formed on the regrown layer 41S, and a drain electrode 42D is formed on the regrown layer 41D. To form the source electrode 42S and the drain electrode 42D, a metal layer (not shown) that constitutes the source electrode 42S and the drain electrode 42D is first formed. When forming the metal layer, for example, a growth mask (not shown) having an opening formed in the region where the metal layer is to be formed is used for film formation, and then the growth mask is removed together with the metal layer (not shown) formed thereon. In other words, lift-off is performed.

[0041] 7, a passivation film 50 is formed on the dielectric film 31, the regrown layer 41S, the regrown layer 41D, the source electrode 42S, and the drain electrode 42D. The passivation film 50 covers the dielectric film 31, the regrown layer 41S, the regrown layer 41D, the source electrode 42S, and the drain electrode 42D.

[0042] Next, an opening 50G for a gate is formed in the passivation film 50 (see FIG. 1). The opening 50G can be formed by, for example, RIE using a mask (not shown).

[0043] Next, a gate electrode 43 that contacts the dielectric film 31 through the opening 50G is formed on the passivation film 50 and the dielectric film 31 (see FIG. 1). When forming the gate electrode 43, for example, a metal layer is formed using a growth mask (not shown) that has an opening formed in the region where the gate electrode 43 is to be formed, and then the growth mask is removed together with the metal layer (not shown) formed thereon. In other words, lift-off is performed.

[0044] Next, an opening 50S for the source and an opening 50D for the drain are formed in the passivation film 50 (see FIG. 1). The openings 50S and 50D can be formed by, for example, RIE using a mask (not shown).

[0045] In this manner, the semiconductor device 1 can be manufactured.

[0046] In the semiconductor device 1 according to the embodiment, the buffer layer 21 contains Fe atoms as an impurity (dopant), which allows the buffer layer 21 to have high resistance and facilitates high output and high-frequency characteristics. Furthermore, because the upper surface 21A of the buffer layer 21, the upper surface 22A of the barrier layer 22, and the upper surface 23A of the channel layer 23 have N polarity, diffusion of Fe atoms from the buffer layer 21 to the channel layer 23 and reduction in electron mobility due to the Fe atoms diffused into the channel layer 23 are less likely to occur than in the case of Ga polarity. Therefore, by reducing the distance L1 between the upper surface 21A of the buffer layer 21 and the lower surface 23B of the channel layer 23, high electron mobility can be achieved in the channel region 26, while improving heat dissipation (thermal conduction) from the channel layer 23 to the substrate 10.

[0047] Furthermore, since the upper surface 22A of the barrier layer 22 and the upper surface 23A of the channel layer 23 have N polarity, the distance between the channel region 26 and the source electrode 42S and the drain electrode 42D can be easily shortened, and low resistance can be easily achieved.

[0048] The thickness of the barrier layer 22 is, for example, 1 nm or more and 50 nm or less. If the thickness of the barrier layer 22 is less than 1 nm, the density of the 2DEG may be low, reducing electron mobility, or the number of Fe atoms diffusing from the buffer layer 21 to the channel layer 23 may increase. If the thickness of the barrier layer 22 is greater than 50 nm, the thermal conduction from the channel layer 23 to the substrate 10 may decrease. The thickness of the barrier layer 22 may be 5 nm or more and 40 nm or less, or may be 10 nm or more and 30 nm or less. In this embodiment, the thickness of the barrier layer 22 is equal to the distance L1.

[0049] The average concentration of Fe atoms in the channel layer 23 is, for example, 2×10 16 cm -3 The average concentration of Fe atoms in the channel layer 23 is 2×10 16 cm -3 When the average concentration of Fe atoms in the channel layer 23 is, for example, 1.5×10 16 cm -3May be less than 1 x 10 16 cm -3 The concentration of Fe atoms in the channel layer 23 may be less than 1000 ppm. If the concentration of Fe atoms in the channel layer 23 is too low, the characteristics will not be degraded.

[0050] The average concentration of Fe atoms in the buffer layer 21 is, for example, 5×10 17 cm -3 The average concentration of Fe atoms in the buffer layer 21 is 5×10 17 cm -3 When the average concentration of Fe atoms in the buffer layer 21 is 7×10 or more, the buffer layer 21 can have a high resistance. 17 cm -3 May be greater than 1 x 10 18 cm -3 The average concentration of Fe atoms in the buffer layer 21 may be, for example, 1×10 20 cm -3 The average concentration of Fe atoms in the buffer layer 21 is 1×10 or less. 20 cm -3 If the average concentration of Fe atoms is higher than 1×10, the crystallinity of the buffer layer 21 may be reduced, and the crystallinity of the barrier layer 22, the channel layer 23, and the cap layer 24 may also be reduced. 20 cm -3 If an attempt is made to form the buffer layer 21 having a resistivity higher than this, Fe may precipitate, which may cause abnormal growth of the barrier layer 22 and the channel layer 23 thereon. For example, the buffer layer 21 has a resistivity of 1 MΩ·m or more.

[0051] The concentration of Fe atoms in the buffer layer 21 and the concentration of Fe atoms in the channel layer 23 can be measured by secondary ion mass spectrometry (SIMS).

[0052] Furthermore, when the buffer layer 21 is a GaN layer, the barrier layer 22 is an AlGaN layer, and the channel layer 23 is a GaN layer, the buffer layer 21, the barrier layer 22, and the channel layer 23 can be easily and stably formed.

[0053] Next, a modification of the embodiment will be described. The modification differs from the first embodiment mainly in the configuration of the nitride semiconductor layer 20. Fig. 8 is a cross-sectional view showing a semiconductor device according to the modification of the embodiment.

[0054] As shown in FIG. 8, in a semiconductor device 2 according to a modified example of the embodiment, a nitride semiconductor layer 20 has a nucleation layer 27 and a second buffer layer 28 in addition to a buffer layer 21, a barrier layer 22, a channel layer 23 and a cap layer 24.

[0055] The nucleation layer 27 is located between the substrate 10 and the buffer layer 21. The nucleation layer 27 is, for example, an AlN layer. An upper surface 27A of the nucleation layer 27 has N polarity, and a lower surface 27B has Al polarity. The nucleation layer 27 functions as a nucleus for the growth of the nitride semiconductor layer 20.

[0056] The second buffer layer 28 is located between the buffer layer 21 and the barrier layer 22. The second buffer layer 28 is, for example, a GaN layer, and the conductivity type of the second buffer layer 28 is undoped (i-type). An upper surface 28A of the second buffer layer 28 has N polarity, and a lower surface 28B has Ga polarity. The second buffer layer 28 makes it difficult for Fe atoms to diffuse from the barrier layer 22 to the channel layer 23. Therefore, the average concentration of Fe atoms in the channel layer 23 of the modified example is smaller than the average concentration of Fe atoms in the channel layer 23 of the embodiment. Furthermore, in the modified example, the average concentration of Fe atoms in the channel layer 23 is smaller than the average concentration of Fe atoms in the barrier layer 22, the average concentration of Fe atoms in the barrier layer 22 is smaller than the average concentration of Fe atoms in the second buffer layer 28, and the average concentration of Fe atoms in the second buffer layer 28 is smaller than the average concentration of Fe atoms in the buffer layer 21.

[0057] Other configurations of the semiconductor device 2 are the same as those of the semiconductor device 1. The semiconductor device 2 also provides the same effects as the semiconductor device 1.

[0058] The distance L1 is, for example, 1 nm or more and 50 nm or less. If the distance L1 is less than 1 nm, the barrier layer 22 may become thin, resulting in a low 2DEG density and reduced electron mobility, or Fe atoms may be more likely to diffuse from the buffer layer 21 to the channel layer 23. If the distance L1 is greater than 50 nm, the heat dissipation from the channel layer 23 to the substrate 10 may be reduced. The distance L1 may be 5 nm or more and 40 nm or less, or 10 nm or more and 30 nm or less.

[0059] Here, an experiment conducted by the inventors of the present application will be described. In this experiment, SiC substrates 60 with C-polarity or Si-polarity on the upper surface were prepared, and GaN layers 61 containing Fe were formed on the SiC substrates. GaN layers 62 without intentional doping with Fe atoms were then formed on the GaN layer 61. In the formation of the GaN layer 61, the average concentration was 1×10 18 cm -3 The GaN layer 61 was doped with Fe atoms so that the thickness thereof was 500 nm. The GaN layer 62 was 1200 nm. The concentration of Fe atoms was measured for each sample by SIMS. The results are shown in FIG. 9. In sample No. 1, which used a SiC substrate 60 with an upper surface having a Si polarity, the upper surfaces of the GaN layer 61 and the GaN layer 62 had a Ga polarity, while in sample No. 2, which used a SiC substrate 60 with an upper surface having a C polarity, the upper surfaces of the GaN layer 61 and the GaN layer 62 had an N polarity.

[0060] 9, the concentration of Fe atoms in the GaN layer 62 decreases with increasing distance from the interface 63 between the GaN layers 61 and 62. However, in sample No. 1, the concentration of Fe atoms in the GaN layer 62 is 1×10 16 cm -3 This is because, when the GaN layer 61 is used as a buffer layer and the GaN layer 62 is used as a channel layer with the same polarity as in sample No. 1, the concentration of Fe atoms in the channel region is reduced to 1×10 16 cm -3On the other hand, in sample No. 2, the concentration of Fe atoms in the GaN layer 62 is 1×10 16 cm -3 This means that when the GaN layer 61 is used as a buffer layer and the GaN layer 62 is used as a channel layer with the same polarity as in sample No. 2, if the channel region is about 50 nm away from the buffer layer containing Fe, the concentration of Fe atoms in the channel region can be reduced to 1×10 16 cm -3 The following shows what can be achieved: Therefore, according to Sample No. 2, the distance between the buffer layer containing Fe and the channel region can be made much shorter than in Sample No. 1, and the thermal resistance can be reduced much more.

[0061] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0062] 1, 2: Semiconductor device 10: Circuit board 20: Nitride semiconductor layer 21: Buffer layer 21A, 22A, 23A, 24A, 27A, 28A: Top 21B, 22B, 23B, 24B, 27B, 28B: Bottom surface 22: Barrier layer 23: Channel layer 24: Cap layer 26: Channel region 27: Nucleation layer 28: Second buffer layer 31: Dielectric film 31D, 31S: Opening 40D, 40S: recessed 41D, 41S: Regrowth layer 42D: Drain electrode 42S: Source electrode 43: Gate electrode 50: Passivation film 50D, 50G, 50S: Open 60:SiC substrate 61, 62: GaN layer 63: Interface L1: distance

Claims

1. a buffer layer containing iron atoms and having a nitrogen polarity on the top surface; a barrier layer having a nitrogen polarity on the upper surface and above the buffer layer; a channel layer having a nitrogen polarity on the top surface and above the barrier layer; The semiconductor device has:

2. 2. The semiconductor device according to claim 1, wherein the barrier layer has a thickness of 1 nm or more and 50 nm or less.

3. 2. The semiconductor device according to claim 1, wherein a distance between the upper surface of said buffer layer and the lower surface of said channel layer is not less than 1 nm and not more than 50 nm.

4. The average concentration of iron atoms in the channel layer is 2×10 １６ cm －３ 4. The semiconductor device according to claim 1, wherein:

5. The average concentration of iron atoms in the buffer layer is 5×10 １７ cm －３ The semiconductor device according to any one of claims 1 to 3, wherein:

6. the barrier layer has a thickness of 1 nm or more and 50 nm or less; The average concentration of iron atoms in the channel layer is 2×10 １６ cm －３ is as follows: The average concentration of iron atoms in the buffer layer is 5×10 １７ cm －３ 2. The semiconductor device according to claim 1, wherein:

7. the buffer layer is a gallium nitride layer; the barrier layer is an aluminum gallium nitride layer; 7. The semiconductor device according to claim 1, wherein the channel layer is a gallium nitride layer.

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