Substrate for semiconductor package and method for manufacturing substrate for semiconductor package

By employing barrier metal films to separate wirings from the insulating layers, the issue of metal diffusion-induced short-circuiting is resolved, enhancing the insulation reliability of organic interposers.

JP2025142089APending Publication Date: 2025-09-29RESONAC CORP
View PDF 6 Cites 0 Cited by

Patent Information

Application Number
JP2025120589
Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Priority Date
2016-03-25
Filing Date
2025-07-17
Publication Date
2025-09-29

AI Technical Summary

Technical Problem

The diffusion of metal materials used for forming fine wirings in organic insulating laminates leads to short-circuiting issues, compromising the insulation reliability of organic interposers.

Method used

The use of barrier metal films, specifically a first barrier metal film between the wiring and the inner surface of the groove and a second barrier metal film between the wiring and the second organic insulating layer, prevents metal diffusion and enhances insulation reliability.

Benefits of technology

The implementation of barrier metal films effectively suppresses short circuits between wirings, improving the insulation reliability of organic interposers by preventing metal diffusion into the insulating layers.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure 2025142089000001_ABST
    Figure 2025142089000001_ABST
Patent Text Reader

Abstract

To provide an organic interposer and a method for manufacturing the organic interposer capable of improving insulation reliability.SOLUTION: An organic interposer 10 includes: an organic insulating laminate 12 comprising a plurality of organic insulating layers; and a plurality of wires 13 arranged in the organic insulating laminate 12, where the wires 13 and the organic insulating layers are separated by a barrier metal film 14. The organic insulating laminate 12 may include: a first organic insulating layer 21 having a plurality of grooves 21a having the wires 13 disposed therein; and a second organic insulating layer 22 laminated on the first organic insulating layer 21 in such a way as to embed the wires 13.SELECTED DRAWING: Figure 2
Need to check novelty before this filing date? Find Prior Art

Description

[Technical Field]

[0001] FIELD The present disclosure relates to organic interposers and methods for manufacturing organic interposers. [Background technology]

[0002] To increase the density and performance of semiconductor packages, a packaging format has been proposed in which chips with different performance are mixed in a single package. In this case, cost-effective, high-density interconnect technology between chips is becoming important (see, for example, Patent Document 1).

[0003] Non-Patent Documents 1 and 2 describe a package-on-package (PoP) configuration in which different packages are connected by stacking them on top of one another using flip-chip mounting. This PoP configuration is widely used in smartphones, tablet devices, etc.

[0004] Furthermore, other forms of packaging multiple chips at high density have been proposed, such as packaging technology using an organic substrate with high-density wiring (organic interposer), fan-out type packaging technology (FO-WLP: Fan Out-Wafer Level Package) with through-mold vias (TMV: Through Mold Via), packaging technology using silicon or glass interposers, packaging technology using through-silicon vias (TSV: Through Silicon Via), and packaging technology using chips embedded in a substrate for inter-chip transmission.

[0005] In particular, when semiconductor chips are mounted on an organic interposer or FO-WLP, a fine wiring layer is required to electrically connect the semiconductor chips with each other at high density (see, for example, Patent Document 2). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Special Publication No. 2012-529770 [Patent Document 2] US Patent Application Publication No. 2011 / 0221071 [Non-patent literature]

[0007] [Non-Patent Document 1] Jinseong Kim et al., “Application of Through Mold Via (TMV) as PoP Base Package”, Electronic Components and Technology Conference (ECTC), p.1089-1092 (2008) [Non-patent document 2] SW Yoon et al., “Advanced Low Profile PoP Solution with Embedded Wafer Level PoP (eWLB-PoP) Technology”, ECTC, p.1250-1254 (2012) Summary of the Invention [Problem to be solved by the invention]

[0008] An organic interposer having a laminate (organic insulating laminate) formed by stacking multiple organic insulating layers may be used in build-up substrates, wafer-level packages (WLPs), fan-out PoP bottom packages, etc. For example, when multiple fine wirings with line widths and space widths of 10 μm or less are arranged in this organic insulating laminate, the wirings are formed using the trench method. The trench method is a method in which a metal layer that will become the wiring is formed in a trench (groove) formed in the surface of an organic insulating layer by plating or other methods. Therefore, the shape of the wiring formed on the organic insulating layer follows the shape of the groove.

[0009] When forming fine wiring in an organic insulating laminate by trench processing, a highly conductive metal material such as copper may be used to reduce costs and suppress increases in wiring resistance. When such metal material is used to form wiring, the metal material may diffuse into the organic insulating laminate. In this case, there is a risk of short-circuiting between wirings via the diffused metal material, which poses a problem in the insulation reliability of the organic interposer.

[0010] An object of the present invention is to provide an organic interposer that can improve insulation reliability and a method for manufacturing the same. [Means for solving the problem]

[0011] The organic interposer according to the first aspect of the present invention comprises an organic insulating laminate including a plurality of organic insulating layers and a plurality of wirings arranged within the organic insulating laminate, the wirings and the organic insulating layers being separated by a barrier metal film.

[0012] In this organic interposer, the wiring and the organic insulating layer are separated by a barrier metal film. Therefore, the diffusion of the metal material in the wiring into the organic insulating laminate is suppressed by the barrier metal film. Therefore, short circuits between multiple wirings via the diffused metal material can be suppressed, thereby improving the insulation reliability of the organic interposer.

[0013] The organic insulating laminate may include a first organic insulating layer having a plurality of grooves in which wiring is arranged, and a second organic insulating layer laminated on the first organic insulating layer so as to embed the wiring. In this case, each of the plurality of wirings has a shape that conforms to the grooves of the first organic insulating layer. Therefore, by forming a plurality of grooves with fine widths and intervals, fine wiring can be easily formed.

[0014] The barrier metal film may include a first barrier metal film provided between the wiring and the inner surface of the trench, and a second barrier metal film provided between the wiring and the second organic insulating layer. In this case, the first barrier metal film effectively suppresses diffusion of the metal material in the wiring into the first organic insulating layer. Furthermore, the second barrier metal film effectively suppresses diffusion of the metal material into the second organic insulating layer.

[0015] The first barrier metal film may contain at least one of titanium, nickel, palladium, chromium, tantalum, tungsten, and gold, which are all less likely to diffuse into the first and second organic insulating layers, thereby further improving the insulation reliability of the organic interposer.

[0016] The second barrier metal film may be a plated film. In this case, the second barrier metal film can be selectively formed on the wiring in the trench, which simplifies the manufacturing process of the organic interposer.

[0017] The second barrier metal film may be a nickel-plated film. In this case, the second barrier metal film can be easily formed with excellent flatness. In addition, nickel is less likely to diffuse into the first and second organic insulating layers, which can favorably improve the insulation reliability of the organic interposer.

[0018] The second barrier metal film may be a palladium plating film. In this case, the second barrier metal film can be easily thinned. In addition, since palladium does not easily diffuse into the first and second organic insulating layers, the insulation reliability of the organic interposer can be suitably improved.

[0019] The thickness of the second barrier metal film may be 0.001 μm or more and 1 μm or less, in which case the second barrier metal film effectively prevents the metal material in the wiring from diffusing into the second organic insulating layer.

[0020] The surface roughness of the second barrier metal film may be 0.01 μm or more and 1 μm or less. In this case, the second barrier metal film can adhere well to the second organic insulating layer. Furthermore, breaks in the organic interposer due to the surface roughness of the second barrier metal film can be suppressed.

[0021] The thickness of the first organic insulating layer may be 1 μm or more and 10 μm or less, in which case a plurality of grooves having widths and intervals of 10 μm or less can be formed using the first organic insulating layer.

[0022] The first organic insulating layer may be a cured film formed by curing a photosensitive organic insulating resin containing a photoacid generator, a compound having a phenolic hydroxyl group, and a thermosetting resin. In this case, grooves with fine widths and intervals can be easily formed in the first organic insulating layer. In addition, the moisture content of the first organic insulating layer can be reduced, making it difficult for metal materials to diffuse into the first organic insulating layer. This improves the insulation reliability of the organic interposer.

[0023] A method for manufacturing an organic interposer according to a second aspect of the present invention includes a first step of forming a plurality of grooves in a first organic insulating layer, a second step of forming a first barrier metal film on the first organic insulating layer so as to cover the inner surfaces of the grooves, a third step of forming a wiring layer on the first barrier metal film so as to fill the grooves, a fourth step of thinning the wiring layer so as to expose the first organic insulating layer, a fifth step of forming a second barrier metal film so as to cover the wiring layer in the grooves, and a sixth step of forming a second organic insulating layer on the first organic insulating layer and the second barrier metal film.

[0024] In this method for manufacturing an organic interposer, a first barrier metal film can be formed between the inner surface of each groove and the wiring layer by performing steps 1 to 3. Furthermore, a second barrier metal film can be formed between the wiring layer and the second organic insulating layer in the stacking direction of the organic insulating layers by performing steps 4 to 6. Therefore, the first and second barrier metal films suppress diffusion of the metal material in the wiring layer into the first and second organic insulating layers. Therefore, short circuits between multiple wirings via the diffused metal material can be suppressed, thereby improving the insulation reliability of the organic interposer.

[0025] In the third step, the wiring layer may be formed by plating using the first barrier metal film as a seed layer. In this case, the wiring layer can be formed so that the first barrier metal film is sandwiched between the first organic insulating layer and the wiring layer. This effectively suppresses the diffusion of metal materials in the wiring layer into the first organic insulating layer.

[0026] In the fifth step, the second barrier metal film may be formed by plating using the wiring layer as a seed layer. In this case, the second barrier metal film can be selectively formed on the wiring layer, which simplifies the manufacturing process of the organic interposer.

[0027] In the fourth step, a portion of the wiring layer in the groove may be removed, and in the fifth step, a second barrier metal film may be formed to fill the groove. In this case, since the second barrier metal film is formed to fill the groove, it is possible to suppress the formation of steps in the organic interposer due to the second barrier metal film. This allows semiconductor elements and the like to be mounted smoothly on the organic interposer. [Effects of the Invention]

[0028] According to the present invention, it is possible to provide an organic interposer having good insulation reliability and a method for manufacturing the same. [Brief explanation of the drawings]

[0029] [Figure 1]FIG. 1 is a schematic cross-sectional view of a semiconductor package having an organic interposer according to this embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view of the organic interposer according to this embodiment. [Figure 3] 3(a) to 3(c) are diagrams illustrating a method for manufacturing an organic interposer. [Figure 4] 4(a) and (b) are diagrams illustrating a method for manufacturing an organic interposer. [Figure 5] 5(a) and 5(b) are diagrams illustrating a method for manufacturing an organic interposer. [Figure 6] 6(a) and 6(b) are diagrams illustrating a method for manufacturing an organic interposer. [Figure 7] 7(a) and (b) are diagrams illustrating a method for manufacturing an organic interposer. [Figure 8] 8(a) and (b) are diagrams illustrating a method for manufacturing an organic interposer. [Figure 9] 9(a) and 9(b) are diagrams illustrating a method for manufacturing an organic interposer. [Figure 10] 10(a) and 10(b) are diagrams illustrating a method for manufacturing an organic interposer. [Figure 11] FIG. 11(a) is a plan view showing a sample for measurement and evaluation of the example, and FIG. 11(b) is a cross-sectional view taken along line XIb-XIb in FIG. 11(a). [Figure 12] FIG. 12(a) is a plan view showing a sample for measurement and evaluation of a comparative example, and FIG. 12(b) is a cross-sectional view taken along line XIIb-XIIb in FIG. 12(a). [Figure 13] FIG. 13(a) is a graph showing the results of the high-acceleration life test of Example 2 and Comparative Example 2, and FIG. 13(b) is a graph showing the results of the high-acceleration life test of Example 3 and Comparative Example 3. [Figure 14]Figure 14(a) shows the EDX analysis results for Cu in a cross-sectional sample of the measurement and evaluation specimen of Example 3, Figure 14(b) shows the EDX analysis results for Ti in the cross-sectional sample, and Figure 14(c) shows the EDX analysis results for Ni in the cross-sectional sample. DETAILED DESCRIPTION OF THE INVENTION

[0030] Hereinafter, the present embodiment will be described in detail with reference to the drawings. In the following description, the same or equivalent parts will be denoted by the same reference numerals, and duplicated explanations will be omitted. Furthermore, unless otherwise specified, the positional relationships such as up, down, left, and right will be based on the positional relationships shown in the drawings. Furthermore, the dimensional ratios of the drawings are not limited to those shown in the drawings.

[0031] When terms such as "left," "right," "front," "back," "top," "bottom," "upper," "lower," "first," and "second" are used in the description and claims of the present embodiment, they are intended for explanatory purposes and do not necessarily mean that these relative positions are permanent. Furthermore, the terms "layer" and "film" encompass not only structures that are formed over the entire surface when viewed from a plan view, but also structures that are formed on a portion of the surface. Furthermore, the term "process" includes not only independent processes but also processes that cannot be clearly distinguished from other processes, as long as the intended purpose of the process is achieved. Furthermore, in the numerical ranges described in stages in this specification, the upper or lower limit of a certain numerical range may be replaced with the upper or lower limit of the numerical range of another process.

[0032] 1 is a schematic cross-sectional view of a semiconductor package having an organic interposer according to this embodiment. The organic interposer of the present disclosure is suitable for use in a package configuration that requires an interposer for mounting different types of chips together.

[0033] As shown in FIG. 1, a semiconductor package 100 is a device in which semiconductor chips 2A and 2B are mounted on an organic interposer 10 provided on a substrate 1. The semiconductor chips 2A and 2B are fixed to the organic interposer 10 by corresponding underfills 3A and 3B, respectively, and are electrically connected to each other via surface wiring 16 (details of which will be described later) provided within the organic interposer 10. The substrate 1 is an encapsulated body formed by encapsulating semiconductor chips 2C and 2D and electrodes 5A and 5B with an insulating material 4. The semiconductor chips 2C and 2D in the substrate 1 can be connected to an external device via the electrodes exposed from the insulating material 4. The electrodes 5A and 5B function, for example, as conductive paths for electrically connecting the organic interposer 10 to an external device.

[0034] Each of the semiconductor chips 2A to 2D may be, for example, a graphic processing unit (GPU), a volatile memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), a non-volatile memory such as a flash memory, an RF chip, a silicon photonics chip, a microelectromechanical system (MEMS), or a sensor chip. The semiconductor chips 2A to 2D may have TSVs. Each of the semiconductor chips 2A to 2D may be, for example, a chip in which semiconductor elements are stacked. In this case, semiconductor elements stacked using TSVs can be used. The thickness of the semiconductor chips 2A and 2B is, for example, 200 μm or less. From the viewpoint of thinning the semiconductor package 100, the thickness of the semiconductor chips 2A and 2B is preferably 100 μm or less. Furthermore, from the viewpoint of ease of handling, the thickness of the semiconductor chips 2A and 2B is more preferably 30 μm or more.

[0035] The underfills 3A and 3B are, for example, capillary underfill (CUF), mold underfill (MUF), paste underfill (NCP), film underfill (NCF), or photosensitive underfill. Each of the underfills 3A and 3B is mainly composed of a liquid curing resin (e.g., epoxy resin). The insulating material 4 is, for example, a curing resin having insulating properties.

[0036] Next, the organic interposer 10 according to this embodiment will be described in detail with reference to FIG. 2. The organic interposer 10 according to this embodiment is an organic substrate that supports semiconductor elements and the like, and is, for example, a build-up substrate formed by laminating a material (prepreg) in which glass cloth or carbon fiber is impregnated with resin, a substrate for wafer-level packaging, a coreless substrate, a substrate fabricated by thermally curing a sealing material, or a substrate in which a chip is sealed or embedded. The shape of the organic interposer 10 depends on the shape of the substrate 11 described below, and may be a wafer shape (approximately circular in plan view) or a panel shape (approximately rectangular in plan view). From the viewpoint of suppressing warpage, the thermal expansion coefficient of the organic interposer 10 is preferably, for example, 40 ppm / °C or less. From the viewpoint of the insulation reliability of the organic interposer 10, the thermal expansion coefficient is preferably 20 ppm / °C or less.

[0037] The organic interposer 10 provided on the substrate 11 shown in Figure 2 includes an organic insulating laminate 12 including a plurality of organic insulating layers, a plurality of wirings 13 arranged within the organic insulating laminate 12, a barrier metal film 14 covering the wirings 13, through wirings 15 penetrating the organic insulating laminate 12, and surface wirings 16 formed on and near the surface of the organic insulating laminate 12.

[0038] The substrate 11 is a support that supports the organic interposer 10. The shape of the substrate 11 in a plan view is, for example, circular or rectangular. If the substrate 11 is circular, it has a diameter of, for example, 200 mm to 450 mm. If the substrate 11 is rectangular, one side of the substrate 11 is, for example, 300 mm to 700 mm.

[0039] The substrate 11 is, for example, a silicon substrate, a glass substrate, or a peelable copper foil. The substrate 11 may be, for example, a build-up substrate, a substrate for wafer-level packaging, a coreless substrate, a substrate produced by thermally curing a sealing material, or a substrate in which a chip is sealed or embedded. When a silicon substrate or a glass substrate is used as the substrate 11, a temporary fixing layer (not shown) may be provided to temporarily fix the organic interposer 10 and the substrate 11. In this case, the substrate 11 can be easily peeled from the organic interposer 10 by removing the temporary fixing layer. Note that the peelable copper foil is a laminate in which a support, a release layer, and a copper foil are stacked in this order. In the peelable copper foil, the support corresponds to the substrate 11, and the copper foil corresponds to the material of a portion of the copper wiring included in the through wiring 15.

[0040] The organic insulating laminate 12 includes a first organic insulating layer 21 having a plurality of grooves 21a in which corresponding wirings 13 are arranged, and a second organic insulating layer 22 laminated on the first organic insulating layer 21 so as to bury the wirings 13. The organic insulating laminate 12 also has a plurality of openings 12a in which through wirings 15 are provided.

[0041] The plurality of grooves 21a are provided on the surface of the first organic insulating layer 21 opposite to the substrate 11. In a cross section taken along a direction perpendicular to the extension direction of the grooves 21a, each of the grooves 21a has a substantially rectangular shape. Therefore, the inner surface of the grooves 21a has side surfaces and a bottom surface. The plurality of grooves 21a also have a predetermined line width L and space width S. Each of the line width L and space width S is, for example, 0.5 μm to 10 μm, preferably 0.5 μm to 5 μm, and more preferably 2 μm to 5 μm. From the viewpoint of realizing high-density transmission of the organic interposer 10, the line width L is preferably 1 μm to 5 μm. The line width L and space width S may be set to be the same as or different from each other. The line width L corresponds to the width of the grooves 21a in a direction perpendicular to the extension direction of the grooves 21a in a plan view. The space width S corresponds to the distance between adjacent grooves 21a. The depth of the groove 21a corresponds to, for example, the thickness of the fourth organic insulating layer 24, which will be described later.

[0042] The surface roughness of the inner surface of the groove portion 21a is preferably 0.01 μm to 0.1 μm. When the surface roughness is 0.01 μm or more, the adhesion of the object that comes into close contact with the first organic insulating layer 21 in the groove portion 21a and the temperature cycle resistance are improved. When the surface roughness is 0.1 μm or less, short circuits of the wiring 13 are suppressed, and the high-frequency characteristics of the wiring 13 tend to be improved. The surface roughness of the inner surface of the groove portion 21a is calculated, for example, by observing the cross section of the groove portion 21a with an electron microscope. Note that the surface roughness is the arithmetic mean roughness (Ra) specified in JIS B 0601 2001, and all references to "surface roughness" below will refer to "surface roughness Ra." Temperature cycle resistance refers to resistance to volumetric changes, performance degradation, damage, etc. that occur due to temperature changes.

[0043] The first organic insulating layer 21 is provided between the substrate 11 and the second organic insulating layer 22. The storage modulus of the first organic insulating layer 21 at room temperature is, for example, 500 MPa to 10 GPa. When the storage modulus is 500 MPa or more, stretching of the first organic insulating layer 21 during grinding can be suppressed. This can prevent, for example, the stretched resin material from covering the wiring 13 in the groove portion 21a. Furthermore, when the storage modulus is 10 GPa or less, for example, breakage of the grinding blade can be prevented, and as a result, increase in the surface roughness of the first organic insulating layer 21, etc. can be suppressed. Note that "room temperature" refers to a temperature of about 25°C.

[0044] The first organic insulating layer 21 includes a third organic insulating layer 23 located on the substrate 11 side and a fourth organic insulating layer 24 located on the second organic insulating layer 22 side. A plurality of openings corresponding to the grooves 21a are provided in a portion of the fourth organic insulating layer 24. The surfaces of the third organic insulating layer 23 exposed by these openings form the bottom surfaces of the inner surfaces of the grooves 21a. The fourth organic insulating layer 24 forms each of the side surfaces of the inner surfaces of the grooves 21a.

[0045] The third organic insulating layer 23 and the fourth organic insulating layer 24 each have a thickness of, for example, 0.5 μm to 10 μm. Therefore, the thickness of the first organic insulating layer 21 is, for example, 1 μm to 20 μm. When the thickness of the first organic insulating layer 21 is 1 μm or more, the first organic insulating layer 21 contributes to stress relaxation of the organic insulating laminate 12, thereby improving the temperature cycle resistance of the organic insulating laminate 12. When the thickness of the first organic insulating layer 21 is 20 μm or less, warping of the organic insulating laminate 12 is suppressed, and, for example, wiring and the like can be easily exposed when the organic insulating laminate 12 is ground. From the viewpoint of forming wiring 13 with a width of 3 μm or less by exposure and development, the thickness of the first organic insulating layer 21 is preferably 15 μm or less, and more preferably 10 μm or less.

[0046] Each of the first organic insulating layer 21 and the second organic insulating layer 22 in the organic insulating laminate 12 is, for example, liquid or film-like and contains a curable insulating material. From the viewpoints of flatness of the organic insulating layer and manufacturing costs, a film-like material (organic insulating material) is preferred. In this case, even if the surface roughness of the substrate 11 is 300 μm or more, for example, the surface roughness of the organic insulating laminate 12 can be reduced. Furthermore, it is preferable that the film-like organic insulating material can be laminated at 40°C to 120°C. By setting the lamination temperature to 40°C or higher, the tack (adhesiveness) of the organic insulating material at room temperature can be prevented from increasing and good handleability can be maintained. By setting the lamination temperature to 120°C or lower, the occurrence of warping in the organic insulating laminate 12 can be suppressed.

[0047] The thermal expansion coefficient of the cured organic insulating material is, for example, 80 ppm / °C or less from the viewpoint of suppressing warpage of the organic insulating layer (and the organic insulating laminate 12). From the viewpoint of the insulation reliability of the organic interposer 10, the thermal expansion coefficient is preferably 70 ppm / °C or less. Furthermore, from the viewpoints of the stress relaxation property and processing accuracy of the organic insulating material, the thermal expansion coefficient is more preferably 20 ppm / °C or more.

[0048] From the viewpoints of ease of processing and processing accuracy, the organic insulating material is preferably a photosensitive organic insulating material (photosensitive insulating resin). From the viewpoints of heat resistance and ease of handling, this photosensitive insulating resin is more preferably a negative-type photosensitive insulating resin. The photocurable insulating resin may contain a photoradical initiator or a photoacid generator, but from the viewpoint of ease of microprocessing, it is preferable that a photoacid generator be contained. From the above viewpoints, the organic insulating layer is most preferably a negative-type photosensitive insulating resin film containing a photoacid generator.

[0049] The photoacid generator is not particularly limited as long as it is a compound that generates an acid upon irradiation with light. From the viewpoint of efficient acid generation, the photoacid generator is preferably, for example, an onium salt compound or a sulfonimide compound. Examples of the onium salt compound include iodonium salts and sulfonium salts. Specific examples include diaryliodonium salts such as diphenyliodonium trifluoromethanesulfonate, diphenyliodonium p-toluenesulfonate, diphenyliodonium hexafluoroantimonate, diphenyliodonium hexafluorophosphate, and diphenyliodonium tetrafluoroborate; triarylsulfonium salts such as triphenylsulfonium trifluoromethanesulfonate, triphenylsulfonium p-toluenesulfonate, and triphenylsulfonium hexafluoroantimonate; 4-tert-butylphenyl-diphenylsulfonium p-toluenesulfonate; and 4,7-di-n-butoxynaphthyltetrahydrothiophenium trifluoromethanesulfonate. Specific examples of the sulfonimide compound include N-(trifluoromethylsulfonyloxy)succinimide, N-(trifluoromethylsulfonyloxy)phthalimide, N-(trifluoromethylsulfonyloxy)diphenylmaleimide, N-(trifluoromethylsulfonyloxy)bicyclo[2.2.1]hept-5-ene-2,3-dicarboximide, N-(trifluoromethylsulfonyloxy)naphthalimide, N-(p-toluenesulfonyloxy)-1,8-naphthalimide, and N-(10-camphorsulfonyloxy)-1,8-naphthalimide.

[0050] From the viewpoint of resolution, a compound having a trifluoromethanesulfonate group, a hexafluoroantimonate group, a hexafluorophosphate group, or a tetrafluoroborate group may be used as the photoacid generator.

[0051] The photosensitive insulating resin is preferably soluble in a 2.38% by mass aqueous solution of tetramethylammonium. From the viewpoints of the resolution, storage stability, and insulation reliability of the photosensitive insulating resin, the photosensitive insulating resin preferably contains a compound having a phenolic hydroxyl group. Examples of the compound having a phenolic hydroxyl group include phenol / formaldehyde condensation novolac resin, cresol / formaldehyde condensation novolac resin, phenol-naphthol / formaldehyde condensation novolac resin, polyhydroxystyrene and its polymer, phenol-xylylene glycol condensation resin, cresol-xylylene glycol condensation resin, and phenol-dicyclopentadiene condensation resin.

[0052] The photosensitive insulating resin preferably contains a thermosetting resin. Examples of thermosetting resins include acrylate resins, epoxy resins, cyanate ester resins, maleimide resins, allylnadimide resins, phenolic resins, urea resins, melamine resins, alkyd resins, unsaturated polyester resins, diallyl phthalate resins, silicone resins, resorcinol formaldehyde resins, triallyl cyanurate resins, polyisocyanate resins, resins containing tris(2-hydroxyethyl)isocyanurate, resins containing triallyl trimellitate, and thermosetting resins synthesized from cyclopentadiene. From the viewpoints of the resolution, insulation reliability, and adhesion to metals of the photosensitive insulating resin, the thermosetting resin is more preferably a compound having a methylol group, an alkoxyalkyl group, or a glycidyl group.

[0053] From the above viewpoints, it is most preferable that each of the first organic insulating layer 21 and the second organic insulating layer 22 be a cured film formed by curing a photosensitive organic insulating resin containing a photoacid generator, a compound having a phenolic hydroxyl group, and a thermosetting resin. Each of the first organic insulating layer 21 and the second organic insulating layer 22 may contain a filler. From the viewpoints of ease of processing and processing accuracy, the average particle size of the filler is, for example, 500 nm or less. It is preferable that the content of the filler in the first organic insulating layer 21 (or the second organic insulating layer 22) is less than 1 mass %. It is also more preferable that the first organic insulating layer 21 and the second organic insulating layer 22 do not contain a filler.

[0054] As described above, the multiple wirings 13 are provided in the corresponding grooves 21a and function as conductive paths within the organic interposer 10. For this reason, the width of the wirings 13 is approximately equal to the line width L of the grooves 21a, and the distance between adjacent wirings 13 is approximately equal to the space width S of the grooves 21a. From the viewpoint of effectively functioning as conductive paths, the wirings 13 preferably contain a metal material having high conductivity. Examples of metal materials having high conductivity include copper, aluminum, or silver. These metal materials tend to diffuse into the organic insulating laminate 12 when heated. From the viewpoints of conductivity and cost, the metal material contained in the wirings 13 is preferably copper.

[0055] The barrier metal film 14 is a metal film provided to separate the wiring 13 from the first organic insulating layer 21 and the second organic insulating layer 22. The barrier metal film 14 includes a first barrier metal film 31 provided between the wiring 13 and the inner surface of the groove 21a, and a second barrier metal film 32 provided between the wiring 13 and the second organic insulating layer 22. Therefore, the first barrier metal film 31 is provided to separate the wiring 13 from the inner surface of the groove 21a (i.e., the first organic insulating layer 21). In addition, the second barrier metal film 32 is provided to separate the wiring 13 from the second organic insulating layer 22.

[0056] The first barrier metal film 31 is a conductive film for preventing diffusion of metal materials in the wiring 13 into the first organic insulating layer 21, and is formed along the inner surface of the groove 21a. The first barrier metal film 31 contains at least one of titanium, nickel, palladium, chromium, tantalum, tungsten, and gold, which is a metal material that is unlikely to diffuse into the organic insulating layer. From the viewpoint of adhesion to the inner surface of the groove 21a, the first barrier metal film 31 is preferably a titanium film or an alloy film containing titanium. Furthermore, from the viewpoint of forming the first barrier metal film 31 by sputtering, the first barrier metal film 31 is preferably a titanium film, a tantalum film, a tungsten film, a chromium film, or an alloy film containing at least one of titanium, tantalum, tungsten, and chromium.

[0057] The thickness of the first barrier metal film 31 is less than half the width of the groove portion 21a and less than the depth of the groove portion 21a, and is, for example, 0.001 μm to 0.5 μm. From the viewpoint of preventing diffusion of the metal material in the interconnect 13, the thickness of the first barrier metal film 31 is preferably 0.01 μm to 0.5 μm. Furthermore, from the viewpoint of flatness of the first barrier metal film 31 and increasing the amount of current flowing through the interconnect 13, the thickness of the first barrier metal film 31 is preferably 0.001 μm to 0.3 μm. For these reasons, the thickness of the first barrier metal film 31 is most preferably 0.01 μm to 0.3 μm.

[0058] The second barrier metal film 32 is a conductive film for preventing diffusion of metal materials in the wiring 13 into the second organic insulating layer 22, and is formed to cover the wiring 13. The second barrier metal film 32 contains at least one of the metal materials that are unlikely to diffuse into the organic insulating layer, such as titanium, nickel, palladium, chromium, tantalum, tungsten, cobalt, and gold. The second barrier metal film 32 may be a stack of different metal films.

[0059] The second barrier metal film 32 is preferably a plated film (for example, an electroless plated film) using the wiring 13 as a seed layer. Therefore, the second barrier metal film 32 is preferably a nickel plated film, a palladium plated film, a cobalt plated film, a gold plated film, or an alloy plated film containing at least one of nickel, palladium, cobalt, and gold. From the viewpoints of adhesion to the wiring 13 and temperature cycle resistance, a nickel plated film or a palladium plated film is preferable.

[0060] Examples of nickel plating films include electroless nickel-phosphorus alloy plating films containing phosphorus, electroless nickel-boron alloy plating films containing boron, and electroless nickel-nitrogen alloy plating films containing nitrogen. The nickel content of the nickel plating film is preferably 80% by mass or more. By having a nickel content of 80% by mass or more, the effect of improving the insulation reliability of the organic interposer 10 by the second barrier metal film 32 is effectively exhibited. From the viewpoint of insulation reliability, the nickel plating film is preferably an electroless nickel-phosphorus alloy plating film.

[0061] The second barrier metal film 32 is preferably an electroless palladium plating film, from the viewpoint that good insulation reliability can be obtained with a thickness of 0.1 μm or less. Examples of electroless palladium plating films include displacement palladium plating films, electroless palladium plating films using a formic acid compound as a reducing agent, palladium-phosphorus alloy plating films using hypophosphorous acid or phosphorous acid as a reducing agent, and palladium-boron alloy plating films using a boron compound.

[0062] The thickness of the second barrier metal film 32 is, for example, 0.001 μm to 1 μm. From the viewpoint of the yield of the second barrier metal film 32, the thickness of the second barrier metal film 32 is preferably 0.01 μm to 1 μm. Furthermore, from the viewpoints of improving the production takt time, thinning, and temperature cycle resistance of the second barrier metal film 32, the thickness is more preferably 0.001 μm to 0.5 μm. From the viewpoints of thinning the second barrier metal film 32 and the resolution of the photosensitive insulating resin, the thickness is even more preferably 0.001 μm to 0.3 μm. From these viewpoints, the thickness of the second barrier metal film 32 is most preferably 0.01 μm to 0.3 μm.

[0063] The surface roughness Ra of the second barrier metal film 32 is affected by the surface roughness of the wiring 13 and is, for example, 0.01 μm to 1 μm. When the surface roughness Ra of the second barrier metal film 32 is 0.01 μm or more, it is possible to ensure reliability such as adhesion between the second barrier metal film 32 and the second organic insulating layer 22 and temperature cycle resistance. When the surface roughness Ra of the second barrier metal film 32 is 1 μm or less, it is possible to prevent disconnections in the organic interposer 10 due to unevenness occurring during the formation of the second organic insulating layer 22 and to prevent a decrease in the resolution of the organic insulating laminate 12. From the viewpoint of adhesion to the second organic insulating layer 22, the surface roughness Ra of the second barrier metal film 32 is preferably 0.03 μm or more. From the viewpoint of temperature cycle resistance, it is preferable that the surface roughness Ra of the second barrier metal film 32 is 0.5 μm or less. From the viewpoint of high frequency characteristics, it is more preferable that the surface roughness Ra of the second barrier metal film 32 is 0.1 μm or less. From the above viewpoints, it is most preferable that the surface roughness Ra of the second barrier metal film 32 is 0.03 μm to 0.1 μm.

[0064] In the organic interposer 10, the surface roughness Ra of the combined surface of the first organic insulating layer 21 (i.e., the fourth organic insulating layer 24) and the second barrier metal film 32 is, for example, 0.01 μm to 1 μm. When the surface roughness Ra of the above surface is 0.01 μm or more, the adhesion between the first organic insulating layer 21 (and the second barrier metal film 32) and the second organic insulating layer 22 is improved. Furthermore, when the surface roughness of the above surface is 1 μm or less, warping of the organic insulating laminate 12 is suppressed, and, for example, when the organic insulating laminate 12 is ground, wiring and the like can be easily exposed. The surface roughness Ra of the above surface is calculated, for example, by scanning a 100 × 100 μm area including both the first organic insulating layer 21 and the second barrier metal film 32 using a laser microscope (Olympus Corporation, "LEXT OLS3000").

[0065] The surface roughness Ra of the combined surface of the first organic insulating layer 21 and the second barrier metal film 32 can be controlled by planarizing the wiring 13 and the first organic insulating layer 21. Examples of planarization processes for the surface include chemical mechanical polishing (CMP) and fly-cutting. From the viewpoint of suppressing the occurrence of dishing on the wiring 13, it is preferable to use the fly-cutting method. The fly-cutting method is a method of physically grinding an object using a grinding device such as a surface planer.

[0066] The through wiring 15 is a wiring embedded in the opening 12a of the organic insulating laminate 12, and functions as a connection terminal to an external device. The through wiring 15 is composed of multiple wiring layers 15a to 15c stacked on top of each other. The wiring layer 15b includes a wiring layer formed simultaneously with the wiring 13 and a metal film formed simultaneously with the barrier metal film 14.

[0067] The surface wiring 16 is wiring for electrically connecting the semiconductor chips mounted on the organic interposer 10. Therefore, both ends of the surface wiring 16 are exposed from the organic interposer 10, and the surface wiring 16 other than these both ends is embedded in the organic interposer 10 (more specifically, the second organic insulating layer 22). Therefore, the second organic insulating layer 22 includes at least two organic insulating layers.

[0068] Next, a manufacturing method of the organic interposer 10 according to this embodiment will be described with reference to FIGS. 3 to 10. The organic interposer 10 formed by the manufacturing method described below is particularly suitable for applications requiring miniaturization and increased pin count. FIG. 4(b) is an enlarged view of a portion of FIG. 4(a). Similarly, each of FIGS. 5(b), 6(b), 7(b), 8(b), and 9(b) is an enlarged view of a portion of the corresponding drawing.

[0069] First, as a first step, as shown in FIG. 3(a), a wiring layer 15a is formed on the substrate 11. The wiring layer 15a is formed by patterning a metal film formed on the substrate 11. In the first step, the metal film is formed by, for example, a coating method, a physical vapor deposition method (PVD method) such as vacuum deposition or sputtering, a printing method or spray method using a metal paste, or various plating methods. In this embodiment, copper foil is used as the metal film.

[0070] In addition, when a temporary fixing layer (not shown) is provided between the substrate 11 and the wiring layer 15a, the temporary fixing layer may contain, for example, a resin containing a non-polar component such as polyimide, polybenzoxazole, silicone, or fluorine; a resin containing a component that expands or foams when heated or exposed to ultraviolet light (UV); a resin containing a component that undergoes a crosslinking reaction when heated or exposed to UV light; or a resin that generates heat when exposed to light. Examples of methods for forming the temporary fixing layer include spin coating, spray coating, and lamination. From the viewpoint of achieving both high levels of ease of handling and carrier releasability, it is preferable that the temporary fixing layer be easily peeled off by an external stimulus such as light or heat. From the viewpoint of being able to peel the temporary fixing layer so that it does not remain on the organic interposer 10 to be manufactured later, it is most preferable that the temporary fixing layer contain a resin that expands in volume when heated.

[0071] When a temporary fixing layer is provided between the substrate 11 and the wiring layer 15a, the wiring layer 15a may be formed from a peelable copper foil. In this case, the substrate 11 corresponds to the support of the peelable copper foil, and the temporary fixing layer corresponds to the release layer of the peelable copper foil.

[0072] 3(b), a third organic insulating layer 23 is formed on the substrate 11 so as to cover the wiring layer 15a. In the second step, the third organic insulating layer 23, which is a film containing a negative photosensitive insulating resin, is attached to the substrate 11 to cover the wiring layer 15a. Then, the third organic insulating layer 23 is subjected to an exposure process, a development process, a curing process, or the like, as necessary.

[0073] 3(c), in the third step, a fourth organic insulating layer 24 is formed on the third organic insulating layer 23, thereby forming the first organic insulating layer 21. In the third step, similar to the second step, the fourth organic insulating layer 24 in the form of a film containing a negative photosensitive insulating resin is attached to the third organic insulating layer 23. Then, the fourth organic insulating layer 24 is subjected to an exposure process, a development process, a curing process, or the like, as necessary.

[0074] Next, as a fourth step shown in FIGS. 4(a) and 4(b), a plurality of grooves 21a and openings 21b are formed in the first organic insulating layer 21 (also referred to as the first step). In the fourth step, the plurality of grooves 21a and openings 21b are formed by, for example, laser ablation, photolithography, or imprinting. From the viewpoints of miniaturization of the grooves 21a and formation costs, photolithography is preferably used. Therefore, the plurality of grooves 21a are formed by subjecting the first organic insulating layer 21 to exposure and development treatments. The openings 21b are formed so as to expose the wiring layer 15a. Note that when a photosensitive insulating resin is used for the first organic insulating layer 21, the pattern of the grooves 21a can be formed smoothly and in a short time. This allows the wiring described below to have excellent high-frequency characteristics.

[0075] In the photolithography, the photosensitive insulating resin can be exposed by a known method such as a projection exposure method, a contact exposure method, or a direct writing exposure method. In addition, an alkaline aqueous solution such as sodium carbonate or TMAH may be used to develop the photosensitive insulating resin.

[0076] In the fourth step, after forming the plurality of grooves 21a and openings 21b, the first organic insulating layer 21 may be further heat-cured. In this case, for example, the heating temperature is set to 100 to 200°C, and the heating time is set to 30 minutes to 3 hours, to heat-cur the first organic insulating layer 21.

[0077] Next, as a fifth step shown in FIGS. 5(a) and 5(b), a first barrier metal film 31 is formed on the first organic insulating layer 21 so as to cover the inner surface of the groove portion 21a (also referred to as a second step). In the fifth step, the first barrier metal film 31 is formed by, for example, a coating method, a PVD method, a printing method or a spray method using a metal paste, or various plating methods. In the coating method, the first barrier metal film 31 is formed by coating a palladium or nickel complex on the first organic insulating layer 21 and then heating it. In the metal paste method, the first barrier metal film 31 is formed by coating a paste containing metal particles such as nickel or palladium on the first organic insulating layer 21 and then sintering it. In this embodiment, the first barrier metal film 31 is formed by sputtering, which is a type of PVD method. The first barrier metal film 31 is formed so as to also cover the inner surface of the opening portion 21b.

[0078] Next, as a sixth step shown in FIGS. 6(a) and 6(b), a wiring layer 13A is formed on the first barrier metal film 31 so as to fill the grooves 21a (also referred to as a third step). In the sixth step, the wiring layer 13A is formed, for example, by a method using a metal paste or a plating method using the first barrier metal film 31 as a seed layer. The thickness of the wiring layer 13A is preferably 0.5 to 3 times the thickness of the first organic insulating layer 21. When the thickness of the wiring layer 13A is 0.5 times or more, it tends to be possible to suppress an increase in the surface roughness Ra of the wiring 13 formed in a later step. Furthermore, when the thickness of the wiring layer 13A is 3 times or less, it tends to suppress warping of the wiring layer 13A and to provide good adhesion to the first organic insulating layer 21. The wiring layer 13A is formed so as to also fill the openings 21b.

[0079] Next, as shown in FIGS. 7(a) and 7(b), in the seventh step, the wiring layer 13A is thinned so as to expose the first organic insulating layer 21 (also referred to as the fourth step). In the seventh step, the portions of the wiring layer 13A outside the grooves 21a and the openings 21b and the portions of the first barrier metal film 31 that do not cover the grooves 21a or the openings 21b are removed, thereby exposing the first organic insulating layer 21 and thinning the wiring layer 13A. This forms the wiring 13 embedded in the grooves 21a. This thinning process may be a planarization process of the combined surface of the first organic insulating layer 21 and the wiring 13. In this case, the target portions of the wiring layer 13A and the first barrier metal film 31 are removed by CMP or flycutting, and the surface of the first organic insulating layer 21 is polished or ground to be planarized.

[0080] When CMP is used in the seventh step, the slurries used may include, for example, a slurry containing alumina, which is generally used for polishing resins; a slurry containing hydrogen peroxide and silica, which is used for polishing the first barrier metal film 31; and a slurry containing hydrogen peroxide and ammonium persulfate, which is used for polishing the wiring layer 13A. From the viewpoint of reducing costs and controlling the surface roughness Ra to 0.01 μm to 1 μm, it is preferable to grind the first organic insulating layer 21, the first barrier metal film 31, and the wiring layer 13A (wiring 13) using a slurry containing alumina. Using CMP tends to be costly. Furthermore, when the first organic insulating layer 21, the first barrier metal film 31, and the wiring layer 13A (wiring 13) are simultaneously planarized, dishing of the wiring 13 tends to occur due to differences in polishing speed, resulting in significant loss of flatness of the combined surface of the first organic insulating layer 21 and the wiring 13. Therefore, from the viewpoint of setting the surface roughness Ra of the above-mentioned surface to 0.03 μm to 0.1 μm, it is more preferable to grind the first organic insulating layer 21, the first barrier metal film 31, and the wiring layer 13A (wiring 13) by a fly-cut method using a surface planer.

[0081] Next, as shown in FIGS. 8(a) and 8(b), in the eighth step, a second barrier metal film 32 is formed to cover the wiring 13, which is the wiring layer 13A in the trench 21a (also referred to as the fifth step). In the eighth step, the second barrier metal film 32 is formed, for example, by a PVD method, a method using a metal paste, or a plating method using the wiring 13 as a seed layer. From the viewpoint of forming the second barrier metal film 32 on the wiring 13 with good selectivity, it is preferable to form the second barrier metal film 32 by a plating method using the wiring 13 as a seed layer. Note that, before the plating process, the exposed first organic insulating layer 21 may be cleaned with an acid or protected with benzotriazole or the like. Note that, by going through the eighth step, the wiring layer 15b provided on the wiring layer 15a is completed.

[0082] In the eighth step, the second barrier metal film 32 is preferably formed on the wiring 13 as well as on the portion of the first barrier metal film 31 that contacts the side surface of the trench 21 a. In this case, the wiring 13 can be covered without any gaps by the first barrier metal film 31 and the second barrier metal film 32.

[0083] Next, as a ninth step, as shown in FIGS. 9(a) and 9(b), a second organic insulating layer 22 is formed on the first organic insulating layer 21 and the second barrier metal film 32 (also referred to as a sixth step). In the ninth step, a film-like second organic insulating layer 22 containing a negative-type photosensitive insulating resin is attached to the first organic insulating layer 21 and the second barrier metal film 32. The second organic insulating layer 22 may be the same film as the first organic insulating layer 21, or may be formed using a different photosensitive insulating resin. From the viewpoint of preventing diffusion of the metal constituting the wiring 13, it is preferable not to perform a development process on the second organic insulating layer 22.

[0084] 10(a), in a tenth step, an opening 22a is formed in the second organic insulating layer 22. In the tenth step, the opening 22a is formed so as to expose the wiring layer 15b. The opening 22a is formed by, for example, photolithography or the like.

[0085] Next, as an eleventh step, as shown in FIG. 10(b), a metal material is filled into the opening 22a to form a wiring layer 15c, thereby forming the through wiring 15. In the eleventh step, the wiring layer 15c is formed, for example, by a PVD method or various plating methods. Examples of the metal material include copper, nickel, and tin. After the eleventh step, the organic interposer 10 shown in FIG. 2 is manufactured by forming the surface wiring 16 and the like. If a temporary fixing layer is provided, the organic interposer 10 may be peeled off from the substrate 11.

[0086] According to the organic interposer 10 having the configuration described above, the wiring 13 is separated from the first organic insulating layer 21 and the second organic insulating layer 22 by the barrier metal film 14. Therefore, the diffusion of the metal material in the wiring 13 into the organic insulating laminate is suppressed by the barrier metal film 14. Therefore, it is possible to suppress short circuits between the multiple wirings 13 via the diffused metal material, thereby improving the insulation reliability of the organic interposer 10.

[0087] The organic insulating laminate 12 includes a first organic insulating layer 21 having a plurality of grooves 21a in which the wirings 13 are arranged, and a second organic insulating layer 22 laminated on the first organic insulating layer 21 so as to embed the wirings 13. Therefore, each of the plurality of wirings 13 has a shape that follows the grooves 21a of the first organic insulating layer 21. Therefore, by forming a plurality of grooves 21a having fine widths and intervals, fine wirings 13 can be easily formed.

[0088] The barrier metal film 14 includes a first barrier metal film 31 provided between the wiring 13 and the inner surface of the trench 21a, and a second barrier metal film 32 provided between the wiring 13 and the second organic insulating layer 22. Therefore, the first barrier metal film 31 effectively suppresses the diffusion of the metal material in the wiring 13 into the first organic insulating layer 21. Furthermore, the second barrier metal film 32 effectively suppresses the diffusion of the metal material into the second organic insulating layer 22.

[0089] The first barrier metal film 31 contains at least one of titanium, nickel, palladium, chromium, tantalum, tungsten, and gold. Titanium, nickel, palladium, chromium, tantalum, tungsten, and gold are all less likely to diffuse into the first organic insulating layer 21 and the second organic insulating layer 22, and therefore the insulation reliability of the organic interposer 10 can be further improved.

[0090] The second barrier metal film 32 may be a plated film. In this case, the second barrier metal film 32 can be selectively formed on the wiring 13 in the groove portion 21a, thereby simplifying the manufacturing process of the organic interposer 10. For example, the resist application process, sputtering process, and resist removal process for forming the second barrier metal film 32 can be omitted.

[0091] The second barrier metal film 32 may be a nickel plating film. In this case, the second barrier metal film 32 can be easily formed with good flatness. In addition, since nickel does not easily diffuse into the first organic insulating layer 21 and the second organic insulating layer 22, the insulation reliability of the organic interposer 10 can be suitably improved.

[0092] The second barrier metal film 32 may be a palladium plating film. In this case, the second barrier metal film 32 can be formed thin. In addition, since palladium does not easily diffuse into the first organic insulating layer 21 and the second organic insulating layer 22, the insulation reliability of the organic interposer 10 can be suitably improved.

[0093] The thickness of the second barrier metal film 32 may be 0.001 μm or more and 1 μm or less. In this case, the second barrier metal film 32 effectively prevents the metal material in the wiring 13 from diffusing into the second organic insulating layer 22.

[0094] The surface roughness Ra of the second barrier metal film 32 may be 0.01 μm or more and 1 μm or less. In this case, the second barrier metal film 32 can adhere well to the second organic insulating layer 22. Furthermore, breaks in the organic interposer 10 due to the surface roughness of the second barrier metal film 32 can be suppressed.

[0095] The thickness of the first organic insulating layer 21 may be 1 μm or more and 10 μm or less. In this case, the first organic insulating layer 21 can be used to form a plurality of grooves 21a having widths and intervals of 10 μm or less.

[0096] The first organic insulating layer 21 may be a cured film formed by curing a photosensitive organic insulating resin containing a photoacid generator, a compound having a phenolic hydroxyl group, and a thermosetting resin. In this case, grooves 21a having fine widths and intervals can be easily formed in the first organic insulating layer 21. In addition, since the moisture content of the first organic insulating layer 21 can be reduced, metal materials are less likely to diffuse into the first organic insulating layer 21. Therefore, the insulation reliability of the organic interposer 10 can be improved.

[0097] According to the manufacturing method of the organic interposer 10 of this embodiment, by performing the fourth to sixth steps, a first barrier metal film 31 can be formed between the inner surface of each groove portion 21a and the wiring layer 13A. Furthermore, by performing the seventh to ninth steps, a second barrier metal film 32 can be formed between the wiring 13 and the second organic insulating layer 22 in the stacking direction of the organic insulating layers. Therefore, the first barrier metal film 31 and the second barrier metal film 32 suppress diffusion of the metal material in the wiring 13 into the first organic insulating layer 21 and the second organic insulating layer 22. Therefore, short-circuiting between the multiple wirings 13 via the diffused metal material can be suppressed, thereby improving the insulation reliability of the organic interposer 10.

[0098] In the sixth step, the wiring layer 13A may be formed by plating using the first barrier metal film 31 as a seed layer. In this case, the wiring layer 13A can be formed so that the first barrier metal film 31 is sandwiched between the first organic insulating layer 21 and the wiring layer 13A. This effectively suppresses the diffusion of the metal material in the wiring layer 13A into the first organic insulating layer 21.

[0099] In the eighth step, the second barrier metal film 32 may be formed by plating using the wiring 13 as a seed layer. In this case, the second barrier metal film 32 can be selectively formed on the wiring 13 without using, for example, a resist. This allows steps such as a resist formation step and a resist removal step to be omitted when forming the second barrier metal film 32, thereby simplifying the manufacturing process of the organic interposer 10.

[0100] The wiring 13 in the organic interposer 10 may also be formed by, for example, a semi-additive method. The semi-additive method involves forming a seed layer, forming a resist with a desired pattern on the seed layer, thickening the exposed portions of the seed layer using electroplating or other methods, removing the resist, and then etching the thin seed layer to obtain the desired wiring. However, when using the semi-additive method, significant damage is inflicted on the wiring when etching the thin seed layer. Additionally, it is difficult to ensure the adhesion strength of the wiring to the organic insulating layer. For this reason, when using the semi-additive method to form fine wiring with line and space widths of, for example, 5 μm or less, the yield of the organic interposer tends to decrease significantly. Therefore, in this embodiment, to prevent this yield decrease, a trench method is adopted in the fourth step, in which grooves 21 a are formed in the first organic insulating layer 21 and the wiring 13 is formed in the grooves 21 a.

[0101] Although the organic interposer and the manufacturing method thereof according to an embodiment of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiment and may be modified as appropriate without departing from the spirit of the present disclosure. For example, the cross-sectional shape of the groove portion 21a formed in the first organic insulating layer 21 is not limited to a substantially rectangular shape, and may be other shapes such as a substantially trapezoidal shape or a substantially semicircular shape.

[0102] In the above embodiment, the wiring 13, the wiring layers 15a to 15c, the first barrier metal film 31, the second barrier metal film 32, and the surface wiring 16, etc. may each have a single-layer structure or a multi-layer structure consisting of multiple conductive layers.

[0103] In the above embodiment, the first organic insulating layer 21 includes both the third organic insulating layer 23 and the fourth organic insulating layer 24, but this is not limited to this. For example, the first organic insulating layer 21 may have a single-layer structure. In this case, the second and third steps in the above manufacturing method can be combined into one step, simplifying the manufacturing process of the organic interposer 10.

[0104] In the seventh step of the manufacturing method according to the above embodiment, a portion of the wiring layer 13A (wiring 13) in the groove 21a may be removed, and then in the eighth step, a second barrier metal film 32 may be formed to fill the groove 21a. In this case, since the second barrier metal film 32 is formed to fill the groove 21a, the formation of a step in the organic interposer 10 due to the second barrier metal film 32 can be suppressed. That is, the surface roughness Ra of the combined surface of the second organic insulating layer 22 and the second barrier metal film 32 can be reduced. This allows a semiconductor element or the like to be favorably mounted on the organic interposer 10. Note that the removal of the portion of the wiring 13 in the groove 21a may be achieved, for example, by utilizing dishing that occurs during CMP. Furthermore, the portion of the wiring 13 in the groove 21a may be, for example, at least a portion of the wiring 13 located in the upper half of the groove 21a.

[0105] In the above embodiment, an adhesion aid may be included in the organic insulating layer included in the organic insulating laminate 12. Examples of the adhesion aid include a silane coupling agent, and a triazole or tetrazole-based compound.

[0106] As the silane coupling agent, a compound having a nitrogen atom is preferably used to improve adhesion to metal. Specific examples include N-2-(aminoethyl)-3-aminopropylmethyldimethoxysilane, N-2-(aminoethyl)-3-aminopropyltrimethoxysilane, 3-aminopropyltrimethoxysilane, 3-aminopropyltriethoxysilane, 3-triethoxysilyl-N-(1,3-dimethylbutylidene)propylamine, N-phenyl-3-aminopropyltrimethoxysilane, tris-(trimethoxysilylpropyl)isocyanurate, 3-ureidopropyltrialkoxysilane, and 3-isocyanatopropyltriethoxysilane. From the viewpoints of the effects of addition, heat resistance, production costs, and the like, the amount of the silane coupling agent used is preferably 0.1 to 20 parts by mass per 100 parts by mass of the compound having a phenolic hydroxyl group.

[0107] Examples of triazole compounds include 2-(2'-hydroxy-5'-methylphenyl)benzotriazole, 2-(2'-hydroxy-3'-tert-butyl-5'-methylphenyl)-5-chlorobenzotriazole, 2-(2'-hydroxy-3',5'-di-tert-amylphenyl)benzotriazole, 2-(2'-hydroxy-5'-tert-octylphenyl)benzotriazole, and 2,2'-methylenebis[6-(2H-benzotriazol-2-yl)-4-tert-octylphenol]. 1-[N,N-bis(2-ethylhexyl)aminomethyl]methylbenzotriazole, 2,2'-[[(methyl-1H-benzotriazol-1-yl)methyl]imino]bisethanol, and the like.

[0108] Examples of tetrazole compounds include 1H-tetrazole, 5-amino-1H-tetrazole, 5-methyl-1H-tetrazole, 5-phenyl-1H-tetrazole, 1-methyl-5-ethyl-1H-tetrazole, 1-methyl-5-mercapto-1H-tetrazole, 1-phenyl-5-mercapto-1H-tetrazole, 1-(2-dimethylaminoethyl)-5-mercapto-1H-tetrazole, 2-methoxy-5-(5-trifluoromethyl-1H-tetrazol-1-yl)-benzaldehyde, 4,5-di(5-tetrazolyl)-[1,2,3]triazole, 1-methyl-5-benzoyl-1H-tetrazole, etc. From the viewpoints of the effects of addition, heat resistance, and production costs, the amount of the triazole or tetrazole compound used is preferably 0.1 to 20 parts by mass per 100 parts by mass of the compound having a phenolic hydroxyl group.

[0109] The silane coupling agent, triazole-based compound, and tetrazole-based compound may be used alone or in combination.

[0110] Furthermore, an ion trapping agent may be added to the organic insulating layer. The ion trapping agent adsorbs ionic impurities in the organic insulating layer, thereby improving the insulating reliability during moisture absorption. Examples of such ion trapping agents include compounds known as copper inhibitors for preventing copper from ionizing and dissolving, such as triazine thiol compounds and phenol-based reducing agents, and inorganic compounds such as powdered bismuth-, antimony-, magnesium-, aluminum-, zirconium-, calcium-, titanium-, and tin-based compounds, as well as mixtures of these compounds.

[0111] Examples of the ion scavenger include inorganic ion scavengers manufactured by Toagosei Co., Ltd. (trade names: IXE-300 (antimony-based), IXE-500 (bismuth-based), IXE-600 (antimony and bismuth mixed), IXE-700 (magnesium and aluminum mixed), IXE-800 (zirconium-based), and IXE-1100 (calcium-based)). These may be used alone or in combination of two or more. From the viewpoints of the effect of addition, heat resistance, production costs, etc., the amount of the ion scavenger used is preferably 0.01 to 10 parts by mass per 100 parts by mass of the compound having a phenolic hydroxyl group. [Example]

[0112] The present invention will be described in more detail by the following examples, but the present invention is not limited to these examples.

[0113] Example 1 The measurement and evaluation samples shown in Figures 11(a) and (b) were prepared as follows. First, a 5 µm-thick photosensitive insulating resin film 52 was attached to a 150 mm-thick silicon wafer 51. This photosensitive insulating resin film 52 was formed as follows. First, a cresol novolac resin (manufactured by Asahi Organic Chemicals Co., Ltd., product name: TR-4020G, 100 parts by mass), 1,3,4,6-tetrakis(methoxymethyl)glycoluril (30 parts by mass), trimethylolpropane triglycidyl ether (40 parts by mass), a triarylsulfonium salt (manufactured by San-Apro Co., Ltd., product name: CPI-310B, 8 parts by mass), and methyl ethyl ketone (100 parts by mass) were blended to obtain a photosensitive insulating composition. Next, the obtained photosensitive insulating composition was applied to a polyethylene terephthalate film (manufactured by Teijin DuPont Films Co., Ltd., product name: A-53) and dried in an oven at 90°C for 10 minutes to obtain a photosensitive insulating resin film 52 with a thickness of 5 μm.

[0114] Next, the photosensitive insulating resin film 52 attached to the silicon wafer 51 was subjected to exposure, heating, development, and thermosetting in that order. Next, a 5 μm-thick photosensitive insulating resin film 53 formed in the same manner as the photosensitive insulating resin film 52 was attached to the photosensitive insulating resin film 52. The attached photosensitive insulating resin film 53 was then exposed to light through a photomask, and then subjected to heating, development, and thermosetting in that order. This patterning of the photosensitive insulating resin film 53 resulted in the formation of interdigitated comb-like first grooves 53a and second grooves 53b, first connecting portions 53c connecting the first grooves 53a, and second connecting portions 53d connecting the second grooves 53b. The widths of the first grooves 53a and the second grooves 53b were each set to 10 μm. These widths correspond to the line width L of the wiring, which will be described later. The distance (space width S) between adjacent first groove portion 53a and second groove portion 53b was set to 10 μm, and the length of each groove was set to 1 mm.

[0115] Next, a 0.05 μm-thick barrier metal film 54 containing titanium was formed on the photosensitive insulating resin film 53 by sputtering. Next, a copper layer was formed by electroplating using the barrier metal film 54 as a seed layer, filling the first groove 53a, the second groove 53b, the first connection portion 53c, and the second connection portion 53d. Next, a fly-cut method using a surface planer was used to grind away a portion of the copper layer and the portions of the barrier metal film 54 that did not cover the inner surfaces of the first groove 53a, the second groove 53b, the first connection portion 53c, and the second connection portion 53d. This resulted in the formation of a first wiring 55a buried in the first groove 53a, a second wiring 55b buried in the second groove 53b, a first connection wiring 55c buried in the first connection portion 53c, and a second connection wiring 55d buried in the second connection portion 53d. An automatic surface planer (manufactured by Disco Corporation, product name "DAS8930") was used as the surface planer. In addition, in the grinding by the flycut method, the feed rate was set to 1 mm / s and the spindle rotation speed was set to 2000 min -1 was set to.

[0116] Next, a 0.2 μm-thick barrier metal film 56 containing a nickel-phosphorus alloy was formed by electroless plating using the first wiring 55a, the second wiring 55b, the first connecting wiring 55c, and the second connecting wiring 55d as seed layers. Next, a 5 μm-thick photosensitive insulating resin film 57 formed in the same manner as the photosensitive insulating resin film 52 was attached so as to expose at least a portion of the first connecting wiring 55c and a portion of the second connecting wiring 55d. The attached photosensitive insulating resin film 57 was then subjected to an exposure process, a heating process, a development process, and a thermal curing process in sequence. This resulted in the measurement and evaluation sample 50 shown in FIGS. 11(a) and 11(b). In this measurement and evaluation sample 50, the first wiring 55a and the first connecting wiring 55c are connected to each other and are covered by the barrier metal films 54 and 56. Similarly, the second wiring 55b and the second connection wiring 55d are connected to each other and are covered with barrier metal films 54, 56. The first wiring 55a and the first connection wiring 55c are insulated from the second wiring 55b and the second connection wiring 55d by photosensitive insulating resin films 52, 53, 57.

[0117] In order to confirm the insulation reliability of the measurement and evaluation sample 50 described above, a highly accelerated life test (HAST) was conducted as described below. In this test, a voltage of 3.3 V was applied to the first connection wiring 55c and the second connection wiring 55d under conditions of 85% humidity and 130°C, and the sample was left standing for a predetermined time. This allowed the change in the insulation between the first wiring 55a and the second wiring 55b over time to be measured. In this test, the resistance value between the first wiring 55a and the second wiring 55b was found to be 1×10 200 hours after the start of the test. 6 If it is above Ω, it is rated as A, and if it is below 1 × 10 6 If it was less than Ω, it was rated as B. The results of the high acceleration life test of Example 1 are shown in Table 1 below.

[0118] Example 2 The measurement and evaluation sample 50 was formed in the same manner as in Example 1, except that the line width L and space width S were set to 5 μm, and the high-acceleration life test described above was performed. The results of the high-acceleration life test of Example 2 are shown in Table 1 below.

[0119] Example 3 The measurement and evaluation sample 50 was formed in the same manner as in Example 1, except that the line width L and space width S were set to 2 μm, and the high-acceleration life test described above was performed. The results of the high-acceleration life test for Example 3 are shown in Table 1 below.

[0120] Example 4 A measurement and evaluation sample 50 was formed in the same manner as in Example 2, except that a solder resist film (manufactured by Hitachi Chemical Co., Ltd., product name: FZ-2700GA, thickness: 30 μm) was used as the photosensitive insulating resin film 57. The above-mentioned high-acceleration life test was performed on this measurement and evaluation sample 50. The results of the high-acceleration life test of Example 4 are shown in Table 1 below.

[0121] Example 5 A measurement and evaluation sample 50 was formed in the same manner as in Example 3, except that a solder resist film (manufactured by Hitachi Chemical Co., Ltd., product name: FZ-2700GA, thickness: 30 μm) was used as the photosensitive insulating resin film 57. The above-mentioned high-acceleration life test was performed on this measurement and evaluation sample 50. The results of the high-acceleration life test of Example 5 are shown in Table 1 below.

[0122] (Comparative Example 1) 12(a) and 12(b), a measurement and evaluation sample 50A was formed in the same manner as in Example 1, except that the barrier metal film 56 was not provided on the first wiring 55a, the second wiring 55b, the first connecting wiring 55c, and the second connecting wiring 55d. That is, the measurement and evaluation sample 50A was formed so that the first wiring 55a, the second wiring 55b, the first connecting wiring 55c, and the second connecting wiring 55d were in contact with the photosensitive insulating resin film 57. The measurement and evaluation sample 50A was subjected to the high-acceleration life test described above. The results of the high-acceleration life test of Comparative Example 1 are shown in Table 1 below.

[0123] (Comparative Example 2) A measurement and evaluation sample 50A was formed in the same manner as in Example 2, except that the barrier metal film 56 was not provided on the first wiring 55a, the second wiring 55b, the first connecting wiring 55c, and the second connecting wiring 55d. The measurement and evaluation sample 50A was subjected to the high-acceleration life test described above. The results of the high-acceleration life test for Comparative Example 2 are shown in Table 1 below.

[0124] (Comparative Example 3) A measurement and evaluation sample 50A was formed in the same manner as in Example 3, except that the barrier metal film 56 was not provided on the first wiring 55a, the second wiring 55b, the first connecting wiring 55c, and the second connecting wiring 55d. The measurement and evaluation sample 50A was subjected to the high-acceleration life test described above. The results of the high-acceleration life test for Comparative Example 3 are shown in Table 1 below.

[0125] Comparative Example 4 A measurement and evaluation sample 50A was formed in the same manner as in Example 4, except that the barrier metal film 56 was not provided on the first wiring 55a, the second wiring 55b, the first connecting wiring 55c, and the second connecting wiring 55d. The measurement and evaluation sample 50A was subjected to the high-acceleration life test described above. The results of the high-acceleration life test for Comparative Example 4 are shown in Table 1 below.

[0126] (Comparative Example 5) A measurement and evaluation sample 50A was formed in the same manner as in Example 5, except that the barrier metal film 56 was not provided on the first wiring 55a, the second wiring 55b, the first connecting wiring 55c, and the second connecting wiring 55d. The measurement and evaluation sample 50A was subjected to the high-acceleration life test described above. The results of the high-acceleration life test for Comparative Example 5 are shown in Table 1 below.

[0127] [Table 1]

[0128] In Table 1 above, the case where the barrier metal film 56 is provided is indicated as "Y," and the case where the barrier metal film 56 is not provided is indicated as "N." Furthermore, in Table 1 above, the case where the photosensitive insulating resin film 57 is formed in the same manner as the photosensitive insulating resin film 52 is indicated as "α," and the case where the photosensitive insulating resin film 57 is formed using a solder resist film is indicated as "β." As can be seen from Table 1, the results of the high-acceleration life test for Examples 1 to 5 were all graded A, while the results of the high-acceleration life test for Comparative Examples 1 to 5 were all graded B. These results demonstrate that the insulation reliability of the measurement and evaluation samples varies greatly depending on whether or not the barrier metal film 56 is provided.

[0129] FIG. 13(a) is a graph showing the results of the high-acceleration life test for Example 2 and Comparative Example 2, and FIG. 13(b) is a graph showing the results of the high-acceleration life test for Example 3 and Comparative Example 3. In FIGS. 13(a) and 13(b), the horizontal axis represents time, and the vertical axis represents the resistance value between the first wiring 55a and the second wiring 55b. In FIG. 13(a), data 61 represents the test result for Example 2, and data 62 represents the test result for Comparative Example 2. In FIG. 13(b), data 63 represents the test result for Example 3, and data 64 represents the test result for Comparative Example 3.

[0130] As shown in FIG. 13(a), in Example 2, even after 300 hours had passed since the start of the test, the resistance between the first wiring 55a and the second wiring 55b was 1×10 6 On the other hand, in Comparative Example 2, the resistance value decreased rapidly at about 20 hours after the start of the test, reaching 1×10 6 Similarly, as shown in FIG. 13(b), in Example 3, the resistance between the first wiring 55a and the second wiring 55b was 1×10 Ω or less even after 200 hours had passed since the start of the test. 6 On the other hand, in Comparative Example 3, the resistance value decreased rapidly after a few hours from the start of the test, reaching 1×10 6 It became less than Ω.

[0131] 14(a) to 14(c) show the results of analyzing the copper, titanium, and nickel components of a cross-sectional sample of measurement and evaluation sample 50 after 250 hours of the curing rate life test of Example 3 using a TEM (transmission electron microscope) / EDX (energy dispersive X-ray analyzer). FIG. 14(a) shows the analysis results for Cu (copper) in the cross-sectional sample of measurement and evaluation sample 50, FIG. 14(b) shows the analysis results for Ti (titanium) in the cross-sectional sample, and FIG. 14(c) shows the analysis results for Ni (nickel) in the cross-sectional sample. The above analysis was performed using a JEOL Ltd. JEM-2100F as the TEM and a JEOL Ltd. JED-2300 as the EDX, with an acceleration voltage set to 200 kV. In Example 3, no elution of the wiring or barrier metal into the photosensitive insulating resin film was observed after the EDX analysis test. Specifically, no diffusion of copper constituting the copper layer surrounded by barrier metal films 54 and 56 into the photosensitive insulating resin film, no diffusion of titanium constituting barrier metal film 54 into the photosensitive insulating resin film, and no diffusion of nickel constituting barrier metal film 56 into the photosensitive insulating resin film were confirmed.

[0132] When the measurement and evaluation samples 50A of Comparative Examples 2 and 3 were visually inspected after the high-acceleration life test, it was confirmed that at least the photosensitive insulating resin film 57 was contaminated due to some factor in Comparative Examples 2 and 3. On the other hand, when the measurement and evaluation samples 50 of Examples 2 and 3 were visually inspected after the high-acceleration life test, no contamination of the photosensitive insulating resin films 52, 53, and 57 was confirmed.

[0133] From the above, it is presumed that the rapid decrease in resistance value in Comparative Examples 2 and 3 is due to the fact that the metal material in the first wiring 55a and the second wiring 55b diffused into the photosensitive insulating resin film 57, and the first wiring 55a and the second wiring 55b were short-circuited via the diffused metal material. On the other hand, in Examples 2 and 3, it is presumed that the diffusion of the metal material in the first wiring 55a or the second wiring 55b into the photosensitive insulating resin films 52, 53, 57 was prevented by the barrier metal films 54, 56, and the first wiring 55a and the second wiring 55b were not short-circuited. [Explanation of symbols]

[0134] 1...substrate, 2A to 2D...semiconductor chip, 3A, 3B...underfill, 4...insulating material, 10...organic interposer, 11...substrate, 12...organic insulating laminate, 13...wiring, 13A...wiring layer, 14...barrier metal film, 15...through wiring, 21...first organic insulating layer, 21a...groove portion, 21b...opening, 22...second organic insulating layer, 31...first barrier metal film, 32...second barrier metal film, 100...semiconductor package, L...line width, S...space width.

Claims

1. an organic insulating laminate comprising a plurality of organic insulating layers; a plurality of wirings arranged within the organic insulating laminate; The organic interposer includes a barrier metal film that separates the wiring from the organic insulating layer.

2. The organic insulating laminate is a first organic insulating layer having a plurality of grooves in which the wiring is disposed; The organic interposer according to claim 1 , further comprising: a second organic insulating layer laminated on said first organic insulating layer so as to bury said wiring.

3. The barrier metal film is a first barrier metal film provided between the wiring and the inner surface of the trench; The organic interposer according to claim 2 , further comprising: a second barrier metal film provided between said wiring and said second organic insulating layer.

4. The organic interposer of claim 3 , wherein the first barrier metal film comprises at least one of titanium, nickel, palladium, chromium, tantalum, tungsten, and gold.

5. 5. The organic interposer according to claim 3, wherein the second barrier metal film is a plated film.

6. The organic interposer according to claim 5 , wherein the second barrier metal film is a nickel plating film.

7. The organic interposer according to claim 5 , wherein the second barrier metal film is a palladium plating film.

8. 8. The organic interposer according to claim 3, wherein the second barrier metal film has a thickness of 0.001 μm or more and 1 μm or less.

9. 9. The organic interposer according to claim 3, wherein the second barrier metal film has a surface roughness of 0.01 μm or more and 1 μm or less.

10. 10. The organic interposer according to claim 2, wherein the first organic insulating layer has a thickness of 1 μm or more and 10 μm or less.

11. The organic interposer according to any one of claims 2 to 10, wherein the first organic insulating layer is a cured film formed by curing a photosensitive organic insulating resin containing a photoacid generator, a compound having a phenolic hydroxyl group, and a thermosetting resin.

12. a first step of forming a plurality of grooves in a first organic insulating layer; a second step of forming a first barrier metal film on the first organic insulating layer so as to cover the inner surface of the groove; a third step of forming a wiring layer on the first barrier metal film so as to fill the trench; a fourth step of thinning the wiring layer so that the first organic insulating layer is exposed; a fifth step of forming a second barrier metal film so as to cover the wiring layer in the trench; and a sixth step of forming a second organic insulating layer on the first organic insulating layer and the second barrier metal film.

13. The method for manufacturing an organic interposer according to claim 12 , wherein in the third step, the wiring layer is formed by a plating method using the first barrier metal film as a seed layer.

14. The method for manufacturing an organic interposer according to claim 12 or 13, wherein in the fifth step, the second barrier metal film is formed by a plating method using the wiring layer as a seed layer.

15. In the fourth step, a part of the wiring layer in the groove is removed, The method for manufacturing an organic interposer according to claim 14 , wherein in the fifth step, the second barrier metal film is formed so as to fill the groove portion.

Citation Information

Patent Citations

  • Multilayer wiring board and manufacture thereof

    JP1995079078A

  • Substrate treatment method and device thereof

    JP2006216937A

  • Method of manufacturing electronic component and electronic component

    JP2012015405A

  • Semiconductor device and manufacturing method of the same

    JP2012146752A

  • A multi-chip package and a method for providing die-to-die interconnects for a multi-chip package.

    JP2012529770A