Semiconductor device

Abstract

To suppress a short circuit between bond fingers.SOLUTION: A semiconductor device according to an embodiment includes: a semiconductor chip; and a wiring substrate on which the semiconductor chip and an insulation layer having an opening part are disposed on a first surface, the wiring substrate having a plurality of bond fingers arranged along a first direction that is a longitudinal direction of the opening part and electrically connectable to the semiconductor chip in the opening part, a power supply layer supplying a power supply voltage to the semiconductor chip between a first surface and a second surface opposite to the first surface, and a ground layer supplying a ground potential to the semiconductor chip. The plurality of bond fingers has a configuration in which a first bond finger that is a bond finger connected to the ground layer and a second bond finger that is a bond finger connected to the power supply layer are alternately arranged at equal distances. Each of the two third bond fingers, which are two bond fingers disposed at both ends of the opening part in the first direction among the plurality of bond fingers, is the first bond finger, and one of the two third bond fingers is a dummy terminal that is not connected to the semiconductor chip.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] A semiconductor device has a semiconductor chip mounted on a wiring substrate. A plurality of bond fingers are arranged on the mounting surface of the wiring substrate to electrically connect to the semiconductor chip. The bond fingers include a first bond finger that supplies a ground potential to the semiconductor chip and a second bond finger that supplies a power supply voltage.

[0003] At this time, metal components may leach out of the second bond finger. This leaching of metal components is particularly evident in, for example, HAST (High Accelerated Temperature and Humidity Stress Test). The leached metal components may become leak paths, causing short circuits between adjacent bond fingers. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2012-0153506 [Patent Document 2] U.S. Patent Application Publication No. 2003-0042597 [Patent Document 3] U.S. Patent Application Publication No. 2003-0052420 Summary of the Invention [Problem to be solved by the invention]

[0005] One embodiment provides a semiconductor device capable of suppressing shorts between bond fingers. [Means for solving the problem]

[0006] The semiconductor device of the embodiment comprises a semiconductor chip, a wiring substrate on which the semiconductor chip and an insulating layer having an opening are disposed on a first surface, a plurality of bond fingers arranged along a first direction which is the longitudinal direction of the opening and which can be electrically connected to the semiconductor chip at the opening, and a power supply layer which supplies a power supply voltage to the semiconductor chip and a ground layer which supplies a ground potential to the semiconductor chip between the first surface and a second surface opposite the first surface, wherein the plurality of bond fingers have a configuration in which first bond fingers which are bond fingers connected to the ground layer and second bond fingers which are bond fingers connected to the power supply layer are arranged alternately at equal distances, and two third bond fingers which are two bond fingers of the plurality of bond fingers disposed at both ends of the opening in the first direction are each the first bond finger, and one of the two third bond fingers is a dummy terminal which is not connected to the semiconductor chip. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a schematic cross-sectional view showing an example of a configuration of a semiconductor device according to an embodiment; [Figure 2] 1 is a schematic top view showing an example of a configuration of a semiconductor device according to an embodiment; [Figure 3] 2. FIG. 2 is a cross-sectional view taken along line AA in FIG. [Figure 4] FIG. 2 is a top view schematically showing the elution state of metal components when HAST is performed on the semiconductor device according to the embodiment. [Figure 5] FIG. 10 is a partial top view showing the configuration around an opening of a semiconductor device according to a first modification. [Figure 6] FIG. 10 is a partial top view showing the configuration around an opening of a semiconductor device according to Modification 2. [Figure 7] FIG. 11 is a partial top view showing the configuration around an opening of a semiconductor device according to Modification 3. [Figure 8] FIG. 11 is a partial top view showing the configuration around an opening of a semiconductor device according to Modification 4. [Figure 9]FIG. 10 is a top view schematically showing the elution state of metal components when HAST is performed on a semiconductor device according to a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described in detail with reference to the drawings. Note that the present invention is not limited to the following embodiments. Furthermore, the components in the following embodiments include those that can be easily imagined by a person skilled in the art or those that are substantially the same.

[0009] (Embodiment) Hereinafter, the embodiment will be described in detail with reference to FIGS.

[0010] 1 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device 1 according to an embodiment, and is also a cross-sectional view taken along line BB in FIG.

[0011] In this specification, the semiconductor chip 21 side of the semiconductor device 1 is referred to as the upper side, and the wiring board 11 side is referred to as the lower side. The up-down direction of the semiconductor device 1 is referred to as the Z direction. The X direction is the direction along the surface of the wiring board 11, which will be described later. The direction intersecting the X direction and the Z direction is referred to as the Y direction. The X direction, Y direction, and Z direction may be perpendicular to each other. The direction indicated by one arrow on each of the X axis, Y axis, and Z axis is referred to as the positive direction, and the opposite direction is referred to as the negative direction. The X direction is an example of the second direction, and the Y direction is an example of the first direction.

[0012] As shown in Fig. 1, the semiconductor device 1 is configured as a package in which a semiconductor chip 21 is sealed. The semiconductor device 1 includes a wiring board 11, a semiconductor chip 21, solder balls 31, a sealing member 41, and bonding wires 51. The semiconductor chip 21 is disposed on the upper surface of the wiring board 11. The semiconductor chip 21 and the wiring board 11 are connected via the bonding wires 51. A plurality of solder balls 31 are disposed on the lower surface of the wiring board 11. The wiring board 11, the semiconductor chip 21, and the bonding wires 51 are covered with the sealing member 41.

[0013] The wiring board 11 includes an insulating layer 12 , a wiring layer 13 , bond fingers 14 , and a solder resist layer 15 .

[0014] The insulating layer 12 is made of a prepreg or the like made of carbon fiber, glass fiber, aramid fiber, or the like impregnated with a thermosetting resin such as an epoxy resin before curing.

[0015] Bond fingers 14 and a solder resist layer 15 are formed in this order on the upper surface of the insulating layer 12. The bond fingers 14 are terminals made of a conductive material such as Cu. A plurality of bond fingers 14 are formed on the upper surface of the insulating layer 12. Some of the plurality of bond fingers 14 connect at their lower surfaces to vias 133a and a power supply layer 131, which will be described later. Other bond fingers 14 connect at their lower surfaces to vias 134a and a ground layer 132, which will be described later. The plurality of bond fingers 14 are configured to be connectable at their upper surfaces to bonding wires 51.

[0016] The solder resist layer 15 is an insulating layer that protects the multiple bond fingers 14. The solder resist layer 15 is formed around, including between adjacent bond fingers and above, the multiple bond fingers 14, and electrically insulates these bond fingers 14. The solder resist layer 15 has openings 151 at positions that overlap with the multiple bond fingers 14 when viewed from the Z direction. This exposes at least a portion of each bond finger 14, allowing connection between the bond fingers 14 and bonding wires 51. The solder resist layer 15 is an example of an insulating layer.

[0017] Hereinafter, the surface of wiring board 11 on which solder resist layer 15 is formed may be referred to as surface 10a, which is a first surface. Also, the surface of wiring board 11 opposite surface 10a, i.e., the bottom surface of wiring board 11, may be referred to as surface 10b, which is a second surface.

[0018] The wiring layer 13 includes a conductive material such as Cu. The wiring layer 13 includes a power supply layer 131 and a ground layer 132 that extend along the X and Y directions between the surface 10a and the surface 10b. The wiring layer 13 also includes vias 133a and 134 that extend in the Z direction between the surface 10a and the surface 10b and connect to the power supply layer 131 and the ground layer 132, respectively.

[0019] Specifically, the power supply layer 131 is connected to the via 133a. The via 133a is exposed on the upper surface and the lower surface of the insulating layer 12, and is connected to one of the plurality of bond fingers 14 and one of the plurality of solder balls 31 (described later). In this way, the power supply layer 131 electrically connects the bond fingers 14 and the solder balls 31. The power supply layer 131 supplies a power supply voltage, which is supplied via the solder balls 31 from an external device (not shown), to one of the plurality of bond fingers 14.

[0020] The ground layer 132 is connected to the via 134a. The via 134a is exposed on the upper surface and the lower surface of the insulating layer 12, and is connected to one of the multiple bond fingers 14 and one of the multiple solder balls 31. In this way, the ground layer 132 electrically connects the bond fingers 14 and the solder balls 31. The ground layer 132 supplies a ground potential, which is supplied via the solder balls 31 from an external device (not shown), to one of the multiple bond fingers 14.

[0021] A plurality of solder balls 31 are provided on the surface 10b of the wiring board 11 so as to protrude from the surface 10b. The plurality of solder balls 31 include a conductive material such as Sn. One end of each solder ball 31 is connected to, for example, the via 133a or the via 134a, and the other end is connected to, for example, an external device (not shown). As a result, a power supply voltage is supplied from the external device to the power supply layer 131 via some of the plurality of solder balls 31, and a ground potential is supplied from the external device to the ground layer 132 via the other solder balls 31.

[0022] A semiconductor chip 21 is mounted on the surface 10a of the wiring substrate 11. The semiconductor chip 21 is a small piece obtained by dividing a silicon substrate or the like. The semiconductor chip 21 is, for example, a memory chip of a nonvolatile memory. The semiconductor chip 21 has electrode pads 22 that are electrically connected to, for example, the nonvolatile memory. The semiconductor chip 21 is arranged on the surface 10a with the surface on which the electrode pads 22 are provided facing upward. The electrode pads 22 include a metal material such as Cu. A bonding wire 51 is connected to the electrode pad 22. This allows the semiconductor chip 21 to be electrically connected to a plurality of bond fingers 14 via the bonding wire 51.

[0023] The sealing member 41 seals the entire structure on the surface 10a, such as the semiconductor chip 21 and the bonding wires 51. The sealing member 41 is made of a thermosetting resin, such as an epoxy resin or an acrylic resin.

[0024] 1 shows an example in which one semiconductor chip 21 is mounted on the same semiconductor device, the number of semiconductor chips 21 mounted is not limited to the above and may be any number. For example, two or more semiconductor chips 21 may be mounted on the surface 10a of the wiring substrate 11.

[0025] Next, the connection of the bond fingers 14 will be described in detail with reference to FIGS.

[0026] 2 is a schematic top view showing an example of the configuration of the semiconductor device 1 according to the embodiment, in which components such as a sealing member 41 are omitted.

[0027] 2, the semiconductor device 1 is formed in a substantially rectangular shape when viewed from the Z direction. A semiconductor chip 21 is disposed in the approximate center of the semiconductor device 1. A plurality of electrode pads 22 are formed on the upper surface of the semiconductor chip 21. The electrode pads 22 are arranged in a row along the Y direction, for example, at both ends of the semiconductor chip 21 in the X direction.

[0028] Note that, from here on, the configuration of the semiconductor device 1 on the positive X side as viewed from the semiconductor chip 21 will be described, but the negative X side also has the same configuration as the positive X side.

[0029] The electrode pads 22 have a configuration in which first electrode pads 22F (22Fa to 22Fc) and second electrode pads 22S (22Sa to 22Sc) are arranged alternately. For example, in the example of Fig. 2, the first electrode pad 22Fa, the second electrode pad 22Sa, the first electrode pad 22Fb, the second electrode pad 22Sb, the first electrode pad 22Fc, and the second electrode pad 22Sc are arranged in this order from the positive side to the negative side of Y. The first electrode pads 22Fa to 22Fc and the second electrode pads 22Sa to 22Sc are each connected to a bonding wire 51.

[0030] A solder resist layer 15 is disposed around the semiconductor chip 21 when viewed from the Z direction. The solder resist layer 15 has an opening 151 on the outer side in the X direction of the semiconductor chip 21. The opening 151 has a rectangular shape with its longitudinal direction in the Y direction.

[0031] A plurality of bond fingers 14 are arranged in a row along the Y direction at positions corresponding to the openings 151 when viewed from the Z direction. The bond fingers 14 are formed into finger shapes extending in the X direction. As shown in FIG. 2, both ends of the bond fingers 14 in the X direction are covered with a solder resist layer 15. Therefore, the central portion of each of the bond fingers 14 is exposed in the openings 151.

[0032] More specifically, the multiple bond fingers 14 have a configuration in which first bond fingers 14F (14Fa to 14Fd) and second bond fingers 14S (14Sa to 14Sc) are arranged alternately at equal intervals. For example, in the example of Fig. 2, from the positive side to the negative side of Y, the first bond finger 14Fa, the second bond finger 14Sa, the first bond finger 14Fb, the second bond finger 14Sb, the first bond finger 14Fc, the second bond finger 14Sc, and the first bond finger 14Fd are arranged in this order at equal intervals W.

[0033] Two bond fingers, a first bond finger 14Fa and a first bond finger 14Fd, are arranged at both ends of the opening 151 in the Y direction. More specifically, the first bond finger 14Fa is arranged at the end of the opening 151 in the positive Y direction, and the first bond finger 14Fd is arranged at the end of the opening 151 in the negative Y direction. That is, there are more first bond fingers 14F (14Fa to 14Fd) than second bond fingers 14S (14Sa to 14Sc). The first bond fingers 14Fa and the first bond fingers 14Fd are each an example of a third bond finger.

[0034] The first bond fingers 14Fa-14Fc are connected to the first electrode pads 22Fa-22Fc, respectively, via bonding wires 51. The second bond fingers 14Sa-14Sc are connected to the second electrode pads 22Sa-22Sc, respectively, via bonding wires 51. On the other hand, the first bond finger 14Fd is not connected to the bonding wires 51. That is, the first bond finger 14Fd is a dummy terminal that is not connected to the semiconductor chip 21. In other words, one of the two third bond fingers is a dummy terminal that is not connected to the semiconductor chip 21. Hereinafter, the first bond finger 14Fd may be referred to as a dummy terminal 100a.

[0035] Although FIG. 2 shows an example in which first bond fingers 14Fa-Fd and second bond fingers 14Sa-Sc are arranged, the number of arranged bond fingers is not limited to the above and can be any number.

[0036] Fig. 3 is a cross-sectional view taken along the line AA in Fig. 2. Note that in Fig. 3, the sealing member 41, the solder balls 31, and other components are omitted from the illustration.

[0037] 3, the first bond fingers 14Fa-14Fc, the second bond fingers 14Sa-Sc, and a portion of the dummy terminal 100a are exposed in the opening 151. A solder resist layer 15 is formed on both ends of the opening 151 in the Y direction. The upper surface of the solder resist layer 15 is located on the positive Z side of the upper surfaces of the first bond fingers 14Fa-14Fc, the second bond fingers 14Sa-Sc, and the dummy terminal 100a.

[0038] 3, in the opening 151, the first bond fingers 14Fa-14Fc and the dummy terminal 100a are electrically connected to the ground layer 132 through the via 134a. As a result, the first bond fingers 14Fa-14Fc and the dummy terminal 100a are supplied with a ground potential. Furthermore, the second bond fingers 14Sa-Sc are connected to the power supply layer 131 through the via 133a. As a result, the power supply voltage is supplied to the second bond fingers 14Sa-14Sc.

[0039] As shown in FIG. 3, the bond fingers 14 including the first bond fingers 14Fa-14Fc, the second bond fingers 14Sa-14Sc, and the dummy terminal 100a have a three-layer structure consisting of, from the inside, a core layer COR, a plating layer MEa, and a plating layer MEb.

[0040] The core layer COR contains a conductive material such as Cu, and is obtained by etching a Cu layer formed on the insulating layer 12 by, for example, vapor deposition.

[0041] The plating layer MEa also contains a conductive material such as Ni. The plating layer MEa is formed by forming a solder resist layer 15 on the core layer COR and then performing electroplating using the core layer COR exposed in the opening 151 as an electrode. A plating solution and plating lead (not shown) are used for electroplating. When performing electroplating, a predetermined voltage is applied to the core layer COR via the plating lead while the core layer COR is immersed in the plating solution. This forms the plating layer MEa on the surface portion of the core layer COR exposed in the opening 151.

[0042] The plating layer MEb contains a conductive material such as Au. The plating layer MEb is formed by electroplating using the plating layer MEa as an electrode. By forming the plating layer MEa and the plating layer MEb on the core layer COR, connection with the bonding wire 51 becomes easy.

[0043] 3, at least a portion of the dummy terminal 100a in the negative Y direction is covered with the solder resist layer 15. The plating layers MEa and MEb are not formed on the portion covered with the solder resist layer 15. This reduces the exposed area of ​​the core layer COR to be plated, thereby reducing the consumption of plating solution and, as a result, the manufacturing cost of the semiconductor device 1. Furthermore, the plating layers MEa and MEb do not need to be formed on the dummy terminal 100a in the portion not covered with the solder resist layer 15. This is because the bonding wire 51 is not connected to the dummy terminal 100a.

[0044] The semiconductor device 1 having the above-described configuration undergoes various tests before being shipped as a product. In this embodiment, HAST is exemplified. HAST is a test for confirming the reliability of the semiconductor device 1 when placed in an accelerated environment. In HAST, the semiconductor device 1 is set on a test board (not shown), and a power supply voltage and a ground potential, for example, are supplied from an external device via the test board. The test board is then placed in a high-temperature and high-humidity environment for a predetermined time, after which electrical characteristics, etc., are tested. During this test, metal components such as Cu may leach out from the bond fingers 14, for example.

[0045] Here, the elution of metal components from the bond finger 14 when HAST is performed will be described with reference to FIGS.

[0046] Fig. 4 is a top view schematically showing the state of elution of metal components when HAST is performed on the semiconductor device 1 according to the embodiment. On the other hand, Fig. 9 is a top view schematically showing the state of elution of metal components when HAST is performed on the semiconductor device according to the comparative example. Note that in Figs. 4 and 9, the bonding wire 51, the sealing member 41, and other components are not shown.

[0047] As described above, in the semiconductor device 1 according to the embodiment, the first bond finger 14Fa and the dummy terminal 100a are arranged on both ends of the opening 151 in the Y direction. The central portion of the first bond finger 14Fa in the X direction is exposed in the opening 151, while the central portion of the dummy terminal 100a in the X direction is at least partially covered with the solder resist layer 15 (see FIGS. 1 to 3). Furthermore, between the first bond finger 14Fa and the dummy terminal 100a, the first bond fingers 14Fb-14Fc and the second bond fingers 14Sa-14Sc are arranged alternately at intervals W. That is, in the semiconductor device 1 according to the embodiment, either the first bond finger or the dummy terminal 100a is arranged on both sides of each of the second bond fingers 14Sa-14Sc in the Y direction.

[0048] Specifically, as shown in Figure 4, for example, a first bond finger 14Fa and a first bond finger 14Fb are arranged on either side of the second bond finger 14Sa in the Y direction, a first bond finger 14Fb and a first bond finger 14Fc are arranged on either side of the second bond finger 14Sb in the Y direction, and a first bond finger 14Fc and a dummy terminal 100a are arranged on either side of the second bond finger 14Sc in the Y direction.

[0049] 4, when HAST is performed on such a semiconductor device 1, Cu ions Mc may be eluted from the portions of the second bond fingers 14Sa-14Sc exposed in the openings 151. The eluted Cu ions Mc move from each of the second bond fingers 14Sa-14Sc toward the first bond fingers 14Fa-Fc and dummy terminal 100a that sandwich the second bond fingers 14Sa-14Sc from both sides in the Y direction. The elution of Cu ions Mc can occur due to the potential difference between the second bond fingers 14Sa-14Sc, which are supplied with a high-potential (denoted as +) power supply voltage, and the first bond fingers 14Fa-Fc and dummy terminal 100a, which are supplied with a low-potential (denoted as -) ground potential, and moisture in the atmosphere.

[0050] At this time, the amount of Cu ions Mc eluted from each of the second bond fingers 14Sa-14Sc is equal on both sides in the Y direction. Specifically, as shown in FIG. 4, the amount of Cu ions Mc eluted from the second bond finger 14Sc toward the first bond finger Fc is equal to the amount of Cu ions Mc eluted from the second bond finger 14Sc toward the dummy terminal 100a. This is because the first bond finger Fc and the dummy terminal 100a are disposed at equal intervals W relative to the second bond finger 14Sc, and the same potential is applied to the first bond finger Fc and the dummy terminal 100a. As a result, a uniform electric field is formed on both sides of the second bond finger 14Sc, and the Cu ions Mc eluted equally from the second bond finger 14Sc toward the first bond finger 14Fc and the dummy terminal 100a.

[0051] On the other hand, as shown in FIG. 9, in the semiconductor device of the comparative example, the dummy terminal 100a is not arranged at the end of the opening 151 in the negative Y direction.

[0052] When HAST is performed on such a semiconductor device of the comparative example, as shown in FIG. 9, for example, a significantly large amount of Cu ions Mc may be eluted from the second bond finger 14Sc toward the first bond finger 14Fc located in the positive Y direction. This is because the dummy terminal 100a is not disposed on the negative Y direction side of the second bond finger 14Sc. As a result, the electric field formed on both sides of the second bond finger 14Sc becomes uneven, and the amount of Cu ions Mc eluted from the second bond finger 14Sc is concentrated on one side (the positive Y direction side). As a result, the Cu ions Mc may become a leak path, potentially causing a short circuit between the second bond finger 14Sc and the first bond finger 14Fc.

[0053] (Overview) The semiconductor device 1 of the embodiment has a configuration in which first bond fingers 14F, which are bond fingers connected to a ground potential, and second bond fingers 14S, which are bond fingers connected to a power supply layer, are arranged alternately at equal distances. Two bond fingers, first bond fingers 14Fa and 14Fd, which serve as third bond fingers, are arranged at both ends of the opening 151 in the Y direction, and the first bond finger 14Fd is a dummy terminal that is not connected to the semiconductor chip 21.

[0054] In this way, by arranging first bond fingers 14F or dummy terminals 100a, to which the same ground potential is supplied, at both ends of second bond finger 14S in the Y direction with equal spacing W from the second bond finger, the amount of Cu ions Mc eluted from second bond finger 14S can be equally distributed to both sides in the Y direction. This reduces the amount of Cu ions Mc eluted from one side of second bond finger 14S, thereby preventing short circuits between first bond finger 14F and second bond finger 14S. As a result, the life of semiconductor device 1 can be extended.

[0055] (Variation 1) The semiconductor device of Modification 1 will be described with reference to Fig. 5. The semiconductor device of Modification 1 differs from the above-described embodiment in that the dummy terminals are entirely covered with a solder resist layer 15. In the following description, the same components as those in the above-described embodiment are denoted by the same reference numerals, and their description may be omitted.

[0056] 5 is a partial top view showing the configuration around the opening 151 of the semiconductor device according to Modification 1. In addition, in FIG. 5 and subsequent figures, the configuration of the bonding wire 51 and the like is omitted.

[0057] 5, in the semiconductor device of the first modification, the dummy terminals 100b are covered with the solder resist layer 15 (see FIGS. 1 to 3). That is, the dummy terminals 100b are not exposed in the openings 151.

[0058] As a result, the plating layers MEa and MEb are not formed on the dummy terminals 100b, which makes it possible to further reduce the consumption of plating solution.

[0059] Furthermore, even when the dummy terminal 100b is covered with the solder resist layer 15, a uniform electric field is formed on both sides of the second bond finger 14Sc in the Y direction. This is because the first bond finger 14Fc and the dummy terminal 100b are supplied with the same potential, and the first bond finger 14Fc and the dummy terminal 100b are arranged at the same distance W from the second bond finger 14Sc. This makes it possible to prevent short circuits between the first bond finger 14Fc and the second bond finger 14S.

[0060] (Variation 2) A semiconductor device according to Modification 2 will be described with reference to Fig. 6. The semiconductor device according to Modification 2 differs from the above-described embodiment in that one end of each bond finger 14 in the X direction is exposed in an opening 151. Note that, in the following description, the same components as those in the above-described embodiment are denoted by the same reference numerals, and their description may be omitted.

[0061] FIG. 6 is a partial top view showing the configuration around an opening 151 of a semiconductor device according to the second modification.

[0062] 6, one end in the X direction of each of the first bond fingers 14Fa-Fc, dummy terminal 100c, and second bond fingers 14Sa-14Sc is exposed in the opening 151. That is, each of the first bond fingers 14Fa-Fc, dummy terminal 100b, and second bond fingers 14Sa-14Sc is not exposed across the entire X direction of the opening 151. This reduces the exposed area of ​​the core layer COR to be plated, thereby reducing the consumption of plating solution.

[0063] (Variation 3) A semiconductor device of Modification 3 will be described with reference to Figure 7. The semiconductor device of Modification 3 is a modification corresponding to Modification 2, and differs from the above-described embodiment and Modification 2 in that a plated lead is connected to one end of each bond finger 14 that is exposed in the opening 151. Note that, in the following, the same components as those in the above-described embodiment will be assigned the same reference numerals, and their description may be omitted.

[0064] FIG. 7 is a partial top view showing the configuration around an opening 151 of a semiconductor device according to the third modification.

[0065] 7, in the semiconductor device according to the third modification, plating leads 61 are connected to the ends of the first bond fingers 14Fa-Fc, dummy terminal 100c, and second bond fingers 14Sa-14Sc that are exposed in the opening 151. The plating leads 61 extend in the X direction from the ends of each bond finger that are exposed in the opening 151, and terminate at a position that reaches, for example, a side surface 152 of the opening 151. The width in the Y direction of the plating leads 61 is formed narrower than the widths in the Y direction of the first bond fingers 14Fa-Fc, dummy terminal 100c, and second bond fingers 14Sa-14Sc.

[0066] As described above, electroplating uses a plating solution (not shown) and plating leads 61. When electroplating, one end of each plating lead 61 opposite the end connected to each bond finger 14 is connected to an external device (not shown), and a predetermined voltage is supplied to each bond finger 14. After electroplating is completed, for example, plating lead 61 is disconnected at a position where it reaches side surface 152. This electrically separates each bond finger from the others.

[0067] Although FIG. 7 shows an example in which the plated lead 61 is broken at a position where it reaches the side surface 152 of the opening 151, the broken position of the plated lead 61 is not limited to this.

[0068] (Variation 4) A semiconductor device according to Modification 4 will be described with reference to FIG. 8. In the above-described embodiment, the bond fingers 14 were arranged at equal intervals W along the Y direction and formed as fingers extending in the X direction. That is, the X-direction ends of adjacent bond fingers were separated. On the other hand, the semiconductor device according to Modification 4 differs from the above-described embodiment in that the X-direction ends of the second bond fingers are in contact. Note that, in the following, the same reference numerals will be used to designate the same components as those in the above-described embodiment, and their description may be omitted.

[0069] FIG. 8 is a partial top view showing the configuration around an opening 151 of a semiconductor device according to the fourth modification.

[0070] 8, around an opening 151 of the semiconductor device according to Modification 4, first bond fingers 14Fx-14Fz, dummy terminals 100d, and second bond fingers 14Sx-14Sz are alternately arranged at intervals W. Also, vias 133b are arranged at both ends of the second bond fingers 14Sx-14Sz in the X direction.

[0071] Specifically, as shown in Figure 8, for example, a first bond finger 14Fx and a first bond finger 14Fy are arranged on both sides of the second bond finger 14Sx in the Y direction, a first bond finger 14Fy and a first bond finger 14Fz are arranged on both sides of the second bond finger 14Sy in the Y direction, and a first bond finger 14Fz and a dummy terminal 100c are arranged on both sides of the second bond finger 14Sz in the Y direction.

[0072] In this case, the two first bond fingers arranged on either side of the second bond finger 14Sx-14Sz in the Y direction are connected at their ends in the X direction. Specifically, for example, the first bond fingers 14Fx and 14Fy contact each other at a boundary SFx at their ends in the X direction, the first bond fingers 14Fy and 14Fz contact each other at a boundary SFy at their ends in the X direction, and the first bond finger 14Fz and dummy terminal 100d contact each other at a boundary SFz at their ends in the X direction. As a result, the second bond fingers 14Sx-14Sz are sandwiched between the first bond fingers 14Fx-14Fz and the dummy terminal 100d on both sides in the X direction. The boundaries SFx-SFz where the first bond fingers contact each other are located at a distance W in the X direction from the via 133b.

[0073] As described above, the second bond fingers 14Sx-Sz are sandwiched between the first bond fingers 14Fx-14Fz and the dummy terminal 100d at equal distances in the X and Y directions, so that uniform electric fields are formed on both sides of the second bond fingers 14Sx-14Sz in the X and Y directions. As a result, Cu ions Mc eluted from the second bond fingers 14Sx-14Sz are equally dispersed on both sides in the X and Y directions, reducing the amount of elution from one side. This makes it possible to more effectively prevent short circuits between the first and second bond fingers.

[0074] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0075] 1...semiconductor device, 10a...first surface, 10b...second surface, 11...wiring board, 12...insulating layer, 13...wiring layer, 14...bond finger, 14F...first bond finger, 14Fd (100a to 100d)...dummy terminal, 14S...second bond finger, 21...semiconductor chip, 22...electrode pad, 31...solder ball, 41...sealing member, 51...wire bonding, 131...power supply layer, 132...ground layer, 151...opening.

Claims

1. A semiconductor chip; a wiring substrate having the semiconductor chip and an insulating layer having an opening disposed on a first surface, a plurality of bond fingers arranged along a first direction which is a longitudinal direction of the opening and capable of electrically connecting to the semiconductor chip in the opening, and a power supply layer which supplies a power supply voltage to the semiconductor chip and a ground layer which supplies a ground potential to the semiconductor chip between the first surface and a second surface opposite to the first surface, the plurality of bond fingers have a configuration in which first bond fingers which are bond fingers connected to the ground layer and second bond fingers which are bond fingers connected to the power supply layer are arranged alternately at equal distances, and two third bond fingers which are two bond fingers of the plurality of bond fingers arranged at both ends of the opening in the first direction are each the first bond finger, and one of the two third bond fingers is a dummy terminal which is not connected to the semiconductor chip; Semiconductor device.

2. At least a portion of the dummy terminal is covered with the insulating layer. The semiconductor device according to claim 1 .

3. the dummy terminal is covered with the insulating layer; The semiconductor device according to claim 1 .

4. one end of each of the bond fingers in a second direction that intersects with the first direction and is along the first surface is exposed to the opening; The semiconductor device according to claim 1 .

5. a plated lead is connected to one end of each of the bond fingers that is exposed in the opening; The semiconductor device according to claim 4 .

6. the two first bond fingers arranged on both sides of the second bond finger are in contact with each other at both ends in a second direction that intersects the first direction and is along the first surface; The semiconductor device according to claim 1 .

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