Semiconductor chip having on-chip antenna

Abstract

To provide a technique that enhances the degree of freedom regarding a position where a circuit section is formed in a semiconductor chip having an on-chip antenna.SOLUTION: A semiconductor chip mounted on a circuit board includes an on-chip antenna and a circuit section containing circuit elements. The circuit section comprises a wiring connected to circuit elements, chip pads electrically connected to an electrode surface on the circuit board, and inductors formed between the wiring and the chip pads.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a semiconductor chip equipped with an on-chip antenna. [Background technology]

[0002] Semiconductor chips that integrate an integrated circuit and an on-chip antenna are being developed, and one example is disclosed in Patent Document 1. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2023-137179 Summary of the Invention [Problem to be solved by the invention]

[0004] In addition to a wireless circuit that inputs and outputs high-frequency signals to and from an on-chip antenna, it is sometimes desirable to form a circuit that performs a certain function on a semiconductor chip. However, if such a circuit is located near the antenna, the electric field generated around the antenna is affected, resulting in a problem of reduced signal propagation. To avoid this situation, the circuit must be located sufficiently far from the on-chip antenna. This presents a problem of limited flexibility in determining the location of such a circuit within the semiconductor chip. This specification provides a technology that improves the flexibility in determining the location of the circuit in a semiconductor chip equipped with an on-chip antenna. [Means for solving the problem]

[0005] The present specification provides a semiconductor chip mounted on a circuit board. The semiconductor chip may include an on-chip antenna and a circuit section including a circuit element. The circuit section may include wiring connected to the circuit element, chip pads connected to an electrode surface on the circuit board, and an inductor formed between the wiring and the chip pad.

[0006] In the semiconductor chip, an inductor is formed between the wiring and the chip pad. The impedance of an inductor increases as the frequency increases. Therefore, when an inductor is formed between the wiring and the chip pad, the circuit unit can be equivalent to a configuration in which the circuit unit is separated by the inductor in the frequency band of the on-chip antenna. As a result, even if the circuit unit is located near the on-chip antenna, the influence on the electric field generated around the on-chip antenna is suppressed. In the semiconductor chip, the degree of freedom in the position in which the circuit unit is formed is improved. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 2 is a plan view schematically showing the antenna device. [Figure 2] FIG. 2 is a bottom view schematically showing the antenna device. [Figure 3] FIG. 2 is a cross-sectional view schematically showing a stacked structure of semiconductor chips. [Figure 4] 1 is a plan view schematically showing the layout of an on-chip antenna and a circuit section provided on the semiconductor chip of the first embodiment. FIG. [Figure 5] FIG. 10 is a plan view schematically showing the layout of an on-chip antenna and a circuit section provided on a semiconductor chip according to a second embodiment. [Figure 6] FIG. 10 is a plan view schematically showing the layout of an on-chip antenna and a circuit section provided on a semiconductor chip according to a third embodiment. [Figure 7] FIG. 10 is a plan view schematically showing the layout of an on-chip antenna and a circuit section provided on a semiconductor chip according to a fourth embodiment. [Figure 8]FIG. 11 is a plan view schematically showing the layout of an on-chip antenna and a circuit section provided on a semiconductor chip according to a fifth embodiment. [Figure 9] FIG. 13 is a plan view schematically showing the layout of an on-chip antenna and a circuit section provided on a semiconductor chip according to a modification of the fifth embodiment. [Figure 10] FIG. 13 is a plan view schematically showing the layout of an on-chip antenna and a circuit section provided on a semiconductor chip according to a modification of the fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, an antenna device and a semiconductor chip mounted on the antenna device will be described with reference to the drawings. Note that components that are substantially common across multiple embodiments will be denoted by common reference numerals.

[0009] (First embodiment) 1 and 2, the antenna device 100 includes a circuit board 1, a pair of semiconductor chips 2a, 2b and a pair of power supply surfaces 3a, 3b provided on the front surface of the circuit board 1, and a pair of GND surfaces 4a, 4b provided on the back surface of the circuit board 1. As will be described later, an on-chip antenna is formed on each of the pair of semiconductor chips 2a, 2b. Therefore, the antenna device 100 is configured to transmit and receive high-frequency signals between the pair of semiconductor chips 2a, 2b while electrically insulating and isolating the pair of semiconductor chips 2a, 2b. The distance D1 between the pair of semiconductor chips 2a, 2b is not particularly limited, and may be, for example, several millimeters to several tens of millimeters.

[0010] The circuit board 1 has a flat plate shape and is made of a board made of any material. The circuit board 1 is not particularly limited, but may be, for example, a printed circuit board made of a composite material of glass fiber and epoxy resin (i.e., FR-4). In this example, a pair of semiconductor chips 2a, 2b are provided on one circuit board 1, but instead of this example, two circuit boards corresponding to each of the pair of semiconductor chips 2a, 2b may be provided, and communication may be performed between these circuit boards.

[0011] The pair of semiconductor chips 2a, 2b includes the semiconductor chip 2a having an on-chip antenna for transmission and the semiconductor chip 2b having an on-chip antenna for reception. The pair of semiconductor chips 2a, 2b may have a symmetrical structure that is inverted relative to each other in the transmission and reception direction connecting the semiconductor chip 2a and the semiconductor chip 2b (in this example, the left-right direction on the paper). Hereinafter, when there is no need to distinguish between the semiconductor chip 2a and the semiconductor chip 2b, they will be referred to as the semiconductor chip 2.

[0012] 3 shows the layered structure of the semiconductor chip 2. The semiconductor chip 2 has a substrate layer 6 and a wiring layer 8 layered on the substrate layer 6. The substrate layer 6 is configured by layering a lower semiconductor layer 12, a buried insulating layer 13, and an upper semiconductor layer 14. The materials of the lower semiconductor layer 12 and the upper semiconductor layer 14 are not particularly limited, but may be, for example, silicon. The material of the buried insulating layer 13 is not particularly limited, but may be, for example, silicon oxide. In this way, the substrate layer 6 may be configured using an SOI substrate. The upper semiconductor layer 14 is a device layer, and is a layer in which a wireless circuit unit and a non-wireless circuit unit, which will be described later, are formed.

[0013] The wiring layer 8 has an insulating isolation layer 16 and a metal wiring layer 18 provided on the insulating isolation layer 16. The material of the insulating isolation layer 16 is not particularly limited, but may be, for example, silicon oxide. The material of the metal wiring layer 18 is not particularly limited, but may be, for example, aluminum. The metal wiring layer 18 is a layer on which an on-chip antenna, wiring, and inductor, which will be described later, are formed.

[0014] Returning to Figures 1 and 2, the pair of power supply planes 3a, 3b are metal films fixed at a power supply potential. The material of the pair of power supply planes 3a, 3b is not particularly limited, but may be, for example, copper or aluminum. The pair of power supply planes 3a, 3b includes a power supply plane 3a for a transmitting antenna and a power supply plane 3b for a receiving antenna. The power supply plane 3a for a transmitting antenna and the power supply plane 3b for a receiving antenna are arranged at a predetermined distance in the transmitting and receiving direction (in this example, the left-right direction on the paper). The power supply plane 3a for a transmitting antenna is arranged near the semiconductor chip 2a. The power supply plane 3b for a receiving antenna is arranged near the semiconductor chip 2b. Hereinafter, when there is no need to distinguish between the power supply plane 3a for a transmitting antenna and the power supply plane 3b for a receiving antenna, they will be referred to as power supply plane 3.

[0015] The pair of GND planes 4a, 4b are metal films fixed to a GND potential. The material of the pair of GND planes 4a, 4b is not particularly limited, but may be, for example, copper or aluminum. The pair of GND planes 4a, 4b includes a GND plane 4a for a transmitting antenna and a GND plane 4b for a receiving antenna. The GND plane 4a for the transmitting antenna and the GND plane 4b for the receiving antenna are arranged at a predetermined distance in the transmission / reception direction (in this example, the left-right direction on the paper). The GND plane 4a for the transmitting antenna is arranged on the back surface of the circuit board 1, facing the power supply plane 3a for the transmitting antenna arranged on the front surface of the circuit board 1. The GND plane 4b for the receiving antenna is arranged on the back surface of the circuit board 1, facing the power supply plane 3b for the receiving antenna arranged on the front surface of the circuit board 1. Hereinafter, when there is no need to distinguish between the GND plane 4a for the transmitting antenna and the GND plane 4b for the receiving antenna, they will be referred to as GND plane 4.

[0016] As shown in FIG. 4, the semiconductor chip 2 has an on-chip antenna 22, a wireless circuit unit 24, a wireless power supply wiring 26, and a wireless GND wiring 27.

[0017] The on-chip antenna 22 is configured using a part of the metal wiring layer 18 (see FIG. 3 ) disposed on the insulating isolation layer 16 of the semiconductor chip 2. The on-chip antenna 22 is not particularly limited, but may be configured, for example, as a monopole antenna having a meander pattern. In this example, the on-chip antenna 22 extends within the same plane from a feed point 22 a to an open end 22 b, repeatedly moving back and forth along one direction (in this example, the horizontal direction on the paper) while extending in a direction perpendicular to the one direction (in this example, the vertical direction on the paper, hereinafter referred to as the “antenna extension direction”). The frequency band of the on-chip antenna 22 is not particularly limited, but may be, for example, several GHz. The feed point 22 a of the on-chip antenna 22 is connected to the radio circuit unit 24.

[0018] The radio circuit unit 24 has a high-frequency circuit that inputs and outputs high-frequency signals (i.e., modulated waves) to and from the on-chip antenna 22, and is composed of circuit elements such as an oscillator, an amplifier, and a low-noise amplifier. The radio circuit unit 24 has functions such as oscillation, amplification, modulation, and demodulation. The radio circuit unit 24 is connected to each of the radio power supply wiring 26 and the radio GND wiring 27. The radio circuit unit 24 is formed in the upper semiconductor layer 14 (see FIG. 3) of the semiconductor chip 2.

[0019] The wireless power supply wiring 26 and the wireless GND wiring 27 are configured using part of the metal wiring layer 18 (see FIG. 3) disposed on the insulating separation layer 16 of the semiconductor chip 2. The wireless power supply wiring 26 has a wireless power supply pad 28. The wireless power supply pad 28 is electrically connected to the power supply surface 3 via a metal wire. The wireless GND wiring 27 has a wireless GND pad 29. The wireless GND pad 29 is electrically connected to the GND surface 4 (specifically, a metal surface provided on the front surface of the circuit board 1, which is connected via a via to the GND surface 4 provided on the back surface of the circuit board 1) via a metal wire.

[0020] The semiconductor chip 2 further has a non-wireless circuit section 30, a non-wireless power supply wiring 31, a non-wireless GND wiring 32, a first inductor 33, a second inductor 34, a non-wireless power supply pad 35, and a non-wireless GND pad 36.

[0021] The non-wireless circuit unit 30 has a low-frequency circuit that operates at a frequency lower than the frequency band of the on-chip antenna 22, and is configured with circuit elements such as an operational amplifier, a logic circuit, a reference voltage generating circuit, and a power supply circuit. The non-wireless circuit unit 30 has a function for processing low-frequency signal waves included in high-frequency signals transmitted and received by the on-chip antenna 22, for example. The non-wireless circuit unit 30 is connected to each of a non-wireless power supply wiring 31 and a non-wireless GND wiring 32. The non-wireless circuit unit 30 is formed in the upper semiconductor layer 14 (see FIG. 3 ) of the semiconductor chip 2.

[0022] The non-wireless circuit unit 30 is disposed near and parallel to the on-chip antenna 22. More specifically, when viewed from a direction perpendicular to the main surface of the semiconductor chip 2 (hereinafter referred to as "when viewed in a plan view"), the non-wireless circuit unit 30 is disposed adjacent to the on-chip antenna 22 in a direction perpendicular to the antenna extension direction of the on-chip antenna 22. Furthermore, the non-wireless circuit unit 30 extends parallel to the antenna extension direction of the on-chip antenna 22, and is disposed over a range from the feeding point 22a to the open end 22b of the on-chip antenna 22.

[0023] The non-wireless power supply wiring 31, the non-wireless GND wiring 32, the first inductor 33, the second inductor 34, the non-wireless power supply pad 35, and the non-wireless GND pad 36 are configured using part of the metal wiring layer 18 (see FIG. 3 ) disposed on the insulating separation layer 16 of the semiconductor chip 2. The non-wireless power supply wiring 31 and the non-wireless GND wiring 32 extend parallel to the antenna extension direction of the on-chip antenna 22, and extend over the area where the non-wireless circuit unit 30 is formed. The first inductor 33 is configured with wiring having a narrower line width than the non-wireless power supply wiring 31, and has one end in contact with the non-wireless power supply wiring 31 and the other end in contact with the non-wireless power supply pad 35, thereby being connected between the non-wireless power supply wiring 31 and the non-wireless power supply pad 35. The second inductor 34 is configured with wiring having a narrower line width than the non-wireless GND wiring 32, and has one end in contact with the non-wireless GND wiring 32 and the other end in contact with the non-wireless GND pad 36, thereby being connected between the non-wireless GND wiring 32 and the non-wireless GND pad 36. The non-wireless power supply pad 35 is electrically connected to the power supply surface 3 via a metal wire. The non-wireless GND pad 36 is electrically connected to the GND surface 4 via a metal wire (specifically, a metal surface provided on the surface of the circuit board 1, which is connected via a via to the GND surface 4 provided on the back surface of the GND surface 4).

[0024] The first inductor 33 is configured with a first planar coil pattern in a whorl or spiral shape. When viewed from above, the first inductor 33 is wound clockwise along the direction of current (from the non-wireless power supply pad 35 to the non-wireless power supply wiring 31). The wiring between the end of the first inductor 33 and the non-wireless power supply pad 35 is formed in the upper semiconductor layer 14 of the semiconductor chip 2 (see FIG. 3) so as to be in a twisted position with respect to the pattern wiring portion of the first inductor 33, and is connected to each of the end of the first inductor 33 and the non-wireless power supply pad 35 via vias.

[0025] The second inductor 34 is configured with a second planar coil pattern in a whorl or spiral shape. When viewed from above, the second inductor 34 is wound clockwise along the direction of current (from the non-wireless GND wiring 32 to the non-wireless GND pad 36). The wiring between the end of the second inductor 34 and the non-wireless GND pad 36 is formed in the upper semiconductor layer 14 (see FIG. 3 ) of the semiconductor chip 2 so as to be in a twisted position with respect to the pattern wiring portion of the second inductor 34, and is connected to each of the end of the second inductor 34 and the non-wireless GND pad 36 via vias.

[0026] Here, consider an antenna device of a comparative example that does not include the first inductor 33 and the second inductor 34. When viewed from above, it is desirable for the monopole on-chip antenna 22 to generate electric fields from both sides of the on-chip antenna 22 toward mirror images formed on the power supply plane 3 and the GND plane 4. However, in the comparative example, a non-wireless circuit unit 30 is provided parallel to one side of the on-chip antenna 22. If the first inductor 33 and the second inductor 34 are not provided, the non-wireless circuit unit 30 is equivalent to the GND when viewed from the on-chip antenna 22. Therefore, in the comparative example, no electric field is generated from the side of the on-chip antenna 22 where the non-wireless circuit unit 30 is provided. As a result, in the comparative example, the propagation amount at the resonance point of the on-chip antenna 22 is significantly reduced.

[0027] On the other hand, the semiconductor chip 2 of this embodiment is provided with a first inductor 33 and a second inductor 34. The first inductor 33 and the second inductor 34 have higher impedances as the frequency increases. Therefore, in the frequency band of the on-chip antenna 22, the first inductor 33 and the second inductor 34 have high impedance, and the non-wireless circuit unit 30 is separated by the first inductor 33 and the second inductor 34, making it equivalent to a configuration in which the non-wireless circuit unit 30 is essentially absent. As a result, even if the non-wireless circuit unit 30 is arranged parallel to the on-chip antenna 22, the influence of the electric field generated around the on-chip antenna 22 is suppressed. The semiconductor chip 2 of this embodiment has improved flexibility in the position in which the non-wireless circuit unit 30 is arranged, allowing the semiconductor chip 2 to be miniaturized.

[0028] (Second embodiment) The semiconductor chip 2 shown in FIG. 5 is characterized in that the winding direction of the second inductor 34 is opposite to that of the example shown in FIG. 4. In this example, the direction of the current flowing through the pattern wiring portion of the first inductor 33 closest to the second inductor 34 is the same as the direction of the current flowing through the pattern wiring portion of the second inductor 34 closest to the first inductor 33 (downward in this example). This increases the inductance of the first inductor 33 and the second inductor 34. In other words, the first inductor 33 and the second inductor 34 having the required inductance can be configured in a small area. The semiconductor chip 2 can be made smaller.

[0029] The first inductor 33 and the second inductor 34 may be arranged facing each other between different surfaces instead of being arranged on the same plane. In this case, one of the first inductor 33 and the second inductor 34 may be formed in the upper semiconductor layer 14 (see FIG. 3 ) of the semiconductor chip 2, or may be formed using an additional insulating isolation layer and metal wiring layer stacked on the wiring layer 18 of the semiconductor chip 2. In this example, the pattern wiring portions of the first inductor 33 and the second inductor 34 may be arranged so that at least a portion of them face each other in the opposing direction between the different surfaces, and may be configured so that the direction of current flowing through the pattern wiring portions is the same. In this case, the inductance of the first inductor 33 and the second inductor 34 is increased, thereby enabling the semiconductor chip 2 to be miniaturized.

[0030] (Third embodiment) 6 is characterized in that the first inductor 33 and the second inductor 34 are configured in a meander pattern. The first inductor 33 and the second inductor 34 configured in a meander pattern can also achieve the same effects as the above-mentioned whorl-shaped or spiral-shaped planar coil pattern.

[0031] When the first inductor 33 and the second inductor 34 are configured in a meander pattern, the first inductor 33 and the second inductor 34 may be arranged facing each other between different surfaces. In this example, the pattern wiring portions of the first inductor 33 and the second inductor 34 may be arranged so that their entirety faces each other in the facing direction between the different surfaces, and may be configured so that the directions of the flowing currents are the same. In this case, too, the inductance of the first inductor 33 and the second inductor 34 is increased, allowing the semiconductor chip 2 to be made smaller.

[0032] (Fourth embodiment) 7 is characterized by further including an intermediate potential wiring 41, a third inductor 42, and an intermediate potential pad 43. The intermediate potential wiring 41 is connected to the non-wireless circuit unit 30 and is a wiring for supplying an intermediate potential between a power supply potential and a ground potential to the non-wireless circuit unit 30. One end of the third inductor 42 is in contact with the intermediate potential wiring 41, and the other end is in contact with the intermediate potential pad 43, thereby being connected between the intermediate potential wiring 41 and the intermediate potential pad 43. The intermediate potential pad 43 is electrically connected to the intermediate potential surface 5 on the circuit board 1 via a metal wire. These components for supplying an intermediate potential to the non-wireless circuit unit 30 can be formed using the same technology as the above-mentioned components for supplying the power supply potential and the GND potential to the non-wireless circuit unit 30.

[0033] The non-wireless circuit unit 30 may require an intermediate potential between the power supply potential and the GDN potential, in addition to the power supply potential and the GDN potential. In such a case, if the intermediate potential wiring 41 is arranged in parallel with the on-chip antenna 22, there is a concern that it may affect the electric field of the on-chip antenna 22. In this example, the third inductor 42 is also provided for the intermediate potential wiring 41, and therefore, in the frequency band of the on-chip antenna 22, the non-wireless circuit unit 30 is isolated by the third inductor 42, which has high impedance. The semiconductor chip 2 of this embodiment can also achieve the same effects as the other embodiments.

[0034] (Fifth embodiment) The semiconductor chip 2 shown in Fig. 8 is characterized in that the first inductor 133 and the second inductor 134 are configured in a linear pattern. The first inductor 133 extends parallel to the non-wireless power supply wiring 31 and is connected to one of the ends of the non-wireless power supply wiring 31 that is farther from the non-wireless power supply pad 35. The second inductor 134 extends parallel to the non-wireless GND wiring 32 and is connected to one of the ends of the non-wireless GND wiring 32 that is farther from the non-wireless GND pad 36. Since the pattern wiring portions of the first inductor 133 and the second inductor 134 are each long, the parasitic inductance of the first inductor 133 and the second inductor 134 increases. Therefore, the semiconductor chip 2 of this embodiment can achieve the same effects as the other embodiments.

[0035] In the example where the first inductor 133 and the second inductor 134 are configured in a linear pattern, various layouts can be adopted as long as the area of ​​the semiconductor chip 2 is not substantially increased.

[0036] 9, the second inductor 134 extends parallel to the non-wireless power supply wiring 31 and is connected to one of the ends of the non-wireless GND wiring 32 that is farther from the non-wireless GND pad 36. In this example, the pattern wiring portion of the second inductor 134 has an additional portion that extends beyond the non-wireless power supply wiring 31 toward the end of the non-wireless GND wiring 32 (in this example, a portion that extends in the left-right direction on the page), thereby further increasing the parasitic inductance of the second inductor 134. Note that the pattern wiring portion of the first inductor 133 may be configured to have the additional portion.

[0037] 10, the first inductor 133 extends so as to make a circuit around the non-wireless circuit unit 30 and is connected to the end of the non-wireless power supply wiring 31. Since the first inductor 133 is longer, it is possible to further increase the parasitic inductance of the first inductor 133. Note that the second inductor 134 may be configured to make a circuit around the non-wireless circuit unit 30.

[0038] The features of the technology disclosed in this specification are summarized below. Note that the technical elements described below are independent technical elements that exhibit technical usefulness either alone or in various combinations.

[0039] (Feature 1) A semiconductor chip mounted on a circuit board, an on-chip antenna; a circuit section including a circuit element, The circuit unit includes: Wiring connected to the circuit element; chip pads electrically connected to electrode surfaces on the circuit board; an inductor formed between the wiring and the chip pad.

[0040] (Feature 2) 2. The semiconductor chip according to claim 1, wherein the inductor has at least one of a planar coil pattern and a meander pattern.

[0041] (Feature 3) 3. The semiconductor chip according to feature 1 or 2, wherein the circuit unit is arranged adjacent to the on-chip antenna in a direction perpendicular to the antenna extension direction of the on-chip antenna when the semiconductor chip is viewed in a plane.

[0042] (Feature 4) 4. The semiconductor chip according to any one of features 1 to 3, wherein the circuit section has a low-frequency circuit that operates at a frequency lower than the frequency band of the on-chip antenna.

[0043] (Feature 5) The wiring is GND wiring and power supply wiring, The chip pad is a GND pad electrically connected to a GND plane on the circuit board; a power supply pad electrically connected to a power supply surface on the circuit board, The inductor is a first inductor formed between the GND wiring and the GND pad; 5. The semiconductor chip according to any one of features 1 to 4, further comprising: a second inductor formed between the power supply wiring and the power supply pad.

[0044] (Feature 6) the first inductor has a first planar coil pattern; the second inductor has a second planar coil pattern; the first planar coil pattern and the second planar coil pattern are arranged adjacent to each other in the same plane, The semiconductor chip of feature 5, wherein the direction of current flowing through the pattern wiring portion of the first planar coil pattern closest to the second planar coil pattern is the same as the direction of current flowing through the pattern wiring portion of the second planar coil pattern closest to the first planar coil pattern.

[0045] (Feature 7) the first planar coil pattern and the second planar coil pattern are arranged opposite each other on different surfaces, 6. The semiconductor chip according to Feature 5, wherein the directions of currents flowing in opposing pattern wiring portions are the same.

[0046] (Feature 8) the first inductor has a first meander pattern; the second inductor has a second meander pattern, the first meander pattern and the second meander pattern are arranged adjacent to each other in the same plane, The semiconductor chip described in Feature 5, wherein the direction of current flowing through the pattern wiring portion of the first meander pattern closest to the second meander pattern is the same as the direction of current flowing through the pattern wiring portion of the second meander pattern closest to the first meander pattern.

[0047] (Feature 9) the first meander pattern and the second meander pattern are disposed opposite each other on different surfaces, 6. The semiconductor chip according to Feature 5, wherein the directions of currents flowing in opposing pattern wiring portions are the same.

[0048] (Feature 10) The wiring further includes an intermediate potential wiring, the chip pad further includes an intermediate potential pad connected to an intermediate potential electrode on the circuit board; 10. The semiconductor chip according to any one of features 1 to 9, wherein the inductor further includes a third inductor formed between the intermediate potential wiring and the intermediate potential pad.

[0049] Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives alone is technically useful. [Explanation of symbols]

[0050] 1: circuit board, 2: semiconductor chip, 3: power supply plane, 4: GND plane, 22: on-chip antenna, 22a: feed point, 2b: open end, 24: wireless circuit section, 26: wireless power supply wiring, 27: wireless GND wiring, 28: wireless power supply pad, 29: wireless GND pad, 30: non-wireless circuit section, 31: non-wireless power supply wiring, 32: non-wireless GND wiring, 33: first inductor, 34: second inductor, 35: non-wireless power supply pad, 36: non-wireless GND pad

Claims

1. A semiconductor chip mounted on a circuit board, an on-chip antenna; a circuit section including a circuit element, The circuit unit includes: Wiring connected to the circuit element; chip pads electrically connected to electrode surfaces on the circuit board; an inductor formed between the wiring and the chip pad.

2. The semiconductor chip according to claim 1 , wherein the inductor has at least one of a planar coil pattern and a meander pattern.

3. 2. The semiconductor chip according to claim 1, wherein the circuit section is disposed adjacent to the on-chip antenna in a direction perpendicular to an antenna extension direction of the on-chip antenna when the semiconductor chip is viewed in plan view.

4. The semiconductor chip according to claim 1 , wherein the circuit section has a low-frequency circuit that operates at a frequency lower than the frequency band of the on-chip antenna.

5. The wiring is GND wiring, power supply wiring, The chip pad is a GND pad electrically connected to a GND surface on the circuit board; a power supply pad electrically connected to a power supply surface on the circuit board, The inductor is a first inductor formed between the GND wiring and the GND pad; 2. The semiconductor chip according to claim 1, further comprising: a second inductor formed between said power supply wiring and said power supply pad.

6. the first inductor has a first planar coil pattern; the second inductor has a second planar coil pattern; the first planar coil pattern and the second planar coil pattern are arranged adjacent to each other in the same plane, 6. The semiconductor chip according to claim 5, wherein a direction of current flowing through a pattern wiring portion of the first planar coil pattern closest to the second planar coil pattern is the same as a direction of current flowing through a pattern wiring portion of the second planar coil pattern closest to the first planar coil pattern.

7. the first inductor has a first planar coil pattern; the second inductor has a second planar coil pattern; the first planar coil pattern and the second planar coil pattern are arranged opposite each other on different surfaces, 6. The semiconductor chip according to claim 5, wherein the directions of currents flowing in the opposing pattern wiring portions are the same.

8. the first inductor has a first meander pattern, the second inductor has a second meander pattern, the first meander pattern and the second meander pattern are arranged adjacent to each other in the same plane, 6. The semiconductor chip of claim 5, wherein the direction of current flowing through the pattern wiring portion of the first meander pattern closest to the second meander pattern is the same as the direction of current flowing through the pattern wiring portion of the second meander pattern closest to the first meander pattern.

9. the first inductor has a first meander pattern, the second inductor has a second meander pattern, the first meander pattern and the second meander pattern are disposed opposite each other on different surfaces, 6. The semiconductor chip according to claim 5, wherein the directions of currents flowing in the opposing pattern wiring portions are the same.

10. The wiring further includes an intermediate potential wiring, the chip pad further includes an intermediate potential pad connected to an intermediate potential electrode on the circuit board; 10. The semiconductor chip according to claim 1, wherein the inductor further comprises a third inductor formed between the intermediate potential wiring and the intermediate potential pad.

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