Semiconductor device

Abstract

To provide a semiconductor device capable of more appropriately performing recovery from a power shutdown state.SOLUTION: The semiconductor device comprises: a plurality of processing circuits; a stopped circuit determination part determining a first processing circuit to be stopped from the plurality of processing circuits; and a stopping method determination part determining whether an operation stopping method for the first processing circuit is performed as a first stopping method including power shutdown or a second stopping method excluding power shutdown, based on circuit information of each of the first processing circuit and a second processing circuit different from the first processing circuit in the plurality of processing circuits. The stopping method determination part determines the stopping method so that from the plurality of processing circuits, load impedance of processing circuits viewed from a power supply wiring side, which are stopped in operation at the same time by the first stopping method, is equal to or larger than a predetermined impedance.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor integrated circuit capable of low power consumption control. The semiconductor integrated circuit in Patent Document 1 has a clock gating circuit that controls whether a clock signal is supplied to a circuit such as a processor core, and a power switch that controls whether a power supply voltage is supplied to the circuit. Patent Document 1 proposes a technology that achieves both low power consumption and improved processing performance by applying clock gating instead of power shutdown to circuits that frequently stop operation.

[0003] Patent Document 2 discloses a distance measuring sensor having a plurality of signal processing modules that can independently control the power supply. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-119003 [Patent Document 2] Japanese Patent Publication No. 2021-139836 Summary of the Invention [Problem to be solved by the invention]

[0005] In a semiconductor device having a plurality of processing circuits in which power is cut off as in Patent Documents 1 and 2, it may be required to more appropriately restore from the power-off state.

[0006] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor device that can more appropriately recover from a power-off state. [Means for solving the problem]

[0007] According to one disclosure of the present specification, there is provided a semiconductor device comprising: a plurality of processing circuits; a stop circuit determination unit that determines a first processing circuit from among the plurality of processing circuits to be stopped; and a stop method determination unit that determines a method of stopping operation in the first processing circuit to be either a first stop method that includes cutting off power, or a second stop method that does not include cutting off power, based on circuit information for the first processing circuit and a second processing circuit from the plurality of processing circuits that is different from the first processing circuit, wherein the stop method determination unit determines the stop method so that the load impedance, as seen from the power supply wiring side, of processing circuits from the plurality of processing circuits that are stopped at the same time by the first stop method is equal to or greater than a predetermined impedance.

[0008] According to one disclosure of the present specification, there is provided a semiconductor device comprising: a plurality of processing circuits; a stop circuit determination unit that determines a first processing circuit from among the plurality of processing circuits to be stopped; and a stop method determination unit that determines a method of stopping operation in the first processing circuit to be either a first stop method that includes cutting off power, or a second stop method that does not include cutting off power, based on circuit information for the first processing circuit and a second processing circuit from the plurality of processing circuits that is different from the first processing circuit; wherein the stop method determination unit determines the stop method so that the number of processing circuits from the plurality of processing circuits that are stopped at the same time by the first stop method is equal to or less than a threshold value. [Effects of the Invention]

[0009] According to the present invention, a semiconductor device capable of recovering from a power-off state more appropriately is provided. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a functional block diagram of a semiconductor device according to a first embodiment. [Figure 2] 1 is a plan view schematically illustrating a physical layout on a semiconductor substrate in a semiconductor device according to a first embodiment. [Figure 3]4 is a table showing changes over time in the state of a processing circuit in the semiconductor device according to the first embodiment. [Figure 4] 3 is a schematic plan view showing the change over time in the state of a processing circuit in the semiconductor device according to the first embodiment. FIG. [Figure 5] 10A and 10B are schematic plan views showing changes over time in the state of a processing circuit in a semiconductor device according to a comparative example; [Figure 6] 1 is a plan view schematically illustrating a physical layout on a semiconductor substrate in a semiconductor device according to a first embodiment. [Figure 7] FIG. 10 is a functional block diagram of a semiconductor device according to a modified example of the first embodiment. [Figure 8] FIG. 10 is a functional block diagram of a semiconductor device according to a modified example of the first embodiment. [Figure 9] FIG. 10 is a block diagram of a semiconductor device according to a second embodiment. [Figure 10] 10A and 10B are schematic diagrams showing changes over time in the state of a processing circuit in the semiconductor device according to the second embodiment. [Figure 11] FIG. 10 is a block diagram of a semiconductor device according to a third embodiment. [Figure 12] 10A and 10B are schematic diagrams showing changes over time in the state of a processing circuit in a semiconductor device according to a third embodiment. [Figure 13] FIG. 10 is a block diagram of a device according to a fourth embodiment. [Figure 14] FIG. 11 is a block diagram of a device according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The same or corresponding elements in multiple drawings are designated by common reference numerals, and their description may be omitted or simplified.

[0012] [First embodiment] The configuration of a semiconductor device 100 according to this embodiment will be described. FIG. 1 is a functional block diagram of the semiconductor device 100 according to this embodiment. The semiconductor device 100 is, for example, a semiconductor integrated circuit formed on a semiconductor substrate. The semiconductor device 100 has a control unit 200 and a signal processing unit 300.

[0013] The signal processing unit 300 is a signal processing circuit that processes and outputs an input signal. The signal processing unit 300 has a plurality of processing circuits P. Each of the plurality of processing circuits P processes a signal input to the signal processing unit 300. The circuit configurations of the plurality of processing circuits P may be the same or different. The type of signal processed by the signal processing unit 300 is not particularly limited, and for example, the signal processing unit 300 may be an image processing circuit that processes pixel signals output from photoelectric conversion elements. While nine processing circuits P are illustrated in FIG. 1, the number and arrangement of the plurality of processing circuits P are not limited to those shown in FIG. 1.

[0014] The control unit 200 has a mode control unit 201, a stop circuit determination unit 202, and a stop method determination unit 203. The control unit 200 is a control circuit that controls the operation of the semiconductor device 100. In other words, the control unit 200 has a function of controlling the operation of signal processing in the signal processing unit 300.

[0015] The mode control unit 201 outputs operation mode information indicating the operation mode of the semiconductor device 100 to the halted circuit determination unit 202. This operation mode may include settings related to power control in the semiconductor device 100.

[0016] The halt circuit determination unit 202 determines a processing circuit P (first processing circuit) to be halted from among the plurality of processing circuits P based on the operation mode information output from the mode control unit 201. Then, the halt circuit determination unit 202 outputs information indicating the processing circuit P to be halted to the halt method determination unit 203.

[0017] The stop method determination unit 203 determines a method for stopping the operation of the processing circuit P indicated in the information input from the stop circuit determination unit 202. Then, the stop method determination unit 203 outputs a control signal to the processing circuit P to be stopped, for stopping the operation by the determined stop method. The stop method determination unit 203 also outputs a control signal for restoring the processing circuit P whose operation has been stopped.

[0018] The candidate shutdown methods determined by the shutdown method determination unit 203 include at least a first shutdown method including power shutdown (PSO) and a second shutdown method not including power shutdown. In this embodiment, the second shutdown method is clock gating (CG). When determining the shutdown method for a certain processing circuit P, the shutdown method determination unit 203 determines the shutdown method by referring not only to circuit information about the target processing circuit P (first processing circuit) but also to circuit information about other processing circuits P (second processing circuits). The circuit information may be information about the processing circuit P, such as information indicating the layout of circuits including the processing circuit P, or information indicating whether the processing circuit P is in a shutdown state due to a power shutdown. In other words, the circuit information may be information that does not change over time, such as the circuit layout, or information that changes over time, such as the shutdown state of the processing circuit P.

[0019] Power shutoff is a method of reducing power consumption by shutting off the power supplied to the target processing circuit P. On the other hand, clock gating is a method of reducing power consumption by gating the clock signal input to the target processing circuit P to stop changes in potential. With clock gating, the power supply to the processing circuit P itself continues, so the power consumption of a processing circuit P that is clock gated is greater than the power consumption of a processing circuit P that is powered off. Therefore, the power consumption reduction effect of power shutoff is greater than the power consumption reduction effect of clock gating. On the other hand, the recovery time of a processing circuit P that has been clock gated is shorter than the recovery time of a processing circuit P that has been powered off.

[0020] When the processing circuit P recovers from a power-off state, the power supply voltage in the processing circuit P may not reach a predetermined voltage value within a predetermined time, resulting in a malfunction of the circuit. Furthermore, when the processing circuit P recovers from a power-off state, an inrush current generated by supplying a voltage to the processing circuit P may become a noise source, resulting in a malfunction of the circuit. Thus, in a method of stopping the processing circuit P by cutting off the power supply, the circuit may malfunction when recovering from the power-off state. In this embodiment, a method of stopping the processing circuit P that can reduce the occurrence of such malfunctions of the circuit will be described.

[0021] FIG. 2 is a plan view schematically illustrating the physical layout of each element on a semiconductor substrate in a semiconductor device 100 according to this embodiment. FIG. 2 schematically illustrates the physical layout of each element in a plan view relative to the semiconductor substrate. In addition to the control unit 200 and signal processing unit 300 described above, the semiconductor device 100 is also provided with an input / output I / F (interface) 101, a RAM (random access memory) 102, and a ROM (read only memory) 103. The input / output I / F 101 is a circuit that inputs and outputs signals to and from the semiconductor device 100. The RAM 102 is a volatile memory that temporarily stores information to be processed. The ROM 103 is a non-volatile memory that previously stores information required for processing.

[0022] The signal processing unit 300 has multiple processing circuits PA1, PA2, PB1, PB2, PB3, and PB4. The two processing circuits PA1 and PA2 are the same type of processing circuit. The four processing circuits PB1, PB2, PB3, and PB4 are also the same type of processing circuit. On the other hand, the processing circuits PA1 and PA2 are different types of processing circuits from the processing circuits PB1, PB2, PB3, and PB4. The processing circuits PA1 and PA2 and the processing circuits PB1, PB2, PB3, and PB4 have different power supply wiring capacitances.

[0023] The time required to recover from a power-off state depends on the load impedance of each processing circuit as seen from the power supply wiring side. Here, each processing circuit, which is composed of semiconductor elements such as transistors, is equivalent to a capacitive load as seen from the power supply wiring side, and the load impedance is capacitive. Therefore, the delay time when the potential of the power supply wiring changes largely depends on the capacitance acting on the power supply wiring of each processing circuit. When recovering from a power-off state, the potential of the power supply wiring of each processing circuit must reach a predetermined potential. Therefore, the time required to recover from a power-off state differs between processing circuits PA1 and PA2 and processing circuits PB1, PB2, PB3, and PB4 due to the difference in the capacitance of the power supply wiring.

[0024] For simplicity of explanation, the capacitance of the power supply wiring for each of the processing circuits PA1 and PA2 is assumed to be twice the capacitance of the power supply wiring for each of the processing circuits PB1, PB2, PB3, and PB4. Therefore, for example, if the time required to restore processing circuit PB1 from a power-off state is T, the time required to restore processing circuit PA1 from the power-off state is 2T. Also, if the time required to restore processing circuit PB1 from a power-off state is T, the time required to sequentially restore processing circuits PA1 and PB1 from the power-off state is 3T.

[0025] The process of restoring these multiple processing circuits from a power-off state may be performed in parallel. Therefore, the time required for the multiple processing circuits to sequentially recover from a power-off state may not be the simple sum of the times required for each processing circuit to recover from the power-off state. However, when comparing the time required for recovering a single processing circuit from a power-off state with the time required for recovering multiple processing circuits in parallel from a power-off state, the latter is longer. Furthermore, in order to prevent an increase in inrush current when recovering from a power-off state, a process of sequentially restoring each processing circuit from a power-off state may be adopted. For simplicity of explanation, hereinafter, the time required for recovering multiple processing circuits from a power-off state is assumed to be equal to the sum of the times required for each of the multiple processing circuits to recover from the power-off state.

[0026] FIG. 3 is a table showing the time-dependent changes in the states of the processing circuits PA1 to PB4 in the semiconductor device 100 according to this embodiment. FIG. 3 shows the states of the processing circuits PA1 to PB4 at times t1, t2, t3, and t4. "ON" in FIG. 3 indicates that the corresponding processing circuit is in an operating state. "OFF (PSO)" in FIG. 3 indicates that the corresponding processing circuit is in a stopped state due to power shutdown (first stopping method). "OFF (CG)" in FIG. 3 indicates that the corresponding processing circuit is in a stopped state due to clock gating (second stopping method).

[0027] 4 is a schematic plan view showing the time-dependent changes in the states of processing circuits PA1 to PB4 in the semiconductor device 100 according to this embodiment. FIG. 4 shows the time-dependent changes in the states of processing circuits PA1 to PB4 at times t1, t2, t3, and t4, along with their planar physical layout. Boxes representing processing circuits in an operating state are not hatched. Boxes representing processing circuits that are stopped due to either power shutdown or clock gating are hatched in two different ways, as shown in the legend at the bottom of FIG. 4.

[0028] In this embodiment, an example will be described in which a processing circuit to be powered off is selected so that the time required to recover from the power-off state is 4T or less, where T is the time required to recover from the power-off state for the processing circuit PB1. As described above, the time required for multiple processing circuits to recover from the power-off state depends on the total capacitance of the power supply wiring of the multiple processing circuits. Therefore, the condition that the time required to recover from the power-off state is less than a predetermined time corresponds to the condition that the total capacitance of the power supply wiring of processing circuits that are in the power-off state at the same time is less than a threshold. More generally, this condition corresponds to the condition that the load impedance, as seen from the power supply wiring side, of processing circuits that are in the power-off state at the same time is greater than or equal to a predetermined impedance.

[0029] The above-mentioned upper limit of 4T is set based on the allowable recovery time for circuit operation when recovering from a power-off state and the allowable inrush current. That is, if the time required to recover from a power-off state exceeds 4T, the recovery operation may not be completed within the specified time, resulting in a circuit malfunction, or noise due to inrush current may occur, causing a circuit malfunction. Taking these possibilities into consideration, in the examples shown in FIGS. 3 and 4 , processing circuits to be powered off are selected so that the recovery time is within 4T. Because the recovery time is determined based on the states of multiple processing circuits, circuit information for the multiple processing circuits is required for selection. The recovery time for each processing circuit is determined based on factors such as the capacity of the power wiring and can be obtained in advance. This recovery time information is prepared in advance and can be used by the shutdown method determination unit 203 as circuit information for each processing circuit. Furthermore, information indicating whether each processing circuit is already in a shutdown state due to a power-off is used to determine the recovery time. This information can be obtained from past operation history and can be used by the shutdown method determination unit 203 as circuit information for each processing circuit.

[0030] In addition, in this embodiment, the processing circuits to be powered off are selected so that the processing circuits that are powered off are not adjacent to each other. In this way, in this embodiment, the processing circuits to be powered off are selected taking into consideration the allowable recovery time and the physical layout of the multiple processing circuits.

[0031] 3 and 4, the changes in the states of the processing circuits PA1 to PB4 over time will be described in chronological order. At time t1, all of the processing circuits PA1 to PB4 are in an operating state.

[0032] At time t2, the halt circuit determination unit 202 determines the processing circuits PA2, PB1, PB3, and PB4 as those to be halted. Then, the halt method determination unit 203 determines a halt method for the processing circuits PA2, PB1, PB3, and PB4 so that the recovery time when recovering from a power-off state is 4T or less. In the example of FIG. 4, power is cut off to the processing circuits PA2, PB1, and PB4, and clock gating is applied to the processing circuit PB3. The recovery time of the processing circuit PA2 is 2T, and the recovery time of each of the processing circuits PB1 and PB4 is T, so the recovery time when all of the processing circuits PA2, PB1, and PB4 recover from a power-off state is 4T. Therefore, the condition that the recovery time is 4T or less is met.

[0033] At time t3, the halt circuit determination unit 202 determines all of the processing circuits PA1 to PB4 as targets for halt. Then, as at time t2, the halt method determination unit 203 determines a halt method for the processing circuits PA1 to PB4 so that the recovery time is 4T or less. In the example of Figure 4, power shutdown is applied to the processing circuits PA2, PB1, and PB4, and clock gating is applied to the processing circuits PA1, PB2, and PB3. In this situation as well, the condition that the recovery time is 4T or less is met.

[0034] At time t4, the stop circuit determination unit 202 determines that only processing circuit PB2 is to be stopped. Then, as at time t2, the stop method determination unit 203 determines a method for stopping processing circuit PB2 so that the recovery time is 4T or less. In the example of Fig. 4, power shutdown is applied to processing circuit PB2. Since the recovery time of processing circuit PB2 is T, the condition that the recovery time is 4T or less is met.

[0035] Between time t3 and time t4, the processing circuits PA1, PA2, PB1, PB3, and PB4 transition from a stopped state to an operating state. The processing circuits PA2, PB1, and PB4 recover from a power-off state. The recovery time is 4T, which is within the allowable value, and therefore malfunctions of the circuits are suppressed.

[0036] 5 is a schematic plan view showing the time change in the state of the processing circuits in a semiconductor device according to a comparative example. The difference between the example in FIG. 5 and the example in FIG. 4 is that there is no restriction that the recovery time must be 4T or less, and power is cut off to all of the processing circuits to be stopped. As shown in FIG. 5, at time t3, all of the processing circuits PA1 to PB4 are in a power-off state.

[0037] In the example of FIG. 5 , the processing circuits PA1, PA2, PB1, PB3, and PB4 recover from a power-off state between time t3 and time t4. The recovery time is 7T, which exceeds the allowable value. Therefore, when recovering from a power-off state, the power supply voltages of the processing circuits PA1, PA2, PB1, PB3, and PB4 may not reach a predetermined voltage within the predetermined time, resulting in circuit malfunction. Alternatively, a large inrush current may flow through the processing circuits PA1, PA2, PB1, PB3, and PB4, causing noise to generate, resulting in circuit malfunction. In contrast, in the example of FIG. 4 of this embodiment, power shutdown and clock gating are selectively used for multiple processing circuits so that the recovery time does not exceed the allowable value of 4T, thereby suppressing circuit malfunctions due to the above-mentioned factors.

[0038] As described above, the shutdown method determination unit 203 controls the shutdown method of the processing circuit so that the recovery time from the power-off state does not exceed a predetermined allowable value, thereby achieving the effect of reducing power consumption by stopping the processing circuit and appropriately recovering from the power-off state.

[0039] In addition, in this embodiment, in controlling the method of stopping the processing circuit, in addition to the recovery time described above, the physical layout of the circuit including the processing circuit is taken into consideration. This makes it possible to more appropriately suppress malfunctions of the circuit. Two examples of methods that take into consideration the physical layout of the circuit including the processing circuit will be described.

[0040] As a first example of a technique that takes into consideration the physical layout of circuits that include processing circuits, a technique that determines the combination of processing circuits to be powered off by taking into consideration the physical layout of multiple processing circuits will be described with reference again to Figure 4. This technique is applied in the example shown in Figure 4.

[0041] In the example of times t2 and t3 in Figure 4, the three processing circuits PA2, PB1, and PB4 that are in a power-off state are arranged in positions that are not adjacent vertically or horizontally in a plan view. This allows the inrush current that flows through the power wiring when the processing circuits PA2, PB1, and PB4 recover from a power-off state to be dispersed, compared to when the power-off processing circuits are adjacent. This can reduce noise caused by the inrush current. Furthermore, because power can be supplied to the non-adjacent processing circuits PA2, PB1, and PB4 from different power supply terminals on the board, the recovery time from a power-off state can also be reduced.

[0042] As described above, when selecting processing circuits to be powered off, it is desirable to select a combination of processing circuits to be powered off so that the distance between the multiple processing circuits to be powered off is large. This can prevent a large inrush current from flowing locally, further reducing circuit malfunctions. Furthermore, by selecting a combination of processing circuits to be powered off as described above, power can be supplied to the multiple processing circuits from different power supply terminals, thereby reducing the recovery time from the power-off state. This can further reduce circuit malfunctions.

[0043] As a second example of a method that takes into account the physical layout of circuits including processing circuits, a method of determining the combination of processing circuits to be powered off by taking into account the positional relationship between multiple processing circuits and the power supply terminals on the substrate on which the multiple processing circuits are formed will be described with reference to Figure 6.

[0044] Fig. 6 is a plan view schematically illustrating the physical layout on a semiconductor substrate of the semiconductor device 100 according to this embodiment. In addition to the configuration of the semiconductor device 100 shown in Fig. 2, Fig. 6 also illustrates a plurality of pads 104 and 105. The unhatched pads 104 are pads to which signal wiring is connected, and the hatched pads 105 are pads to which power supply wiring is connected.

[0045] Furthermore, the boxes of the processing circuits PA1 to PB4 in Fig. 6 are hatched to indicate the stopped state at time t3 in Fig. 4. That is, in the example of Fig. 6, all of the processing circuits PA1 to PB4 are to be stopped. Power cutoff is applied to the processing circuits PA2, PB1, and PB4, and clock gating is applied to the processing circuits PA1, PB2, and PB3.

[0046] 6, the three processing circuits PA2, PB1, and PB4 that are in a power-off state are arranged closer to the power supply pad 105 in a plan view than the other processing circuits. For example, comparing processing circuit PA1 with processing circuit PA2, processing circuit PA2 is arranged closer to the pad 105 on the top right. Also, comparing processing circuit PB2 with processing circuit PB4, processing circuit PB4 is arranged closer to the two pads 105 on the bottom right. In this way, in the example of FIG. 6, while satisfying the condition that processing circuits in a power-off state are not adjacent to each other, the processing circuits to be powered off are selected in order starting from the processing circuit closest to the power supply pad 105.

[0047] The closer a processing circuit is to power supply pad 105, the smaller the impedance of the power wiring between pad 105 and the processing circuit. Therefore, the closer a processing circuit is to power supply pad 105, the shorter the time required for power restoration. Therefore, when processing circuits PA2, PB1, and PB4 are selected as targets for power shutdown, the time required for restoration from power shutdown can be shortened compared to when, for example, processing circuits PA1, PB2, and PB3 are selected as targets for power shutdown. This can further reduce circuit malfunctions. Therefore, by determining the shutdown method so that processing circuits closer to the power supply terminal are given priority for shutdown by power shutdown, circuit malfunctions can be further reduced.

[0048] In this way, when selecting a processing circuit to be powered off, it is desirable to take the physical layout of the circuit into consideration. An example of the configuration of the shutdown method determination unit 203 that realizes such a selection will be described. Fig. 7 is a functional block diagram of a semiconductor device 100 according to a modified example of this embodiment. In Fig. 7, in addition to the configuration of Fig. 1, a layout information storage unit 204 is further provided in the control unit 200.

[0049] The layout information storage unit 204 stores in advance, as an example of circuit information regarding the plurality of processing circuits, layout information indicating the physical layout of a circuit including the processing circuits. The layout information storage unit 204 is configured with a non-volatile memory. This layout information is stored in the non-volatile memory when the semiconductor device 100 is manufactured and is not rewritten after the semiconductor device 100 is shipped. The layout information storage unit 204 supplies the layout information to the stop method determination unit 203. The stop method determination unit 203 determines a method for stopping the processing circuit by combining information indicating whether the processing circuit is in a stopped state, output from the stop circuit determination unit 202, with the layout information output from the layout information storage unit 204. The stop method determination unit 203 then outputs a control signal to the processing circuit P to be stopped, for stopping the operation using the determined stop method. This allows control that takes into account the physical layout of the plurality of processing circuits.

[0050] 8 is a functional block diagram of a semiconductor device 100 according to a modification of this embodiment. In FIG. 8, a placement information storage device 400 having a function corresponding to the placement information storage unit 204 of FIG. 7 is arranged outside the semiconductor device 100. The placement information storage device 400 includes a non-volatile memory that stores placement information and an interface that supplies the placement information to the semiconductor device 100. Like the placement information storage unit 204, the placement information storage device 400 outputs the placement information to the stopping method determination unit 203. In this way, the placement information may be stored in a device external to the semiconductor device 100.

[0051] As described above, according to this embodiment, a semiconductor device that can more appropriately recover from a power-off state is provided.

[0052] [Second embodiment] The control method for the processing circuit in the semiconductor device 100 of the first embodiment can be applied to various devices having multiple processing circuits. In this embodiment, an example will be described in which the control method for the processing circuit of the first embodiment is applied to a photoelectric conversion device such as an imaging device. In this embodiment, the description of elements common to the first embodiment may be omitted or simplified.

[0053] 9 is a block diagram of a semiconductor device 100 according to this embodiment. The semiconductor device 100 according to this embodiment is a stacked-type photoelectric conversion device in which a light-receiving element layer 110 and a signal processing circuit layer 120 are stacked. This structure can be manufactured, for example, by stacking a first substrate on which the light-receiving element layer 110 is formed and a second substrate on which the signal processing circuit layer 120 is formed. Note that the structure of the semiconductor device 100 according to this embodiment is not limited to a stacked structure, and may also be a single-layer structure. In this case, a circuit having the functions of the light-receiving element layer 110 and the signal processing circuit layer 120 is formed on one substrate.

[0054] The light receiving element layer 110 has a plurality of light receiving elements 111 arranged in a plurality of rows and a plurality of columns. The light receiving elements 111 include photoelectric conversion elements such as photodiodes, and perform photoelectric conversion on incident light to generate pixel signals. The pixel region in which the plurality of light receiving elements 111 are arranged is divided into five regions R1 to R5. The semiconductor device 100 of this embodiment has a function of outputting image information of a region selected from the five regions R1 to R5 based on the detection result of the subject 112.

[0055] The signal processing circuit layer 120 is provided with circuits that perform signal processing on pixel signals output from the multiple light receiving elements 111. The signal processing circuit layer 120 is also provided with a control unit 200 and an input / output I / F 101. The signal processing circuit layer 120 also has five analog-to-digital conversion circuits (AD conversion circuits) AD1 to AD5, five processing circuits P11 to P51, and five processing circuits P12 to P52, corresponding to the five regions R1 to R5, respectively. Analog signals output from the light receiving elements 111 in region R1 are converted to digital signals in the AD conversion circuit AD1, and the converted digital signals are input to the processing circuit P11 and then to the processing circuit P12. Analog signals output from the light receiving elements 111 in regions R2 to R5 are similarly input to the corresponding AD conversion circuits and processing circuits.

[0056] In this embodiment, the five processing circuits P11, P21, P31, P41, and P51 have the same functions. The five processing circuits P12, P22, P32, P42, and P52 also have the same functions. In this case, the five processing circuits P12, P22, P32, P42, and P52 have roughly the same power supply wiring capacitance, and therefore require roughly the same time to recover from a power-off state.

[0057] The control unit 200 controls the entire semiconductor device 100. Similarly to the first embodiment, the control unit 200 has a function to determine which processing circuits to stop and a function to determine a stopping method for the processing circuits to be stopped.

[0058] As described above, each of the AD conversion circuits AD1 to AD5 has the function of converting an input analog signal into a digital signal. However, if the light receiving element 111 can output a digital signal, the AD conversion circuits AD1 to AD5 do not need to be provided. For example, if the light receiving element 111 is a SPAD (Single Photon Avalanche Diode) sensor that has the function of counting incident photons and outputting a digital signal, the AD conversion circuits AD1 to AD5 are omitted.

[0059] Each of the processing circuits P11 to P51 processes the input pixel signal to detect the object 112. When the corresponding processing circuit P11 to P51 detects the object 112, each of the processing circuits P12 to P52 processes the pixel signal to generate image information of the corresponding area. The generated image information is output to the outside of the semiconductor device 100 via the input / output I / F 101. On the other hand, when the processing circuits P11 to P51 do not detect the object 112, the corresponding processing circuit P12 to P52 stops operating. In this way, in this embodiment, processing circuits other than the processing circuit corresponding to the area where the object 112 is detected stop operating. At this time, the method of stopping the operation of each of the processing circuits P12 to P52 can be selected from power shutdown and clock gating, as in the first embodiment.

[0060] The plurality of light receiving elements 111 are scanned row by row in order starting from the top row in Fig. 9. "t11" to "t15" in Fig. 9 indicate the times at which the rows in the illustrated positions are scanned.

[0061] At time t11, the subject 112 is detected only in region R3. Therefore, the processing circuit P32 corresponding to region R3 performs signal processing, and the processing circuits P12, P22, P42, and P52 stop operating.

[0062] At time t12, the subject 112 is not detected in any of the areas, so the processing circuits P12, P22, P32, P42, and P52 stop operating.

[0063] At time t13, the subject 112 is detected in regions R2 and R4. Therefore, the processing circuits P22 and P42 corresponding to regions R2 and R4, respectively, perform signal processing operations, and the processing circuits P12, P32, and P52 stop operating.

[0064] At time t14, the subject 112 is not detected in any of the areas, so the processing circuits P12, P22, P32, P42, and P52 stop operating.

[0065] At time t15, the subject 112 is detected in regions R1, R2, R3, and R5. Therefore, the processing circuits P12, P22, P32, and P52 corresponding to regions R1, R2, R3, and R5, respectively, perform signal processing operations, and the processing circuit P42 stops operating.

[0066] 10 is a schematic diagram showing the change over time in the state of the processing circuits in the semiconductor device 100 according to this embodiment. FIG. 10 schematically shows the change over time in the state of the processing circuits P12 to P52 from time t11 to t15. Boxes representing processing circuits in an operating state are not hatched. Boxes representing processing circuits in a stopped state due to either a power cutoff or clock gating are hatched in the same way as in FIG. 4.

[0067] In the first embodiment, an example is shown in which the recovery times from a power-off state are not the same for multiple processing circuits. However, because the processing circuits P12 to P52 in this embodiment have the same function, it is assumed that the recovery times from a power-off state for each of the processing circuits P12 to P52 are the same. In this case, the recovery time from a power-off state for the entire processing circuits P12 to P52 depends on the number of processing circuits that are recovering from the power-off state. In this embodiment, the change over time in FIG. 10 is explained assuming that the upper limit of the number of processing circuits that can be simultaneously recovered from a power-off state is three.

[0068] At time t11, the subject 112 is detected only in region R3 as described above, and therefore the processing circuits P12, P22, P42, and P52 other than the processing circuit P32 stop operating. Here, power is cut off to the processing circuits P12, P42, and P52, and clock gating is applied to the processing circuit P22.

[0069] At time t12, as described above, the subject 112 is not detected in any of the areas, so the processing circuits P12, P22, P32, P42, and P52 stop operating. Here, power is cut off to the processing circuits P12, P32, and P52, and clock gating is applied to the processing circuits P22 and P42.

[0070] At time t13, the subject 112 is detected in the regions R2 and R4 as described above, so the processing circuits P12, P32, and P52 other than the processing circuits P22 and P42 stop operating. Here, power is cut off for the processing circuits P12, P32, and P52.

[0071] At time t14, as described above, the subject 112 is not detected in any of the areas, so the processing circuits P12, P22, P32, P42, and P52 stop operating. Here, power is cut off to the processing circuits P12, P32, and P52, and clock gating is applied to the processing circuits P22 and P42.

[0072] At time t15, as described above, the subject 112 is detected in the regions R1, R2, R3, and R5, and therefore the processing circuit P42 other than the processing circuits P12, P22, P32, and P52 stops operating. Here, power is cut off to the processing circuit P42.

[0073] As described above, in this embodiment, the method of stopping the processing circuits is controlled so that the number of processing circuits that are in a power-off state at each time is 3 or less. The effect of this embodiment will be explained by focusing on the transition from the state at time t14 to the state at time t15.

[0074] If all processing circuits were in a power-off state at time t14, then when the state at time t14 transitions to the state at time t15, the number of processing circuits that will return from the power-off state will be four. Therefore, the number of processing circuits that will simultaneously return from the power-off state will exceed the upper limit of three, which could result in circuit malfunction. In contrast, in this embodiment, when the state transitions from time t14 to time t15, the number of processing circuits that will return from the power-off state is three, which does not exceed the upper limit, thereby suppressing circuit malfunction.

[0075] In this way, by controlling the method of stopping the processing circuits so that the number of processing circuits that simultaneously return from a power-off state does not exceed a predetermined allowable value, the power consumption reduction effect of stopping the processing circuits can be achieved while the return from the power-off state can be performed appropriately.

[0076] Furthermore, at times t12 and t14, the combination of processing circuits to be powered off is determined taking into consideration the physical layout of the multiple processing circuits, as described in the first embodiment. More specifically, clock gating is applied to the processing circuits between the multiple processing circuits to be powered off, and the multiple processing circuits to be powered off are spaced apart. This can further reduce circuit malfunctions for the same reasons as described in the first embodiment.

[0077] As described above, according to this embodiment, a photoelectric conversion device is provided to which a method is applied that can more appropriately restore from a power-off state.

[0078] [Third embodiment] In this embodiment, another example of a photoelectric conversion device to which the control method of the processing circuit of the first embodiment is applied will be described. In this embodiment, the description of elements common to the first and second embodiments may be omitted or simplified.

[0079] 11 is a block diagram of a semiconductor device 100 according to this embodiment. The semiconductor device 100 according to this embodiment is a stacked photoelectric conversion device in which a light-receiving element layer 110 and a signal processing circuit layer 120 are stacked, as in the second embodiment. However, the structure of the semiconductor device 100 according to this embodiment is not limited to a stacked structure, and may be a single-layer structure. As in the second embodiment, the light-receiving element layer 110 has a plurality of light-receiving elements 111 arranged in a plurality of rows and a plurality of columns.

[0080] The signal processing circuit layer 120 includes circuits that perform signal processing on pixel signals output from the plurality of light receiving elements 111. As shown in Fig. 11, the signal processing circuit layer 120 includes an AD conversion circuit group 121, a processing circuit group 122, a control unit 200, and an input / output I / F 101.

[0081] The AD conversion circuit group 121 includes a plurality of AD conversion circuits. Each of the plurality of AD conversion circuits converts an analog signal output from the light receiving element 111 into a digital signal and outputs the digital signal to the processing circuit group 122. However, if the light receiving element 111 is capable of outputting a digital signal, the AD conversion circuit group does not need to be provided. For example, if the light receiving element 111 is a SPAD sensor that counts incident photons and outputs a digital signal, the AD conversion circuit group is not necessary.

[0082] The processing circuit group 122 includes six processing circuits PBA, PBB, PBC, PBD, PBE, and PBF arranged in series. The six processing circuits PBA, PBB, PBC, PBD, PBE, and PBF are signal processing circuits that sequentially perform various signal processing such as noise subtraction, shading correction, and gain adjustment. In addition, in order to process multiple signals input from the AD conversion circuit group 121 in parallel, multiple sets of the six processing blocks described above are arranged in parallel.

[0083] A selector SL is arranged downstream of the processing circuit PBA and upstream of the processing circuit PBB. The selector SL selectively outputs either an input signal to the processing circuit PBA or an output signal from the processing circuit PBA to the processing circuit PBB in response to a control signal from the control unit 200. This allows the selector SL to select whether or not to skip signal processing in the processing circuit PBA. Similarly, selectors SL are also arranged downstream of the processing circuits PBB, PBC, PBD, PBE, and PBF. These selectors SL can select whether or not to skip signal processing in the processing circuits PBB, PBC, PBD, PBE, and PBF.

[0084] When processing in each of the processing circuits PBA to PBF is skipped, operation of the corresponding processing circuit is unnecessary, and therefore operation is stopped by power-off or clock gating. In addition to controlling the entire semiconductor device 100, the control unit 200 has a function to determine which processing circuits to stop and a function to determine a stopping method for the processing circuits to be stopped. The operation stopping processing described in the first and second embodiments can also be applied to controlling the stopping of operation of the processing circuits in this embodiment.

[0085] 12 is a schematic diagram showing the change over time in the state of the processing circuits in the semiconductor device 100 according to this embodiment. FIG. 12 schematically shows the change over time in the state of the processing circuits PBA to PBF from time t21 to t22. Boxes representing processing circuits in an operating state are not hatched. Boxes representing processing circuits in a stopped state due to either power shutdown or clock gating are hatched in the same way as in FIGS. 4 and 10.

[0086] Although the processing circuits PBA to PBF in this embodiment have different functions, the recovery time from a power-off state for each of the processing circuits PBA to PBF is assumed to be the same. In this case, the recovery time from a power-off state for the entire processing circuits PBA to PBF depends on the number of processing circuits that are to be restored from the power-off state. In this embodiment, the time change in FIG. 12 will be explained assuming that the upper limit of the number of processing circuits that can be simultaneously restored from a power-off state is two.

[0087] At time t21, the processing circuits PBB, PBD, and PBE stop operating. Here, power is cut off to the processing circuits PBB and PBE, and clock gating is applied to the processing circuit PBD.

[0088] At time t22, the processing circuits PBA, PBB, and PBE stop operating. Here, power is cut off to the processing circuits PBB and PBE, and clock gating is applied to the processing circuit PBA.

[0089] As described above, in this embodiment, the method of stopping the processing circuits is controlled so that the number of processing circuits that enter a power-off state at each time is no more than 2. In this way, by controlling the method of stopping the processing circuits so that the number of processing circuits that simultaneously return from a power-off state does not exceed a predetermined allowable value, the effect of reducing power consumption by stopping the processing circuits is obtained, while the return from the power-off state is performed appropriately.

[0090] In this embodiment, the stopping method is selected so that the processing circuits PBB and PBE are maintained in a power-off state between time t21 and time t22. Clock gating is applied to the processing circuits PBA and PBD whose states change between time t21 and time t22. The effects of these are now described.

[0091] When the stopping method of a processing circuit transitions from power-off to clock gating, the voltage supplied to the processing circuit changes, causing an inrush current. Power is also consumed when this inrush current flows. Therefore, for processing circuits that remain in a stopped state for two periods, such as the processing circuits PBB and PBE of this embodiment, power consumption can be reduced by selecting a stopping method that maintains the power-off state if the original state is a power-off state. When the state of multiple processing circuits transitions in this way, the combination of processing circuits to be powered off may be determined taking into account the state before the transition.

[0092] As described above, according to this embodiment, a photoelectric conversion device is provided to which a method is applied that can more appropriately restore from a power-off state.

[0093] [Fourth embodiment] The semiconductor device 100 according to the above-described embodiment can be applied to various devices. Examples of such devices include digital still cameras, digital camcorders, camera heads, copiers, fax machines, mobile phones, vehicle-mounted cameras, observation satellites, and surveillance cameras. Fig. 13 shows a block diagram of a digital still camera as an example of such a device. Fig. 13 shows an example in which the semiconductor device 100 according to the above-described embodiment is applied to a digital still camera.

[0094] The device 70 shown in FIG. 13 includes a barrier 706, a lens 702, an aperture 704, and an imaging device 700 (an example of a semiconductor device or a photoelectric conversion device). The device 70 further includes a signal processing unit (processing device) 708, a timing generating unit 720, an overall control / calculation unit 718 (control unit), a memory unit 710 (storage device), a recording medium control I / F unit 716, a recording medium 714, and an external I / F unit 712. The semiconductor device 100 of the above-described embodiment may be included in the imaging device 700 or the signal processing unit 708. At least one of the barrier 706, the lens 702, and the aperture 704 is an optical device corresponding to the device. The barrier 706 protects the lens 702, and the lens 702 forms an optical image of a subject on the imaging device 700. The aperture 704 varies the amount of light passing through the lens 702. The imaging device 700 converts the optical image formed by the lens 702 into image data (image signals). The signal processing unit 708 performs various corrections, data compression, etc. on the imaging data output from the imaging device 700. The timing generation unit 720 outputs various timing signals to the imaging device 700 and the signal processing unit 708. The overall control / calculation unit 718 controls the entire digital still camera, and the memory unit 710 temporarily stores image data. The recording medium control I / F unit 716 is an interface for recording or reading image data to or from the recording medium 714, which is a removable recording medium such as a semiconductor memory for recording or reading imaging data. The external I / F unit 712 is an interface for communicating with an external computer, etc. Timing signals, etc., may be input from outside the device. The device 70 may also include a display device (monitor, electronic viewfinder, etc.) that displays information obtained by the imaging device 700. The device includes at least a photoelectric conversion device. The device 70 also includes at least one of an optical device, a control device, a processing device, a display device, a storage device, and a mechanical device that operates based on information obtained by the photoelectric conversion device. The mechanical device is a movable part (for example, a robot arm) that operates in response to a signal from the photoelectric conversion device.

[0095] Each pixel may include a plurality of photoelectric conversion units (a first photoelectric conversion unit and a second photoelectric conversion unit). The signal processing unit 708 may be configured to process a pixel signal based on the charge generated in the first photoelectric conversion unit and a pixel signal based on the charge generated in the second photoelectric conversion unit, and acquire information about the distance from the image capturing device 700 to the subject.

[0096] [Fifth embodiment] 14(a) and 14(b) are block diagrams of devices related to an in-vehicle camera according to this embodiment. FIGS. 14(a) and 14(b) show an example in which the semiconductor device 100 according to the above-described embodiment is applied to a moving body such as a vehicle. The device 80 includes an imaging device 800 (an example of the semiconductor device 100 or a photoelectric conversion device) and a signal processing device (processing device) that processes signals from the imaging device 800. The device 80 includes an image processing unit 801 that performs image processing on multiple pieces of image data acquired by the imaging device 800, and a parallax calculation unit 802 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the device 80. The information processing device 30 according to the above-described embodiment may be included in the imaging device 800 or the image processing unit 801. The device 80 also includes a distance measurement unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax calculation unit 802 and the distance measurement unit 803 are an example of a distance information acquisition unit that acquires distance information to an object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 804 may determine the possibility of a collision using any of this distance information. The distance information acquisition unit may be realized by dedicated hardware or a software module. Furthermore, it may be realized by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a combination thereof.

[0097] The device 80 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The device 80 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 804. The device 80 is also connected to an alarm device 830 that issues an alarm to the driver based on the determination result of the collision determination unit 804. For example, if the determination result of the collision determination unit 804 indicates a high collision possibility, the control ECU 820 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel. The device 80 functions as a control means for controlling the operation of controlling the vehicle as described above.

[0098] In this embodiment, the device 80 captures images of the surroundings of the vehicle, for example, the front or rear. Fig. 14(b) shows the device when capturing an image of the area in front of the vehicle (image capturing range 850). A vehicle information acquisition device 810, which serves as an image capturing control means, sends an instruction to the device 80 or the image capturing device 800 to perform an image capturing operation. This configuration can further improve the accuracy of distance measurement.

[0099] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from a lane, etc. Furthermore, the present invention is not limited to vehicles such as automobiles, but can be applied to moving objects (moving devices) such as ships, aircraft, artificial satellites, industrial robots, and consumer robots. In addition, the present invention can be applied to a wide range of devices that use object recognition or biometric recognition, such as intelligent transport systems (ITS) and surveillance systems, without being limited to moving objects.

[0100] [Modified embodiment] The present invention is not limited to the above-described embodiments and can be modified in various ways. For example, an example in which part of the configuration of one embodiment is added to another embodiment, or an example in which part of the configuration of one embodiment is replaced with part of the configuration of another embodiment, is also an embodiment of the present invention.

[0101] The disclosure of this specification includes the complement of the concepts described in this specification. In other words, if this specification states, for example, that "A is B" (A=B), then this specification is deemed to disclose or suggest that "A is not B" even if the statement that "A is not B" (A≠B) is omitted. This is because when "A is B," it is assumed that the case where "A is not B" is taken into consideration.

[0102] The disclosure of this specification includes the following configurations. (Configuration 1) a plurality of processing circuits; a stop circuit determination unit that determines a first processing circuit to be stopped from among the plurality of processing circuits; a stop method determination unit that determines a method for stopping the operation of the first processing circuit to be either a first stop method that includes power shutdown or a second stop method that does not include power shutdown, based on circuit information of the first processing circuit and a second processing circuit that is different from the first processing circuit among the plurality of processing circuits; and The stop method determination unit determines the stop method so that the load impedances of the processing circuits that are simultaneously stopped by the first stop method, as viewed from the power supply wiring side, are equal to or greater than a predetermined impedance. A semiconductor device characterized by: (Configuration 2) The circuit information includes information indicating whether the processing circuit corresponding to the circuit information is already in the stopped state by the first stopping method. 2. The semiconductor device according to configuration 1. (Configuration 3) The circuit information includes information indicating the layout of a circuit including a processing circuit corresponding to the circuit information. 3. The semiconductor device according to configuration 1 or 2. (Configuration 4) The circuit information further includes information indicating a positional relationship between a processing circuit corresponding to the circuit information and a power supply terminal on a substrate on which the plurality of processing circuits are formed. 4. The semiconductor device according to configuration 3. (Configuration 5) The stop method determination unit determines the stop method such that the operation of the processing circuit closest to the power supply terminal is stopped by the first stop method. 5. The semiconductor device according to configuration 4. (Configuration 6) The stop circuit determination unit determines the stop method such that a plurality of processing circuits that are stopped by the first stop method among the plurality of processing circuits are not adjacent to each other in a plan view of a board on which the plurality of processing circuits are arranged. 6. The semiconductor device according to any one of configurations 3 to 5. (Configuration 7) a storage unit that stores the circuit information of each of the plurality of processing circuits; The stop method determination unit acquires the circuit information from the storage unit. 7. The semiconductor device according to any one of configurations 1 to 6. (Configuration 8) The shutdown method determination unit acquires the circuit information from a device external to the semiconductor device. 7. The semiconductor device according to any one of configurations 1 to 6. (Configuration 9) The recovery time of the processing circuit stopped by the second stopping method is shorter than the recovery time of the processing circuit stopped by the first stopping method. 9. The semiconductor device according to any one of configurations 1 to 8. (Configuration 10) The power consumption of the processing circuit stopped by the second stopping method is greater than the power consumption of the processing circuit stopped by the first stopping method. 10. The semiconductor device according to any one of configurations 1 to 9. (Configuration 11) The second stopping method includes clock gating. 11. The semiconductor device according to any one of configurations 1 to 10. (Configuration 12) The plurality of processing circuits processes pixel signals based on outputs of the plurality of photoelectric conversion elements. 12. The semiconductor device according to any one of configurations 1 to 11. (Configuration 13) The plurality of processing circuits have the same function 13. The semiconductor device according to configuration 12. (Configuration 14) the region in which the plurality of photoelectric conversion elements are arranged is divided into a plurality of regions, A pixel signal generated in each of the plurality of regions is processed by a corresponding one of the plurality of processing circuits. 14. The semiconductor device according to configuration 12 or 13. (Configuration 15) The stop circuit determination unit determines, as the first processing circuit, a processing circuit other than a processing circuit corresponding to an area determined based on the pixel signal, from among the plurality of processing circuits. 15. The semiconductor device according to configuration 14. (Configuration 16) The stop circuit determination unit determines, as the first processing circuit, a processing circuit other than a processing circuit corresponding to an area in which a subject is detected based on the pixel signal, from among the plurality of processing circuits. 16. The semiconductor device according to structure 14 or 15. (Configuration 17) the plurality of processing circuits process the pixel signals in series; the plurality of processing circuits are configured to be able to skip operations of some of the processing circuits; The stop circuit determination unit determines, from among the plurality of processing circuits, a processing circuit whose operation is to be skipped as the first processing circuit. 13. The semiconductor device according to configuration 12. (Configuration 18) a plurality of processing circuits; a stop circuit determination unit that determines a first processing circuit to be stopped from among the plurality of processing circuits; a stop method determination unit that determines a method for stopping the operation of the first processing circuit to be either a first stop method that includes power shutdown or a second stop method that does not include power shutdown, based on circuit information of the first processing circuit and a second processing circuit that is different from the first processing circuit among the plurality of processing circuits; and The stop method determination unit determines the stop method such that the number of processing circuits that are stopped at the same time by the first stop method among the plurality of processing circuits is equal to or less than a threshold. A semiconductor device characterized by: (Configuration 19) a photoelectric conversion device including the semiconductor device according to any one of structures 1 to 18; an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device. (Configuration 20) 20. The device according to claim 19, wherein the processing device acquires distance information from the photoelectric conversion device to the subject.

[0103] The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program. It can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0104] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0105] 100 Semiconductor device 202 Stop circuit determining section 203 Stopping method determining section P processing circuit

Claims

1. a plurality of processing circuits; a stop circuit determination unit that determines a first processing circuit to be stopped from among the plurality of processing circuits; a stop method determination unit that determines a method for stopping the operation of the first processing circuit to be either a first stop method that includes power shutdown or a second stop method that does not include power shutdown, based on circuit information of the first processing circuit and a second processing circuit that is different from the first processing circuit among the plurality of processing circuits; and The stop method determination unit determines the stop method so that the load impedances of the processing circuits that are stopped at the same time by the first stop method, as viewed from the power supply wiring side, are equal to or greater than a predetermined impedance. A semiconductor device characterized by:

2. The circuit information includes information indicating whether the processing circuit corresponding to the circuit information is already in the stopped state by the first stopping method.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

3. The circuit information includes information indicating the layout of a circuit including a processing circuit corresponding to the circuit information.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

4. The circuit information further includes information indicating a positional relationship between a processing circuit corresponding to the circuit information and a power supply terminal on a substrate on which the plurality of processing circuits are formed.

4. The semiconductor device according to claim 3.

5. The stop method determination unit determines the stop method such that the operation of the processing circuit closest to the power supply terminal is stopped by the first stop method.

5. The semiconductor device according to claim 4.

6. The stop circuit determination unit determines the stop method so that a plurality of processing circuits that are stopped by the first stop method among the plurality of processing circuits are not adjacent to each other in a plan view of a board on which the plurality of processing circuits are arranged.

4. The semiconductor device according to claim 3.

7. a storage unit that stores the circuit information of each of the plurality of processing circuits; The stop method determination unit acquires the circuit information from the storage unit.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

8. The shutdown method determination unit acquires the circuit information from a device external to the semiconductor device.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

9. The recovery time of the processing circuit stopped by the second stopping method is shorter than the recovery time of the processing circuit stopped by the first stopping method.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

10. The power consumption of the processing circuit stopped by the second stopping method is greater than the power consumption of the processing circuit stopped by the first stopping method.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

11. The second stopping method includes clock gating.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

12. The plurality of processing circuits processes pixel signals based on outputs of the plurality of photoelectric conversion elements.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

13. The plurality of processing circuits have the same function 13. The semiconductor device according to claim 12.

14. the region in which the plurality of photoelectric conversion elements are arranged is divided into a plurality of regions, A pixel signal generated in each of the plurality of regions is processed by a corresponding one of the plurality of processing circuits.

13. The semiconductor device according to claim 12.

15. The stop circuit determination unit determines, as the first processing circuit, a processing circuit other than a processing circuit corresponding to an area determined based on the pixel signal, from among the plurality of processing circuits.

15. The semiconductor device according to claim 14.

16. The stop circuit determination unit determines, as the first processing circuit, a processing circuit other than a processing circuit corresponding to an area in which a subject is detected based on the pixel signal, from among the plurality of processing circuits.

15. The semiconductor device according to claim 14.

17. the plurality of processing circuits process the pixel signals in series; the plurality of processing circuits are configured to be able to skip operations of some of the processing circuits; The stop circuit determination unit determines, as the first processing circuit, a processing circuit whose operation is to be skipped among the plurality of processing circuits.

13. The semiconductor device according to claim 12.

18. a plurality of processing circuits; a stop circuit determination unit that determines a first processing circuit to be stopped from among the plurality of processing circuits; a stop method determination unit that determines a method for stopping the operation of the first processing circuit to be either a first stop method that includes power shutdown or a second stop method that does not include power shutdown, based on circuit information of the first processing circuit and a second processing circuit that is different from the first processing circuit among the plurality of processing circuits; and The stop method determination unit determines the stop method such that the number of processing circuits that are stopped at the same time by the first stop method among the plurality of processing circuits is equal to or less than a threshold. A semiconductor device characterized by:

19. A photoelectric conversion device including the semiconductor device according to any one of claims 1 to 18; an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device.

20. 20. The device according to claim 19, wherein the processing device acquires distance information from the photoelectric conversion device to a subject.

Images