Semiconductor device

Abstract

To provide a semiconductor device with which a length of a wire can be shortened.SOLUTION: A semiconductor device A1 comprises: a first lead 1 having a first face 101 which is directed to a first side z1 in a first direction z; a semiconductor element 4 which is loaded on the first face 101 and includes a plurality of electrodes 41; a second lead 2 which is conducted to the semiconductor element 4; and a sealing resin 7 which covers at least a portion of each of the first lead 1 and the second lead 2, and the semiconductor element 4. The semiconductor device further comprises: a conductive layer 52 including an insulation layer 51 and one or more wiring parts 521; a first wire 61 which is connected to the electrodes 41 and the wiring parts 521; and a second wire 62 which is connected to the second lead 2. The first wire 61, the wiring parts 521 and the second wire 62 are included in conduction paths of the electrodes 41 and the second lead 2.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses an example of a conventional semiconductor device. The semiconductor device disclosed in this document includes a die pad, a semiconductor element, multiple leads, multiple wires, and a resin member. The semiconductor element is mounted on the die pad. The semiconductor element is individually connected to the multiple leads via multiple wires. An encapsulating resin covers the semiconductor element, the multiple wires, and portions of the die pad and the multiple leads. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-146270

[0004] [overview] The semiconductor element and the leads may be arranged in various ways. Depending on the arrangement of the semiconductor element and the leads, the length of the wires may become long. The longer the wires, the more likely they are to interfere with adjacent wires, semiconductor elements, etc.

[0005] The present disclosure has been made in light of the above circumstances, and an object of the present disclosure is to provide a semiconductor device that allows the length of wires to be shortened.

[0006] The semiconductor device provided by the present disclosure comprises a first lead having a first surface facing a first side in a first direction, a semiconductor element mounted on the first surface and having a plurality of electrodes, a second lead conductive to the semiconductor element, and a sealing resin covering at least a portion of the first lead and the second lead and the semiconductor element, and further comprises a conductive layer including an insulating layer and one or more wiring portions, a first wire connected to the electrode and the wiring portion, and a second wire connected to the second lead, and the first wire, the wiring portion, and the second wire are included in the conduction path between the electrode and the second lead.

[0007] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a bottom view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. [Figure 5] FIG. 5 is a cross-sectional view taken along line VV in FIG. [Figure 6] FIG. 6 is a plan view showing a first modified example of the semiconductor device according to the first embodiment of the present disclosure. [Figure 7] FIG. 7 is a plan view showing a second modified example of the semiconductor device according to the first embodiment of the present disclosure. [Figure 8] FIG. 8 is a plan view showing a semiconductor device according to the second embodiment of the present disclosure. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. [Figure 10] FIG. 10 is a plan view showing a semiconductor device according to the second embodiment of the present disclosure. [Figure 11]FIG. 11 is a partially enlarged cross-sectional view taken along line XI-XI in FIG.

[0009] [Detailed explanation] Preferred embodiments of the present disclosure will now be described in detail with reference to the drawings.

[0010] The terms "first," "second," "third," etc. in this disclosure are used for identification purposes only and are not intended to impose any ranking on their objects.

[0011] In this disclosure, unless otherwise specified, the terms "a certain object A is formed on an object B" and "a certain object A is formed on an object B" include "a certain object A is formed directly on an object B" and "a certain object A is formed on an object B with another object interposed between the objects A and B." Similarly, the terms "a certain object A is disposed on an object B" and "a certain object A is disposed on an object B" include "a certain object A is disposed directly on an object B" and "a certain object A is disposed on an object B with another object interposed between the objects A and B," unless otherwise specified. Similarly, the term "a certain object A is located on an object B" includes "a certain object A is located on an object B in contact with the object B" and "a certain object A is located on an object B with another object interposed between the objects A and B," unless otherwise specified. Furthermore, unless otherwise specified, the phrase "an object A overlaps an object B when viewed in a certain direction" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." Furthermore, in this disclosure, "a surface A faces (one side or the other side of) direction B" is not limited to the case where the angle of surface A with respect to direction B is 90°, but also includes the case where surface A is tilted with respect to direction B.

[0012] 1 to 5 show a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device A1 of this embodiment includes a first lead 1, a plurality of second leads 2, a semiconductor element 4, a plurality of relay boards 5, a plurality of first wires 61, a plurality of second wires 62, and a sealing resin 7. The electrical function and package structure, such as the external shape, of the semiconductor device A1 are not limited in any way. In the illustrated example, the semiconductor device A1 may be, for example, a QFN (Quad Flat Non-leaded package). The size of the semiconductor device A1 as viewed in the first direction z is not limited in any way, and the size in the second direction x or the third direction y may be, for example, 6 mm or more and 10 mm or less.

[0013] Fig. 1 is a plan view showing the semiconductor device A1. Fig. 2 is a bottom view showing the semiconductor device A1. Fig. 3 is a cross-sectional view taken along line III-III in Fig. 1. Fig. 4 is a cross-sectional view taken along line IV-IV in Fig. 1. Fig. 5 is a cross-sectional view taken along line VV in Fig. 1.

[0014] In these figures, the first direction of the present disclosure is defined as the first direction z. One side of the first direction z is referred to as the first side z1, and the other side as the second side z2. Furthermore, a direction perpendicular to the first direction z is defined as the second direction x. One side of the second direction x is referred to as the first side x1, and the other side as the second side x2. Furthermore, a direction perpendicular to the first direction z and the second direction x is defined as the third direction y. One side of the third direction y is referred to as the first side y1, and the other side as the second side y2.

[0015] The sealing resin 7 covers at least a portion of each of the first lead 1 and the second lead 2 and the semiconductor element 4. The sealing resin 7 may contain, for example, an epoxy resin, and may further contain a plurality of granular fillers (not shown).

[0016] The sealing resin 7 may have a first resin surface 71, a second resin surface 72, a third resin surface 73, a fourth resin surface 74, a fifth resin surface 75, and a sixth resin surface 76.

[0017] The resin first surface 71 is a surface facing the first side z1 in the first direction z and may be a flat surface. The resin second surface 72 is a surface facing the second side x2 in the first direction z and may be a flat surface. The resin third surface 73 is a surface facing the first side x1 in the second direction x and may be a flat surface. The resin fourth surface 74 is a surface facing the second side x2 in the second direction x and may be a flat surface. The resin fifth surface 75 is a surface facing the first side y1 in the third direction y and may be a flat surface. The resin sixth surface 76 is a surface facing the second side y2 in the third direction y and may be a flat surface.

[0018] The first lead 1 includes a metal such as Cu (copper), Ni (nickel), or Fe (iron), or an alloy thereof. The first lead 1 has a first surface 101 and a second surface 102. The first surface 101 faces a first side z1 in the first direction z and may be a flat surface. The second surface 102 faces a second side z2 in the first direction z and may be a flat surface. The second surface 102 may be exposed from the resin second surface 72. The size of the first lead 1 as viewed in the first direction z is not limited in any way, and the size in the second direction x or the third direction y may be 3 mm or more and 7 mm or less, for example.

[0019] The shape of the first surface 101 is not limited in any way. In the illustrated example, the first surface 101 may have a first edge 11, a second edge 12, a third edge 13, and a fourth edge 14. The first edge 11 is located on a first side x1 in the second direction x and extends along the third direction y. The second edge 12 is located on a second side x2 in the second direction x and extends along the third direction y. The first edge 11 and the second edge 12 are spaced apart from each other in the second direction x. The third edge 13 is located on a first side y1 in the third direction y and extends along the second direction x, and the fourth edge 14 is located on a second side y2 in the third direction y and extends along the second direction x. The third edge 13 and the fourth edge 14 are spaced apart from each other in the third direction y. The third edge 13 and the fourth edge 14 are respectively connected to both ends of the first edge 11 and the second edge 12. Such a first surface 101 may have a rectangular shape when viewed in the first direction z.

[0020] A connecting lead (not shown) may be connected to the first lead 1. The connecting lead may extend from the first lead 1 toward the outside of the sealing resin 7 and may support the first lead 1 during the manufacture of the semiconductor device A1.

[0021] The multiple second leads 2 are spaced apart from the first leads 1 when viewed in the first direction z. The arrangement of the multiple second leads 2 is not limited in any way. In the illustrated example, the multiple second leads 2 may include multiple second leads 2 arranged in the third direction y between the first edge 11 and the resin third surface 73. The multiple second leads 2 may also include multiple second leads 2 arranged in the third direction y between the second edge 12 and the resin fourth surface 74. The multiple second leads 2 may also include multiple second leads 2 arranged in the second direction x between the third edge 13 and the resin fifth surface 75. The multiple second leads 2 may also include multiple second leads 2 arranged in the second direction x between the fourth edge 14 and the resin sixth surface 76.

[0022] The second lead 2 may include a pad portion 21 and a terminal portion 22. The pad portion 21 may face a first side z1 in the first direction z and may be covered with the sealing resin 7. The terminal portion 22 is exposed from the sealing resin 7 and may be used as a terminal surface when mounting the semiconductor device A1. In the illustrated example, the terminal portion 22 faces a second side z2 in the first direction z and is exposed from the resin second surface 72.

[0023] The semiconductor element 4 is a component that performs the main electrical function of the semiconductor device A1. In this embodiment, the number of semiconductor elements 4 is one, but the number of semiconductor elements 4 is not limited in any way. The semiconductor device of the present disclosure may be configured to include multiple semiconductor elements 4. The size of the semiconductor element 4 as viewed in the first direction z is not limited in any way, and the size in the second direction x or the third direction y may be, for example, 1 mm or more and 5 mm or less.

[0024] There is no limitation on the specific configuration of the semiconductor element 4. The semiconductor element 4 may be, for example, a circuit element collectively referred to as an LSI (Large Scale Integration) or an IC (Integrated Circuit), or may be a functional element such as a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). The semiconductor element 4 may have an element body 40 and a plurality of electrodes 41.

[0025] The element body 40 includes a semiconductor material such as Si (silicon). In the illustrated example, the element body 40 has a rectangular shape when viewed in the first direction z. The element body 40 may include a circuit (not shown) that realizes the electrical function that the semiconductor element 4 should perform.

[0026] The multiple electrodes 41 are located on a first side z1 in the first direction z of the element body 40. The size, shape, arrangement, etc. of the multiple electrodes 41 are not limited in any way. In the illustrated example, the multiple electrodes 41 are arranged along the four sides of the element body 40.

[0027] The semiconductor element 4 is mounted on the first surface 101. In the illustrated example, the semiconductor element 4 may be bonded to the first surface 101 by a bonding material 49. The bonding material 49 may be, for example, a conductive bonding material such as solder or Ag (silver) paste, or an insulating bonding material.

[0028] The relay board 5 is spaced apart from the semiconductor element 4. The semiconductor device A1 may include only one relay board 5, or may include multiple relay boards 5. The relay board 5 includes an insulating layer 51 and a conductive layer 52.

[0029] The insulating layer 51 includes a material exhibiting electrical insulation properties, such as a semiconductor material such as silicon (Si), a resin, or a ceramic. In the illustrated example, the insulating layer 51 may include silicon (Si). The size of the insulating layer 51 is not particularly limited, and the thickness in the first direction z may be, for example, 100 μm or more and 400 μm or less.

[0030] The conductive layer 52 is disposed on the insulating layer 51. The conductive layer 52 may include a metal such as Al (aluminum), Ag (silver), Cu (copper), Au (gold), Pd (palladium), or an alloy thereof. In the illustrated example, the conductive layer 52 may be laminated on a surface of the insulating layer 51 facing the first side z1 in the first direction z.

[0031] The conductive layer 52 includes one or more wiring portions 521. The wiring portion 521 may be included in the conductive path between the electrode 41 and the second lead 2. In the illustrated example, the conductive layer 52 may include a plurality of wiring portions 521.

[0032] The insulating layer 51 may have a groove 511. The groove 511 is, for example, a portion recessed toward the second side z2 in the first direction z, and crosses the insulating layer 51. The insulating layer 51 can be cut by folding or the like along the groove 511.

[0033] In the illustrated example, the semiconductor device A1 includes three relay boards 5. Two relay boards 5 are arranged along the second edge 12. In these relay boards 5, a plurality of wiring portions 521 are arranged along the third direction y. In these relay boards 5, a groove portion 511 extends along the second direction x. Two wiring portions 521 are located on either side of the groove portion 511. Two wiring portions 521 are located between two groove portions 511.

[0034] In the relay board 5 disposed along the fourth edge 14, a plurality of wiring portions 521 are arranged in the second direction x. In this relay board 5, the groove portions 511 extend in the third direction y.

[0035] The relay members 5 located along both the second edge 12 and the fourth edge 14 overlap with another relay member 5 when viewed in the second direction x, and overlap with another relay member 5 when viewed in the third direction y. The relay members 5 located along both the second edge 12 and the fourth edge 14 do not need to overlap with the semiconductor element 4 when viewed in the second direction x, and do not need to overlap with the semiconductor element 4 when viewed in the third direction y.

[0036] The multiple relay boards 5 of this embodiment may be mounted on the first surface 101. The relay boards 5 may be bonded to the first surface 101 via, for example, a bonding layer 59. The bonding layer 59 may be a conductive bonding material, an insulating bonding material, or the like.

[0037] The plurality of first wires 61 may be included in the conductive path between the electrode 41 and the second lead 2. The first wires 61 include a metal such as Au (gold), Cu (copper), or Al (aluminum), or an alloy thereof. The diameter of the first wires 61 is not particularly limited and may be, for example, 10 μm or more and 30 μm or less. The first wires 61 are connected to the electrode 41 and the wiring portion 521.

[0038] The plurality of second wires 62 may be included in the conductive path between the electrode 41 and the second lead 2. The second wires 62 include a metal such as Au (gold), Cu (copper), or Al (aluminum), or an alloy thereof. The diameter of the second wires 62 is not limited and may be, for example, 10 μm or more and 30 μm or less. The second wires 62 are connected to the wiring portion 521 and the pad portion 21.

[0039] The conductive path between the plurality of electrodes 41 and the second lead 2 included in the semiconductor device A1 includes a configuration made up of a first wire 61, one wiring portion 521, and a second wire 62.

[0040] The third wire 63 may be included in the conduction path between the electrode 41 and the second lead 2. The third wire 63 includes a metal such as Au (gold), Cu (copper), or Al (aluminum), or an alloy thereof. The wire diameter of the third wire 63 is not limited and may be, for example, 10 μm or more and 30 μm or less. The third wire 63 is connected to two wiring portions 521. For example, the first wire 61 is connected to one wiring portion 521, and the second wire 62 is connected to the other wiring portion 521. In this case, the conduction path between the electrode 41 and the second lead 2 includes the first wire 61, one wiring portion 521, the third wire 63, the other wiring portion 521, and the second wire 62.

[0041] The fourth wire 64 may be included in the conduction path between the electrode 41 and the second lead 2. The fourth wire 64 includes a metal such as Au (gold), Cu (copper), or Al (aluminum), or an alloy thereof. The wire diameter of the fourth wire 64 is not limited and may be, for example, 10 μm or more and 30 μm or less. The fourth wire 64 is connected to two wiring portions 521. The third wire 63 is connected to one wiring portion 521, and the fourth wire 64 is connected to the other wiring portion 521. In this case, the conduction path between the electrode 41 and the second lead 2 includes the first wire 61, one wiring portion 521, the third wire 63, the other wiring portion 521, the fourth wire 64, the other wiring portion 521, and the second wire 62.

[0042] Next, the operation of the semiconductor device A1 will be described.

[0043] According to this embodiment, the conduction path between the electrode 41 and the second lead 2 includes the first wire 61, the wiring portion 521, and the second wire 62. This allows the lengths of the first wire 61 and the second wire 62 to be shorter than when the electrode 41 and the second lead 2 are connected by a single first wire 61 or a single second wire 62. This reduces problems caused by the length of the first wire 61, the second wire 62, etc. One example of such a problem is that when a resin material is injected to form the sealing resin 7, the flow of the resin material causes a long wire to bend and come into contact with an adjacent wire. According to this embodiment, such wire contact can be suppressed.

[0044] The relay board 5 is mounted on the first surface 101 together with the semiconductor element 4. This makes it possible to set various conductive paths between the multiple second leads 2 and the multiple electrodes 41 using the relay board 5, without changing the semiconductor element 4 and the first lead 1. Therefore, various semiconductor elements 4 can be used without changing the external dimensions of the semiconductor device A1, the arrangement of the multiple second leads 2, etc.

[0045] If the conduction path between the electrode 41 and the second lead 2 further includes a third wire 63, the length of the wire can be further shortened, or the distance between the electrode 41 and the second lead 2 can be set greater. If the conduction path between the electrode 41 and the second lead 2 further includes a fourth wire 64, the distance between the electrode 41 and the second lead 2 can be set greater. As can be seen from these embodiments, there is no limitation on the number of wiring portions 521 and wires included in the conduction path between one electrode 41 and 2.

[0046] 6 to 11 show other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above embodiment are given the same reference numerals. Furthermore, the configurations of the various parts in each of the modified examples and each of the embodiments can be combined with each other as appropriate within the scope of not causing technical contradictions.

[0047] 6 shows a first modified example of the semiconductor device A1. The semiconductor device A11 of this modified example includes three relay boards 5. One relay board 5 is located between the semiconductor element 4 and the second edge 12 and overlaps with the semiconductor element 4 when viewed in the second direction x. Another relay board 5 is located between the semiconductor element 4 and the fourth edge 14 and overlaps with the semiconductor element 4 when viewed in the third direction y. Yet another relay board 5 is located between the semiconductor element 4 and the third edge 13 and overlaps with the semiconductor element 4 when viewed in the third direction y.

[0048] This modification can shorten the lengths of the first wires 61 and the second wires 62. This modification can shorten the lengths of the multiple first wires 61 and second wires 62 that are respectively arranged on the second side x2 in the second direction x, the first side y1 in the third direction y, and the second side y2 in the third direction y from the semiconductor element 4.

[0049] 7 shows a second modified example of the semiconductor device A1. The semiconductor device A12 of this modified example includes four relay boards 5. One relay board 5 is located between the semiconductor element 4 and the first edge 11 and overlaps with the semiconductor element 4 when viewed in the second direction x. Another relay board 5 is located between the semiconductor element 4 and the second edge 12 and overlaps with the semiconductor element 4 when viewed in the second direction x. Another relay board 5 is located between the semiconductor element 4 and the fourth edge 14 and overlaps with the semiconductor element 4 when viewed in the third direction y. Another relay board 5 is located between the semiconductor element 4 and the third edge 13 and overlaps with the semiconductor element 4 when viewed in the third direction y.

[0050] This modification can shorten the lengths of the first wires 61 and the second wires 62. This modification can shorten the lengths of the multiple first wires 61 and second wires 62 arranged on the first side x1 and the second side x2 in the second direction x and the first side y1 and the second side y2 in the third direction y from the semiconductor element 4, respectively.

[0051] 8 and 9 show a semiconductor device according to a second embodiment of the present disclosure. The semiconductor device A2 of this embodiment may further include a third lead 3.

[0052] The third lead 3 includes a metal such as Cu (copper), Ni (nickel), or Fe (iron), or an alloy thereof. The third lead 3 has a third surface 301 and a fourth surface 302. The third surface 301 faces a first side z1 in the first direction z and may be a flat surface. The fourth surface 302 faces a second side z2 in the first direction z and may be a flat surface. The fourth surface 302 may be exposed from the resin second surface 72. The third lead 3 may be disposed, for example, on the second side x2 in the second direction x relative to the first lead 1, and the specific arrangement is not limited thereto. The third lead 3 is spaced apart from the first lead 1.

[0053] In this embodiment, one relay board 5 is mounted on the first surface 101, and two relay boards 5 are mounted on the third surface 303.

[0054] This embodiment can reduce the lengths of the first wire 61 and the second wire 62. As can be understood from this embodiment, the relay board 5 is not limited to being mounted on the first surface 101 together with the semiconductor element 4, and may be mounted on another member other than the first lead 1, such as the third lead 3. Alternatively, the relay board 5 may be configured to be supported by the sealing resin 7 without being mounted on another member.

[0055] 10 and 11 show a semiconductor device according to a third embodiment of the present disclosure. In the semiconductor device A3 of this embodiment, the configuration of one relay board 5 is different from that of the relay board 5 of the above-described embodiments.

[0056] Of the three relay members 5, the relay member 5 located along the second edge 12 and on the first side y1 in the third direction y has a conductive layer 52 including a first layer 52A and a second layer 52B, and an insulating layer 51 including a first insulating layer 51A and a second insulating layer 51B.

[0057] The first insulating layer 51A and the second insulating layer 51B are stacked in the first direction z. The first insulating layer 51A is located on a first side z1 in the first direction z with respect to the second insulating layer 51B.

[0058] The first layer 52A is located on a first side z1 in the first direction z of the first insulating layer 51A. The second layer 52B is located between the first insulating layer 51A and the second insulating layer 51B.

[0059] The first layer 52A includes a plurality of first wiring portions 521 A. The second layer 52B includes a plurality of second wiring portions 521 B. The first wiring portions 521A and the second wiring portions 521B may intersect with each other when viewed in the first direction z.

[0060] The first layer 52A may further include a plurality of first pad portions 522A. The relay board 5 may further include a plurality of conductive connecting portions 529.

[0061] The conductive interconnection portion 529 may penetrate the first insulating layer 51A in the first direction z. The conductive interconnection portion 529 provides electrical continuity between the first pad portion 522A and the second wiring portion 521B.

[0062] With this configuration, in the relay board 5, the first wire 61 and the second wire 62 are electrically connected via the first wiring portion 521A. The first wire 61 and the second wire 62 are also electrically connected via the first pad portion 522A, the conductive connecting portion 529, the first pad portion 522A, the conductive connecting portion 529, and the conductive layer 522. In other words, the conductive path between a certain electrode 41 and the second lead 2 and the conductive path between another electrode 41 and the second lead 2 intersect with each other when viewed in the first direction z.

[0063] This embodiment can shorten the lengths of the first wire 61 and the second wire 62. The relay member 5, which is located along the second edge 12 and on the first side y1 in the third direction y, can change the arrangement order in the third direction y of the plurality of electrodes 41 and the plurality of second leads 2 that are electrically connected to each other. This makes it possible to produce different semiconductor devices A3 in which the arrangement of the plurality of second leads 2 is different, using semiconductor elements 4 with the same configuration.

[0064] The semiconductor device according to the present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the semiconductor device according to the present disclosure can be freely modified in various ways.

[0065] [Appendix 1] a first lead (1) having a first surface (101) facing a first side (z1) in a first direction (z); a semiconductor element (4) mounted on the first surface (101) and having a plurality of electrodes (41); a second lead (2) electrically connected to the semiconductor element (4); a sealing resin (7) that covers at least a portion of each of the first lead (1) and the second lead (2) and the semiconductor element (4), an insulating layer (51) and a conductive layer (52) including one or more wiring portions (521); a first wire (61) connected to the electrode (41) and the wiring portion (521); and a second wire (62) connected to the second lead (2), The semiconductor device (A1) includes the first wire (61), the wiring portion (521), and the second wire (62) in a conduction path between the electrode (41) and the second lead (2). [Appendix 2] The semiconductor device (A1) according to appendix 1, wherein the second wire (62) is connected to the wiring portion (521) to which the first wire (61) is connected. [Appendix 3] The semiconductor device (A1) according to appendix 1 or 2, wherein the relay board (5) is mounted on the first surface (101). [Appendix 4] 4. The semiconductor device (A1) according to any one of appendices 1 to 3, wherein the conductive layer (52) includes a plurality of the wiring portions (521). [Appendix 5] The insulating layer (51) has a groove (511), The semiconductor device (A1) according to appendix 4, wherein the two wiring portions (521) are arranged with the groove portion (511) therebetween. [Appendix 6] 6. The semiconductor device (A1) according to any one of appendices 1 to 5, comprising a plurality of the relay boards (5). [Appendix 7] The first surface (101) is a first edge (11) located on a first side (x1) in a second direction (x) intersecting the first direction (z) and extending along a third direction (y) intersecting the first direction (z) and the second direction (x); a second edge (12) located on the second side (x2) in the second direction (x) and extending along the third direction (y); a third edge (13) located on the first side (y1) in the third direction (y) and extending along the second direction (x); and A semiconductor device (A1) according to any one of appendices 1 to 6, having a fourth edge (14) located on the second side (y2) in the third direction (y) and extending along the second direction (x). [Appendix 8] The semiconductor element (4) is positioned biased toward the first side (x1) in the second direction (x), 8. The semiconductor device (A1) according to claim 7, wherein the relay board (5) is located between the semiconductor element (4) and the second edge (12). [Appendix 9] The semiconductor device (A1) described in Appendix 8 further comprises a relay member (5) arranged in a third direction (y) and spaced apart from the relay member (5) located between the semiconductor element (4) and the second edge (12). [Appendix 10] the semiconductor element (4) is positioned biased toward the first side (y1) in the third direction (y), 10. The semiconductor device (A1) according to any one of appendices 7 to 9, wherein the relay board (5) is located between the semiconductor element (4) and the terminal portion (22). [Appendix 11] The second wire (62) 1 further includes a third wire (63) connected to the wiring portion (521) to which the first wire (61) connected to the wiring portion (521) and another wiring portion (521) is connected, The semiconductor device (A1) according to any one of appendices 1 to 10, wherein the conductive path further includes the third wire. [Appendix 12] the third wire (63) is connected to a wiring portion (521) different from the wiring portion (521) to which the second wire (62) is connected, The device further includes a fourth wire (64) connected to the wiring portion (521) to which the second wire (62) is connected and the wiring portion (521) to which the third wire (63) is connected, The semiconductor device (A1) according to Appendix 11, wherein the conductive path further includes the fourth wire (64). [Appendix 13] A semiconductor device (A1) described in any one of Appendices 1 to 10, wherein the second wire (62) is connected to a wiring portion (521) different from the wiring portion (521) to which the first wire (61) is connected. [Appendix 14] The semiconductor device (A1) according to any one of appendices 1 to 13, comprising two relay boards (5) arranged on both sides of the semiconductor element (4) in the second direction (x). [Appendix 15] The semiconductor device (A1) according to any one of appendices 1 to 14, comprising two relay members (5) arranged on both sides of the semiconductor element (4) in the third direction (y). [Appendix 16] A semiconductor device (A3) according to any one of Appendices 1 to 15, wherein the conductive layer (52) includes a first layer (52A) and a second layer (52B) positioned apart in the first direction (z) and sandwiching at least a portion of the insulating layer (51). [Explanation of symbols]

[0066] A1, A11, A12, A2, A3: semiconductor device 1: First lead 2: Second lead 3: Third lead 4: Semiconductor elements 5: Relay member 7: Sealing resin 11: First edge 12: Second edge 13: Third edge 14: Fourth edge 21: Pad section 22:Terminal section 40: Element body 41: Electrode 49: Bonding material 51: Insulating layer 51A: First insulating layer 51B: Second insulating layer 52: Conductive layer 52A: 1st layer 52B: 2nd layer 59: Bonding layer 61: First wire 62: Second wire 63: Third wire 64: 4th wire 71:Resin first side 72:Resin second side 73:Resin 3rd side 74:Resin 4th side 75:Resin 5th side 76:Resin 6th side 101: 1st page 102:Second side 301:Side 3 302:Side 4 303: 3rd page 511: Groove 521: Wiring section 521A: 1st wiring section 521B: 2nd wiring section 522: Conductive layer 522A: First pad section 529: Conductive contact x :Second direction x1 :1st side x2: 2nd side y: third direction y1: First side y2: Second side z: first direction z1 :1st side z2: Second side

Claims

1. a first lead having a first surface facing a first side in a first direction; a semiconductor element mounted on the first surface and having a plurality of electrodes; a second lead electrically connected to the semiconductor element; a sealing resin that covers at least a portion of each of the first lead and the second lead and the semiconductor element, a conductive layer including an insulating layer and one or more wiring portions; a first wire connected to the electrode and the wiring portion; a second wire connected to the second lead; a conductive path between the electrode and the second lead including the first wire, the wiring portion, and the second wire;

2. The semiconductor device according to claim 1 , wherein the second wire is connected to the wiring portion to which the first wire is connected.

3. The semiconductor device according to claim 1 , wherein the relay board is mounted on the first surface.

4. The semiconductor device according to claim 1 , wherein said conductive layer includes a plurality of said wiring portions.

5. the insulating layer has a groove; The semiconductor device according to claim 4 , wherein the two wiring portions are arranged with the groove portion therebetween.

6. The semiconductor device according to claim 1 , further comprising a plurality of said relay boards.

7. The first surface is a first edge located on a first side in a second direction intersecting the first direction and extending along a third direction intersecting the first direction and the second direction; a second edge located on a second side in the second direction and along the third direction; a third edge located on the first side in the third direction and along the second direction; and 7. The semiconductor device according to claim 1, further comprising a fourth edge located on a second side in the third direction and extending along the second direction.

8. the semiconductor element is positioned offset toward the first side in the second direction, The semiconductor device according to claim 7 , wherein the relay member is located between the semiconductor element and the second edge.

9. The semiconductor device according to claim 8 , further comprising a relay member arranged in a third direction and spaced apart from the relay member located between the semiconductor element and the second edge.

10. the semiconductor element is positioned offset toward the first side in the third direction, The semiconductor device according to claim 7 , wherein the relay member is located between the semiconductor element and the terminal portion.

11. the second wire 1 further includes a third wire connected to the wiring portion to which the first wire connected to the wiring portion and another wiring portion is connected, The semiconductor device according to claim 1 , wherein the conductive path further includes the third wire.

12. the third wire is connected to a wiring portion different from the wiring portion to which the second wire is connected, a fourth wire connected to the wiring portion to which the second wire is connected and to the wiring portion to which the third wire is connected; The semiconductor device according to claim 11 , wherein the conductive path further includes the fourth wire.

13. The semiconductor device according to claim 1 , wherein the second wire is connected to the wiring portion different from the wiring portion to which the first wire is connected.

14. The semiconductor device according to claim 1 , further comprising two relay members disposed on both sides of the semiconductor element in the second direction.

15. The semiconductor device according to claim 1 , further comprising two relay members disposed on both sides of the semiconductor element in the third direction.

16. The semiconductor device according to claim 1 , wherein said conductive layer includes a first layer and a second layer positioned apart in said first direction with at least a portion of said insulating layer sandwiched therebetween.

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