Multilayer ceramic capacitor

Abstract

To provide a multilayer ceramic capacitor in which an occurrence of a layer loosening when mechanical stress is applied is suppressed.SOLUTION: In a multilayer ceramic capacitor 1, the amount of segregation of silicon and magnesium in an outer layer side 711 of an outermost internal electrode layer 301 is larger than the amount of segregation of silicon and magnesium in an inner layer side 712 of the outermost internal electrode layer 301. When a region defined by a region 320 where the outermost internal electrode layer 301 exists and the segregation region 330 of silicon and magnesium present in contact with the outermost internal electrode layer 301 is defined as a first region 340, a line edge roughness A of the outer layer side 711 of the first region 340 is larger than a line edge roughness B of an inner layer side 712 of the first region 340.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor. [Background technology]

[0002] For example, the multilayer ceramic capacitor described in Patent Document 1 includes a capacitor body made of a sintered ceramic body made of a dielectric material such as barium titanate. The capacitor body includes internal electrode layers made of a noble metal material such as silver or a silver-palladium alloy, or a base metal material such as nickel, with ceramic layers serving as dielectric layers interposed between them. The internal electrode layers are alternately routed to one end face and the other end face of the capacitor body. The alternately routed internal electrode layers are electrically connected to external electrodes at different potentials.

[0003] The internal electrode layers of the multilayer capacitor described in Patent Document 1 are made of a metal material, and the external electrodes are made of a glass component and multiple metal components, including the same metal or metals that can be alloyed with the internal electrode layers. The external electrodes are bonded to the wiring board via a conductive resin adhesive. The area occupancy rate of the metal components relative to the cross-sectional area of ​​the external electrodes is in the range of 60% to 95%. This makes it possible for the multilayer capacitor described in Patent Document 1 to be mounted on the wiring board inexpensively and with high reliability without using solder. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-237137 Summary of the Invention [Problem to be solved by the invention]

[0005] Incidentally, the laminate included in a typical multilayer ceramic capacitor as described above has an inner layer portion and an outer layer portion in the height direction. The inner layer portion is a portion where dielectric layers and internal electrode layers are laminated. The outer layer portion is a portion where only dielectric layers are arranged, without internal electrode layers. Conventionally, the mechanical bonding strength between the inner layer portion and the outer layer portion is not strong. Therefore, when mechanical stress is applied to the multilayer ceramic capacitor, there is a problem in that layer peeling occurs between the inner layer portion and the outer layer portion.

[0006] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a multilayer ceramic capacitor in which the occurrence of layer peeling when mechanical stress is applied is suppressed. [Means for solving the problem]

[0007] The multilayer ceramic capacitor of the present invention comprises a laminate including a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, a first main surface and a second main surface opposing each other in a height direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the height direction and the width direction, the laminate including an internal layer portion formed by alternately laminating the dielectric layers and the internal electrode layers, and external layer portions arranged to sandwich the internal layer portion from the first main surface side and the second main surface side; a first external electrode arranged on the first end surface; and a second external electrode arranged on the second end surface. In a multilayer ceramic capacitor having two external electrodes, when the internal electrode layer arranged closest to the outer layer portion is defined as an outermost internal electrode layer, the amount of segregation of silicon and magnesium on the outer layer side of the outermost internal electrode layer is greater than the amount of segregation of silicon and magnesium on the inner layer side of the outermost internal electrode layer, and when a region defined by a region where the outermost internal electrode layer exists and a region where silicon and magnesium are segregated and in contact with the outermost internal electrode layer is defined as a first region, a line edge roughness A on the outer layer side of the first region is greater than a line edge roughness B on the inner layer side of the first region. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a multilayer ceramic capacitor in which the occurrence of layer peeling when mechanical stress is applied is suppressed. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is an external perspective view of a multilayer ceramic capacitor according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a cross-sectional view taken along line 101-101 in FIG. [Figure 3] FIG. 3 is a cross-sectional view taken along line 102-102 of FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along line 103-103 in FIG. [Figure 5] FIG. 5 is a cross-sectional view taken along line 104-104 in FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along line 101-101 in FIG. [Figure 7] FIG. 7 is an enlarged view of the portion corresponding to the framed area 110 in FIG. [Figure 8] FIG. 8 is an enlarged view of the portion corresponding to the framed area 110 in FIG. [Figure 9] FIG. 9 is a diagram for explaining line edge roughness. [Figure 10] FIG. 10 is a diagram showing the evaluation results of the example and the comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0010] (multilayer ceramic capacitors) A multilayer ceramic capacitor 1 according to an embodiment of the present disclosure will be described with reference to the drawings. FIG. 1 is an external perspective view of the multilayer ceramic capacitor 1 according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along line 101-101 of FIG. 1. FIG. 3 is a cross-sectional view taken along line 102-102 of FIG. 2. FIG. 4 is a cross-sectional view taken along line 103-103 of FIG. 2. FIG. 5 is a cross-sectional view taken along line 104-104 of FIG. 2.

[0011] 1, the multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape. The multilayer ceramic capacitor 1 includes a laminate 2 having a substantially rectangular parallelepiped shape and a pair of external electrodes 40 disposed at both ends of the laminate 2 and spaced apart from each other.

[0012] In Fig. 1, arrow T indicates the height direction of the multilayer ceramic capacitor 1 and the laminate 2. This height direction T is also the thickness direction and lamination direction of the multilayer ceramic capacitor 1 and the laminate 2. In Fig. 1, arrow L indicates the length direction of the multilayer ceramic capacitor 1 and the laminate 2, which is perpendicular to the height direction T. In Fig. 1, arrow W indicates the width direction of the multilayer ceramic capacitor 1 and the laminate 2, which is perpendicular to the height direction T and the length direction L. A pair of external electrodes 40 is disposed at one end and the other end of the length direction L of the laminate 2, respectively.

[0013] The cross section shown in Figure 2 is called the LT cross section, the cross section shown in Figure 3 is called the WT cross section, and the cross sections shown in Figure 4 and Figure 5 are called the LW cross sections.

[0014] (Laminate) The two surfaces of the laminate 2 that face each other in the height direction T are called the first main surface 3 and the second main surface 4. The two surfaces that face each other in the length direction L, which is perpendicular to the height direction T of the laminate, are called the first end surface 7 and the second end surface 8. The two surfaces of the laminate 2 that face each other in the width direction W, which is perpendicular to the height direction T and the length direction L, are called the first side surface 5 and the second side surface 6.

[0015] As shown in FIG. 1, the laminate 2 has a substantially rectangular parallelepiped shape. The length of the laminate 2 in the longitudinal direction L does not have to be longer than the length of the laminate 2 in the width direction W. The corners and ridges of the laminate 2 are preferably rounded. A corner is a portion where three surfaces of the laminate intersect. A ridge is a portion where two surfaces of the laminate intersect. The shape of part or all of the surfaces constituting the laminate 2 may have irregularities formed thereon.

[0016] The size of the laminate 2 is not limited. The preferred length of the laminate 2 in the longitudinal direction L is 0.2 mm or more and 6 mm or less. The preferred length of the laminate 2 in the height direction T is 0.05 mm or more and 5 mm or less. The preferred length of the laminate 2 in the width direction W is 0.1 mm or more and 5 mm or less.

[0017] (Division in the height direction) 2 and 3 , the laminate 2 is divided into an inner layer portion 10 and a main surface side outer layer portion 11 in the height direction T. The main surface side outer layer portion 11 includes a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13. The first main surface side outer layer portion 12 and the second main surface side outer layer portion 13 are located on either side of the inner layer portion 10 in the height direction T. In other words, the laminate 2 is divided into the first main surface side outer layer portion 12, the inner layer portion 10, and the second main surface side outer layer portion 13.

[0018] (dielectric layer) The inner layer portion 10 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 alternately stacked in the height direction T. The inner layer portion 10 includes, in the height direction T, the internal electrode layer 30 located closest to the first main surface 3 to the internal electrode layer 30 located closest to the second main surface 4. In the inner layer portion 10, the multiple internal electrode layers 30 are arranged facing each other with the dielectric layer 20 interposed therebetween. The inner layer portion 10 is a portion that generates electrostatic capacitance and essentially functions as a capacitor. The dielectric layer 20 included in the inner layer portion 10 is called an inner dielectric layer 21. The dielectric layer 20 included in the first main surface side outer layer portion 12 and the dielectric layer 20 included in the second main surface side outer layer portion 13 are called outer dielectric layers 22.

[0019] The multiple dielectric layers 20 are made of a dielectric material. Examples of the dielectric material are dielectric ceramics containing components such as barium titanate, calcium titanate, strontium titanate, or calcium zirconate. The dielectric material may be made by adding a secondary component such as a manganese compound, an iron compound, a copper compound, a cobalt compound, or a nickel compound to these main components. A preferred dielectric material is one containing barium titanate as the main component.

[0020] The preferred thickness of the dielectric layer 20 is 0.2 μm or more and 10 μm or less. The preferred number of laminated dielectric layers 20 is 15 or more and 1200 or less. The number of dielectric layers 20 is the sum of the number of inner dielectric layers 21 and the number of outer dielectric layers 22.

[0021] (Internal electrode layer) The multiple internal electrode layers 30 include multiple first internal electrode layers 31 and multiple second internal electrode layers 32. The first internal electrode layers 31 and the second internal electrode layers 32 are alternately arranged in the height direction T with the dielectric layer 20 sandwiched between them. The first internal electrode layers 31 are extended to the first end face 7. The second internal electrode layers 32 are extended to the second end face 8.

[0022] As shown in Fig. 4, the first internal electrode layer 31 is divided into a first opposing portion 33 and a first lead portion 35. The first opposing portion 33 is a portion that faces the second internal electrode layer 32 with the dielectric layer 20 sandwiched therebetween. The first lead portion 35 is a portion that is led from the first opposing portion 33 to the first end face 7. The first lead portion 35 is exposed at the first end face 7.

[0023] As shown in Fig. 5, the second internal electrode layer 32 is divided into a second opposing portion 34 and a second lead portion 36. The second opposing portion 34 is a portion that faces the first internal electrode layer 31 with the dielectric layer 20 sandwiched therebetween. The second lead portion 36 is a portion that is led from the second opposing portion 34 to the second end face 8. The second lead portion 36 is exposed at the second end face 8.

[0024] In the multilayer ceramic capacitor 1, capacitance is formed by the first opposing portion 33 and the second opposing portion 34 facing each other via the dielectric layer 20. This allows the multilayer ceramic capacitor 1 to exhibit capacitor characteristics.

[0025] The shapes of the first opposing portion 33 and the second opposing portion 34 are not limited. A preferred shape for the first opposing portion 33 and the second opposing portion 34 is a rectangular shape. Similarly, the shapes of the first drawer portion 35 and the second drawer portion 36 are not limited. A preferred shape for the first drawer portion 35 and the second drawer portion 36 is a rectangular shape. In the above-mentioned rectangular shape, the corners of the rectangular shape may be rounded. The corners of the rectangular shape may be formed at an angle.

[0026] The length in the width direction W of the first facing portion 33 and the length in the width direction W of the first lead portion 35 may be the same. Either the length in the width direction W of the first facing portion 33 or the length in the width direction W of the first lead portion 35 may be shorter. The length in the width direction W of the second facing portion 34 and the length in the width direction W of the second lead portion 36 may be the same. Either the length in the width direction W of the second facing portion 34 or the length in the width direction W of the second lead portion 36 may be shorter.

[0027] Examples of materials for the first internal electrode layers 31 and the second internal electrode layers 32 are conductive materials such as metals such as nickel, copper, silver, palladium, and gold, and alloys containing at least one of these metals. When an alloy is used, an example of the material for the first internal electrode layers 31 and the second internal electrode layers 32 is an alloy of silver and palladium.

[0028] A preferred example of the thickness of each of the first internal electrode layers 31 and the second internal electrode layers 32 is 0.2 μm or more and 2.0 μm or less. A preferred total number of layers of the first internal electrode layers 31 and the second internal electrode layers 32 is 15 or more and 1000 or less.

[0029] (Outer layer on main surface side) As shown in FIGS. 2 and 3 , a portion consisting of a set of multiple dielectric layers 20 located between the first main surface 3 and the internal electrode layer 30 closest to the first main surface 3 is called the first main surface side outer layer portion 12. The first main surface side outer layer portion 12 is located on the first main surface 3 side of the laminate 2. A portion consisting of a set of multiple dielectric layers 20 located between the second main surface 4 and the internal electrode layer 30 closest to the second main surface 4 is called the second main surface side outer layer portion 13. The second main surface side outer layer portion 13 is located on the second main surface 4 side of the laminate 2. The dielectric layers 20 used in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13 may both be the same as the dielectric layers 20 used in the internal layer portion 10. The material of the internal dielectric layer 21 and the material of the external dielectric layer 22 may be the same.

[0030] (electrode facing part) The portion where the first opposing portion 33 of the first internal electrode layer 31 and the second opposing portion 34 of the second internal electrode layer 32 oppose each other is called the electrode opposing portion 14. The electrode opposing portion 14 is part of the internal layer portion 10. Figures 4 and 5 show the range of the electrode opposing portion 14 in the width direction W and length direction L. The electrode opposing portion 14 is also called the capacitor effective portion.

[0031] (W direction division) The laminate 2 is divided in the width direction W into a first side surface side outer layer portion 15, an electrode facing portion 14, and a second side surface side outer layer portion 16. The first side surface side outer layer portion 15 is a portion including a dielectric layer 20 located between the electrode facing portion 14 and the first side surface 5. The second side surface side outer layer portion 16 is a portion including a dielectric layer 20 located between the electrode facing portion 14 and the second side surface 6. Figures 3, 4, and 5 show the ranges in the width direction W of the first side surface side outer layer portion 15, the electrode facing portion 14, and the second side surface side outer layer portion 16. The first side surface side outer layer portion 15 and the second side surface side outer layer portion 16 are called W gaps or side gaps.

[0032] (L direction division) The laminate 2 is divided into a first end face side outer layer portion 17, an electrode facing portion 14, and a second end face side outer layer portion 18 in the longitudinal direction L. The first end face side outer layer portion 17 is a portion including the dielectric layer 20 and the first lead portion 35 located between the electrode facing portion 14 and the first end face 7. The first end face side outer layer portion 17 is an assembly of the portions of the multiple dielectric layers 20 on the first end face 7 side and the multiple first lead portions 35. The second end face side outer layer portion 18 is a portion including the dielectric layer 20 and the second lead portion 36 located between the electrode facing portion 14 and the second end face 8. The second end face side outer layer portion 18 is an assembly of the portions of the multiple dielectric layers 20 on the second end face 8 side and the multiple second lead portions 36. 2, 4, and 5 show the ranges in the length direction L of the first end surface side outer layer portion 17, the electrode opposing portion 14, and the second end surface side outer layer portion 18. The first end surface side outer layer portion 17 and the second end surface side outer layer portion 18 are called L gaps or end gaps.

[0033] (external electrode) The external electrodes 40 include a first external electrode 41 and a second external electrode 42. The first external electrode 41 is an external electrode arranged on the first end face 7 side of the laminate 2. The second external electrode 42 is an external electrode arranged on the second end face 8 side of the laminate 2.

[0034] The first external electrode 41 and the second external electrode 42 have the same basic configuration. The first external electrode 41 and the second external electrode 42 have shapes that are approximately symmetrical with respect to the WT cross section at the center of the length direction L of the multilayer ceramic capacitor 1.

[0035] The first external electrode 41 is disposed on the first end face 7. The first external electrode 41 contacts the first lead portions 35 of each of the multiple first internal electrode layers 31 exposed at the first end face 7. The first external electrode 41 is electrically connected to the multiple first internal electrode layers 31. The first external electrode 41 may also be disposed on part of the first main surface 3 and part of the second main surface 4, as well as part of the first side surface 5 and part of the second side surface 6. In this embodiment, the first external electrode 41 is formed to extend from on the first end face 7 to part of the first main surface 3 and part of the second main surface 4, as well as part of the first side surface 5 and part of the second side surface 6.

[0036] The second external electrode 42 is disposed on the second end face 8. The second external electrode 42 contacts the second lead portions 36 of each of the second internal electrode layers 32 exposed at the second end face 8. The second external electrode 42 is electrically connected to the second internal electrode layers 32. The second external electrode 42 may also be disposed on a portion of the first main surface 3 and a portion of the second main surface 4, as well as a portion of the first side surface 5 and a portion of the second side surface 6. In this embodiment, the second external electrode 42 is formed to extend from the second end face 8 to a portion of the first main surface 3 and a portion of the second main surface 4, as well as a portion of the first side surface 5 and a portion of the second side surface 6.

[0037] In the laminate 2, a capacitance is formed by the first opposing portion 33 of the first internal electrode layer 31 and the second opposing portion 34 of the second internal electrode layer 32 opposing each other via the dielectric layer 20. Therefore, the characteristics of a capacitor are exhibited between the first external electrode 41 connected to the first internal electrode layer 31 and the second external electrode 42 connected to the second internal electrode layer 32.

[0038] (base electrode layer) 2, 4, and 5, the first external electrode 41 includes a first base electrode layer 51 and a first plating layer 71. The first plating layer 71 is disposed on the first base electrode layer 51. The second external electrode 42 includes a second base electrode layer 52 and a second plating layer 72. The second plating layer 72 is disposed on the second base electrode layer 52.

[0039] The first base electrode layer 51 is disposed on the first end face 7. The first base electrode layer 51 contacts the first lead portions 35 of each of the multiple first internal electrode layers 31 exposed at the first end face 7. The first base electrode layer 51 is formed to extend from the first end face 7 to a portion of the first main surface 3 and a portion of the second main surface 4, as well as a portion of the first side surface 5 and a portion of the second side surface 6.

[0040] The second base electrode layer 52 is disposed on the second end face 8. The second base electrode layer 52 contacts the second lead portions 36 of each of the plurality of second internal electrode layers 32 exposed at the second end face 8. The second base electrode layer 52 is formed to extend from the second end face 8 to a portion of the first main surface 3 and a portion of the second main surface 4, as well as a portion of the first side surface 5 and a portion of the second side surface 6.

[0041] The first base electrode layer 51 and the second base electrode layer 52 are baked layers. The baked layer preferably contains a metal component. In addition to the metal component, the baked layer preferably contains at least one of a glass component and a ceramic component. The metal component includes at least one selected from, for example, copper, nickel, silver, palladium, a silver-palladium alloy, and gold. The glass component includes at least one selected from, for example, boron, silicon, barium, magnesium, aluminum, and lithium. The ceramic component may be the same type of ceramic material as the dielectric layer 20. The ceramic component may be a different type of ceramic material from the dielectric layer 20. The ceramic component may include at least one selected from, for example, barium titanate, calcium titanate, a mixed crystal material in which part of the barium in barium titanate is replaced with calcium, strontium titanate, calcium zirconate, and the like.

[0042] An example of a baked layer is a layer formed by applying and baking a conductive paste containing glass and metal to a laminate. The baked layer is formed by simultaneously firing a pre-fired laminated chip, which is the material for the laminate including multiple internal electrode layers and multiple dielectric layers, and the conductive paste applied to the laminated chip. Alternatively, the baked layer is formed by firing the laminated chip to obtain a laminate, and then applying and baking a conductive paste to the laminate. When the conductive paste is baked after obtaining the laminate, the baked layer is preferably formed by baking a conductive paste to which a ceramic material has been added instead of a glass component. When using a conductive paste to which a ceramic material has been added, the added ceramic material is preferably the same type of ceramic material as the dielectric layer. The baked layer may be multiple layers.

[0043] A preferred example of the thickness in the length direction L of the first base electrode layer 51 on the first end face 7 is approximately 10 μm or more and 200 μm or less at the center in the height direction T and width direction W of the first base electrode layer 51.

[0044] A preferred example of the thickness in the length direction L of the second base electrode layer 52 on the second end face 8 is approximately 10 μm or more and 200 μm or less at the center in the height direction T and width direction W of the second base electrode layer 52.

[0045] When the first base electrode layer 51 is provided on a portion of at least one of the first main surface 3 or the second main surface 4, an example of a preferred thickness in the height direction T of the first base electrode layer 51 provided on this portion is approximately 3 μm or more and 40 μm or less at the center in the length direction L and width direction W of the first base electrode layer 51 provided on this portion.

[0046] When the first base electrode layer 51 is provided on a portion of at least one of the first side surface 5 or the second side surface 6, an example of a preferred thickness in the width direction W of the first base electrode layer 51 provided on this portion is approximately 3 μm or more and 40 μm or less at the center in the length direction L and height direction T of the first base electrode layer 51 provided on this portion.

[0047] When the second base electrode layer 52 is provided on a portion of at least one of the first main surface 3 and the second main surface 4, an example of a preferred thickness in the height direction T of the second base electrode layer 52 provided on this portion is approximately 3 μm or more and 40 μm or less at the center in the length direction L and width direction W of the second base electrode layer 52 provided on this portion.

[0048] When the second base electrode layer 52 is provided on a portion of at least one of the first side surface 5 or the second side surface 6, an example of a preferred thickness in the width direction W of the second base electrode layer 52 provided on this portion is approximately 3 μm or more and 40 μm or less at the center in the length direction L and height direction T of the second base electrode layer 52 provided on this portion.

[0049] The first plating layer 71 is disposed so as to cover the first base electrode layer 51. The second plating layer 72 is disposed so as to cover the second base electrode layer 52.

[0050] The first plating layer 71 and the second plating layer 72 may contain at least one selected from, for example, copper, nickel, tin, silver, palladium, a silver-palladium alloy, and gold. The first plating layer 71 and the second plating layer 72 may each be formed of multiple layers. A preferred structure for the first plating layer 71 and the second plating layer 72 is a two-layer structure in which a tin plating layer is formed on a nickel plating layer.

[0051] The first plating layer 71 is disposed so as to cover the first base electrode layer 51. In this embodiment, the first plating layer 71 includes a first nickel plating layer 73 and a first tin plating layer 75. The first tin plating layer 75 is located on the first nickel plating layer 73.

[0052] The second plating layer 72 is disposed so as to cover the second base electrode layer 52. In this embodiment, the second plating layer 72 includes a second nickel plating layer 74 and a second tin plating layer 76. The second tin plating layer 76 is located on the second nickel plating layer 74.

[0053] The nickel plating layer prevents the first base electrode layer 51 and the second base electrode layer 52 from being eroded by solder when mounting the multilayer ceramic capacitor 1. The tin plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. The tin plating layer facilitates mounting of the multilayer ceramic capacitor 1. The first nickel plating layer 73, the first tin plating layer 75, the second nickel plating layer 74, and the second tin plating layer 76 each preferably have a thickness of 2 μm or more and 10 μm or less.

[0054] The external electrode 40 may include a conductive resin layer containing conductive particles and a thermosetting resin. When the external electrode 40 includes a conductive resin layer, the conductive resin layer may be disposed so as to cover the baked layer. When the conductive resin layer is disposed so as to cover the baked layer, the conductive resin layer is disposed between the baked layer and the plated layer. The baked layer corresponds to the first base electrode layer 51 and the second base electrode layer 52. The plated layer corresponds to the first plating layer 71 and the second plating layer 72. The conductive resin layer may completely cover the baked layer. The conductive resin layer may also cover a portion of the baked layer.

[0055] Conductive resin layers containing thermosetting resins are more flexible than conductive layers made of plating films or fired conductive pastes. Therefore, when a multilayer ceramic capacitor is subjected to physical shock or shock due to thermal cycling, the conductive resin layer functions as a buffer layer. Therefore, the conductive resin layer prevents cracks from occurring in the multilayer ceramic capacitor.

[0056] Examples of metals constituting the conductive particles include silver, copper, nickel, tin, bismuth, or an alloy containing at least two of these metals. The conductive particles preferably contain silver. An example of the conductive particles is silver metal powder. Silver has the lowest resistivity among metals. Silver is suitable as an electrode material. Silver is a noble metal. Silver is resistant to oxidation. Silver has high weather resistance. For these reasons, silver metal powder is suitable as the conductive particles.

[0057] The conductive particles may be metal powder whose surface is silver-coated. When using conductive particles whose surface is silver-coated, the metal powder is preferably a powder of copper, nickel, tin, bismuth, or an alloy thereof. In order to maintain the properties of silver while making the base metal inexpensive, it is preferable to use a silver-coated metal powder.

[0058] The conductive particles may be copper or nickel that has been subjected to an antioxidant treatment. The conductive particles may be metal powder whose surface is coated with tin, nickel, or copper. When using metal powder whose surface is coated with tin, nickel, or copper, the metal powder is preferably silver, copper, nickel, tin, bismuth, or an alloy powder containing at least two of these metals.

[0059] The shape of the conductive particles is not limited. Examples of the shape of the conductive particles include spherical and flat shapes. It is preferable to use a mixture of spherical metal powder and flat metal powder.

[0060] The conductive particles contained in the conductive resin layer mainly play a role in ensuring the electrical conductivity of the conductive resin layer. When multiple conductive particles come into contact with each other, a conductive path is formed inside the conductive resin layer.

[0061] Examples of the resin constituting the conductive resin layer may include at least one selected from various known thermosetting resins such as epoxy resin, phenol resin, urethane resin, silicone resin, and polyimide resin. Among these, one of the most suitable resins is epoxy resin. Epoxy resins have excellent heat resistance, moisture resistance, and adhesion. The resin of the conductive resin layer preferably contains a curing agent in addition to the thermosetting resin. When an epoxy resin is used as the base resin, the curing agent for the epoxy resin may be any of various known compounds such as phenol-based, amine-based, acid anhydride-based, imidazole-based, active ester-based, and amide-imide-based compounds.

[0062] The conductive resin layer may be formed of multiple layers. The preferred thickness of the thickest part of the conductive resin layer is 10 μm or more and 150 μm or less.

[0063] The above is the basic configuration of the multilayer ceramic capacitor 1. The length in the length direction L of the multilayer ceramic capacitor 1, including the laminate 2 and the external electrodes 40, is preferably 0.2 mm or more and 6 mm or less. The length in the height direction T of the multilayer ceramic capacitor 1 is preferably 0.05 mm or more and 5 mm or less. The length in the width direction W of the multilayer ceramic capacitor 1 is preferably 0.1 mm or more and 5 mm or less.

[0064] (Silicon and magnesium segregation, segregated area) In the multilayer ceramic capacitor 1 of this embodiment, there are portions in the laminate 2 where silicon or magnesium segregates. These portions are referred to as segregation portions 80. The segregation portions 80 are not uniformly present in the laminate 2 but are unevenly distributed. This will be described with reference to FIG. 6. FIG. 6 is a cross-sectional view taken along line 101-101 in FIG. 1. However, in FIG. 6, each portion is depicted more simply than in FIG. 2, which is also a cross-sectional view taken along line 101-101 in FIG. 1. Meanwhile, in FIG. 6, the segregation portions 80 are depicted with emphasis.

[0065] (Outermost internal electrode layer) Of the internal electrode layers 30, the internal electrode layer 30 closest to the main surface side outer layer portion 11 (outer layer portion) is defined as the outermost internal electrode layer 301. The distribution of segregation portions 80 in the vicinity of the outermost internal electrode layer 301 will be described. FIG. 6 shows two outermost internal electrode layers 301: one close to the first main surface side outer layer portion 12, and the other close to the second main surface side outer layer portion 13. In the following description, the outermost internal electrode layer 301 close to the first main surface side outer layer portion 12 will be used as an example to describe the outermost internal electrode layer 301. Note that the following description also applies to the other outermost internal electrode layer 301.

[0066] (Outer and inner layer sides of the outermost internal electrode layer) In the multilayer ceramic capacitor 1 of this embodiment, the segregation amounts of silicon and magnesium on the outer layer side 711 of the outermost internal electrode layer 301 are greater than the segregation amounts of silicon and magnesium on the inner layer side 712 of the outermost internal electrode layer 301 .

[0067] Here, the outer layer side 711 of the outermost internal electrode layer 301 refers to the side of the outermost internal electrode layer 301 that is in contact with the main surface-side outer layer portion 11. The inner layer side 712 of the outermost internal electrode layer 301 refers to the side opposite to the outer layer side 711.

[0068] (Outer and inner surfaces of the outermost internal electrode layer) Of the two surfaces of the outermost internal electrode layer 301 parallel to the length direction L, the surface on the outer layer side 711 is referred to as the outer layer surface 311. Of the two surfaces of the outermost internal electrode layer 301 parallel to the length direction L, the surface on the inner layer side 712 is referred to as the inner layer surface 312.

[0069] The segregation amount of silicon and magnesium on the outer layer side 711 of the outermost internal electrode layer 301 refers to the amount of segregation portion 80 protruding from the outer layer surface 311 toward the outer layer side 711. On the other hand, the segregation amount of silicon and magnesium on the inner layer side 712 of the outermost internal electrode layer 301 refers to the amount of segregation portion 80 protruding from the inner layer surface 312 toward the inner layer side 712. In other words, the segregation amount of silicon and magnesium refers to the segregation portion 80 at least a part of which is in contact with the outermost internal electrode layer 301.

[0070] As shown in FIG. 6, in the multilayer ceramic capacitor 1 of this embodiment, the amount of silicon and magnesium segregated on the outer layer side 711 of the outermost internal electrode layer 301 is greater than the amount of silicon and magnesium segregated on the inner layer side 712 of the outermost internal electrode layer 301.

[0071] (Evaluation of segregation amount) The amount of segregation can be evaluated by observing a cross section of the laminate 2. This will be explained with reference to Figs. 7 and 8. Figs. 7 and 8 are both enlarged views of a portion corresponding to the framed area 110 in Fig. 6. Figs. 7 and 8 are both images taken with a reflected electron microscope. The black areas in Fig. 7 are segregation regions 80. The amount of segregation can be evaluated based on the area of ​​the segregation regions 80.

[0072] 8, the segregation amounts of silicon and magnesium on the outer layer side 711 of the outermost internal electrode layer 301 are greater than the segregation amounts of silicon and magnesium on the inner layer side 712 of the outermost internal electrode layer 301. The segregation portions 80 will be described in more detail below.

[0073] (Area where the outermost internal electrode layer exists) In the outermost internal electrode layer 301, a region where the material for the internal electrode layer 30 constituting the outermost internal electrode layer 301 exists is referred to as a presence region 320 of the outermost internal electrode layer 301. The presence region 320 of the outermost internal electrode layer 301 corresponds to a region sandwiched between an outer layer surface 311 and an internal layer surface 312 in the LT cross section shown in FIG.

[0074] (Silicon and magnesium segregation region) The region formed by the entire segregation portion 80 that is in contact with the outermost internal electrode layer 301 is referred to as a silicon and magnesium segregation region 330. In Figures 6 to 8, reference numerals are written on parts of the segregation region 330. The segregation region 330 is not necessarily continuous in the length direction L.

[0075] (First area) The region 320 where the outermost internal electrode layer 301 exists and the region 330 where silicon and magnesium are segregated are combined to form a first region 340 .

[0076] (Line Edge Roughness) The line edge roughness of the first region 340 will now be described. Line edge roughness refers to the variation in the position of the line edge. In the multilayer ceramic capacitor 1 of this embodiment, the line edge roughness of the end portion on the outer layer side 711 of the first region 340 is greater than the line edge roughness of the end portion on the inner layer side 712 of the first region 340.

[0077] Line edge roughness will be described with reference to Fig. 9. Line edge roughness is calculated in the following two stages. (1) The coordinates of the edge points of the measurement line are obtained, and an approximate straight line is calculated based on those coordinates. The edge points are set at 16 nm intervals in the direction perpendicular to the thickness direction (horizontal direction). (2) The deviation between the calculated approximation curve and the edge point is calculated as the line edge roughness.

[0078] Fig. 9 is a diagram for explaining how to calculate line edge roughness. Two measurement lines, measurement line 501 and measurement line 502, are shown in Fig. 9. However, the method for calculating the approximate line and the method for calculating the line edge roughness are the same for measurement line 501 and measurement line 502.

[0079] Diagram 601 on the left side of Figure 9 illustrates a method for determining approximate straightness. Black circles 511 to 515 on measurement line 501 and black circles 521 to 525 on measurement line 502 indicate the edge points of the measurement line. To calculate line edge roughness, first, approximate straight lines are determined for the edge points of the measurement line. The determined approximate straight lines are approximate straight lines 531 and 532.

[0080] Next, as indicated by arrow 600, the process moves to calculating line edge roughness based on the obtained approximate lines 531 and 532. Diagram 602 on the right side of FIG. 9 illustrates a method for calculating edge roughness. Edge roughness is the deviation of each edge point from the approximate line. Black circles 516 to 519 on measurement line 501 and black circles 526 to 529 on measurement line 502 indicate the edge points of the measurement line. For example, the deviation between edge point 516 on measurement line 501 and approximate line 531 is the amount indicated by arrow 541. Hereinafter, the amount indicated by arrow 541 will be referred to as edge roughness 541.

[0081] Next, a specific method for determining the line edge roughness will be described. For the measurement line 501, the edge roughness 541 of the edge point 516, the edge roughness 542 of the edge point 517, the edge roughness 543 of the edge point 518, and the edge roughness of the edge point 519 are averaged. This average value is taken as the line edge roughness. Note that the edge point 519 is located on the approximate line 531. Therefore, the edge roughness of the edge point 519 is 0. The line edge roughness of the measurement line 502 can also be determined in the same manner as for the measurement line 502.

[0082] In the multilayer ceramic capacitor 1 of this embodiment, the line edge roughness was determined according to the following specifications. Image analysis and measurement software: WinROOF (product name) Measurement magnification: 10,000 times Image: Backscattered electron image Number of fields: average of 5 fields

[0083] Specifically, in the above specifications, the internal electrode layer 30 within the field of view is divided into 624 sections in the length direction L. The average value of the edge roughness of each section is then taken as the line edge roughness. In other words, the average value of the edge roughness for n=624 is taken as the line edge roughness.

[0084] The line edge roughness of each of the five visual fields is calculated, and the average value of the five calculated line edge roughness values ​​is defined as the line edge roughness of the present disclosure.

[0085] (Line edge roughness on the outer layer side and line edge roughness on the inner layer side) In the multilayer ceramic capacitor 1 of this embodiment, the line edge roughness (LER) A of the outer layer side 711 of the first region 340 is larger than the line edge roughness (LER) B of the inner layer side 712 of the first region 340.

[0086] 8, the contour line of the outer layer side 711 of the first region 340 is shown as the outer layer side line 341 of the first region. Similarly, the contour line of the inner layer side 712 of the first region 340 is shown as the inner layer side line 342 of the first region. The line edge roughness A of the outer layer side line 341 of the first region is greater than the line edge roughness B of the inner layer side line 342 of the first region.

[0087] The multilayer ceramic capacitor 1 of this embodiment, with the above-described configuration, can provide a multilayer ceramic capacitor 1 in which layer peeling is suppressed when mechanical stress is applied, particularly between the inner layer portion 10 and the main-surface-side outer layer portion 11.

[0088] According to the above-described configuration, only the outer layer side 711 of the outermost internal electrode layer 301 has large line edge roughness, that is, large surface irregularities.

[0089] This strengthens the mechanical bond between the inner layer portion 10 and the outer layer portion 13 on the main surface side, thereby suppressing layer peeling.

[0090] Furthermore, with the above configuration, the inner layer side 712 of the outermost internal electrode layer 301 is smooth, so that the reliability of the multilayer ceramic capacitor 1 is less likely to decrease.

[0091] (Internal electrode layer thickness and line edge roughness) A more preferable range of the line edge roughness will be explained. Regarding the thickness 701 of the internal electrode layer 30 shown in Fig. 6, its average thickness is defined as C. The value obtained by dividing the line edge roughness A on the outer layer side 711 of the first region 340 described above by the average thickness C of the internal electrode layer 30, that is, the ratio (A / C), is defined as value D. The value D is preferably 0.093 or more and 0.341 or less.

[0092] If the value D is less than 0.093, the unevenness on the outer layer side 711 of the outermost internal electrode layer 301 is not sufficient relative to the thickness of the internal electrode layer 30. Therefore, there are cases where the suppression of layer peeling is insufficient.

[0093] On the other hand, if the value D exceeds 0.341, the unevenness will be too large, which will weaken the mechanical bond between the inner layer portion 10 and the main surface-side outer layer portion 13. As a result, the prevention of layer peeling may be insufficient.

[0094] (Line edge roughness on the outer layer side and line edge roughness on the inner layer side) The ratio (A / B) of the line edge roughness A on the outer layer side 711 of the first region 340 to the line edge roughness B on the inner layer side 712 of the first region 340 described above is defined as a value E. The value E is preferably 1.23 or more and 6.70 or less.

[0095] By setting the values ​​D and E within the above-mentioned ranges, the line edge roughness can be increased only on the outer layer side 711 of the outermost internal electrode layer 301, thereby increasing the irregularities. This further strengthens the mechanical bond between the internal layer portion 10 and the main surface-side outer layer portion 11. As a result, layer peeling can be further suppressed.

[0096] (Area ratio of outer layer to inner layer) The areas of the outer layer side 711 and the inner layer side 712 of the first region 340 will be described. Fig. 8 shows the area 721 of the outer layer side 711 of the first region 340 and the area 722 of the inner layer side 712 of the first region 340. The ratio of the area of ​​the outer layer side 711 of the first region 340 to the area 722 of the inner layer side 712 of the first region 340 is defined as F. The value F is preferably 1.1 or more and 3.30 or less.

[0097] With the above configuration, the line edge roughness increases only on the outer layer side 711 of the outermost internal electrode layer 301, and the unevenness also increases. This further strengthens the mechanical bond between the inner layer portion 10 and the main surface-side outer layer portion 11. As a result, the effect of suppressing layer peeling can be significantly achieved.

[0098] Note that the value F exceeding 1 indicates that the amount of segregation of silicon and magnesium on the outer layer side 711 of the outermost internal electrode layer 301 is greater than the amount of segregation of silicon and magnesium on the inner layer side 712 of the outermost internal electrode layer 301.

[0099] (Area measurement method) A method for measuring the area of ​​first region 340 will be described with reference to FIGS. (1) First, in the region where the metal material constituting the internal electrode layer 30, for example, nickel, is present, outer lines are drawn on both side ends in the height direction T. Lines 401 and 403 shown in Figs. 7 and 8 are the outer lines. (2) Next, a center line is drawn in the center in the height direction T between the line 401 and the line 403. The line 402 shown in Figures 7 and 8 is the center line. The center line 402 is defined as the center of the internal electrode layer 30 in the height direction T. (3) Next, the areas on both sides of the center line 402 in the first region 340 are calculated. The area surrounded by the center line 402 and the outer layer side line 341 of the first region 340 is the area 721 of the outer layer side 711 of the first region 340. The area surrounded by the center line 402 and the inner layer side line 342 of the first region 340 is the area 722 of the inner layer side 712 of the first region 340. (4) Next, the ratio of the determined area 721 to the area 722 is calculated. When determining the area, the area of ​​magnesium segregation and magnesium present together with nickel is measured.

[0100] Examples and Comparative Examples The evaluation results of the example and the comparative example will be described with reference to Fig. 10. Fig. 10 is a diagram showing the evaluation results of the example and the comparative example. First, the samples used for the evaluation will be described. (sample) Dimensions of the multilayer ceramic capacitor: Length (L) x Width (W) x Height (T) = 3.15mm x 1.65mm x 1.65mm Ceramic material: Barium titanate Capacitance: 10μF Internal electrode layer material: Nickel According to the manufacturing method described below, samples in which the manufacturing conditions were adjusted so as to have different line edge roughness were manufactured in lots as samples of Examples 1 to 22 and Comparative Examples 1 to 3. The samples in each lot were manufactured under the same manufacturing conditions. For each Example and Comparative Example, n=3 samples for measuring line edge roughness and thickness of the internal electrode layer and n=100 samples for evaluating layer peeling were taken out and prepared from the same lot. In measuring the line edge roughness and the internal electrode layer, the average value of the measurement results of n=3 was used.

[0101] (Method for evaluating layer peeling) After firing, the laminated body is inspected for appearance by mechanical sorting to check for peeling between the inner and outer layers (n=100 pieces). (Judgment criteria) The judgement is based on the number of peeled pieces per 100 pieces. 0 or more and 10 or less: ◎ 11 or more and 30 or less:○ 31 or more and 70 or less: △ 71 or more and 100 or less:×

[0102] (Evaluation results) As shown in Figure 9, when the line edge roughness A on the outer layer side of the first region was greater than the line edge roughness B on the inner layer side of the first region, the layer peeling after firing was judged to be either ◎, ◯, or △.

[0103] When the ratio D of the line edge roughness A on the outer layer side of the first region to the average thickness C of the internal electrode layer was 0.093 or more and 0.341 or less, and the ratio E of the line edge roughness A on the outer layer side of the first region to the line edge roughness B on the inner layer side of the first region was 1.23 or more and 6.70 or less, the layer peeling after firing was judged to be either ◎ or ◯.

[0104] (Manufacturing method of multilayer ceramic capacitors) A method for manufacturing a multilayer ceramic capacitor will now be described. Note that the method for manufacturing a multilayer ceramic capacitor is not limited to the method below.

[0105] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. Both the dielectric sheet for the dielectric layer 20 and the conductive paste for the internal electrode layer 30 contain a binder and a solvent. The binder and solvent may be known. An example of a paste made of a conductive material is a paste in which an organic binder and an organic solvent are added to a metal powder.

[0106] A conductive paste for the internal electrode layer 30 is printed on the dielectric sheet using a printing plate whose pattern is designed to have the shape of the internal electrode layer 30. Examples of printing methods include screen printing and gravure printing. In this way, a dielectric sheet on which the pattern of the first internal electrode layer 31 is formed and a dielectric sheet on which the pattern of the second internal electrode layer 32 is formed are prepared.

[0107] A predetermined number of dielectric sheets on which the pattern of the internal electrode layer 30 is not printed are stacked to form a portion that will become the first main surface side outer layer portion 12 on the first main surface 3 side. Dielectric sheets on which the pattern of the first internal electrode layer 31 is printed and dielectric sheets on which the pattern of the second internal electrode layer 32 is printed are stacked alternately in sequence on top of that to form a portion that will become the internal layer portion 10. A predetermined number of dielectric sheets on which the pattern of the internal electrode layer 30 is not printed are stacked on top of this portion that will become the internal layer portion 10 to form a portion that will become the second main surface side outer layer portion 13 on the second main surface 4 side. In this way, a laminated sheet is obtained.

[0108] Here, by increasing the concentrations of silicon and magnesium in the dielectric sheet corresponding to the main surface side outer layer portion, it is possible to selectively segregate silicon and magnesium to the outer layer side of the outermost internal electrode layer. Also, by adding a magnesium compound with a large particle size to the dielectric sheet corresponding to the main surface side outer layer portion, it is possible to selectively segregate magnesium to the outer layer side of the outermost internal electrode layer.

[0109] The laminated sheet is then pressed in the height direction by means of a hydrostatic press or the like to produce a laminated block.

[0110] The laminated block is then cut into individual pieces of a predetermined size to obtain a plurality of laminated chips, which may then be polished by barrel polishing or the like to round off corners and ridges.

[0111] The laminated chip is then fired to produce a laminate. The firing temperature is preferably 900° C. or higher and 1400° C. or lower. The firing temperature can be changed depending on the materials of the dielectric and internal electrode layers.

[0112] A conductive paste that will become the base electrode layer 50 is applied to both end surfaces of the laminate 2. In this embodiment, the base electrode layer 50 is a baked layer. The baked layer can be formed by applying a conductive paste containing a glass component and a metal to the laminate 2 by a method such as dipping, and then performing a baking process. The temperature for the baking process at this time is preferably 700°C or higher and 900°C or lower.

[0113] The laminated chip before firing and the conductive paste applied to the laminated chip may be fired simultaneously. In this case, the fired layer is preferably formed by firing a material containing a ceramic material instead of a glass component. In this case, the ceramic material added is preferably the same type as that of the dielectric layer 20. In this case, the conductive paste is applied to the laminated chip before firing, and the laminated chip and the conductive paste applied to the laminated chip are fired simultaneously to form the laminate 2 with the fired layer.

[0114] Thereafter, a plating layer is formed on the surface of the base electrode layer 50, which is made of a baked layer. In this embodiment, a first plating layer 71 is formed on the surface of the first base electrode layer 51. A second plating layer 72 is formed on the surface of the second base electrode layer 52. In this embodiment, a nickel plating layer and a tin plating layer are formed as the plating layers. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which makes the process more complicated. Therefore, it is usually preferable to use electrolytic plating. The nickel plating layer and the tin plating layer are formed sequentially, for example, by barrel plating.

[0115] When a conductive resin layer is provided, the conductive resin layer may be disposed so as to cover the baked layer. When providing the conductive resin layer, a conductive resin paste containing a thermosetting resin and a metal component is applied onto the baked layer, followed by heat treatment at a temperature of 250 to 550°C or higher. This causes the thermosetting resin to thermally harden, forming a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. To prevent the resin from scattering and the various metal components from oxidizing, the oxygen concentration is preferably 100 ppm or less.

[0116] Through the above manufacturing steps, the multilayer ceramic capacitor 1 is manufactured.

[0117] The present invention is not limited to the configurations of the above-described embodiments, and can be appropriately modified and applied within the scope of the present invention. A combination of two or more of the individual desirable configurations described in the above-described embodiments also constitutes the present invention. [Explanation of symbols]

[0118] 1. Multilayer ceramic capacitors 2. Laminate 3 First main surface 4 Second main surface 5. First Aspect 6. The Second Aspect 7 First end face 8 Second end face 10 Inner layer 11 Outer layer on main surface side 14 Electrode facing part 20 dielectric layer 21 Inner dielectric layer 22 outer dielectric layer 30 Internal electrode layer 40 External electrode 41 First external electrode 42 Second external electrode 50 Base electrode layer 80 Silicon and magnesium segregation 301 Outermost internal electrode layer 311 Outer layer surface 312 Inner layer surface 320 Outermost layer internal electrode layer presence area 330 Silicon and magnesium segregation regions 340 First Region 341 Outer layer line of the first area 342 Inner layer line of the first area 701 Internal electrode layer thickness 711 Outer layer side 712 Inner layer side 721 Area of ​​the outer layer of the first region 722 Area of ​​the outer layer of the second region L lengthwise T Height direction W width direction

Claims

1. a plurality of dielectric layers stacked one upon the other and a plurality of internal electrode layers stacked one upon the other; a first main surface and a second main surface facing each other in a height direction; a first side surface and a second side surface facing each other in a width direction perpendicular to the height direction; a first end surface and a second end surface facing each other in a length direction perpendicular to the height direction and the width direction; an inner layer portion formed by alternately stacking the dielectric layers and the internal electrode layers; a laminate including outer layer portions arranged to sandwich the inner layer portion from the first principal surface side and the second principal surface side; a first external electrode disposed on the first end surface; a second external electrode disposed on the second end surface; In a multilayer ceramic capacitor having When the internal electrode layer arranged closest to the outer layer portion is defined as the outermost internal electrode layer, the segregation amounts of silicon and magnesium on the outer layer side of the outermost internal electrode layer are greater than the segregation amounts of silicon and magnesium on the inner layer side of the outermost internal electrode layer, When a region defined by a region where the outermost internal electrode layer exists and a region where silicon and magnesium segregate and are in contact with the outermost internal electrode layer is defined as a first region, A multilayer ceramic capacitor, wherein a line edge roughness A on the outer layer side of the first region is larger than a line edge roughness B on the inner layer side of the first region.

2. a ratio (A / C) of a line edge roughness A on the outer layer side of the first region to an average thickness C of the internal electrode layer is defined as D; When the ratio (A / B) of the line edge roughness A on the outer layer side of the first region to the line edge roughness B on the inner layer side of the first region is defined as E, D is equal to or greater than 0.093 and equal to or less than 0.341, 2. The multilayer ceramic capacitor according to claim 1, wherein E is 1.23 or more and 6.70 or less.

3. When the ratio of the area of ​​the outer layer side of the first region to the area of ​​the inner layer side of the first region is F, 3. The multilayer ceramic capacitor according to claim 1, wherein F is 1.1 or more and 3.30 or less.

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