Insulated circuit board

Abstract

To provide an insulated circuit board that has excellent electrical conductivity and thermal conductivity and facilitates handling during soldering by reducing an amount of curvature causing a convex on a side of a circuit layer so as to inhibit peeling of the circuit layer and a heat dissipating layer and cracking of a ceramic substrate.SOLUTION: An insulated circuit board 10 includes a ceramic substrate 11, a circuit layer 12 formed on one surface of the ceramic substrate 11, and a heat dissipating layer 13 formed on the other surface of the ceramic substrate 11. A circuit pattern is formed on the circuit layer 12. The circuit layer 12 has a smaller area than the heat dissipating layer 13. The circuit layer 12 and the heat dissipating layer 13 are composed of a copper material. A ratio N1 / N2 of a maximum crystal grain diameter N1 of the circuit layer 12 and a maximum crystal grain diameter N2 of the heat dissipating layer 13 is 0.6 or less.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an insulating circuit board comprising a ceramic substrate, a circuit layer formed on one surface of the ceramic substrate, and a heat dissipation layer formed on the other surface of the ceramic substrate. [Background technology]

[0002] Currently, semiconductor devices in which semiconductor elements such as transistors, CPUs, and IGBTs are mounted on insulated circuit boards are used in automobiles, railway vehicles, elevators, industrial equipment, etc. Here, the power semiconductor elements used to control high-power electric vehicles and hybrid vehicles generate a large amount of heat, so the insulated circuit boards on which these elements are mounted are required to have high heat dissipation properties. A widely used insulating circuit board is one that includes a ceramic substrate made of, for example, aluminum nitride or silicon nitride, a circuit layer formed by bonding a metal plate with excellent conductivity and heat dissipation properties to one side of the ceramic substrate, and a heat dissipation layer with excellent heat dissipation properties formed on the other side.

[0003] For example, Patent Document 1 proposes an insulating circuit board in which a circuit layer and a heat dissipation layer are formed by bonding copper plates to one surface and the other surface of a ceramic substrate. In Patent Document 1, copper plates are placed on one side and the other side of a ceramic substrate with an Ag-Cu-Ti based brazing filler metal interposed therebetween, and the copper plates are joined by heat treatment (so-called active metal brazing method). In this active metal brazing method, a brazing filler metal containing Ti, which is an active metal, is used, which improves the wettability between the molten brazing filler metal and the ceramic substrate, resulting in good bonding between the ceramic substrate and the copper plate. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 3211856 Summary of the Invention [Problem to be solved by the invention]

[0005] Recently, semiconductor devices in which semiconductor elements are mounted on insulated circuit boards have become smaller and thinner, and the heat generated by the mounted semiconductor elements themselves has also increased, so insulated circuit boards are required to have higher heat dissipation capabilities than ever before. In order to achieve high heat dissipation, it is effective to make the circuit layer and heat dissipation layer thicker. However, if a circuit layer is formed by bonding multiple metal pieces so that a circuit pattern is formed on one side of a ceramic substrate, and a heat dissipation layer is formed by bonding a metal plate without a pattern on the other side, the heat dissipation layer will have a larger volume than the circuit layer, and the thicker the heat dissipation layer, the greater the difference in thermal stress between the heat dissipation layer and the circuit layer, resulting in a greater amount of warping with the circuit layer side convex.

[0006] As the amount of warping increases, there is a problem that this leads to peeling of the metal plate and cracking of the ceramic substrate, which leads to a decrease in electrical insulation and heat dissipation. Furthermore, there is a problem that insulated circuit boards with a large amount of warping, with the circuit layer side being convex, are difficult to handle when soldering IGBTs, SiC, etc.

[0007] The present invention has been made in view of the above-mentioned circumstances, and has an object to provide an insulated circuit board that is excellent in electrical conductivity and thermal conductivity, and that is easy to handle during soldering, by suppressing the amount of warping that causes the circuit layer side to become convex, thereby suppressing peeling of the circuit layer and heat dissipation layer and cracking of the ceramic substrate. [Means for solving the problem]

[0008] In order to solve the above-mentioned problems, the insulated circuit board of aspect 1 of the present invention is an insulated circuit board comprising a ceramic substrate, a circuit layer formed on one side of the ceramic substrate, and a heat dissipation layer formed on the other side of the ceramic substrate, wherein a circuit pattern is formed on the circuit layer, the area of ​​the circuit layer is smaller than that of the heat dissipation layer, the circuit layer and the heat dissipation layer are made of copper material, and the ratio N1 / N2 of the maximum crystal grain size N1 of the circuit layer to the maximum crystal grain size N2 of the heat dissipation layer is 0.6 or less.

[0009] In the insulating circuit board of aspect 1 of the present invention, a circuit pattern is formed on the circuit layer, and the area of ​​the circuit layer is smaller than that of the heat dissipation layer, resulting in a convex warp on the circuit layer side. The circuit layer and the heat dissipation layer are made of copper, and the ratio N1 / N2 of the maximum crystal grain size N1 of the circuit layer to the maximum crystal grain size N2 of the heat dissipation layer is set to 0.6 or less, so the crystal grains in the circuit layer are finer than the crystal grains in the heat dissipation layer, and the yield stress of the circuit layer is greater than that of the heat dissipation layer. This increases the stress required for plastic deformation of the circuit layer, making it possible to minimize the amount of warpage that convexly forms on the circuit layer side. Therefore, peeling of the circuit layer and heat dissipation layer and cracking of the ceramic substrate are suppressed, resulting in excellent electrical conductivity and thermal conductivity, and also making handling during soldering easier.

[0010] The insulating circuit board of aspect 2 of the present invention is the insulating circuit board of aspect 1, characterized in that the Vickers hardness H1 of the circuit layer and the Vickers hardness H2 of the heat dissipation layer are in the range of 20 HV or more and 60 HV or less, and the ratio H1 / H2 of the Vickers hardness H1 of the circuit layer to the Vickers hardness H2 of the heat dissipation layer is in the range of 0.9 or more and 1.1 or less. According to the insulating circuit board of aspect 2 of the present invention, the Vickers hardness H1 of the circuit layer and the Vickers hardness H2 of the heat dissipation layer are within the range of 20 HV or more and 60 HV or less, so that the insulating circuit board has excellent strength and can suppress the occurrence of cracks in the ceramic substrate. Furthermore, the ratio H1 / H2 of the Vickers hardness H1 of the circuit layer to the Vickers hardness H2 of the heat dissipation layer is set within the range of 0.9 or more and 1.1 or less, so there is no difference in Vickers hardness between the circuit layer and the heat dissipation layer, and the occurrence of warping can be further suppressed. [Effects of the Invention]

[0011] According to the present invention, by suppressing the amount of warping that causes the circuit layer side to become convex, it is possible to provide an insulated circuit board that is excellent in electrical conductivity and thermal conductivity, suppresses peeling of the circuit layer and heat dissipation layer, and suppresses cracking of the ceramic substrate, and is easy to handle during soldering. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a schematic explanatory diagram of a power module using an insulating circuit board according to an embodiment of the present invention. FIG. [Figure 2] 1A and 1B are explanatory diagrams of an insulating circuit board according to an embodiment of the present invention, in which (a) is a plan view and (b) is a cross-sectional view. [Figure 3] 1 is a flowchart of a method for manufacturing an insulating circuit board according to an embodiment of the present invention. [Figure 4] 1A to 1C are schematic explanatory views of a method for manufacturing an insulating circuit board according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0013] Insulated circuit boards according to embodiments of the present invention will be described below with reference to the accompanying drawings. The following embodiments are specifically described to provide a better understanding of the spirit of the invention, and unless otherwise specified, do not limit the present invention. Furthermore, the drawings used in the following description may show essential parts enlarged for the sake of clarity, and the dimensional proportions of the components may not necessarily be the same as those in actuality.

[0014] FIG. 1 is a cross-sectional view of a semiconductor device (power module) equipped with an insulating circuit board according to this embodiment. The power module 1 shown in Figure 1 includes an insulating circuit board 10 on which a circuit layer 12 and a heat dissipation layer 13 are arranged, a semiconductor element 3 bonded to one surface (the upper surface in Figure 1) of the circuit layer 12 via a bonding layer 2, and a heat sink 5 arranged on the other side (the lower side in Figure 1) of the heat dissipation layer 13.

[0015] The semiconductor element 3 is made of a semiconductor material such as Si, etc. The semiconductor element 3 and the circuit layer 12 are bonded together via a bonding layer 2. The bonding layer 2 is made of, for example, an Sn--Ag based, Sn--In based, or Sn--Ag--Cu based solder material.

[0016] The heat sink 5 is used to dissipate heat from the insulating circuit board 10. The heat sink 5 is made of copper or a copper alloy, and in this embodiment is made of phosphorus-deoxidized copper. The heat sink 5 is provided with a flow path for a cooling fluid to flow. In this embodiment, the heat sink 5 and the heat dissipation layer 13 are joined together by a solder layer 7 made of a solder material. The solder layer 7 is made of, for example, a Sn—Ag-based, Sn—In-based, or Sn—Ag—Cu-based solder material.

[0017] As shown in Figures 1 and 2, the insulating circuit board 10 of this embodiment includes a ceramic substrate 11, a circuit layer 12 disposed on one surface (the upper surface in Figure 1) of the ceramic substrate 11, and a heat dissipation layer 13 disposed on the other surface (the lower surface in Figure 1) of the ceramic substrate 11. In this embodiment, the circuit layer 12 and the heat dissipation layer 13 are made of a copper material that has excellent electrical and thermal conductivity.

[0018] The ceramic substrate 11 is made of ceramics such as silicon nitride (Si3N4) and aluminum nitride (AlN), which have excellent insulating and heat dissipation properties. In this embodiment, the ceramic substrate 11 is made of silicon nitride (Si3N4), which has particularly excellent heat dissipation properties. The thickness of the ceramic substrate 11 is set, for example, within the range of 0.2 mm to 1.5 mm, and in this embodiment, it is set to 0.32 mm.

[0019] As shown in FIG. 4, the circuit layer 12 is formed by joining a metal plate 22 made of copper or a copper alloy to one surface (the upper surface in FIG. 4) of the ceramic substrate 11. In this embodiment, the circuit layer 12 is formed by bonding a rolled sheet of oxygen-free copper to the ceramic substrate 11.

[0020] As shown in FIG. 4, the heat dissipation layer 13 is formed by joining a metal plate 23 made of copper or a copper alloy to the other surface (the lower surface in FIG. 4) of the ceramic substrate 11. In this embodiment, the heat dissipation layer 13 is formed by bonding a rolled sheet of oxygen-free copper to the ceramic substrate 11.

[0021] In this embodiment, the circuit layer 12 has a circuit pattern formed thereon, as shown in FIG. 2(a), and is structured so that two or more metal plates are arranged, and the area S1 of the circuit layer 12 (the total area in a plan view of the metal plates that make up the circuit layer 12) is smaller than the area S2 of the heat dissipation layer. In the insulating circuit board 10 of this embodiment, as described above, the area S1 of the circuit layer 12 (the total area in a plan view of the metal plates that make up the circuit layer 12) is smaller than the area S2 of the heat dissipation layer, and therefore, a convex warp occurs on the circuit layer 12 side due to the difference in thermal stress caused by the thermal history when the metal plates 22 and 23 are joined.

[0022] In this embodiment, it is preferable that the thickness t1 of the circuit layer 12 and the thickness t2 of the heat dissipation layer 13 are each set within the range of 0.1 mm to 3.0 mm. Furthermore, it is preferable that the ratio t1 / t2 of the thickness t1 of the circuit layer 12 to the thickness t2 of the heat dissipation layer 13 be within a range of 0.3 to 1.4. In this embodiment, the thickness t1 of the circuit layer 12 and the thickness t2 of the heat dissipation layer 13 are both 0.8 mm.

[0023] In insulating circuit board 10 of this embodiment, the ratio N1 / N2 of the maximum crystal grain size N1 of circuit layer 12 made of copper material to the maximum crystal grain size N2 of heat dissipation layer 13 is set to 0.6 or less. That is, in this embodiment, the crystal grains of circuit layer 12 are configured to be finer than the crystal grains of heat dissipation layer 13. The ratio N1 / N2 is preferably 0.5 or less, and more preferably 0.4 or less. There is no particular lower limit to the ratio N1 / N2, but it is 0.1 or more.

[0024] In addition, in insulating circuit board 10 of this embodiment, the ratio D1 / D2 of the average crystal grain size D1 of circuit layer 12 made of a copper material to the average crystal grain size D2 of heat dissipation layer 13 is preferably 0.9 or less. There is no particular lower limit to the ratio D1 / D2, but it is preferably 0.1 or more. Furthermore, in insulating circuit board 10 of this embodiment, it is preferable that the ratio R1 / R2 of the standard deviation R1 of the crystal grain size of circuit layer 12 made of a copper material to the standard deviation R2 of the crystal grain size of heat dissipation layer 13 is 0.5 or less. There is no particular lower limit to the ratio R1 / R2, but it is 0.1 or more.

[0025] In addition, in insulating circuit board 10 of this embodiment, it is preferable that the Vickers hardness H1 of circuit layer 12 and the Vickers hardness H2 of heat dissipation layer 13 are in the range of 20 HV or more and 60 HV or less. When the Vickers hardness H1 of the circuit layer 12 and the Vickers hardness H2 of the heat dissipation layer 13 are 20 HV or more, the circuit layer 12 and the heat dissipation layer 13 are sufficiently hard and resistant to deformation, allowing for good bonding to other components (such as semiconductor elements and heat sinks).On the other hand, when the Vickers hardness H1 of the circuit layer 12 and the Vickers hardness H2 of the heat dissipation layer 13 are 60 HV or less, the circuit layer 12 and the heat dissipation layer 13 are not harder than necessary, preventing cracks from occurring in the ceramic substrate 11 due to thermal stress. The Vickers hardness H1 of the circuit layer 12 and the Vickers hardness H2 of the heat dissipation layer 13 are more preferably 25 HV or more, and even more preferably 30 HV or more. On the other hand, the Vickers hardness H1 of the circuit layer 12 and the Vickers hardness H2 of the heat dissipation layer 13 are more preferably 50 HV or less, and even more preferably 40 HV or less.

[0026] In addition, in insulating circuit board 10 according to this embodiment, the ratio H1 / H2 of the Vickers hardness H1 of circuit layer 12 to the Vickers hardness H2 of heat dissipation layer 13 is preferably within the range of 0.9 to 1.1. That is, in this embodiment, it is preferable that there is no difference in Vickers hardness between circuit layer 12 and heat dissipation layer 13.

[0027] In the insulating circuit board 10 of this embodiment, in order to configure the crystal grain size in the circuit layer 12 and the heat dissipation layer 13 as described above, the copper material constituting the circuit layer 12 and the copper material constituting the heat dissipation layer 13 are different. The circuit layer 12 is made of a copper material that is suppressed from recrystallizing at the bonding temperature (e.g., 800°C) when bonding the ceramic substrate 11 and the metal plate 22, and the heat dissipation layer 13 is made of a copper material that recrystallizes at the bonding temperature (e.g., 800°C) when bonding the ceramic substrate 11 and the metal plate 23. This results in a difference in recrystallization when bonding the metal plates 22, 23 to the ceramic substrate 11, and the crystal grains of the circuit layer 12 become finer than the crystal grains of the heat dissipation layer 13.

[0028] For example, the circuit layer 12 is oxygen-free copper containing elements that suppress recrystallization (e.g., Mg, Al, Si, P, S, Ca, Cr, Mn, Fe, Ni, Co, Zr, Ag, Sn, Sb, Te, etc.) as impurities, with the total content of these impurity elements being within the range of 30 mass ppm or more and 50 mass ppm or less. On the other hand, the heat dissipation layer 13 is made of oxygen-free copper in which the total content of the above-mentioned impurity elements that suppress recrystallization is limited to 20 mass ppm or less.

[0029] A method for manufacturing the insulating circuit board 10 according to this embodiment will be described below with reference to FIGS.

[0030] (Joint material placement process S01) First, a ceramic substrate 11 is prepared, and as shown in Figure 4, a bonding material 25 is disposed between the metal plate 22 that will become the circuit layer 12 and the ceramic substrate 11, and between the metal plate 23 that will become the heat dissipation layer 13 and the ceramic substrate 11. In this embodiment, the bonding material 25 is in a paste form, and is preferably applied by screen printing to the bonding surfaces of the metal plates 22 and 23 and then dried. The thickness of the bonding material 25 after drying is preferably in the range of 10 μm to 50 μm.

[0031] In this embodiment, the bonding material 25 contains Ag and active metals (Ti, Zr, Nb, Hf), and specifically, is an Ag-Ti brazing filler metal (Ag-Cu-Ti brazing filler metal). The Ag-Ti brazing filler metal (Ag-Cu-Ti brazing filler metal) preferably contains Cu in the range of 0% to 45% by mass, Ti as an active metal in the range of 0.5 to 20% by mass, and the balance being Ag and unavoidable impurities.

[0032] (Lamination process S02) Next, the metal plate 22 and the ceramic substrate 11 are laminated with the bonding material 25 interposed therebetween, and the ceramic substrate 11 and the metal plate 23 are laminated with the bonding material 25 interposed therebetween. In this embodiment, a plurality of metal plates 22 that form the circuit layer 12 are arranged on one surface of the ceramic substrate 11 in a circuit pattern.

[0033] (Joining process S03) Next, the stacked metal plate 22, bonding material 25, ceramic substrate 11, bonding material 25, and metal plate 23 are pressed in the stacking direction and placed in a vacuum furnace and heated to generate a liquid phase at the interface between the metal plates 22, 23 and the ceramic substrate 11, and then cooled to solidify the liquid phase, thereby bonding the metal plate 22, ceramic substrate 11, and metal plate 23.

[0034] Here, the bonding temperature in the bonding step S03 is preferably set within a range of 800°C or higher and 850°C or lower. The holding time at the bonding temperature in the bonding step S03 is preferably within a range of 20 minutes to 80 minutes. The pressure load in the joining step S03 is preferably set within a range of 0.029 MPa or more and 2.94 MPa or less.

[0035] The degree of vacuum in the bonding process S03 is 1×10 -6 Pa or more 5×10 -2 It is preferable to set it in the range of Pa or less. The cooling temperature in the bonding step S03 (the cooling rate from the bonding temperature to 780° C., which is the Ag—Cu eutectic temperature) is preferably within the range of 2° C. / min to 20° C. / min.

[0036] As described above, the insulating circuit board 10 of this embodiment is manufactured by the bonding material applying step S01, the laminating step S02, and the bonding step S03.

[0037] According to the insulating circuit board 10 of this embodiment configured as described above, a circuit pattern is formed on the circuit layer 12, and the area S1 of the circuit layer 12 (the total area of ​​the metal plates constituting the circuit layer 12) is smaller than the area of ​​the heat dissipation layer 13, so that a convex warp is formed on the circuit layer 12 side. Since the circuit layer 12 and the heat dissipation layer 13 are made of copper material and the ratio N1 / N2 of the maximum crystal grain size N1 of the circuit layer 12 to the maximum crystal grain size N2 of the heat dissipation layer 13 is set to 0.6 or less, the crystal grains of the circuit layer 12 are finer than the crystal grains of the heat dissipation layer 13, and the yield stress on the circuit layer 12 side is greater than the yield stress of the heat dissipation layer 13. This increases the stress required for plastic deformation of the circuit layer 12, making it possible to minimize the amount of warpage that convexly forms toward the circuit layer 12 side.

[0038] In this embodiment, when the Vickers hardness H1 of the circuit layer 12 and the Vickers hardness H2 of the heat dissipation layer 13 are within the range of 20 HV or more and 60 HV or less, the circuit layer 12 and the heat dissipation layer 13 have excellent strength and are less likely to deform, and can be well bonded to other components (semiconductor element 3 and heat sink 30), while also preventing cracks from occurring in the ceramic substrate due to thermal stress. Furthermore, in this embodiment, when the ratio H1 / H2 of the Vickers hardness H1 of the circuit layer 12 to the Vickers hardness H2 of the heat dissipation layer 13 is within the range of 0.9 or more and 1.1 or less, there is no difference in Vickers hardness between the circuit layer 12 and the heat dissipation layer 13, and the occurrence of warping can be suppressed, making it possible to further reduce the amount of warping that is convex toward the circuit layer 12.

[0039] Although the embodiment of the present invention has been described above, the present invention is not limited to this and can be modified as appropriate within the scope of the technical idea of ​​the invention. For example, in the present embodiment, a power module is described as being configured by mounting a semiconductor element on an insulating circuit board, but the present invention is not limited to this. For example, an LED module may be configured by mounting an LED element on a circuit layer of an insulating circuit board, or a thermoelectric module may be configured by mounting a thermoelectric element on a circuit layer of an insulating circuit board.

[0040] Furthermore, in the insulating circuit board of this embodiment, the ceramic substrate has been described as being made of silicon nitride (Si3N4), but this is not limitative and other ceramic substrates such as aluminum nitride (AlN) and alumina (Al2O3) may also be used.

[0041] Furthermore, in this embodiment, a configuration has been described in which a circuit layer is formed by joining multiple metal plates made of copper material in a circuit pattern to one surface of a ceramic substrate, but this is not limited to this, and a single metal plate may be joined to one surface of a ceramic substrate, and then a circuit pattern may be formed by etching.

[0042] In addition, in this embodiment, the copper material constituting the circuit layer and the heat dissipation layer has been described as having different compositions, but this is not limited to this, and it is sufficient that the ratio N1 / N2 of the maximum crystal grain size N1 of the circuit layer to the maximum crystal grain size N2 of the heat dissipation layer is 0.6 or less, and the crystal grain size may be controlled by adjusting the heat treatment conditions of the copper material, etc. [Example]

[0043] The results of confirmation experiments conducted to confirm the effects of the present invention will be described below.

[0044] First, a ceramic substrate (40 mm x 40 mm x 0.32 mm thick) made of Si3N4 was prepared. Additionally, the metal plates shown in Table 1 were prepared as copper plates to serve as the circuit layer and heat dissipation layer. The metal plate to serve as the circuit layer was 18 mm x 23 mm x 0.8 mm thick, and the metal plate to serve as the heat dissipation layer was 18 mm x 46 mm x 0.8 mm thick. As a bonding material, Ag-Ti paste (Ag-0.7 mass % Ti) was placed between the ceramic substrate and the metal plate to obtain a laminate of metal plate / ceramic substrate / metal plate.

[0045] For the above laminate, vacuum level: 1.0 x 10 -3The metal plate and ceramic substrate were bonded under pressure and heat treatment under the following conditions: Pa, pressure load in the stacking direction: 0.2 MPa, bonding temperature: 830°C, holding time: 30 minutes, cooling rate to 780°C: 3°C / min, to produce an insulated circuit board.

[0046] The obtained insulating circuit board was evaluated as follows, and the evaluation results are shown in Tables 1 and 2.

[0047] (Evaluation of crystal grain size) The ceramic substrate with the circuit layer and heat dissipation layer bonded was surface treated by immersing it in 60vol% pure nitric acid for 1 to 3 minutes. The surface was observed at 40x magnification using a microscope (Keyence VHX), and three 5mm lines were drawn randomly. The maximum diameter of the crystal grains where they intersected was measured, and the average was taken as the crystal grain size.

[0048] (Method for calculating maximum crystal grain size) Using a microscope (Keyence VHX) at 20x magnification, the maximum crystal grain size in the circuit layer and the maximum crystal grain size in the heat dissipation layer were searched for and measured. The grain size was calculated by taking the longest length of the crystal grain as the maximum crystal grain size.

[0049] (Vickers hardness) The Vickers hardness of the circuit layer and the heat dissipation layer was evaluated using a Vickers hardness tester (Shimada Manufacturing Co., Ltd. HSV-30). The evaluation conditions were a load of 294.21 N and a pressing time of 15 seconds. The calculation method was in accordance with JIS R 1610.

[0050] (Warpage amount) The amount of warpage was evaluated at room temperature using a shadow moire device (TherMoire AXP2.0 manufactured by Akrometrix). The measurement surface was the heat dissipation layer side, and the value of the maximum height - minimum height of the heat dissipation layer was taken as the amount of warpage.

[0051] [Table 1]

[0052] [Table 2]

[0053] In Comparative Examples 1 and 2, the ratio N1 / N2 of the maximum crystal grain size N1 of the circuit layer to the maximum crystal grain size N2 of the heat dissipation layer exceeded 0.6, and the amount of warpage that was convex toward the circuit layer side increased. In contrast, in Examples 1-6 of the present invention, the ratio N1 / N2 of the maximum crystal grain size N1 of the circuit layer to the maximum crystal grain size N2 of the heat dissipation layer was set to 0.6 or less, and the amount of warp that was convex toward the circuit layer side was kept small.

[0054] From the results of the above confirmatory experiments, it was confirmed that according to the present invention, by suppressing the amount of warping that causes the circuit layer side to become convex, it is possible to provide an insulated circuit board that has excellent electrical conductivity and thermal conductivity, suppresses peeling of the circuit layer and heat dissipation layer, and cracks in the ceramic substrate, and is easy to handle during soldering. [Explanation of symbols]

[0055] 10. Insulated circuit board 11 Ceramic substrate 12 circuit layers 13 Heat dissipation layer

Claims

1. An insulating circuit board comprising: a ceramic substrate; a circuit layer formed on one surface of the ceramic substrate; and a heat dissipation layer formed on the other surface of the ceramic substrate, a circuit pattern is formed on the circuit layer, and the area of ​​the circuit layer is smaller than that of the heat dissipation layer; An insulated circuit board characterized in that the circuit layer and the heat dissipation layer are made of copper material, and the ratio N1 / N2 of the maximum crystal grain size N1 of the circuit layer to the maximum crystal grain size N2 of the heat dissipation layer is 0.6 or less.

2. a Vickers hardness H1 of the circuit layer and a Vickers hardness H2 of the heat dissipation layer are in the range of 20 HV or more and 60 HV or less; 2. The insulating circuit board according to claim 1, wherein the ratio H1 / H2 of the Vickers hardness H1 of the circuit layer to the Vickers hardness H2 of the heat dissipation layer is in the range of 0.9 to 1.1.

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