Electronic device

Abstract

To provide an electronic device capable of reducing poor bonding between two chips.SOLUTION: An electronic device includes: a first chip having a first substrate having a first surface and a wiring part having a wiring layer and provided on the first surface; a second chip having a second substrate having a second surface facing the wiring part in a first direction; a connection part provided between the wiring part and the second surface and electrically connected to the wiring layer; and a bonding part provided between the wiring part and the second surface and bonding the first chip and the second chip. The connection part has a capacitive coupling structure in which the metal parts respectively provided on the wiring part and the second surface face each other in the first direction with a gap therebetween.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to electronic devices. [Background technology]

[0002] Devices are known in which two chips are joined by metal-to-metal bonding. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-282038 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of an embodiment of the present invention is to provide an electronic device that can reduce bonding failures between two chips. [Means for solving the problem]

[0005] According to an embodiment of the present invention, an electronic device comprises a first chip having a first substrate with a first surface, a wiring portion having a wiring layer and provided on the first surface, a second chip having a second substrate with a second surface facing the wiring portion in a first direction, a connection portion provided between the wiring portion and the second surface and electrically connected to the wiring layer, and a joint portion provided between the wiring portion and the second surface and joining the first chip and the second chip, wherein the connection portion has a capacitive coupling structure in which metal portions provided on the wiring portion and the second surface, respectively, face each other in the first direction across a gap. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional view of an electronic device according to a first embodiment. [Figure 2]FIG. 10 is a schematic plan view of an electronic device according to a second embodiment. [Figure 3] 3 is a cross-sectional view taken along the line AA in FIG. 2. [Figure 4] 3 is a cross-sectional view of FIG. 2 taken along line B-B. [Figure 5] 3 is a cross-sectional view taken along CC in FIG. 2. [Figure 6] 10 is a graph showing the results of simulation 1. [Figure 7] 10 is a graph showing the results of simulation 2. DETAILED DESCRIPTION OF THE INVENTION

[0007] Each embodiment will be described below with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. Furthermore, identical or similar elements are given the same reference numerals.

[0008] [First embodiment] 1, the electronic device 1 of the first embodiment includes a first chip 101, a second chip 102, a first connecting portion 31, a second connecting portion 32, and a bonding portion 90. A plurality of bonding portions 90 are provided between the first chip 101 and the second chip 102. The first chip 101 and the second chip 102 are bonded to each other via the bonding portions 90 and stacked in a first direction Z. Two directions perpendicular to the first direction Z are defined as a second direction X and a third direction Y. The second direction X and the third direction Y are perpendicular to each other.

[0009] First chip 101 has first substrate 11 and wiring section 40. First substrate 11 has first surface 11A. First substrate 11 is, for example, a silicon substrate.

[0010] The wiring section 40 is provided on the first surface 11A. The wiring section 40 has an insulating layer 42 and a wiring layer 41 provided in the insulating layer 42. The wiring section 40 has, for example, a multi-layer wiring structure, and the wiring layers 41 on different layers are electrically connected to each other by conductive vias.

[0011] The second chip 102 has a second substrate 12 and an element portion 80. The second substrate 12 has a second surface 12A facing the wiring portion 40 in the first direction Z. The second substrate 12 is, for example, a silicon substrate. The wiring portion 40 is located between the first surface 11A and the second surface 12A in the first direction Z.

[0012] The element portion 80 is provided on the second surface 12A. The element portion 80 is located between the wiring portion 40 and the second surface 12A in the first direction Z. The element portion 80 has a first electrode 81 and a second electrode 82. The element portion 80 includes, for example, an n-type semiconductor layer and a p-type semiconductor layer provided on the second surface 12A side, and has functions such as a diode, a transistor, a light-emitting element, and a light-receiving element. Different potentials are applied to the first electrode 81 and the second electrode 82.

[0013] The first connection portion 31 and the second connection portion 32 are provided between the wiring portion 40 and the second surface 12A, and are electrically connected to the wiring layer 41.

[0014] The first connection portion 31 has a first metal portion 21 and a second metal portion 22. The first metal portion 21 is provided on the wiring portion 40 and is electrically connected to the wiring layer 41 through a conductive via. The second metal portion 22 contacts the first electrode 81 of the second chip 102 and is electrically connected to the first electrode 81. The first connection portion 31 has a capacitive coupling structure in which the metal portions face each other in the first direction Z with a gap g between them. The first metal portion 21 and the second metal portion 22 face each other in the first direction Z with a gap g between them. The gap g is an air gap.

[0015] The second connection portion 32 has a third metal portion 23 and a fourth metal portion 24. The third metal portion 23 is provided on the wiring portion 40 and is electrically connected to the wiring layer 41 through a conductive via. The fourth metal portion 24 contacts the second electrode 82 of the second chip 102 and is electrically connected to the second electrode 82. The second connection portion 32 has a capacitive coupling structure in which the metal portions face each other in the first direction Z with a gap g between them. The third metal portion 23 and the fourth metal portion 24 face each other in the first direction Z with a gap g between them.

[0016] Gold, for example, can be used as the material for the first metal portion 21, the second metal portion 22, the third metal portion 23, and the fourth metal portion 24. The first metal portion 21 and the third metal portion 23 are located apart from each other on the wiring portion 40. Different potentials are applied to the first metal portion 21 and the third metal portion 23 through the wiring layer 41. For example, a positive potential is applied to the first metal portion 21, and a ground potential (0 V) is applied to the third metal portion 23.

[0017] The first chip 101 is a control chip that controls the element unit 80. A control circuit including semiconductor transistors and the like is formed on the first surface 11A side of the first substrate 11, and the control circuit is electrically connected to the wiring layer 41. A first electrode 81 of the element unit 80 is electrically connected to the wiring layer 41 via a first connection portion 31. A second electrode 82 of the element unit 80 is electrically connected to the wiring layer 41 via a second connection portion 32. A ground potential, for example, is applied to the first substrate 11 and the second substrate 12.

[0018] For example, a plurality of element portions 80 are provided on second surface 12A of second substrate 12. Therefore, a plurality of first connection portions 31 and a plurality of second connection portions 32 are provided between first chip 101 and second chip 102.

[0019] A plurality of bonding portions 90 are provided between the wiring portion 40 of the first chip 101 and the second surface 12A of the second chip 102. The plurality of bonding portions 90 are provided around and between the plurality of element portions 80. For example, a first bonding portion 91 is formed on the wiring portion 40, a second bonding portion 92 is formed on the second surface 12A, the first bonding portion 91 and the second bonding portion 92 are brought into contact with each other, a load is applied to the first bonding portion 91 and the second bonding portion 92 in the first direction Z, and heating is performed as necessary to bond the first bonding portion 91 and the second bonding portion 92 together. The first chip 101 and the second chip 102 are bonded to each other by the plurality of bonding portions 90 integrated by bonding the first bonding portion 91 and the second bonding portion 92 together. The height (thickness in the first direction Z) of the first bonding portion 91 is set to be greater than the height (thickness in the first direction Z) of the first metal portion 21 and the height (thickness in the first direction Z) of the third metal portion 23. The height (thickness in the first direction Z) of the second joint portion 92 is greater than the height (thickness in the first direction Z) of the second metal portion 22 and the height (thickness in the first direction Z) of the fourth metal portion 24. Examples of materials and joining methods for the joint portion 90 will be described later.

[0020] As a comparative example, the first connection portion 31 and the second connection portion 32, which electrically connect the first chip 101 and the second chip 102, can also be used as a joining member to join the first chip 101 and the second chip 102. In this case, the first metal portion 21 and the second metal portion 22 are brought into contact with each other, and the third metal portion 23 and the fourth metal portion 24 are brought into contact with each other, and a load is applied to these metal portions in the first direction Z, and heating is applied, thereby directly joining the first metal portion 21 and the second metal portion 22, and directly joining the third metal portion 23 and the fourth metal portion 24. As the number of joining points between the metal portions increases, the contact area between the metal portions increases. When there is a limit to the load that can be applied by the joining device, the increased contact area between the metal portions results in an insufficient load for joining, making joining more likely to fail.

[0021] According to this embodiment, the first connecting portion 31 and the second connecting portion 32 are not joined to each other, but are capacitively coupled via a gap g. The first chip 101 and the second chip 102 are joined by a joint 90 provided separately from the first connecting portion 31 and the second connecting portion 32. While the first connecting portion 31 and the second connecting portion 32, which electrically connect the first chip 101 and the second chip 102, are limited in material and number, the joint 90 does not need to be conductive, and the number of joints 90 may be fewer than the number of electrodes 81, 82 of the second chip 102. A material that can be bonded with a lower load can be selected for the joint 90, and by reducing the number of joints 90, a sufficient load can be applied to the joints 90. This reduces poor bonding.

[0022] Furthermore, a first wafer including the configuration of the first chip 101 and a second wafer including the configuration of the second chip 102 can be bonded at the wafer level via bonding portion 90 and diced into individual electronic devices 1. This can improve throughput and reduce the cost of the electronic devices 1.

[0023] A voltage obtained by subtracting the voltage division amount applied to the capacitance of the connection parts 31 and 32 is applied between the first electrode 81 and the second electrode 82. At the connection parts 31 and 32, an appropriate voltage can be applied between the first electrode 81 and the second electrode 82 by optimizing the capacitance value by adjusting the size of the gap g in the first direction Z, for example.

[0024] [Second embodiment] FIG. 2 is a schematic plan view of an electronic device 2 according to the second embodiment. Fig. 3 is a cross-sectional view taken along the line AA in Fig. 2. Fig. 3 shows a cross section of a portion where the first connection portion 31 is arranged. Fig. 4 is a cross-sectional view taken along line BB in Fig. 2. Fig. 4 shows a cross section of a portion where the second connection portion 32 is arranged. Fig. 5 is a cross-sectional view taken along CC in Fig. 2. Fig. 5 shows a cross section of a portion where a joint 90 is arranged.

[0025] The electronic device 2 of the second embodiment includes a first chip 201, a second chip 202, a first connecting portion 31, a second connecting portion 32, and a bonding portion 90. A plurality of bonding portions 90 are provided between the first chip 201 and the second chip 202. The first chip 201 and the second chip 202 are bonded to each other via the bonding portions 90 and stacked in the first direction Z.

[0026] The first chip 201 has a first substrate 11 and a wiring portion 40. The first substrate 11 has a first surface 11A. The first substrate 11 is, for example, a silicon substrate. The first chip 201 has a first penetrating portion h1 that penetrates the first substrate 11 and the wiring portion 40 in the first direction Z.

[0027] The wiring section 40 is provided on the first surface 11A. The wiring section 40 has an insulating layer 42 and a wiring layer provided in the insulating layer 42. The wiring layer has a first wiring layer 41A and a second wiring layer 41B. The wiring section 40 has, for example, a multi-layer wiring structure, and different wiring layers are electrically connected to each other by conductive vias.

[0028] The second chip 202 has a second substrate 12, a first electrode 51, and a second electrode 52. The second substrate 12 has a second surface 12A facing the wiring unit 40 in the first direction Z. The second substrate 12 is, for example, a silicon substrate. The wiring unit 40 is located between the first surface 11A and the second surface 12A in the first direction Z. The second chip 202 has a second through portion h2 penetrating the second substrate 12 in the first direction Z. The first through portion h1 of the first chip 201 and the second through portion h2 of the second chip 202 are aligned in the first direction Z and form a through hole H in the electronic device 2. The through hole H penetrates the second substrate 12, the wiring unit 40, and the first substrate 11 in the first direction Z. For example, a ground potential is applied to the first substrate 11 and the second substrate 12.

[0029] A first conductive film 61 and a second conductive film 62 are provided on the second surface 12A of the second substrate 12, with an insulating film 70 interposed therebetween. A first electrode 51 and a second electrode 52 are provided on the inner surface 12C of the second penetrating portion h2, with the insulating film 70 interposed therebetween. The insulating film 70 is, for example, a silicon oxide film. The insulating film 70 is provided between the second surface 12A and the first conductive film 61, between the second surface 12A and the second conductive film 62, between the inner surface 12C and the first electrode 51, and between the inner surface 12C and the second electrode 52. Note that if the second substrate 12 has insulating properties, the insulating film 70 need not be provided.

[0030] 2, the first electrode 51 and the second electrode 52 are separated from each other in the circumferential direction of the inner surface 12C on the inner surface 12C of the second through portion h2. The first conductive film 61 and the second conductive film 62 are separated from each other on the second surface 12A by an insulating film 70. The first electrode 51 is electrically connected to the first conductive film 61. The second electrode 52 is electrically connected to the second conductive film 62. Different potentials are applied to the first electrode 51 and the second electrode 52.

[0031] As shown in FIG. 3 , the first connection portion 31 is provided between the wiring portion 40 and the second surface 12A, and includes a first metal portion 21 and a second metal portion 22. The first metal portion 21 is provided on the wiring portion 40 and is electrically connected to the first wiring layer 41A through a conductive via. The second metal portion 22 is in contact with the first conductive film 61 and is electrically connected to the first conductive film 61. The second metal portion 22 is electrically connected to the first electrode 51 through the first conductive film 61. The first connection portion 31 has a capacitive coupling structure in which the metal portions face each other in the first direction Z with a gap g between them. The first metal portion 21 and the second metal portion 22 face each other in the first direction Z with the gap g between them.

[0032] As shown in FIG. 4, the second connection portion 32 is provided between the wiring portion 40 and the second surface 12A and has a third metal portion 23 and a fourth metal portion 24. The third metal portion 23 is provided on the wiring portion 40 and is electrically connected to the second wiring layer 41B through a conductive via. The fourth metal portion 24 is in contact with the second conductive film 62 and is electrically connected to the second conductive film 62. The fourth metal portion 24 is electrically connected to the second electrode 52 through the second conductive film 62. The second connection portion 32 has a capacitive coupling structure in which the metal portions face each other in the first direction Z with a gap g between them. The third metal portion 23 and the fourth metal portion 24 face each other in the first direction Z with a gap g between them.

[0033] Different potentials are applied to the first metal portion 21 and the third metal portion 23. For example, a positive potential is applied to the first metal portion 21 through the first wiring layer 41A, and a ground potential is applied to the third metal portion 23 through the second wiring layer 41B.

[0034] 2 and 5, a plurality of bonding portions 90 are provided between the wiring portion 40 of the first chip 201 and the second surface 12A of the second chip 202. For example, a first bonding portion 91 is formed on the wiring portion 40, a second bonding portion 92 is formed on the second surface 12A, the first bonding portion 91 and the second bonding portion 92 are brought into contact with each other, a load is applied to the first bonding portion 91 and the second bonding portion 92 in the first direction Z, and heating is performed as necessary, thereby bonding the first bonding portion 91 and the second bonding portion 92 together. The first chip 201 and the second chip 202 are bonded to each other by the plurality of bonding portions 90 that are integrated by bonding the first bonding portion 91 and the second bonding portion 92 together.

[0035] As shown in FIG. 2 , the electronic device 2 includes a plurality of through holes H, a plurality of first connection portions 31, a plurality of second connection portions 32, and a plurality of bonding portions 90. The plurality of through holes H are aligned in the second direction X and the third direction Y. One first conductive film 61 is arranged in a one-to-one correspondence with each through hole H. One first connection portion 31 is arranged in contact with the first conductive film 61 in a one-to-one correspondence with each through hole H. One through hole H is located between adjacent first connection portions 31 in the third direction Y. One through hole H is located between adjacent second connection portions 32 in the second direction X. Two second connection portions 32 are arranged for one through hole H, sandwiching the through hole H in the second direction X. The number of second connection portions 32 is greater than the number of first connection portions 31. The potentials of the plurality of second electrodes 52 can be collectively controlled via the plurality of second connection portions 32 and the common second conductive film 62. The potential of each of the plurality of first electrodes 51 is individually controlled through the corresponding first connection portion 31 and first conductive film 61.

[0036] The joints 90 are arranged between adjacent first connection portions 31 in the second direction X and between adjacent second connection portions 32 in the third direction Y. The number of the joints 90 may be smaller than the number of the connection portions 31, 32.

[0037] The electronic device 2 of the second embodiment can be used as a pixel array for deflecting electron beams in a multi-electron beam exposure apparatus that uses multiple electron beams to write a pattern on a resist on a substrate such as glass. The electron beams pass through the through-holes H. The electron beams passing through the through-holes H can be deflected by an electric field generated between the first electrode 51 and the second electrode 52.

[0038] By joining two chips (first chip 201 and second chip 202) each having a through-hole, it is possible to form an electronic device 2 having a deep through-hole that would be difficult to form in a single chip.

[0039] In a multi-electron beam exposure apparatus, the trend toward an increased number of pixels, which increases the number of through holes H, also increases the number of connecting parts, and the contact area between metal parts tends to increase.

[0040] According to this embodiment, the first connecting portion 31 and the second connecting portion 32 are not joined to each other, but are capacitively coupled via a gap g. The first chip 201 and the second chip 202 are joined by a joint 90 provided separately from the first connecting portion 31 and the second connecting portion 32. While the first connecting portion 31 and the second connecting portion 32, which electrically connect the first chip 201 and the second chip 202, are restricted in material and number, the joint 90 does not need to be conductive, and the number of joints 90 may be fewer than the number of electrodes 51, 52 of the second chip 202. A material that can be bonded with a lower load can be selected for the joint 90, and by reducing the number of joints 90, a sufficient load can be applied to the joints 90. This reduces poor bonding.

[0041] Furthermore, a first wafer including the configuration of the first chip 201 and a second wafer including the configuration of the second chip 202 can be bonded at the wafer level via bonding portion 90 and separated into individual electronic devices 2. This can improve throughput and reduce the cost of the electronic devices 2.

[0042] A voltage obtained by subtracting the voltage division amount applied to the capacitance of the connection parts 31 and 32 is applied between the first electrode 51 and the second electrode 52. At the connection parts 31 and 32, an appropriate voltage can be applied between the first electrode 51 and the second electrode 52 by optimizing the capacitance value by adjusting the size of the gap g in the first direction Z, for example.

[0043] (Simulation 1) Using a cross-sectional structure in which first electrode 51 and second electrode 52 face each other across through hole H as a model, the potential was calculated by simulation when 5 V was applied to first metal portion 21 and 0 V was applied to third metal portion 23, first substrate 11, and second substrate 12. The results are shown in FIG.

[0044] 6, x=0 on the horizontal axis represents a position 3 μm from the first electrode 51 toward the second electrode 52. The inner surface of the first electrode 51 facing the second electrode 52 is at a position x=3 μm, and the inner surface of the second electrode 52 facing the first electrode 51 is at a position x=−3 μm. The position of x=0 coincides with the central axis of the through hole H.

[0045] Graph a shows the results for a structure in which the size of the gap g (size in the first direction Z) between the first connecting portion 31 and the second connecting portion 32 is zero. Graph b shows the results for a structure in which the size of the gap g is 0.1 μm. Graph c shows the results for a structure in which the size of the gap g is 0.05 μm. d shows the results for a structure in which the size of the gap g is 0.005 μm.

[0046] 6, the smaller the gap g, the smaller the potential drop compared to structure a without gap g. In structure d, where the gap g is 0.005 μm, the potential can be improved to approximately 84% of the potential of structure a without gap g.

[0047] (Simulation 2) Using the same model as Simulation 1, we estimated the time constant when writing 5V to the first electrode 51 (deflection electrode). The time constant is the product of the wiring resistance and the load capacitance, and if the wiring resistance is the same, it is thought that the time constant is determined by the magnitude of the load capacitance. From the results in Figure 7, we can see that the smaller the gap g, the smaller the load capacitance, and the shorter the time it takes to write to the deflection electrode.

[0048] An example of the material and joining method for the joining portion 90 will be described below.

[0049] A resin member can be used for the bonding portion 90. For example, a photosensitive resist can be used for the resin member of the bonding portion 90. A resist film is formed on each of the first chips 101, 201 and the second chips 102, 202 by, for example, spin coating. The resist film is then pre-baked to semi-harden it. The resist film is then patterned into the first bonding portion 91 and the second bonding portion 92 by exposure and development. The first bonding portion 91 and the second bonding portion 92 are then brought into contact with each other, and a load is applied to the first bonding portion 91 and the second bonding portion 92 in the first direction Z, followed by heating. As a result, the first bonding portion 91 and the second bonding portion 92 are completely hardened and thermocompression-bonded to form the bonding portion 90, bonding the first chips 101, 201 and the second chips 102, 202. Before completely curing by heating, misalignment is checked while the first bonding portion 91 and the second bonding portion 92 are in contact with each other, and if necessary, the first bonding portion 91 and the second bonding portion 92 are peeled off and brought into contact again, and this checking for misalignment can be repeated until satisfactory alignment is achieved. Misalignment can be checked, for example, using alignment marks formed on the first chips 101, 201 side and the second chips 102, 202 side.

[0050] The bonding portion 90 may be made of an inorganic material. For example, a silicon oxide film may be used as the inorganic material for the bonding portion 90. The first bonding portion 91 and the second bonding portion 92 are formed of an inorganic film (e.g., a silicon oxide film) on the first chip 101, 201 side and the second chip 102, 202 side, respectively. Then, the first bonding portion 91 and the second bonding portion 92 are subjected to a plasma treatment using, for example, Ar. This plasma treatment removes surface contamination and exposes dangling bonds of Si on the surface of the silicon oxide film, for example. Then, the first bonding portion 91 and the second bonding portion 92 are brought into contact with each other, and a load is applied to the first bonding portion 91 and the second bonding portion 92 in the first direction Z, followed by heating. Due to the bonding between Si, the first bonding portion 91 and the second bonding portion 92 are thermocompression-bonded to form the bonding portion 90, bonding the first chip 101, 201 to the second chip 102, 202. By using an inorganic member that is harder than a resin member and a metal member as the joint 90, the joint 90 is less likely to be crushed by the load during joining, and the size of the gap g in the connecting portions 31 and 32 is easier to control.

[0051] A metal member can be used for the joint 90. Examples of the metal member for the joint 90 include gold, copper, and solder. The first and second joints 91 and 92 are formed on the first chips 101 and 201 and the second chips 102 and 202, respectively, using a metal member. The first and second joints 91 and 92 are then brought into contact with each other, and a load is applied to the first and second joints 91 and 92 in the first direction Z. The joints are then heated. The first and second joints 91 and 92 are then integrated to form the joint 90, bonding the first chips 101 and 201 to the second chips 102 and 202. Before applying the load and heat, the first and second joints 91 and 92 are checked for misalignment while in contact with each other, and if necessary, the first and second joints 91 and 92 are separated and re-contacted to check for misalignment. This process can be repeated until satisfactory alignment is achieved. Metallic members are less likely to become charged than resinous and inorganic members, so abnormal deflection of the electron beam can be easily suppressed when a metallic member is used for the joint 90. When gold, which is less likely to oxidize among metallic members, is used, the joint 90 can be made even less likely to become charged.

[0052] The plurality of first connection portions 31 and the plurality of second connection portions 32 may include connection portions in which metal portions facing each other in the first direction Z are not joined but at least partially contact each other.

[0053] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0054] 1, 2...electronic device, 11...first substrate, 11A...first surface, 12...second substrate, 12A...second surface, 12C...inner surface, 21...first metal portion, 22...second metal portion, 23...third metal portion, 24...fourth metal portion, 31...first connection portion, 32...second connection portion, 40...wiring portion, 41...wiring layer, 41A...first wiring layer, 41B...second wiring layer, 51...first electrode, 52...second electrode, 61...first conductive film, 62...second conductive film, 70...insulating film, 80...element portion, 81...first electrode, 82...second electrode, 90...junction portion, 91...first joint portion, 92...second joint portion, 101...first chip, 102...second chip, 201...first chip, 202...second chip, g...gap, H...through hole

Claims

1. a first chip including a first substrate having a first surface, and a wiring portion having a wiring layer and provided on the first surface; a second chip having a second substrate having a second surface facing the wiring portion in the first direction; a connection portion provided between the wiring portion and the second surface and electrically connected to the wiring layer; a bonding portion provided between the wiring portion and the second surface, the bonding portion bonding the first chip and the second chip; Equipped with The electronic device, wherein the connection portion has a capacitive coupling structure in which metal portions provided on the wiring portion and the second surface, respectively, face each other in the first direction across a gap.

2. the connection portion has a first connection portion and a second connection portion to which different potentials are applied, The electronic device is a through hole penetrating the first substrate, the wiring portion, and the second substrate in the first direction; a first electrode provided on an inner surface of the through hole penetrating the second substrate and electrically connected to the first connection portion; a second electrode provided on an inner surface of the through hole penetrating the second substrate and electrically connected to the second connection portion; The electronic device of claim 1 further comprising:

3. a first conductive film provided on the second surface of the second substrate and electrically connected to the first electrode and the first connection portion; a second conductive film provided on the second surface of the second substrate and electrically connected to the second electrode and the second connection portion; The electronic device of claim 2 further comprising:

4. the second substrate is a silicon substrate, 4. The electronic device according to claim 3, further comprising insulating films provided between the inner surface of the through hole and the first electrode, between the inner surface of the through hole and the second electrode, between the second surface and the first conductive film, and between the second surface and the second conductive film.

5. The electronic device according to claim 2 , comprising a plurality of the through holes, a plurality of the first connection portions, and a plurality of the second connection portions.

6. one first connection portion is arranged in one-to-one correspondence with one of the through holes, The electronic device according to claim 5 , wherein the number of the second connecting portions is greater than the number of the first connecting portions.

7. The electronic device according to claim 1 , wherein the joint is a resin member.

8. The electronic device according to claim 1 , wherein the bonding portion is an inorganic material.

9. The electronic device according to claim 1 , wherein the joint is a metal member.

10. The electronic device according to claim 1 , wherein the size of the gap in the first direction is 0.005 μm or less.

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