Electronic device

Abstract

To provide an electronic device capable of reducing poor bonding between two chips.SOLUTION: An electronic device includes: a first substrate; a second substrate; a wiring part provided on a first surface of the first substrate; a first connection part having a first metal part provided on the wiring part and a second metal part provided on a second surface of the second substrate and opposed to the first metal part in a first direction; a third metal part provided on the wiring part; and a second connection part having a fourth metal part provided on the second surface of the second substrate and opposed to the third metal part in the first direction. One of the first connection part and the second connection part has a bonding structure of the metal parts, and the other of the first connection part and the second connection part is capacitively coupled via a gap.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to electronic devices. [Background technology]

[0002] Devices are known in which two chips are joined by metal-to-metal bonding. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-282038 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of an embodiment of the present invention is to provide an electronic device that can reduce bonding failures between two chips. [Means for solving the problem]

[0005] According to an embodiment of the present invention, an electronic device comprises a first substrate having a first surface, a second substrate having a second surface, a wiring portion provided on the first surface and positioned between the first surface and the second surface in a first direction and having a wiring layer, a first connection portion having: a first metal portion provided on the wiring portion and electrically connected to the wiring layer, and a second metal portion provided on the second surface of the second substrate and facing the first metal portion in the first direction, and a second connection portion having: a third metal portion provided on the wiring portion and electrically connected to the wiring layer, and a fourth metal portion provided on the second surface of the second substrate and facing the third metal portion in the first direction, wherein one of the first connection portion and the second connection portion is a joint structure between metal portions, and the other of the first connection portion and the second connection portion is capacitively coupled via a gap. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional view of an electronic device according to a first embodiment. [Figure 2] FIG. 10 is a schematic plan view of an electronic device according to a second embodiment. [Figure 3] 3 is a cross-sectional view taken along the line AA in FIG. 2. [Figure 4] 3 is a cross-sectional view of FIG. 2 taken along line B-B. [Figure 5] 10 is a graph showing the results of simulation 1. [Figure 6] 10 is a graph showing the results of simulation 2. [Figure 7] 10 is a graph showing the results of Simulation 3. DETAILED DESCRIPTION OF THE INVENTION

[0007] Each embodiment will be described below with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. Furthermore, identical or similar elements are given the same reference numerals.

[0008] [First embodiment] As shown in Fig. 1, the electronic device 1 of the first embodiment includes a first chip 101, a second chip 102, a first connecting portion 31, and a second connecting portion 32. The first chip 101 and the second chip 102 are joined via one of the first connecting portion 31 and the second connecting portion 32 (first connecting portion 31 in the example shown in Fig. 1), and are stacked in a first direction Z. Two directions perpendicular to the first direction Z are defined as a second direction X and a third direction Y. The second direction X and the third direction Y are perpendicular to each other.

[0009] First chip 101 has first substrate 11 and wiring section 40. First substrate 11 has first surface 11A. First substrate 11 is, for example, a silicon substrate.

[0010] The wiring section 40 is provided on the first surface 11A. The wiring section 40 has an insulating layer 42 and a wiring layer 41 provided in the insulating layer 42. The wiring section 40 has, for example, a multi-layer wiring structure, and the wiring layers 41 on different layers are electrically connected to each other by conductive vias.

[0011] The second chip 102 has a second substrate 12 and an element portion 80. The second substrate 12 has a second surface 12A. The second substrate 12 is, for example, a silicon substrate. The wiring portion 40 is located between the first surface 11A and the second surface 12A in the first direction Z.

[0012] The element portion 80 is provided on the second surface 12A. The element portion 80 is located between the wiring portion 40 and the second surface 12A in the first direction Z. The element portion 80 has a first electrode 81 and a second electrode 82. The element portion 80 includes, for example, an n-type semiconductor layer and a p-type semiconductor layer provided on the second surface 12A side, and has functions such as a diode, a transistor, a light-emitting element, and a light-receiving element. Different potentials are applied to the first electrode 81 and the second electrode 82.

[0013] The first connection portion 31 has a first metal portion 21 and a second metal portion 22. The first metal portion 21 is provided on the wiring portion 40 and is electrically connected to the wiring layer 41 through a conductive via. The second metal portion 22 is provided on the second surface 12A of the second substrate 12 and faces the first metal portion 21 in the first direction Z. The second metal portion 22 contacts the first electrode 81 of the second chip 102 and is electrically connected to the first electrode 81.

[0014] The second connection portion 32 has a third metal portion 23 and a fourth metal portion 24. The third metal portion 23 is provided on the wiring portion 40 and is electrically connected to the wiring layer 41 through a conductive via. The fourth metal portion 24 is provided on the second surface 12A of the second substrate 12 and faces the third metal portion 23 in the first direction Z. The fourth metal portion 24 contacts the second electrode 82 of the second chip 102 and is electrically connected to the second electrode 82.

[0015] The first metal portion 21 and the third metal portion 23 are located apart from each other on the wiring portion 40. Different potentials are applied to the first metal portion 21 and the third metal portion 23 through the wiring layer 41. For example, a positive potential is applied to the first metal portion 21, and a ground potential (0 V) is applied to the third metal portion 23.

[0016] One of the first connection portion 31 and the second connection portion 32 has a joint structure between metal portions, and the other of the first connection portion 31 and the second connection portion 32 is capacitively coupled via a gap g. In the example shown in Fig. 1, the first connection portion 31 has a joint structure between a first metal portion 21 and a second metal portion 22, and the second connection portion 32 is capacitively coupled via the gap g.

[0017] Each metal portion of the first connection portion 31 and the second connection portion 32 is made of, for example, gold. The joint structure between the first metal portion 21 and the second metal portion 22 is a gold-to-gold joint structure. The third metal portion 23 and the fourth metal portion 24 face each other in the first direction Z, separated by a gap g. The gap g is an air gap.

[0018] The first chip 101 is a control chip that controls the element unit 80. A control circuit including a semiconductor transistor and the like is formed on the first surface 11A side of the first substrate 11, and the control circuit is electrically connected to the wiring layer 41. A first electrode 81 of the element unit 80 is electrically connected to the wiring layer 41 via a first connection portion 31 in which metal portions are directly joined to each other. A second electrode 82 of the element unit 80 is electrically connected to the wiring layer 41 via capacitive coupling at a second connection portion 32. A ground potential, for example, is applied to the first substrate 11 and the second substrate 12.

[0019] For example, a plurality of element portions 80 are provided on second surface 12A of second substrate 12. Therefore, a plurality of first connection portions 31 and a plurality of second connection portions 32 are arranged between first chip 101 and second chip 102.

[0020] The first metal part 21 and the second metal part 22 are brought into contact with each other, a load is applied to the first metal part 21 and the second metal part 22 in the first direction Z, and heating is performed, thereby directly joining the first metal part 21 and the second metal part 22. As the number of joining points between the metal parts increases, the contact area between the metal parts increases. If there is a limit to the load that can be applied by the joining device, as the contact area between the metal parts increases, the load required for joining will be insufficient, making joining more likely to fail.

[0021] According to this embodiment, for example, the metal parts of second connection portion 32 are not joined together but are capacitively coupled via gap g. This reduces the number of joints between metal parts between first chip 101 and second chip 102, and applies a sufficient load to the joint (first connection portion 31), reducing poor joints.

[0022] A voltage obtained by subtracting the voltage division amount applied to the capacitance of the second connection portion 32 is applied to the second electrode 82. For this reason, it tends to be difficult to control the second electrode 82 to a desired potential (ground potential in this example). By optimizing the capacitance value of the second connection portion 32, an appropriate voltage can be applied between the first electrode 81 and the second electrode 82. In addition, in this embodiment, the second substrate 12 may be applied with ground potential, making it easy to set the potential of the second electrode 82 to ground potential. From this perspective, it is preferable that the second connection portion 32, which is applied with ground potential, be capacitively coupled to the first connection portion 31 and the second connection portion 32. In addition, as will be described later, the size of the gap g in the first direction Z between the third metal portion 23 and the fourth metal portion 24 is 3 μm or less.

[0023] [Second embodiment] FIG. 2 is a schematic plan view of an electronic device 2 according to the second embodiment. Fig. 3 is a cross-sectional view taken along the line AA in Fig. 2. Fig. 3 shows a cross section of a portion where a first connection portion 31 in which metal portions are joined together is disposed. Fig. 4 is a cross-sectional view taken along the line BB in Fig. 2. Fig. 4 shows a cross section of a portion where the capacitively coupled second connection portion 32 is arranged.

[0024] The electronic device 2 of the second embodiment includes a first chip 201, a second chip 202, a first connection portion 31, and a second connection portion 32. The first chip 201 and the second chip 202 are joined via one of the first connection portion 31 and the second connection portion 32 (in this embodiment, the first connection portion 31), and are stacked in the first direction Z.

[0025] The first chip 201 has a first substrate 11 and a wiring portion 40. The first substrate 11 has a first surface 11A. The first substrate 11 is, for example, a silicon substrate. The first chip 201 has a first penetrating portion h1 that penetrates the first substrate 11 and the wiring portion 40 in the first direction Z.

[0026] The wiring section 40 is provided on the first surface 11A. The wiring section 40 has an insulating layer 42 and a wiring layer provided in the insulating layer 42. The wiring layer has a first wiring layer 41A and a second wiring layer 41B. The wiring section 40 has, for example, a multi-layer wiring structure, and different wiring layers are electrically connected to each other by conductive vias.

[0027] The second chip 202 has a second substrate 12, a first electrode 51, and a second electrode 52. The second substrate 12 has a second surface 12A. The second substrate 12 is, for example, a silicon substrate. The wiring portion 40 is located between the first surface 11A and the second surface 12A in the first direction Z. The second chip 202 has a second through portion h2 that penetrates the second substrate 12 in the first direction Z. The first through portion h1 of the first chip 201 and the second through portion h2 of the second chip 202 are aligned in the first direction Z and form a through hole H in the electronic device 2. The through hole H penetrates the second substrate 12, the wiring portion 40, and the first substrate 11 in the first direction Z. For example, a ground potential is applied to the first substrate 11 and the second substrate 12.

[0028] A first conductive film 61 and a second conductive film 62 are provided on the second surface 12A of the second substrate 12, with an insulating film 70 interposed therebetween. A first electrode 51 and a second electrode 52 are provided on the inner surface 12C of the second penetrating portion h2, with the insulating film 70 interposed therebetween. The insulating film 70 is, for example, a silicon oxide film. The insulating film 70 is provided between the second surface 12A and the first conductive film 61, between the second surface 12A and the second conductive film 62, between the inner surface 12C and the first electrode 51, and between the inner surface 12C and the second electrode 52. Note that if the second substrate 12 has insulating properties, the insulating film 70 need not be provided.

[0029] 2, the first electrode 51 and the second electrode 52 are separated from each other in the circumferential direction of the inner surface 12C on the inner surface 12C of the second through portion h2. The first conductive film 61 and the second conductive film 62 are separated from each other on the second surface 12A by an insulating film 70. The first electrode 51 is electrically connected to the first conductive film 61. The second electrode 52 is electrically connected to the second conductive film 62. Different potentials are applied to the first electrode 51 and the second electrode 52.

[0030] 3, the first connection portion 31 has a first metal portion 21 and a second metal portion 22. The first metal portion 21 is provided on the wiring portion 40 and is electrically connected to the first wiring layer 41A through a conductive via. The second metal portion 22 is provided on the second surface 12A of the second substrate 12 in contact with the first conductive film 61 and faces the first metal portion 21 in the first direction Z. The second metal portion 22 is electrically connected to the first electrode 51 through the first conductive film 61.

[0031] 4, the second connection portion 32 has a third metal portion 23 and a fourth metal portion 24. The third metal portion 23 is provided on the wiring portion 40 and is electrically connected to the second wiring layer 41B through a conductive via. The fourth metal portion 24 is provided on the second surface 12A of the second substrate 12 in contact with the second conductive film 62 and faces the third metal portion 23 in the first direction Z. The fourth metal portion 24 is electrically connected to the second electrode 52 (shown in FIG. 3) through the second conductive film 62.

[0032] The first metal portion 21 and the third metal portion 23 are located apart from each other on the wiring portion 40. Different potentials are applied to the first metal portion 21 and the third metal portion 23 through the first wiring layer 41A and the second wiring layer 41B. For example, a positive potential is applied to the first metal portion 21, and a ground potential is applied to the third metal portion 23.

[0033] One of the first connection portion 31 and the second connection portion 32 has a joint structure between metal portions, and the other of the first connection portion 31 and the second connection portion 32 is capacitively coupled via a gap g. In this embodiment, the first connection portion 31 has a joint structure between the first metal portion 21 and the second metal portion 22, and the second connection portion 32 is capacitively coupled via the gap g.

[0034] Each metal portion of the first connection portion 31 and the second connection portion 32 is made of, for example, gold. The joint structure between the first metal portion 21 and the second metal portion 22 is a gold-to-gold joint structure. The third metal portion 23 and the fourth metal portion 24 face each other in the first direction Z, separated by a gap g. The gap g is an air gap.

[0035] As shown in FIG. 2 , the electronic device 2 includes a plurality of through holes H, a plurality of first connection portions 31, and a plurality of second connection portions 32. The plurality of through holes H are aligned in the second direction X and the third direction Y. One first conductive film 61 is arranged in one-to-one correspondence with each through hole H. One first connection portion 31 is arranged in contact with the first conductive film 61 in one-to-one correspondence with each through hole H. One through hole H is located between adjacent first connection portions 31 in the third direction Y. One through hole H is located between adjacent second connection portions 32 in the second direction X. Two second connection portions 32 are arranged for one through hole H, sandwiching the through hole H in the second direction X. The number of second connection portions 32 is greater than the number of first connection portions 31. The potentials of the plurality of second electrodes 52 can be collectively controlled via the plurality of second connection portions 32 and the common second conductive film 62. The potential of each of the plurality of first electrodes 51 is individually controlled through the corresponding first connection portion 31 and first conductive film 61.

[0036] The electronic device 2 of the second embodiment can be used as a pixel array for deflecting electron beams in a multi-electron beam exposure apparatus that uses multiple electron beams to write a pattern on a resist on a substrate such as glass. The electron beams pass through the through-holes H. The electron beams passing through the through-holes H can be deflected by an electric field generated between the first electrode 51 and the second electrode 52.

[0037] By joining two chips (first chip 201 and second chip 202) each having a through-hole, it is possible to form an electronic device 2 having a deep through-hole that would be difficult to form in a single chip.

[0038] In the electronic device 2, the first metal portion 21 and the second metal portion 22 are brought into contact with each other, and a load is applied to the first metal portion 21 and the second metal portion 22 in the first direction Z, and heating is performed, thereby directly bonding the first metal portion 21 and the second metal portion 22. As the trend toward increasing the number of pixels in a multi-electron beam exposure apparatus increases, the number of connection portions also increases, and the contact area between the metal portions tends to increase.

[0039] According to this embodiment, for example, in second connection portion 32, the metal portions are not joined together but are capacitively coupled via gap g. This reduces the number of joints between the metal portions between first chip 201 and second chip 202, and applies a sufficient load to the joint (first connection portion 31), reducing poor joints.

[0040] A voltage obtained by subtracting the voltage division amount applied to the capacitance of the second connection portion 32 is applied to the second electrode 52. For this reason, it tends to be difficult to control the second electrode 52 to a desired potential (ground potential in this example). By optimizing the capacitance value of the second connection portion 32, an appropriate voltage can be applied between the first electrode 51 and the second electrode 52. Furthermore, in this embodiment, the second substrate 12 may be supplied with ground potential, making it easy to set the potential of the second electrode 52 to ground potential. From this perspective, it is preferable to capacitively couple the first connection portion 31 and the second connection portion 32 with the second connection portion 32 supplied with ground potential.

[0041] (Simulation 1) Using a cross-sectional structure in which first electrode 51 and second electrode 52 face each other across through-hole H as a model, the potential was calculated by simulation when 5 V was applied to first metal portion 21 and 0 V was applied to third metal portion 23. The results are shown in FIG.

[0042] In FIG. 5, x=0 on the horizontal axis represents a position 3 μm from the first electrode 51 toward the second electrode 52. The inner surface of the first electrode 51 facing the second electrode 52 is located at x=3 μm, and the inner surface of the second electrode 52 facing the first electrode 51 is located at x=-3 μm. The position of x=0 coincides with the central axis of the through hole H. (a) represents the result when the second connection portion 32 to which 0 V is applied has a capacitively coupled structure via gap g, and the first connection portion 31 to which 5 V is applied has a joint structure between metal parts. (b) represents the result when the second connection portion 32 to which 0 V is applied has a joint structure between metal parts, and the first connection portion 31 to which 5 V is applied has a capacitively coupled structure via gap g. The size of gap g (size in the first direction Z) was 0.1 μm. 0 V was applied to the first substrate 11 and the second substrate 12.

[0043] In addition, when a simulation was also performed for the case where both the first connection portion 31 and the second connection portion 32 were made to have a metal-to-metal joint structure (comparative example), the results were almost consistent with graph a. From this result, it can be seen that even if the second connection portion 32 on the 0V side has a capacitively coupled structure, an electric field equivalent to that generated when a metal-to-metal joint structure is used is generated within the through hole H. This may be due to the fact that the second electrode 52 is nearly grounded due to the large capacitance between the first substrate 11 and the second substrate 12. On the other hand, as shown in graph b, when the first connection portion 31 side to which 5V is applied has a capacitively coupled structure, the potential at the position x=0 is about 1 / 5 lower than that of graph a and the comparative example.

[0044] (Simulation 2) Figure 6 shows the results of a simulation of the gap dependency of the output voltage when, in the above model, the second connection part 32, to which 0 V is applied, has a capacitive coupling structure via gap g, and the first connection part 31, to which 5 V is applied, has a joint structure between metal parts. The horizontal axis represents the size of gap g, and the vertical axis represents the output voltage Vout. All conditions other than the size of gap g are the same as in Simulation 1 above.

[0045] From the results of FIG. 6, when the size of the gap g is 3 μm or less, the decrease in the output voltage Vout can be suppressed to within approximately 0.4% of when the gap is 0.

[0046] (Simulation 3) Using a model with the same conditions as Simulation 2, we estimated the time constant when writing 5V to the first electrode 51 (deflection electrode). The time constant is the product of the wiring resistance and the load capacitance, and if the wiring resistance is assumed to be constant, it is thought that the time constant is determined by the magnitude of the load capacitance. From the results in Figure 7, we can see that the load capacitance is constant regardless of the size of the gap g (including 0), and that the gap g does not slow down the time it takes to write to the deflection electrode.

[0047] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0048] 1, 2...electronic device, 11...first substrate, 11A...first surface, 12...second substrate, 12A...second surface, 12C...inner surface, 21...first metal portion, 22...second metal portion, 23...third metal portion, 24...fourth metal portion, 31...first connection portion, 32...second connection portion, 40...wiring portion, 41...wiring layer, 41A...first wiring layer, 41B...second wiring layer, 51...first electrode, 52...second electrode, 61...first conductive film, 62...second conductive film, 70...insulating film, 80...element portion, 81...first electrode, 82...second electrode, 101...first chip, 102...second chip, 201...first chip, 202...second chip, g...gap, H...through hole

Claims

1. a first substrate having a first surface; a second substrate having a second surface; a wiring portion provided on the first surface, positioned between the first surface and the second surface in a first direction, and having a wiring layer; a first connection portion including a first metal portion provided on the wiring portion and electrically connected to the wiring layer, and a second metal portion provided on the second surface of the second substrate and facing the first metal portion in the first direction; a second connection portion including: a third metal portion provided on the wiring portion and electrically connected to the wiring layer; and a fourth metal portion provided on the second surface of the second substrate and facing the third metal portion in the first direction; Equipped with An electronic device, wherein one of the first connection portion and the second connection portion is a joint structure between metal portions, and the other of the first connection portion and the second connection portion is capacitively coupled via a gap.

2. a through hole having a first through portion that passes through the first substrate in the first direction and a second through portion that passes through the second substrate in the first direction and is aligned with the first through portion in the first direction; a first electrode provided on an inner surface of the second penetration portion and electrically connected to the second metal portion; a second electrode provided on an inner surface of the second penetration portion and electrically connected to the fourth metal portion; The electronic device of claim 1 further comprising:

3. a first conductive film provided on the second surface of the second substrate and electrically connected to the first electrode and the second metal portion; a second conductive film provided on the second surface of the second substrate and electrically connected to the second electrode and the fourth metal portion; The electronic device of claim 2 further comprising:

4. the second substrate is a silicon substrate, 4. The electronic device according to claim 3, further comprising insulating films provided between the inner surface of the second penetrating portion and the first electrode, between the inner surface of the second penetrating portion and the second electrode, between the second surface and the first conductive film, and between the second surface and the second conductive film.

5. The electronic device according to claim 2 , comprising a plurality of the through holes, a plurality of the first connection portions, and a plurality of the second connection portions.

6. one first connection portion is arranged in one-to-one correspondence with one of the through holes, The electronic device according to claim 5 , wherein the number of the second connecting portions is greater than the number of the first connecting portions.

7. a positive potential is applied to the first metal portion and a ground potential is applied to the third metal portion; the first metal portion and the second metal portion are joined to each other, The electronic device according to claim 1 , wherein the third metal portion and the fourth metal portion are capacitively coupled via the gap.

8. The electronic device according to claim 7 , wherein the size of the gap between the third metal portion and the fourth metal portion in the first direction is 3 μm or less.

9. The electronic device according to claim 1 , wherein the joint structure between the metal portions is a gold-to-gold joint structure.

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