Display panel, display panel assembly, and electronic device including display panel

Abstract

To provide a technique about a display panel with improved reliability.SOLUTION: A display panel, in which a display region and a non-display region are defined, includes a lower substrate, an upper substrate, and a filler disposed between the lower substrate and the upper substrate. In the non-display region, a first edge region extending in a first direction, a second edge region disposed apart from the first edge region in a second direction that is perpendicular to the first direction and extending in the first direction, a third edge region extending in the second direction and coupling one side of the first edge region and one side of the second edge region, and a fourth edge region disposed apart from the third edge region in the first direction and extending in the second direction are defined. In at least one region of the first edge region to the fourth edge region, sealing is disposed between the upper substrate and the lower substrate. In at least one region of the first edge region to the fourth edge region, the filler is disposed extending from the display region.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a display panel and a display panel assembly for manufacturing a plurality of unit display panels. [Background technology]

[0002] Electronic devices such as televisions, mobile phones, tablets, navigation systems, game consoles, etc. may include a display panel for displaying images. The display panel may include a lower substrate and an upper substrate, each of which includes a light-emitting element.

[0003] A display panel assembly for manufacturing a plurality of unit display panels may include a lower mother substrate, an upper mother substrate, a seal for bonding the lower mother substrate and the upper mother substrate, and a filler. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Chinese Utility Model No. 208352346 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a display panel with improved reliability.

[0006] Another object of the present invention is to provide a display panel assembly with improved processability. [Means for solving the problem]

[0007] In one embodiment of the present invention, a display panel has a display area and a non-display area surrounding the display area defined therein. The display panel includes a lower substrate including a light-emitting element layer, an upper substrate disposed on the lower substrate, and a filler disposed between the lower substrate and the upper substrate, overlapping the display area. The non-display area is defined with a first edge area extending in a first direction, a second edge area extending in the first direction and spaced apart from the first edge area in a second direction perpendicular to the first direction, a third edge area extending in the second direction and connecting one side of the first edge area with one side of the second edge area, and a fourth edge area extending in the second direction and spaced apart from the third edge area in the first direction. A seal is disposed between the upper substrate and the lower substrate in at least one of the first to fourth edge areas. The filler is disposed in at least one of the first to fourth edge areas, extending from the display area.

[0008] The seal may be disposed directly between the upper substrate and the lower substrate to bond the upper substrate and the lower substrate.

[0009] The seal may be disposed in one of the first to fourth edge regions, and the filler may be extended and disposed in the remaining three regions of the first to fourth edge regions where the seal is not disposed.

[0010] The seal may be disposed in two of the first to fourth edge regions, and the filler may be extended and disposed in the remaining two of the first to fourth edge regions where the seal is not disposed.

[0011] The seal may be disposed in three of the first to fourth edge regions, and the filler may be extended and disposed in the remaining region of the first to fourth edge regions where the seal is not disposed.

[0012] The non-display area may further include a pad area spaced apart from the display area and adjacent to the first edge area.

[0013] The lower substrate may further include a sealing layer disposed on the light-emitting element layer, the sealing layer including a first inorganic sealing layer disposed on the light-emitting element layer, an organic sealing layer disposed on the first inorganic sealing layer, and a second inorganic sealing layer disposed on the organic sealing layer, and the seal may overlap the first inorganic sealing layer and the second inorganic sealing layer but not overlap the organic sealing layer.

[0014] In one embodiment of the present invention, a display panel assembly includes a plurality of unit display panels, each having a display area and a non-display area surrounding the display area. The display panel assembly includes a lower mother substrate including light-emitting elements, an upper mother substrate disposed on the lower mother substrate, and a filler disposed between the lower mother substrate and the upper mother substrate, overlapping the display area. The non-display area is defined by a first edge region extending in a first direction, a second edge region extending in the first direction and spaced apart from the first edge region in a second direction perpendicular to the first direction, a third edge region extending in the second direction and connecting one side of the first edge region with one side of the second edge region, and a fourth edge region extending in the second direction and spaced apart from the third edge region in the first direction. A seal is disposed between the upper mother substrate and the lower mother substrate in at least one of the first to fourth edge regions. The filler is disposed in at least one of the first to fourth edge regions, extending from the display area.

[0015] The display device may further include a cutting area surrounding each of the plurality of unit display panels.

[0016] The seal may be disposed directly between the upper and lower mother substrates to bond the upper and lower mother substrates together.

[0017] The non-display area may further include a pad area spaced apart from the display area and adjacent to the first edge area.

[0018] The plurality of unit display panels may include a plurality of first unit display panels and a plurality of second unit display panels spaced apart from the plurality of first unit display panels in the first direction and alternately arranged, and the seal may be disposed in two of the first to fourth edge regions defined in the plurality of first unit display panels, and the filler may be extended and disposed in the remaining two of the first to fourth edge regions defined in the plurality of first unit display panels where the seal is not disposed.

[0019] The seal may be disposed in one of the first to fourth edge regions defined in the plurality of second unit display panels, and the filler may be extended and disposed in the remaining three regions where the seal is not disposed among the first to fourth edge regions defined in the plurality of second unit display panels.

[0020] In the plurality of first unit display panels, the seal may be disposed in the second edge region and the third edge region, and the filler may be extended and disposed in the first edge region and the fourth edge region, and in the plurality of second unit display panels, the seal may be disposed in the second edge region, and the filler may be extended and disposed in the first edge region, the third edge region, and the fourth edge region.

[0021] In the plurality of first unit display panels, the seal may be disposed in the first edge region and the third edge region, and the filler may be extended and disposed in the second edge region and the fourth edge region, and in the plurality of second unit display panels, the seal may be disposed in the first edge region, and the filler may be extended and disposed in the second edge region, the third edge region, and the fourth edge region.

[0022] The seal may be disposed in two of the first to fourth edge regions defined in the plurality of second unit display panels, and the filler may be extended and disposed in the remaining two of the first to fourth edge regions defined in the plurality of second unit display panels where the seal is not disposed.

[0023] In both the plurality of first unit display panels and the plurality of second unit display panels, the seal may be disposed in the first edge region and the second edge region, and the filler may be extended and disposed in the third edge region and the fourth edge region.

[0024] In both the plurality of first unit display panels and the plurality of second unit display panels, the seal may be disposed in the first edge region and the third edge region, and the filler may be extended and disposed in the second edge region and the fourth edge region.

[0025] The seal may be disposed in three of the first to fourth edge regions defined in the plurality of second unit display panels, and the filler may be extended and disposed in the remaining region where the seal is not disposed among the first to fourth edge regions defined in the plurality of second unit display panels.

[0026] In the plurality of first unit display panels, the seal may be disposed in the first edge region and the second edge region, and the filler may be extended and disposed in the third edge region and the fourth edge region, and in the plurality of second unit display panels, the seal may be disposed in the first edge region, the second edge region, and the fourth edge region, and the filler may be extended and disposed in the third edge region. [Effects of the Invention]

[0027] According to the above, it is possible to provide a technique relating to a display panel with improved reliability.

[0028] When one embodiment of the present invention is applied to a display panel, underfilling, overfilling, and / or bursting of the sealant used to bond (bond) the upper and lower substrates can be minimized, thereby improving the reliability of the display panel.

[0029] In addition, when one embodiment of the present invention is applied, the display panel assembly minimizes the amount of seal placement required to bond the upper and lower mother substrates, thereby minimizing problems caused by bending and overlapping of the seal, thereby improving processability. [Brief explanation of the drawings]

[0030] [Figure 1] 1 is an assembled perspective view of an electronic device according to an embodiment of the present invention; [Figure 2] 1 is an exploded perspective view of an electronic device according to an embodiment of the present invention; [Figure 3A] 3 is a cross-sectional view of the electronic device taken along line II' shown in FIG. 2. [Figure 3B] 3 is a cross-sectional view of the electronic device taken along line II' shown in FIG. 2. [Figure 4] 1 is a plan view of a display panel according to an embodiment of the present invention; [Figure 5] 1 is a cross-sectional view of a portion of a display area according to one embodiment of the present invention. [Figure 6] 1 is a cross-sectional view of a portion of a display panel according to an embodiment of the present invention. [Figure 7] 1 is a cross-sectional view of a portion of a display panel according to an embodiment of the present invention. [Figure 8A] 1 is a plan view of a display panel assembly according to an embodiment of the present invention; [Figure 8B] 1 is a plan view of a display panel assembly according to an embodiment of the present invention; [Figure 8C] 1 is a plan view of a display panel assembly according to an embodiment of the present invention; [Figure 8D] 1 is a plan view of a display panel assembly according to an embodiment of the present invention; [Figure 8E] 1 is a plan view of a display panel assembly according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0031] Because the present invention can be modified in various ways and can take various forms, specific embodiments are shown by way of example in the drawings and described in detail herein, but it is understood that it is not intended to limit the invention to the particular forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention.

[0032] In this specification, the singular expression includes the plural expression unless the context clearly indicates otherwise.

[0033] In this specification, the terms "comprise" or "have" and the like are intended to specify the presence of any feature, number, step, operation, component, part, or combination thereof described above in the specification, but are to be understood as not precluding the presence or possible addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0034] As used herein, when a component (or region, layer, portion, etc.) is referred to as being "on," "coupled," or "bonded" to another component, it means that it may be directly disposed / coupled / bonded to the other component, or that a third component may be disposed therebetween.

[0035] In this specification, terms such as "under," "below," "on," and "above" are used to describe the relationship between components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0036] In this specification, the phrase "disposed on" can refer to being disposed not only above but also below any one member.

[0037] As used herein, "directly disposed" may mean that there is no additional layer, film, region, plate, etc. between one layer, film, region, plate, etc. and another. For example, "directly disposed" may mean that two layers or two members are disposed without using an additional member such as an adhesive member between them.

[0038] As used herein, "and / or" includes all possible combinations of one or more of the associated components.

[0039] In this specification, terms such as "first," "second," etc. are used to describe various components, but the components are not limited to these terms. These terms are used only to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the present invention.

[0040] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present invention belongs. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted to have a meaning consistent with the meaning they have in the context of the relevant art, and should not be interpreted in an overly ideal or formal sense unless explicitly defined herein.

[0041] The same reference numerals refer to the same components, and in the drawings, thickness, proportions, and dimensions of the components are exaggerated for the purpose of effectively explaining the technical contents.

[0042] Hereinafter, a display panel and a display panel assembly according to an embodiment of the present invention will be described with reference to the accompanying drawings.

[0043] 1 is an assembled perspective view of an electronic device ELD according to an embodiment of the present invention, and FIG. 2 is an exploded perspective view of the electronic device ELD according to an embodiment of the present invention.

[0044] 1, the electronic device ELD may be a device that is activated by an electrical signal to display an image. For example, the electronic device ELD may be a large device such as a television or an exterior billboard, or a small or medium-sized device such as a monitor, a mobile phone, a tablet, a navigation system, a game console, etc. However, the embodiments of the electronic device ELD are merely illustrative and are not limited to any one of them as long as they do not depart from the concept of the present invention.

[0045] An electronic device ELD can be rigid or flexible. "Flexible" refers to the ability to be bent. For example, a flexible electronic device ELD can include a curved electronic device, a rollable device, or a foldable device.

[0046] In this embodiment, the third direction DR3 may be defined as a direction perpendicular to a plane defined by the first direction DR1 and the second direction DR2. The front (or upper) and rear (or lower) surfaces of each component constituting the electronic device ELD may be opposed to each other in the third direction DR3, and the normal directions of the front and rear surfaces may be substantially parallel to the third direction DR3. The distance between the front and rear surfaces defined along the third direction DR3 may correspond to the thickness of the component.

[0047] In this specification, "on a plane" may be defined as a state viewed from the third direction DR3. In this specification, "on a cross section" may be defined as a state viewed from the first direction DR1 or the second direction DR2. Meanwhile, the directions indicated by the first to third directions DR1, DR2, and DR3 are relative concepts and may be converted into other directions.

[0048] The electronic device ELD may display an image IM in a third direction DR3 via a display surface IS parallel to a plane defined by the first direction DR1 and the second direction DR2. The display surface IS may further include a curved surface bent from at least one side of the plane. The display surface IS on which the image IM is displayed may correspond to the front surface of the electronic device ELD. The image IM may include not only dynamic images but also still images. FIG. 1 shows an icon image and a clock as examples of the image IM.

[0049] The electronic device ELD may have a rectangular shape with short sides extending in a first direction DR1 and long sides extending in a second direction DR2 intersecting the first direction DR1 in a plan view, but is not limited thereto, and may have various shapes such as a circle or a polygon in a plan view.

[0050] The electronic device ELD may detect an external input TC applied from the outside. The external input TC may include various types of input, such as force, pressure, temperature, light, etc. In this embodiment, the external input TC is exemplarily illustrated as a touch input by the hand of a user US applied to the front surface of the electronic device ELD. However, this is merely an example, and the external input TC may include any input that can cause a change in the capacitance of the input sensor. The area of ​​the electronic device ELD that detects the external input TC is not limited to the front surface of the electronic device ELD, and the external input TC of the user US applied to the side or back surface of the electronic device ELD may be detected depending on the structure of the electronic device ELD.

[0051] The display surface IS of the electronic device ELD may include an image area IA and a bezel area BZA. The image area IA may be an area where an image IM is displayed. A user may view the image IM through the image area IA. In this embodiment, the image area IA is shown as a rectangle with rounded corners (corners corresponding to the vertices of the rectangle in the example of FIG. 1), but this is merely an illustrative illustration and the image area IA may have a variety of shapes.

[0052] The bezel area BZA may have a predetermined color and may be a light-blocking area. The bezel area BZA may be adjacent to the image area IA. For example, the bezel area BZA may be disposed outside the image area IA and surround it. As a result, the shape of the image area IA may be substantially defined by the bezel area BZA. However, this is an exemplary illustration, and the bezel area BZA may be adjacent to only one side of the image area IA, may be disposed on a side of the electronic device ELD, or may be omitted.

[0053] Referring to FIGS. 1 and 2, the electronic device ELD may include a window WM, a display device DD, an optical member AF, an electronic module EM, a power supply module PSM, and a housing EDC.

[0054] The window WM may be disposed on the display device DD and the optical member AF. The window WM may protect the display device DD from external impacts and scratches. The front surface of the window WM may correspond to the display surface IS of the electronic device ELD.

[0055] The optical element AF may be disposed on the display device DD. The optical element AF may include various embodiments that reduce the reflectance of external light. For example, the optical element AF may include a polarizing film including a phase retarder and / or a polarizer, a multi-layer reflective layer that destructively interferes with reflected light, or a color filter arranged corresponding to the pixel array and emission color of the display panel DP. Unlike the illustration in FIG. 2 , in one embodiment, the electronic device ELD may not include the optical element AF.

[0056] The display device DD generates an image IM to be output to the outside of the electronic device ELD and can sense an external input TC. The display device DD can include a display panel DP and an input sensor ISP.

[0057] The display panel DP may display an image IM in response to an electrical signal. According to an embodiment, the display panel DP may be, but is not limited to, an emissive display panel. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. Hereinafter, the display panel DP will be referred to as an organic light-emitting display panel.

[0058] The input sensor ISP may be disposed on the display panel DP. The input sensor ISP may sense an external input TC and provide an input signal including information about the external input TC so that the display panel DP can generate an image IM corresponding to the external input TC. The input sensor ISP may be driven in various ways, such as, but not limited to, a capacitive type, a resistive type, an infrared type, a sonic type, or a pressure type. Unlike the illustration of FIG. 2, in one embodiment, the electronic device ELD may not include the input sensor ISP.

[0059] The display device DD may include an active area AA and a peripheral area NAA adjacent to the active area AA. The active area AA may be an area where light-emitting elements of the display panel DP and sensing electrodes of the input sensor ISP are arranged, and may be activated by an electrical signal to display an image IM or sense an external input TC. The peripheral area NAA may be an area where driving circuits, signal lines, pads, etc. for driving elements arranged in the active area AA are arranged.

[0060] The active area AA may overlap the image area IA of the electronic device ELD, and the peripheral area NAA may overlap the bezel area BZA of the electronic device ELD. The bezel area BZA may prevent a structure disposed in the peripheral area NAA from being viewed from the outside.

[0061] The display device DD may further include a main circuit board MCB, a flexible circuit film FCB, a data driver DIC, a sensor control circuit T-IC, and a main controller 100.

[0062] The main circuit board MCB may include driving elements, may be electrically connected to the display panel DP and the input sensor ISP via a flexible circuit film FCB, and may be electrically connected to the electronic module EM via a connector.

[0063] The flexible circuit film FCB may be connected to the display panel DP to electrically connect the display panel DP and the main circuit board MCB. The input sensor ISP may be electrically connected to the display panel DP and electrically connected to the main circuit board MCB via the flexible circuit film FCB. However, embodiments are not limited thereto. The input sensor ISP may be electrically connected to the main circuit board MCB via an additional flexible circuit film, or the flexible circuit film FCB may be omitted and the main circuit board MCB may be directly connected to the display panel DP.

[0064] The data driver DIC, the sensor control circuit T-IC, and the main controller 100 may each be provided in the form of an integrated chip. The data driver DIC may be mounted on the display panel DP, and the sensor control circuit T-IC and the main controller 100 may be mounted on the main circuit board MCB. However, embodiments are not limited thereto. For example, the data driver DIC may be mounted on a flexible circuit board FCB.

[0065] The main controller 100 may control the overall operation of the electronic device ELD. For example, the main controller 100 may control the operation of the display panel DP and the input sensor ISP. The main controller 100 may also control the operation of the electronic module EM. The main controller 100 may include at least one microprocessor.

[0066] The data driver DIC may include a driver circuit for driving pixels of the display panel DP. The data driver DIC may receive image data and control signals from the main controller 100. For example, the control signals may include an input vertical synchronization signal, an input horizontal synchronization signal, a main clock, and a data enable signal.

[0067] The sensor control circuit T-IC may provide electrical signals to the input sensor ISPs for driving the input sensor ISPs. The sensor control circuit T-IC may receive control signals, such as a clock signal, from the main controller 100.

[0068] The electronic module EM may include various functional modules necessary for driving the display device DD. For example, the electronic module EM may include a wireless communication module, a video input module, an audio input module, an audio output module, a memory, an external interface module, etc. The modules of the electronic module EM may be mounted on the main circuit board MCB or may be electrically connected to the main circuit board MCB via a separate flexible circuit board.

[0069] The power supply module PSM may be electrically connected to the electronic module EM. The power supply module PSM may provide power necessary for the overall operation of the electronic device ELD. For example, the power supply module PSM may include a conventional battery device.

[0070] The window WM and the housing EDC may be combined to form the exterior of the electronic device ELD. The window WM and the housing EDC may be combined to form an internal space that houses the components of the electronic device ELD. The internal space may house the display device DD, flexible circuit board FCB, main circuit board MCB, electronic module EM, power supply module PSM, etc. The display panel DP may be folded so that the flexible circuit board FCB and main circuit board MCB face the rear surface of the display device DD and housed in the housing EDC.

[0071] The housing EDC may include a relatively rigid material. For example, the housing EDC may include a frame and / or plate made of glass, plastic, or metal, or a combination thereof. The housing EDC may protect the display device DD housed in the housing EDC by absorbing external impacts or preventing penetration of foreign matter / moisture from the outside.

[0072] 3A and 3B are cross-sectional views of the electronic device ELD taken along line II' shown in FIG.

[0073] 3A and 3B show various embodiments of stacked configurations of components included in the electronic device ELD, to which the above-mentioned explanations regarding the window WM, the display panel DP, and the input sensor ISP can be applied.

[0074] 3A and 3B, the window WM may include a base film WBB and a bezel pattern WBM. The base film WBB may include an optically transparent insulating material. The base film WBB may include at least one of a glass film and a synthetic resin film. The base film WBB may have a single-layer structure or a multi-layer structure in which multiple films are combined. The window WM may further include a functional layer, such as an anti-fingerprint layer, a phase control layer, or a hard coating layer, disposed on the base film WBB.

[0075] The bezel pattern WBM may be a color layer formed on one surface of the base film WBB. The bezel pattern WBM may include a colored material. For example, the bezel pattern WBM may include a colored organic film. The bezel pattern WBM may have a single-layer or multi-layer structure. A multi-layer bezel pattern WBM may include a chromatic color layer and an achromatic (especially black) light-shielding layer. The bezel pattern WBM may be formed by deposition, printing, or coating processes.

[0076] The bezel pattern WBM may be disposed in correspondence with a bezel area BZA (see FIG. 1) of the electronic device ELD. A portion of the window WM where the bezel pattern WBM is disposed may have lower light transmittance than an area where the bezel pattern WBM is not disposed.

[0077] A first adhesive layer AL1 may be disposed between the window WM and the optical element AF. The window WM and the optical element AF may be bonded together by the first adhesive layer AL1. However, the first adhesive layer AL1 may be omitted, and the window WM may be disposed directly on the optical element AF.

[0078] 3A, the input sensor ISP may be disposed directly on the display panel DP. The input sensor ISP may be formed by a continuous process on a base surface provided by the display panel DP during the manufacturing process of the display device DD. The input sensor ISP may be integrally bonded to the display panel DP without a separate adhesive layer.

[0079] 3A, the optical element AF can be disposed directly on the display device DD. For example, the optical element AF can be formed by a continuous process on the upper surface of the input sensor ISP. The optical element AF can include a color filter, and can be formed by patterning or printing a color filter composition on the base surface provided by the input sensor ISP.

[0080] 3B, the optical member AF may be bonded to the display device DD via a second adhesive layer AL2. For example, the optical member AF may be provided in the form of a film such as a polarizing film, and may be bonded to the display device DD via a second adhesive layer AL2 disposed on the upper surface of the input sensor ISP.

[0081] 3B , the display device DD may further include a third adhesive layer AL3 disposed between the input sensor ISP and the display panel DP. The input sensor ISP may be coupled to the display panel DP via the third adhesive layer AL3. For example, the input sensor ISP may be provided as a touch panel manufactured in a separate process from the manufacturing process of the display panel DP, and the input sensor ISP may be coupled to the display panel DP via the third adhesive layer AL3 disposed on the upper surface of the display panel DP.

[0082] Each of the first to third adhesive layers AL1, AL2, and AL3 may include a transparent adhesive such as an optically clear adhesive film (OCA), an optically clear resin (OCR), or a pressure-sensitive adhesive film (PSA), but the embodiment is not necessarily limited thereto.

[0083] 3A and 3B are merely illustrative and not limiting. For example, the electronic device ELD may further include a protective layer disposed below the display panel DP, or the optical member AF may be omitted. Furthermore, the stacking order of the optical member AF and the input sensor ISP may be changed, and the optical member AF may be disposed between the display panel DP and the input sensor ISP.

[0084] FIG. 4 is a plan view of a display panel DP according to an embodiment of the present invention.

[0085] Referring to FIG. 4, the display panel DP may include a base layer BL, pixels PX, signal lines SL1 to SLm, DL1 to DLn, EL1 to ELm, CSL1, CSL2, and PL electrically connected to the pixels PX, a scan driver SDV, a data driver DIC, an emission driver EDV, and a pad PD1.

[0086] The base layer BL may provide a base surface on which elements and wiring of the display panel DP are arranged. The base layer BL may include a display area DA and a non-display area NDA. The display area DA may be an area in which pixels PX are arranged and an image is displayed. The non-display area NDA may be an area adjacent to the display area DA in which elements and wiring for driving the pixels PX are arranged and an image is not displayed. The display area DA may correspond to the active area AA (see FIG. 2) of the display device DD, and the non-display area NDA may correspond to the peripheral area NAA (see FIG. 2) of the display device DD.

[0087] A display area DA and a non-display area NDA may be defined on the display panel DP. The non-display area NDA may be disposed so as to surround the display area DA.

[0088] The non-display area NDA may include a border area NDA1. More specifically, the border area NDA1 may include a first border area NDA1-1 extending in a first direction DR1, a second border area NDA1-2 spaced apart from the first border area NDA1-1 in a second direction DR2 and extending in the first direction DR1, a third border area NDA1-3 extending in the second direction DR2 and connecting one side of the first border area NDA1-1 to one side of the second border area NDA1-2, and a fourth border area NDA1-4 spaced apart from the third border area NDA1-3 in the first direction DR1 and extending in the second direction DR2. The fourth border area NDA1-4 may be arranged to connect the other side of the first border area NDA1-1 to the other side of the second border area NDA1-2. In the example of FIG. 4, the first to fourth edge regions NDA1-1 to NDA1-4 and the pad region NDA2 are separated by dashed lines. The display region DA is an inner rectangular region surrounded by the dashed lines. The first edge region NDA1-1 is an area adjacent to the pad region NDA2 side of the display region DA in the second direction DR2. The first edge region NDA1-1 is located between the display region DA and the pad region NDA2. The second edge region NDA1-2 is an area adjacent to the display region DA on the opposite side from the pad region NDA2 side in the second direction DR2. The third edge region NDA1-3 is an area adjacent to the scan driver SDV side of the display region DA in the first direction DR1. The fourth edge region NDA1-4 is an area adjacent to the light-emitting driver EDV side of the display region DA in the first direction DR1. The pad region NDA2 is an area adjacent to the pad PD1 side of the first edge region NDA1-1 in the second direction DR2.

[0089] The non-display area NDA may further include a pad area NDA2 spaced apart from the display area DA and adjacent to the edge area NDA1. Specifically, the pad area NDA2 may be disposed adjacent to the first edge area NDA1-1. Pads PD1 may be disposed in the pad area NDA2.

[0090] Each pixel PX may include a pixel driving circuit configured with a transistor (e.g., a switching transistor, a driving transistor, etc.) and a capacitor, and a light emitting element electrically connected to the pixel driving circuit. The pixel PX may emit light in response to an electrical signal applied to the pixel PX.

[0091] The scan driver SDV, the data driver DIC, and the light emitting driver EDV may be disposed in the non-display area NDA, but at least one of the scan driver SDV, the data driver DIC, and the light emitting driver EDV may be disposed in the display area DA, thereby reducing the area of ​​the non-display area NDA.

[0092] The signal lines SL1-SLm, EL1-ELm, DL1-DLn, CSL1, CSL2, and PL may include scan lines SL1-SLm, data lines DL1-DLn, light-emitting lines EL1-ELm, first and second control lines CSL1 and CSL2, and a power line PL, where m and n are natural numbers greater than or equal to 1. The pixels PX may be electrically connected to corresponding scan lines, data lines, and light-emitting lines among the scan lines SL1-SLm, data lines DL1-DLn, and light-emitting lines EL1-ELm. Meanwhile, more types of signal lines may be provided on the display panel DP depending on the configuration of the pixel driving circuit of the pixel PX.

[0093] The scan lines SL1 to SLm may extend in a first direction DR1 and be electrically connected to the scan driver SDV. The data lines DL1 to DLn may extend in a second direction DR2 and be electrically connected to the data driver DIC. The light emitting lines EL1 to ELm may extend in the first direction DR1 and be electrically connected to the light emitting driver EDV.

[0094] The power line PL may include a portion extending in a first direction DR1 and a portion extending in a second direction DR2. The portion of the power line PL extending in the first direction DR1 and the portion of the power line PL extending in the second direction DR2 may be disposed on different layers and connected to each other via a contact hole. However, the present invention is not limited thereto, and the portion of the power line PL extending in the first direction DR1 and the portion of the power line PL extending in the second direction DR2 may be integrally formed on the same layer.

[0095] The power lines PL may have portions extending in a first direction DR1 that extend into the display area DA and be electrically connected to the pixels PX, and portions extending in a second direction DR2 that are disposed in the non-display area NDA and extend toward the pads PD1. The power lines PL may receive a power supply voltage and provide it to the pixels PX.

[0096] The first control line CSL1 may be electrically connected to the scan driver SDV, and the second control line CSL2 may be electrically connected to the emission driver EDV.

[0097] The pads PD1 may be arranged adjacent to a lower end of the non-display area NDA. The pads PD1 may be arranged closer to a lower end of the display panel DP than the data driver DIC. The pads PD1 may be arranged spaced apart along the first direction DR1. The pads DP1 may be electrically connected to a circuit board that provides signals for controlling the operations of the scan driver SDV, the data driver DIC, and the emission driver EDV of the display panel DP.

[0098] Each pad PD1 may be connected to a corresponding signal line among signal lines SL1-SLm, EL1-ELm, DL1-DLn, CSL1, CSL2, and PL. For example, the power supply line PL, the first and second control lines CSL1 and CSL2, and the data lines DL1-DLn may be connected to a corresponding pad PD1. The data lines DL1-DLn may be connected to the corresponding pad PD1 via a data driver DIC.

[0099] The scan driver SDV may generate scan signals in response to scan control signals. The scan signals may be applied to the pixels PX via the scan lines SL1 to SLm. The data driver DIC may generate data voltages corresponding to video signals in response to the data control signals. The data voltages may be applied to the pixels PX via the data lines DL1 to DLn. The light emitting driver EDV may generate light emitting signals in response to light emitting control signals. The light emitting signals may be applied to the pixels PX via the light emitting lines EL1 to ELm.

[0100] The pixels PX can be provided with data voltages in response to scan signals. The pixels PX can display images by emitting light of a brightness corresponding to the data voltage in response to emission signals. The emission time of the pixels PX can be controlled by the emission signals. Thus, the display panel DP can generate images on the display area DA through the pixels PX.

[0101] FIG. 5 is a cross-sectional view of a portion of a display area DA according to an embodiment of the present invention.

[0102] 5 shows in detail some layers of the lower substrate LSB (see FIGS. 6 and 7) of the display panel DP, which will be described later. In particular, FIG. 5 exemplarily shows the light-emitting element OLED and the transistor TR of the pixel PX (see FIG. 4) included in the display area DA of the display panel DP according to one embodiment.

[0103] The display panel DP may include a base layer BL, a circuit layer DP-CL disposed on the base layer BL, a light-emitting element layer DP-OLED, and an upper insulating layer TFL.

[0104] The base layer BL may provide a base surface on which the circuit layer DP-CL, the light-emitting element layer DP-OLED, and the upper insulating layer TFL are disposed. The base layer BL may be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. The base layer BL may be a glass substrate, a metal substrate, or a polymer substrate. However, embodiments of the present invention are not limited thereto, and the base layer BL may include an inorganic layer, an organic layer, or a composite material layer.

[0105] The base layer BL may have a multi-layer structure. For example, the base layer BL may include a first synthetic resin layer, a multi-layer or single-layer inorganic layer, and a second synthetic resin layer disposed on the multi-layer or single-layer inorganic layer. Each of the first and second synthetic resin layers may include, but is not limited to, a polyimide-based resin.

[0106] The circuit layer DP-CL may be disposed on the base layer BL. The circuit layer DP-CL may include multiple insulating layers, multiple conductive layers, and a semiconductor layer. The multiple conductive layers of the circuit layer DP-CL may form signal lines or pixel control circuits.

[0107] The light-emitting element layer DP-OLED may be disposed on the circuit layer DP-CL. The light-emitting element layer DP-OLED may include a light-emitting element. The light-emitting element layer DP-OLED may include, for example, an organic light-emitting element, an inorganic light-emitting element, an organic-inorganic light-emitting element, a micro LED, a nano LED, a quantum dot light-emitting element, an electrophoretic element, an electrowetting element, or the like.

[0108] The top insulating layer TFL may include a capping layer CPL and a thin film encapsulation layer TFE.

[0109] The upper insulating layer TFL is disposed on the light emitting element layer DP-OLED and may protect the light emitting element layer DP-OLED from foreign substances such as moisture, oxygen, and dust particles. The upper insulating layer TFL may seal the light emitting element layer DP-OLED and block moisture and oxygen from entering the light emitting element layer DP-OLED.

[0110] The circuit layer DP-CL includes at least one insulating layer and circuit elements, including signal lines, pixel driving circuits, etc. The circuit layer DP-CL can be formed by forming an insulating layer, a semiconductor layer, and a conductive layer by coating, deposition, etc., and patterning the insulating layer, the semiconductor layer, and the conductive layer by a photolithography process.

[0111] The buffer layer BFL may include at least one inorganic layer, and the semiconductor pattern is disposed on the buffer layer BFL. The buffer layer BFL improves the bonding strength between the base layer BL and the semiconductor pattern.

[0112] The semiconductor pattern may include polysilicon. However, the semiconductor pattern is not limited to this, and may also include amorphous silicon or metal oxide. Figure 5 shows only some of the semiconductor patterns, and other semiconductor patterns may be arranged in other areas of the pixel on a plane. The semiconductor patterns may be arranged in a specific order across the pixel.

[0113] The electrical properties of a semiconductor pattern vary depending on whether it is doped or not. The semiconductor pattern may include a first region A1 with a low doping concentration and conductivity and second regions S1 and D1 with relatively high doping concentration and conductivity. One second region S1 may be disposed on one side of the first region A1, and the other second region D1 may be disposed on the other side of the first region A1. The second regions S1 and D1 may be doped with N-type or P-type dopants. A P-type transistor includes a doped region doped with P-type dopants. The first region A1 may be undoped or may be doped at a lower concentration than the second regions S1 and D1.

[0114] The second regions S1 and D1 may function as electrodes or signal lines. One second region S1 may correspond to the source of the transistor TR, and the other second region D1 may correspond to the drain of the transistor TR. Figure 5 shows a portion of the connection signal line SCL made of a semiconductor pattern. Although not separately shown, the connection signal line SCL may be connected to the drain of the transistor TR on a plane.

[0115] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may overlap a plurality of pixels disposed in the display area DA in common and cover the semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. Not only the first insulating layer 10, but also the insulating layers of the circuit layer DP-CL described below may be inorganic layers and / or organic layers and may have a single-layer or multi-layer structure.

[0116] The gate G1 may be disposed on the first insulating layer 10. The gate G1 may be a part of the metal pattern. The gate G1 overlaps the first area A1. The gate G1 may function as a mask in the process of doping the semiconductor pattern.

[0117] The second insulating layer 20 may be disposed on the first insulating layer 10 and cover the gate G1. The second insulating layer 20 may overlap a plurality of pixels in common. The upper electrode UE may be disposed on the second insulating layer 20. The upper electrode UE may overlap the gate G1. The upper electrode UE may include multiple metal layers. In one embodiment of the present invention, the upper electrode UE may be omitted.

[0118] The third insulating layer 20 may be disposed on the second insulating layer 20 and may cover the upper electrode UE. The first connecting electrode CNE1 may be disposed on the third insulating layer 30. The first connecting electrode CNE1 may be connected to the connecting signal line SCL via a contact hole CNT-1 that penetrates the first to third insulating layers 10 to 30.

[0119] The fourth insulating layer 40 may be disposed on the third insulating layer 30, and the fifth insulating layer 50 may be disposed on the fourth insulating layer 40. The fourth insulating layer 40 may be an organic layer. The second connecting electrode CNE2 may be disposed on the fourth insulating layer 40. The second connecting electrode CNE2 may be connected to the first connecting electrode CNE1 via a contact hole CNT-2 that penetrates the fourth insulating layer 40.

[0120] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 and cover the second connecting electrode CNE2. The fifth insulating layer 50 may be an organic layer.

[0121] The light-emitting element OLED may be disposed on the fifth insulating layer 50. The first electrode AE ​​may be disposed on the fifth insulating layer 50. The first electrode AE ​​is connected to the second connecting electrode CNE2 via a contact hole CNT-3 that penetrates the fifth insulating layer 50. A pixel opening OP is defined in the pixel defining layer PDL, and the pixel defining layer PDL exposes at least a portion of the first electrode AE. The pixel defining layer PDL may be an organic layer.

[0122] The display area DA may include a pixel area PXA and a non-pixel area NPXA adjacent to the pixel area PXA. The non-pixel area NPXA may surround the pixel area PXA. In this embodiment, the pixel area PXA is defined to correspond to a portion of the first electrode AE ​​exposed by the pixel opening OP.

[0123] The light-emitting element OLED may include a first electrode AE, a hole transport region HTR, an emitting layer EML, an electron transport region ETR, and a second electrode CE. The hole transport region HTR may be disposed on the first electrode AE. The emitting layer EML may be disposed on the hole transport region HTR. The second electrode CE may be disposed on the hole transport region HTR. The second electrode CE may have a shape that is integral with the plurality of light-emitting elements OLED.

[0124] The hole transport region HTR, the emission layer EML, and the electron transport region ETR may be formed commonly to a plurality of pixels using an open mask, but at least one of the hole transport region HTR, the emission layer EML, and the electron transport region ETR may be formed by patterning using a mask.

[0125] The upper insulating layer TFL is disposed on the light-emitting element layer DP-OLED and may include a plurality of thin films. According to an embodiment, the upper insulating layer TFL may include a capping layer CPL and an encapsulation layer TFE disposed on the capping layer CPL. The capping layer CPL may be disposed on the second electrode CE and may be in contact with the second electrode CE. The capping layer CPL may include an organic material.

[0126] The encapsulating layer TFE may include a first inorganic encapsulating layer TIOL1, an organic encapsulating layer TOL disposed on the first inorganic encapsulating layer TIOL1, and a second inorganic encapsulating layer TIOL2 disposed on the organic encapsulating layer TOL. The first inorganic encapsulating layer TIOL1 and the second inorganic encapsulating layer TIOL2 may protect the light-emitting element layer DP-OLED from moisture / oxygen, and the organic encapsulating layer TOL may protect the light-emitting element layer DP-OLED from foreign matter such as dust particles.

[0127] 6 and 7 are cross-sectional views of a portion of a display panel DP according to an embodiment of the present invention.

[0128] 6 and 7 show cross sections of the border area NDA1 and a portion of the display area DA adjacent thereto, for example. The border area NDA1 shown in FIGS. 6 and 7 may correspond to at least one of the first to fourth border areas NDA1-1, NDA1-2, NDA1-3, and NDA1-4.

[0129] Referring to Figures 6 and 7, the display panel DP may include a lower substrate LSB, an upper substrate USB arranged on the lower substrate LSB, and a filler FLL arranged between the lower substrate LSB and the upper substrate USB.

[0130] The lower substrate LSB may include the above-mentioned circuit layer DP-CL, light-emitting element layer DP-OLED, and upper insulating layer TFL. The lower substrate LSB may further include a color filter layer CF disposed on the upper insulating layer TFL. Although not shown in FIGS. 6 and 7 , the lower substrate LSB may further include a functional layer for improving light emission quality in addition to the color filter layer CF on the upper insulating layer TFL.

[0131] The upper substrate USB may be referred to as an encapsulation substrate. The upper substrate USB may include a plastic substrate, a glass substrate, a metal substrate, an organic / inorganic composite substrate, etc. The upper substrate USB and the lower substrate LSB may be spaced apart with a predetermined gap therebetween.

[0132] The filler FLL may be disposed to overlap at least the display area DA. The filler FLL may be disposed between the upper substrate USB and the lower substrate LSB, filling the space between the upper substrate USB and the lower substrate LSB. The filler FLL may include a moisture absorbent or a resin material.

[0133] The seal SSL may be disposed between the upper substrate USB and the lower substrate LSB to bond the upper substrate USB and the lower substrate LSB together. The seal SSL may include an organic adhesive or a frit.

[0134] A dam DAM may be disposed in the edge area NDA1. The dam DAM may include an insulating material. On a plane, the dam DAM may be disposed to surround the display area DA.

[0135] Referring to FIG. 6, at least one of the first to fourth edge regions NDA1-1, NDA1-2, NDA1-3, and NDA1-4 (see FIG. 4) may include a seal SSL between the upper substrate USB and the lower substrate LSB. That is, FIG. 6 is a cross-sectional view of a display panel including a seal SSL in the edge region NDA1. The example of FIG. 6 is a cross-sectional view of a display panel including a seal SSL and a filler FLL in the edge region NDA1. The seal SSL may be disposed directly between the upper substrate USB and the lower substrate LSB to bond the upper substrate USB and the lower substrate LSB. In plan view, the seal SSL may be disposed to overlap the first inorganic encapsulating layer TIOL1 and the second inorganic encapsulating layer TIOL2, but not overlap the organic encapsulating layer TOL.

[0136] The filler FLL may be extended from the display area DA and disposed so as to overlap a portion of the area including the seal SSL. The filler FLL extended from the display area DA may be disposed spaced apart from the seal SSL on a plane (in plan view) as shown in Fig. 6, or may be disposed in contact with the seal SSL on a plane. In the example of FIG. 6, above the third direction DR3 of the dam DAM arranged in the edge region NDA1, the end of the seal SSL and the end of the filler FLL are positioned adjacent to each other with a gap therebetween.

[0137] The dam DAM is formed in the non-display area NDA. Specifically, the dam DAM is formed so as to protrude from the base layer BL in a portion located outside the boundary between the display area DA and the non-display area NDA and inside the outer edge of the display panel DP in a plan view.

[0138] The first inorganic encapsulating layer TIOL1 covers the circuit layer DP-CL and the light-emitting element layer DP-OLED. The first inorganic encapsulating layer TIOL1 extends from the display area DA to the non-display area NDA, covering the base layer BL and the dam DAM in a portion of the non-display area NDA. The circuit layer DP-CL and the light-emitting element layer DP-OLED are formed on the base layer BL primarily in the display area DA and may extend to a portion of the non-display area NDA as shown in FIG. 6. The dam DAM is spaced apart from the circuit layer DP-CL and the light-emitting element layer DP-OLED. Thus, in the non-display area NDA, the first inorganic encapsulating layer TIOL1 covers a portion of the circuit layer DP-CL and the light-emitting element layer DP-OLED, the base layer BL between the dam DAM and the circuit layer DP-CL and the light-emitting element layer DP-OLED, the dam DAM, and the base layer BL outside the dam DAM. The dam DAM is formed in a portion located inside the outer edge of the display panel DP, and a first step portion is formed between the top surface of the dam DAM and the top surface of the base layer BL outside the dam DAM. The first step portion is a step corresponding to the height from the upper surface of the base layer BL to the upper surface of the dam DAM. Therefore, the first inorganic sealing layer TIOL1 is arranged so as to have a step corresponding to the first step portion from the dam DAM to the outer portion of the dam DAM.

[0139] The organic sealing layer TOL covers a portion of the first inorganic sealing layer TIOL1. Here, the height of the dam DAM in the third direction DR3 is greater than the combined height of the circuit layer DP-CL and the light-emitting element layer DP-OLED. Therefore, a second step portion is formed between the upper surfaces of the circuit layer DP-CL and the light-emitting element layer DP-OLED and the upper surface of the base layer BL in a portion adjacent thereto, and a third step portion is formed between the upper surface of the base layer BL and the upper surface of the dam DAM. Similarly, steps corresponding to the second and third step portions are formed on the first inorganic sealing layer TIOL1 in the portions extending from the circuit layer DP-CL and the light-emitting element layer DP-OLED to the dam DAM. The second step portion is a step corresponding to the height from the upper surface of the light-emitting element layer DP-OLED to the upper surface of the base layer BL. The third step portion is a step corresponding to the height from the upper surface of the base layer BL to the upper surface of the dam DAM. The organic sealing layer TOL is formed in the portions corresponding to the second and third step portions. Specifically, the organic sealing layer TOL is disposed on the first inorganic sealing layer TIOL1 on the circuit layer DP-CL and the light-emitting element layer DP-OLED, with a thickness corresponding to the difference between the height of the dam DAM and the total height of the circuit layer DP-CL and the light-emitting element layer DP-OLED. The organic sealing layer TOL is disposed on the first inorganic sealing layer TIOL1 on the base layer BL located between the circuit layer DP-CL and the light-emitting element layer DP-OLED and the dam DAM, with a thickness corresponding to the difference between the height of the dam DAM and the height of the base layer BL. The top surface of the first inorganic sealing layer TIOL1 on the dam DAM and the top surface of the organic sealing layer TOL are generally flush with each other. The organic sealing layer TOL is formed so as to be blocked by the dam DAM so as not to be disposed outward from the dam DAM.

[0140] The second inorganic sealing layer TIOL2 is disposed on the first inorganic sealing layer TIOL1 and the organic sealing layer TOL. Specifically, the second inorganic sealing layer TIOL2 is disposed on the organic sealing layer TOL from the display area DA to the dam DAM, and is disposed from the dam DAM outward so as to cover the dam DAM and the first inorganic sealing layer TIOL1 on the base layer BL. The second inorganic sealing layer TIOL2 is disposed generally flat on the organic sealing layer TOL and the dam DAM, and is disposed so as to have a step corresponding to the first step portion in a portion corresponding to the first step portion.

[0141] The color filter CF is disposed on the second inorganic sealing layer TIOL2 in the display area DA and in part of the non-display area NDA. In the example of Fig. 6, the color filter CF is disposed closer to the display area DA than the dam DAM, and is disposed at a position generally corresponding to the organic sealing layer TOL.

[0142] The filler FLL is disposed from a part of the non-display area NDA to the display area DA so as to cover the color filter CF from the edge to the upper surface of the color filter CF. In the example of Fig. 6, the filler FLL is disposed on the second inorganic sealing layer TIOL2 and the color filter CF from a part of the dam DAM to the display area DA.

[0143] The seal SSL is disposed on the second inorganic sealing layer TIOL2 at a position adjacent to the filler FLL in plan view, extending from a part of the non-display area NDA to an outer portion of the display panel DP. In the example of FIG. 6, the seal SSL is disposed on the dam DAM and on the second inorganic sealing layer TIOL2 so as to correspond to the first step portion. In the first step portion, the seal SSL is disposed so as to fill the step of the first step portion. The upper surface of the seal SSL and the upper surface of the filler FLL are generally flush with each other. The upper substrate USB is disposed on the seal SSL and the filler FLL.

[0144] 7, at least one of the first to fourth edge regions NDA1-1, NDA1-2, NDA1-3, and NDA1-4 may not include a seal SSL between the upper substrate USB and the lower substrate LSB but may include a filler FLL. That is, FIG. 7 is a cross-sectional view of a display panel showing a portion of the edge region NDA1 that does not include a seal SSL but includes a filler FLL. In this case, the filler FLL may extend from the display region DA and be disposed in at least one of the first to fourth edge regions NDA1-1, NDA1-2, NDA1-3, and NDA1-4. The filler FLL extended from the display region DA may be disposed over the entire area of ​​at least one of the first to fourth edge regions NDA1-1, NDA1-2, NDA1-3, and NDA1-4 where the seal SSL is not disposed, as shown in FIG.

[0145] In one embodiment, a seal SSL may be disposed in one of the first to fourth edge regions NDA1-1, NDA1-2, NDA1-3, and NDA1-4, and may have a cross section as shown in Fig. 6. In this case, the remaining three regions among the first to fourth edge regions NDA1-1, NDA1-2, NDA1-3, and NDA1-4 where the seal SSL is not disposed may not have the seal SSL disposed therein, and a filler FLL may be disposed extending from the display region DA, and may have a cross section as shown in Fig. 7.

[0146] In another embodiment, the seal SSL may be disposed in two of the first to fourth edge regions NDA1-1, NDA1-2, NDA1-3, and NDA1-4, and may have a cross section as shown in Fig. 6. In this case, the seal SSL may not be disposed in the remaining two of the first to fourth edge regions NDA1-1, NDA1-2, NDA1-3, and NDA1-4, and a filler FLL may be disposed extending from the display area DA, and may have a cross section as shown in Fig. 7.

[0147] In another embodiment, a seal SSL may be disposed in three of the first to fourth edge regions NDA1-1, NDA1-2, NDA1-3, and NDA1-4, and the cross section may be as shown in Fig. 6. In this case, the remaining region among the first to fourth edge regions NDA1-1, NDA1-2, NDA1-3, and NDA1-4 where the seal SSL is not disposed may not be disposed with the seal SSL, and a filler FLL may be disposed extending from the display region DA, and the cross section may be as shown in Fig. 7. As described above, the sole SSL may be disposed in only a portion of the edge area NDA1, while the filler FLL may be disposed in the entire edge area NDA1.

[0148] 8A to 8E are plan views of a display panel assembly according to one embodiment of the present invention.

[0149] The seal SSL is disposed between the upper mother substrate UMB and the lower mother substrate LMB, but in Figures 8A to 8E, the seal SSL is shown visible to show the planar positional relationship of the seal SSL between the upper mother substrate UMB and the lower mother substrate LMB.

[0150] The display panel assembly ASS is used to manufacture a plurality of unit display panels DPUs. Although four unit display panels DPUs are shown arranged in the display panel assembly ASS in Figures 8A to 8E, the number of unit display panels DPUs may be two, three, five or more.

[0151] 8A to 8E, the display panel assembly ASS may include a plurality of unit display panels DPU and a cutting area CA surrounding the plurality of unit display panels DPU on a plane. The cutting area CA may be an area to be removed after cutting.

[0152] The display panel assembly ASS may include an upper mother substrate UMB, a lower mother substrate LMB, and a filler FLL (see FIGS. 6 and 7) disposed between the upper mother substrate UMB and the lower mother substrate LMB. The upper mother substrate UMB and the lower mother substrate LMB may be disposed overlapping each other on a plane.

[0153] The same applies to the unit display panel DPU portion of the upper mother substrate UMB as described above in Figures 6 and 7. The same applies to the unit display panel DPU portion of the lower mother substrate LMB as described above in Figures 6 and 7.

[0154] At least one of the first to fourth edge regions NDA1-1, NDA1-2, NDA1-3, and NDA1-4 may include a seal SSL between the upper mother substrate UMB and the lower mother substrate LMB. The seal SSL may be disposed directly between the upper mother substrate UMB and the lower mother substrate LMB to bond the upper mother substrate UMB and the lower mother substrate LMB.

[0155] The filler FLL may extend from the display area DA of the unit display panel DPU and overlap a portion of the area including the seal SSL. The filler FLL extending from the display area DA may be spaced apart from the seal SSL on a flat surface as shown in FIG. 6, or may alternatively be in contact with the seal SSL on a flat surface.

[0156] At least one of the first to fourth edge regions NDA1-1, NDA1-2, NDA1-3, and NDA1-4 may not include a seal SSL between the upper mother substrate UMB and the lower mother substrate LMB but may include a filler FLL. In this case, the filler FLL may extend from the display area DA and be disposed in at least one of the first to fourth edge regions NDA1-1, NDA1-2, NDA1-3, and NDA1-4. The filler FLL extended from the display area DA may be disposed over the entire area of ​​at least one of the first to fourth edge regions NDA1-1, NDA1-2, NDA1-3, and NDA1-4 where no seal SSL is disposed, as shown in FIG.

[0157] The plurality of unit display panels DPU may include a plurality of first unit display panels DPU1 and a plurality of second unit display panels DPU2 spaced apart from the plurality of first unit display panels DPU1 in the first direction DR1 and alternately arranged.

[0158] In one embodiment, a seal SSL may be disposed in two of the first to fourth edge regions NDA1-1, NDA1-2, NDA1-3, and NDA1-4 defined in each of the first unit display panels DPU1, and the seal SSL may have a cross section as shown in Fig. 6. In this case, a filler FLL may be extended and disposed in the remaining two of the first to fourth edge regions NDA1-1, NDA1-2, NDA1-3, and NDA1-4 defined in each of the first unit display panels DPU1, where the seal SSL is not disposed, and the seal SSL may have a cross section as shown in Fig. 7.

[0159] In one embodiment, a seal SSL may be disposed in one of the first to fourth edge regions NDA1-1, NDA1-2, NDA1-3, and NDA1-4 defined in the plurality of second unit display panels DPU2, and the seal SSL may have a cross section as shown in Fig. 6. In this case, a filler FLL may be extended and disposed in the remaining three edge regions NDA1-1, NDA1-2, NDA1-3, and NDA1-4 defined in the plurality of second unit display panels DPU2, in which the seal SSL is not disposed, and the seal SSL may have a cross section as shown in Fig. 7.

[0160] 8B , in the plurality of first unit display panels DPU1, a seal SSL may be disposed in the second edge region NDA1-2 and the third edge region NDA1-3. In the plurality of first unit display panels DPU1, a seal SSL may not be disposed in the first edge region NDA1-1 and the fourth edge region NDA1-4, and a filler FLL may be disposed therein as an extension. In the plurality of second unit display panels DPU2, a seal SSL may be disposed in the second edge region NDA1-2. In the plurality of second unit display panels DPU2, a seal SSL may not be disposed in the first edge region NDA1-1, the third edge region NDA1-3, and the fourth edge region NDA1-4, and a filler FLL may be disposed therein as an extension.

[0161] 8C , in the plurality of first unit display panels DPU1, a seal SSL may be disposed in the first edge region NDA1-1 and the third edge region NDA1-3. In the plurality of first unit display panels DPU1, a seal SSL may not be disposed in the second edge region NDA1-2 and the fourth edge region NDA1-4, and a filler FLL may be disposed therein as an extension. In the plurality of second unit display panels DPU2, a seal SSL may be disposed in the first edge region NDA1-1. In the plurality of second unit display panels DPU2, a seal SSL may not be disposed in the second edge region NDA1-2, the third edge region NDA1-3, and the fourth edge region NDA1-4, and a filler FLL may be disposed therein as an extension.

[0162] In another embodiment, a seal SSL may be disposed in two of the first to fourth edge regions NDA1-1, NDA1-2, NDA1-3, and NDA1-4 defined in the plurality of second unit display panels DPU2, and the cross section may be as shown in Fig. 6. In this case, a filler FLL may be extended and disposed in the remaining two of the first to fourth edge regions NDA1-1, NDA1-2, NDA1-3, and NDA1-4 defined in the plurality of second unit display panels DPU2, where the seal SSL is not disposed, and the cross section may be as shown in Fig. 7.

[0163] 8A , in both the plurality of first unit display panels DPU1 and the plurality of second unit display panels DPU2, a seal SSL may be disposed in the edge regions of the first edge region NDA1-1 and the second edge region NDA1-2. In the plurality of first unit display panels DPU1 and the plurality of second unit display panels DPU2, a seal SSL may not be disposed in the third edge region NDA1-3 and the fourth edge region NDA1-4, but a filler FLL may be disposed in an extended manner.

[0164] 8E, in the plurality of first unit display panels DPU1 and the plurality of second unit display panels DPU2, the seal SSL may be disposed in the first edge region NDA1-1 and the third edge region NDA1-3. In the plurality of first unit display panels DPU1 and the plurality of second unit display panels DPU2, the seal SSL may not be disposed in the second edge region NDA1-2 and the fourth edge region NDA1-4, but the filler FLL may be disposed in an extended manner.

[0165] In still another embodiment, a seal SSL may be disposed in three of the first to fourth edge regions NDA1-1, NDA1-2, NDA1-3, and NDA1-4 defined in the plurality of second unit display panels DPU2, and the seal SSL may have the cross section shown in Fig. 6. In this case, a filler FLL may be extended and disposed in the remaining region among the first to fourth edge regions NDA1-1, NDA1-2, NDA1-3, and NDA1-4 defined in the plurality of second unit display panels DPU2 where the seal SSL is not disposed, and the seal SSL may have the cross section shown in Fig. 7.

[0166] 8D , in the plurality of first unit display panels DPU1, a seal SSL may be disposed in the first edge region NDA1-1 and the second edge region NDA1-2. In the plurality of first unit display panels DPU1, a seal SSL may not be disposed in the third edge region NDA1-3 and the fourth edge region NDA1-4, but a filler FLL may be disposed therein. In the plurality of second unit display panels DPU2, a seal SSL may be disposed in the first edge region NDA1-1, the second edge region NDA1-2, and the fourth edge region NDA1-4. In the plurality of second unit display panels DPU2, a seal SSL may not be disposed in the third edge region NDA1-3, but a filler FLL may be disposed thereinin an extended manner.

[0167] As shown in Figures 8A to 8E, the edge region NDA1 included in the unit display panel DPU may have a seal SSL disposed in at least one region and no seal SSL disposed in at least one region. A display panel assembly ASS including such a structure can minimize the process of forming the seal SSL compared to a display panel assembly ASS including a structure in which the seal SSL is formed in all edge regions NDA1. Furthermore, bending and overlapping of the seal SSL in regions where edge regions NDA1-1, NDA1-2, NDA1-3, and NDA1-4 contact each other can be minimized. This can prevent the seal SSL from being partially underfilled or overfilled, which can lead to seal SSL rupture failure. For example, edge regions NDA1-1 and NDA1-3 contact each other at the corners of the unit display panel DPU. Furthermore, edge region NDA1 is bent and overlapped from edge region NDA1-1 to edge region NDA1-3. In other words, the edge regions NDA1-1 and NDA1-3 are continuous regions that are curved. When a seal SSL is formed in the edge regions NDA1-1 and NDA1-3, which have such curved and overlapping regions, for example, a seal SSL material that has fluidity before hardening is filled into the seal filling portion of the edge regions NDA1-1 and NDA1-3 (the space where the seal SSL is formed in FIG. 6). In this case, in areas of the edge region NDA1 that contact each other, such as corners, the seal SSL material comes into contact with each other when filled. This can cause the filling pressures of the seal SSL materials to interact with each other, resulting in insufficient filling of the seal SSL material (underfilling) or excessive filling of the seal SSL material (overfilling). In this embodiment, by not forming the seal SSL in all edge regions NDA1 (edge ​​regions NDA1-1, NDA1-2, NDA1-3, and NDA1-4), the number of areas where the edge regions bend and overlap with each other can be reduced. Therefore, the above-mentioned under-filling or over-filling of the seal SSL material can be prevented, and the seal SSL can be prevented from bursting.

[0168] Although the present invention has been described above with reference to preferred embodiments, it should be understood by those skilled in the art or those having ordinary knowledge in the art that various modifications and changes can be made to the present invention without departing from the spirit and technical scope of the present invention as set forth in the claims below. Therefore, the technical scope of the present invention should not be limited to the contents of the detailed description of the specification, but should be determined by the claims. [Explanation of symbols]

[0169] ASS: Display panel assembly UMB: Upper motherboard LMB: Lower motherboard DPU: Unit display panel DP: Display panel USB: Upper board LSB: Lower board NDA: Non-display area DA:Display area

Claims

1. In a display panel in which a display area and a non-display area surrounding the display area are defined, the display panel includes a lower substrate including a light emitting element layer, an upper substrate disposed on the lower substrate, and a filler disposed between the lower substrate and the upper substrate and overlapping the display area, The non-display area includes: a first edge region extending in a first direction; a second edge region disposed apart from the first edge region in a second direction perpendicular to the first direction and extending in the first direction; a third edge region extending in the second direction and connecting one side of the first edge region and one side of the second edge region; and a fourth edge region is defined, the fourth edge region being spaced apart from the third edge region in the first direction and extending in the second direction; a seal is disposed between the upper substrate and the lower substrate in at least one of the first to fourth edge regions; The filler is disposed in at least one of the first to fourth edge regions, extending from the display region.

2. The display panel of claim 1 , wherein the seal is disposed directly between the upper substrate and the lower substrate to bond the upper substrate and the lower substrate together.

3. The seal is disposed in one of the first edge region to the fourth edge region, The display panel of claim 1 , wherein the filler is extended to cover the remaining three areas of the first to fourth edge areas where the seal is not provided.

4. The seal is disposed in two of the first to fourth edge regions, The display panel of claim 1 , wherein the filler is extended to the remaining two areas of the first to fourth edge areas where the seal is not disposed.

5. The seal is disposed in three of the first to fourth edge regions, The display panel of claim 1 , wherein the filler is extended to one of the first to fourth edge regions where the seal is not disposed.

6. The display panel of claim 1 , wherein the non-display area further comprises a pad area spaced apart from the display area and adjacent to the first edge area.

7. The lower substrate is The light-emitting element layer further includes a sealing layer disposed on the light-emitting element layer; the sealing layer includes a first inorganic sealing layer disposed on the light-emitting element layer, an organic sealing layer disposed on the first inorganic sealing layer, and a second inorganic sealing layer disposed on the organic sealing layer; The display panel according to claim 1 , wherein the seal overlaps the first inorganic sealing layer and the second inorganic sealing layer, but does not overlap the organic sealing layer.

8. A display panel assembly including a plurality of unit display panels each having a display area and a non-display area surrounding the display area, the display panel assembly includes a lower mother substrate including a light emitting device, an upper mother substrate disposed on the lower mother substrate, and a filler disposed between the lower mother substrate and the upper mother substrate, the filler overlapping the display area, The non-display area includes: a first edge region extending in a first direction; a second edge region disposed apart from the first edge region in a second direction perpendicular to the first direction and extending in the first direction; a third edge region extending in the second direction and connecting one side of the first edge region and one side of the second edge region; and a fourth edge region is defined, the fourth edge region being spaced apart from the third edge region in the first direction and extending in the second direction; a seal is disposed between the upper and lower mother substrates in at least one of the first to fourth edge regions; The filler is disposed in at least one of the first to fourth edge regions so as to extend from the display area.

9. The display panel assembly of claim 8 , further comprising a cutting region surrounding each of the plurality of unit display panels.

10. The display panel assembly of claim 8 , wherein the seal is disposed directly between the upper and lower mother substrates to bond the upper and lower mother substrates together.

11. The display panel assembly of claim 8 , wherein the non-display area further comprises a pad area spaced apart from the display area and adjacent to the first edge area.

12. the plurality of unit display panels includes a plurality of first unit display panels and a plurality of second unit display panels spaced apart from the plurality of first unit display panels in the first direction and alternately arranged, the sticker is disposed in two of the first to fourth edge regions defined in the plurality of first unit display panels; 9. The display panel assembly of claim 8, wherein the filler is extended and disposed in the remaining two areas where the seal is not disposed among the first to fourth edge areas defined in the plurality of first unit display panels.

13. the seal is disposed in one of the first to fourth edge regions defined in the plurality of second unit display panels; 13. The display panel assembly of claim 12, wherein the filler is extended and disposed in the remaining three areas of the first to fourth edge areas defined in the plurality of second unit display panels where the seal is not disposed.

14. In the plurality of first unit display panels, the seal is disposed on the second edge region and the third edge region; The filler is disposed in an extended manner in the first edge region and the fourth edge region, In the plurality of second unit display panels, The seal is disposed in the second edge region; The display panel assembly of claim 13 , wherein the filler is extended in the first edge region, the third edge region, and the fourth edge region.

15. In the plurality of first unit display panels, The seal is disposed on the first edge region and the third edge region; The filler is disposed in an extended manner in the second edge region and the fourth edge region, In the plurality of second unit display panels, The seal is disposed in the first edge region; The display panel assembly of claim 13 , wherein the filler is extended in the second edge region, the third edge region, and the fourth edge region.

16. The sticker is disposed in two of the first to fourth edge regions defined in the plurality of second unit display panels, 13. The display panel assembly of claim 12, wherein the filler is extended and disposed in the remaining two areas where the seal is not disposed among the first to fourth edge areas defined in the plurality of second unit display panels.

17. In both the plurality of first unit display panels and the plurality of second unit display panels, The seal is disposed on the first edge region and the second edge region; The display panel assembly of claim 16 , wherein the filler is extended in the third edge region and the fourth edge region.

18. In both the plurality of first unit display panels and the plurality of second unit display panels, The seal is disposed on the first edge region and the third edge region; The display panel assembly of claim 16 , wherein the filler is extended in the second edge region and the fourth edge region.

19. the seal is disposed in three of the first to fourth edge regions defined in the plurality of second unit display panels; 13. The display panel assembly of claim 12, wherein the filler is extended and disposed in one of the first to fourth edge regions defined in the plurality of second unit display panels where the seal is not disposed.

20. In the plurality of first unit display panels, The seal is disposed on the first edge region and the second edge region; The filler is extended and disposed in the third edge region and the fourth edge region, In the plurality of second unit display panels, the seal is disposed in the first edge region, the second edge region, and the fourth edge region; The display panel assembly of claim 19 , wherein the filler is extended in the third edge region.

21. a display panel having a display area and a non-display area surrounding the display area defined therein; an input sensor disposed above the display panel; a window positioned over the input sensor; a housing disposed below the display panel, the display panel includes a lower substrate including a light emitting element layer, an upper substrate disposed on the lower substrate, and a filler disposed between the lower substrate and the upper substrate and overlapping the display area, The non-display area includes: a first edge region extending in a first direction; a second edge region disposed apart from the first edge region in a second direction perpendicular to the first direction and extending in the first direction; a third edge region extending in the second direction and connecting one side of the first edge region and one side of the second edge region; and a fourth edge region is defined, the fourth edge region being spaced apart from the third edge region in the first direction and extending in the second direction; a seal is disposed between the upper substrate and the lower substrate in at least one of the first to fourth edge regions; The electronic device has the filler disposed in at least one of the first to fourth edge regions, the filler extending from the display region.

22. 22. The electronic device of claim 21, which is one of a television, an external billboard, a monitor, a mobile phone, a tablet, a navigation system, and a game console.

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