Semiconductor device

Abstract

To provide a transistor having both the light-transmitting property and the so-called normally-off characteristic, a transistor having both the light-transmitting property and a characteristic of reduced off-current, a transistor having both the light-transmitting property and a characteristic of reduced on-current loss, and a transistor whose change in characteristic over time is suppressed.SOLUTION: In a transistor 151, an oxide semiconductor with a wide band gap in which the carrier concentration is suppressed as much as possible is used for an oxide semiconductor layer 123 including a channel formation region. In a source electrode and drain electrodes 115a and 115b, an oxide conductor containing hydrogen and oxygen deficiency is used. Barrier layers 114a and 114b that interrupt the diffusion of hydrogen and oxygen are provided between the oxide conductive layer and the oxide semiconductor layer. The oxide conductive layer and the oxide semiconductor layer are electrically connected to each other through the barrier layers.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device using a semiconductor element and a method for manufacturing the semiconductor device.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to semiconductor elements such as transistors, semiconductor circuits using semiconductor elements, and electro-optical equipment. All devices and electronic equipment are semiconductor devices. [Background technology]

[0003] A transistor is manufactured using an oxide semiconductor for a channel formation region, and the transistor is The technology is attracting attention for its application to physical circuits, ICs, electro-optical devices, and electronic equipment.

[0004] In particular, oxide semiconductors with a wide band gap transmit visible light, so light-transmitting oxides By combining a gate electrode, a source electrode, and a drain electrode using a conductor, a light-transmitting Attempts have been made to fabricate transistors that

[0005] For example, as one mode of a transistor in which an oxide semiconductor is used for a channel formation region, A semiconductor including zinc oxide or an In-Ga-Zn-O-based oxide semiconductor is deposited on a substrate having a surface. A transistor is formed using a thin film (a few to several hundred nm thick) and used as a switch for an image display device. Patent Documents 1 and 2 disclose techniques used in coupling elements and the like.

[0006] In addition, a transistor using an oxide semiconductor for a channel formation region (also referred to as a channel region) has a higher field-effect mobility than a transistor using amorphous silicon. In addition, the oxide semiconductor film can be formed by a sputtering method or the like, and the oxide semiconductor film can be formed by a polycrystalline silicon. The manufacturing process is simpler than that of silicon-based transistors.

[0007] On the other hand, oxide conductors, which are transparent to visible light and conductive, are used in liquid crystal displays and other displays. It is used as a transparent electrode material required for display devices. Many of the oxide conductors in use today contain metal oxides with wide bandgaps.

[0008] Examples of the transparent oxide conductor include an indium oxide tin oxide alloy (InO 3-SnO2, abbreviated as ITO), zinc oxide, zinc oxide doped with aluminum (AZ Examples include gallium-doped zinc oxide (GZO) and zinc oxide doped with gallium (O).

[0009] Many of these light-transmitting oxide conductors are oxide semiconductors to which impurities or the like are added. For example, tin is used in ITO, aluminum in AZO, and is doped with gallium as an impurity.

[0010] In addition, when the oxide conductor is formed into a film by sputtering, the conductivity varies depending on the film formation conditions. For example, Patent Documents 3 and 4 disclose a method for producing a high conductivity The present invention discloses a technique for forming an oxide conductive layer having the above structure in a reducing atmosphere containing hydrogen. When a film is formed in a reducing atmosphere containing hydrogen and oxygen, a conductive oxide film containing hydrogen and oxygen vacancies is formed. It is said that the conductivity of the conductive film is improved.

[0011] Zinc oxide, which is an example of an oxide semiconductor with a wide band gap, exhibits electrical conductivity. Regarding the reason, Non-Patent Document 1 suggests that shallow donor levels formed by hydrogen contribute to this. There are.

[0012] Furthermore, the resolution of the screen of a display device, which is one embodiment of a semiconductor device, is high-definition (HD, 1366 x 768), Full HD (FHD, 1920 x 1080) and high definition The trend is toward high resolutions such as 3840x2048 or 4096x2160. The development of 4K digital cinema display devices is also being accelerated.

[0013] As the resolution of such display devices increases, the pixels become increasingly finer. is remarkable.

[0014] An active matrix semiconductor device in which pixels each having a transistor are arranged in a matrix. In the case of LCDs, as pixels become smaller, the area occupied by the transistors in the pixels increases, resulting in a decrease in the aperture ratio. Therefore, the following problem has arisen: Improved pixel aperture ratio for LCDs, electroluminescent displays ( The technology is expected to be applied to display devices such as EL displays (also known as LED displays) or electronic paper. It is being done.

[0015] In addition, as the number of pixels increases, the writing time per pixel becomes shorter, and the transistors Fast operating characteristics and large on-state current are required. In addition, the recent problem of energy depletion Therefore, there is a demand for a display device with reduced power consumption. When the value is 0, the device has the off-state, or so-called normally-off characteristics, and the off-current is low and there is no unnecessary leakage. There is a need for transistors with reduced current.

[0016] In addition, in the case of large display devices, the screen size is 60 inches or more diagonally, and further, Development is underway with a view to screen sizes of 20 inches or more. There is also a need for technology to suppress the increase in wiring resistance that accompanies larger devices. [Prior art documents] [Patent documents]

[0017] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Patent Document 3] Japanese Patent Application Publication No. 5-275727 [Patent Document 4] Japanese Patent Application Publication No. 9-293693 [Non-patent literature]

[0018] [Non-Patent Document 1] WALLE.C, "Hydrogen as a Cause of Doping in Zinc Oxide", PHYS. REV. LETT. (PHYSICAL REVIEW LETTERS), July 31, 2000, Vol. 85, No. 5, pp. 1012-1015 Summary of the Invention [Problem to be solved by the invention]

[0019] As described above, reduction in power consumption is also required in light-transmitting transistors. The invention was made against this technical background.

[0020] Therefore, the objective is to develop a transistor that has both light transmission and so-called normally-off characteristics. Another object of the present invention is to provide a semiconductor device that has both light-transmitting properties and reduced off-state current. Another object of the present invention is to provide a transistor having light transmittance and low on-current loss. Another object of the present invention is to provide a transistor having excellent characteristics over time. An object of the present invention is to provide a transistor in which change in property is suppressed.

[0021] The invention disclosed below aims to solve any one of the above problems. [Means for solving the problem]

[0022] In order to provide a light-transmitting transistor, a gate electrode is formed using a light-transmitting conductive film. , source electrode, and drain electrode must be fabricated. To reduce the loss, it is necessary to increase the conductivity of the source and drain electrodes. In the case where a light-transmitting conductive layer is used for the source electrode and the drain electrode of a transistor, An oxide conductive layer is preferable, and in particular, it is a layer containing oxygen deficiency and impurities (e.g., hydrogen) that increase the conductivity. The oxide conductive layer containing the metal oxide is preferable because it has high conductivity.

[0023] In addition, in order to provide a light-transmitting transistor, a semiconductor layer including a channel formation region To reduce the power consumption of a transistor, a normally-off transistor is required. The transistor characteristics that the off-current is sufficiently suppressed as well as the operating characteristics are required. The oxide semiconductor layer has a suppressed carrier concentration and a wide band gap. It is suitable for semiconductor layers including formation regions.

[0024] However, oxide conductors containing oxygen vacancies or impurities (such as hydrogen) that have the effect of increasing conductivity The oxide semiconductor layer has a suppressed carrier concentration and a wide band gap. However, if a configuration in which the power supply is directly connected is adopted, the following problems arise.

[0025] Impurities such as hydrogen contained in the oxide conductive layer are converted into oxide through the interface between the oxide conductive layer and the oxide semiconductor layer. When the impurities diffuse into the oxide semiconductor layer, the impurity concentration in the oxide conductive layer decreases, and the impurities in the oxide semiconductor layer As a result, the impurity concentration in the oxide conductive layer decreases, which leads to a decrease in conductivity. The on-state current loss of the transistor increases. This leads to an increase in carrier concentration, resulting in a normally-off operating characteristic and a characteristic where the off-current is sufficiently suppressed. Therefore, it becomes difficult to realize a transistor having the required characteristics.

[0026] In addition, oxygen is introduced into the oxygen vacancies in the oxide conductive layer through the interface between the oxide conductive layer and the oxide semiconductor layer. When oxygen diffuses from the oxide semiconductor layer, the number of oxygen vacancies in the oxide conductive layer decreases, and the oxide semiconductor layer The decrease in oxygen vacancies in the oxide conductive layer leads to a decrease in conductivity. This leads to an increase in on-state current loss of the transistor. The electron deficiency leads to an increase in the carrier concentration, and the normally-off characteristics and off-current are sufficiently suppressed. Therefore, it becomes difficult to realize a transistor with such characteristics.

[0027] In order to achieve the above object, the oxide conductive material forming the source electrode and the drain electrode is and suppressing the transfer of hydrogen and oxygen in a region where the insulating layer is electrically connected to the oxide semiconductor layer. good.

[0028] Specifically, the carrier concentration in the oxide semiconductor layer including the channel formation region is reduced as much as possible. The source electrode and the drain electrode are formed by using an oxide semiconductor having a wide band gap. The rain electrode uses an oxide conductor containing hydrogen and oxygen vacancies, and the oxide conductive layer and the oxide A barrier layer that prevents the diffusion of hydrogen and oxygen is provided between the semiconductor layers, and the barrier layer The oxide conductive layer and the oxide semiconductor layer may be electrically connected to each other.

[0029] That is, one embodiment of the present invention is a light-transmitting gate electrode formed on an insulating surface of a light-transmitting substrate. a first insulating layer on the gate electrode; and a highly purified oxide semiconductor on the first insulating layer. a conductive layer, a first electrode and a second electrode, the ends of which overlap the gate electrode on the oxide semiconductor layer; The semiconductor device further includes a first electrode and a second electrode. a light-transmitting barrier layer between the first electrode and the second electrode; The semiconductor device has a second insulating layer in contact with the surface opposite to the region where the hole is formed. , the carrier concentration of the oxide semiconductor layer is 1×10 14 / cm 3 The first electrode and The second electrode is transparent and has a resistivity of 2000×10 -6 Oxide conductive material with a resistance of less than Ω·cm The semiconductor device includes a nitride-containing barrier layer.

[0030] Furthermore, one embodiment of the present invention is a semiconductor device including a gate wiring electrically connected to a gate electrode. The semiconductor device includes a metal.

[0031] In one embodiment of the present invention, the first electrode or the second electrode is connected to the second insulating layer through an opening formed in the second insulating layer. The semiconductor device has a signal line electrically connected to the second electrode, the signal line including a metal. .

[0032] In addition, one embodiment of the present invention includes a third insulating layer over a signal line, and a first insulating layer is the semiconductor device in contact with the periphery.

[0033] In addition, one aspect of the present invention is a semiconductor device including a first capacitance electrode on a substrate, and a first insulating layer on the first capacitance electrode. and a second capacitance electrode on the first insulating layer. The first capacitance electrode is the same as the gate electrode. a semiconductor including a first electrode and a second electrode, the second electrode including the same material as the first electrode and the second electrode; It is a device.

[0034] In addition, one embodiment of the present invention is a method for manufacturing a semiconductor device including a first insulating layer, a second insulating layer, and a gate insulating layer at an intersection of a gate wiring and a signal line. The present invention also provides the semiconductor device as described above, in which an oxide semiconductor layer is sandwiched.

[0035] Another embodiment of the present invention is a semiconductor device including the above semiconductor device and a second a gate electrode, a first insulating layer on the second gate electrode, and an oxide semiconductor layer on the first insulating layer; a channel protection layer overlapping a channel formation region of the oxide semiconductor layer; and a gate insulating film on the channel protection layer. The second gate electrode has a third electrode having an end portion, and a fourth electrode. the channel protection layer is made of the same material as the wiring, and the channel protection layer is made of the same material as the second insulating layer; The third electrode and the fourth electrode are made of the same material as the signal line.

[0036] Another embodiment of the present invention is a light-transmitting oxide conductive film formed on an insulating surface of a light-transmitting substrate. forming a gate electrode including a gate electrode body; forming a first insulating layer on the gate electrode; A light-transmitting oxide semiconductor layer was formed in an inert gas atmosphere. The substrate is heated at a temperature of 350°C to 700°C to form a barrier layer covering the oxide semiconductor layer. a light-transmitting oxide conductive layer is formed on the barrier layer in a reducing atmosphere; a first electrode having an end portion overlapping the first electrode and electrically connected to the oxide semiconductor layer via a barrier layer; and A second electrode is formed, and a second insulating layer is formed on the oxide semiconductor layer, the first electrode, and the second electrode. The carrier concentration is 1×10 14 / cm 3 and an oxide semiconductor layer with a resistivity of less than 20 00×10 -6 The present invention provides a method for manufacturing a semiconductor device having an oxide conductive layer with a resistivity of Ω·cm or less.

[0037] In this specification, the term "translucent" refers to the property of transmitting light at least in the visible wavelength range. Refers to...

[0038] The term "gate" refers to a gate electrode and a part or all of the gate wiring. The line is a line that electrically connects the gate electrode of at least one transistor to another electrode or another wiring. For example, the scanning lines in a display device are also included in the gate wiring. It can be enjoyed.

[0039] The source refers to a source region, a source electrode, and part or all of the source wiring. The source region is a region of the semiconductor layer whose resistivity is below a certain value. An electrode is a conductive layer that supplies carriers to a semiconductor layer. In order to electrically connect the source electrode of one transistor to another electrode or another wiring, For example, a signal line in a display device is electrically connected to a source electrode. In this case, the source wiring also includes the signal line.

[0040] The drain refers to the drain region, the drain electrode, and part or all of the drain wiring. The drain region is the region of the semiconductor layer whose resistivity is below a certain value. The drain electrode is a conductive layer through which carriers flow out of the semiconductor layer. The wiring is a wiring that connects the drain electrode of at least one transistor to another electrode or another wiring. For example, the signal line in a display device is a drain electrode. When the signal line is electrically connected to the electrode, the drain wiring also includes the signal line.

[0041] In addition, in this document (specification, claims, drawings, etc.), The source and drain are interchangeable depending on the transistor structure and operating conditions. It is difficult to determine whether the deviation is the source or the drain. In the specification, claims, drawings, etc., The arbitrarily selected terminal is referred to as one of the source and drain, and the other terminal is referred to as the source and drain. It is written as the other side of the inn.

[0042] In this specification, silicon nitride oxide refers to a material containing more nitrogen than oxygen as its composition. Preferably, the composition range is within the range of 0.1 to 1.0 μm, as measured by RBS and HFS. The range is oxygen 5 to 30 atomic %, nitrogen 20 to 55 atomic %, silicon 25 to 35 atomic %, water The content ratio of the constituent elements is in the range of 10 to 30 atomic %. The total value does not exceed 100 atomic percent. [Effects of the Invention]

[0043] A transistor having light-transmitting and normally-off characteristics can be provided. It is possible to provide a transistor having reduced current characteristics. It is possible to provide a transistor having characteristics with little loss. As a result, the above-described light-transmitting transistor having excellent reliability can be provided. [Brief explanation of the drawings]

[0044] [Figure 1] 1A to 1C illustrate a semiconductor device according to an embodiment; [Figure 2] FIG. 10 is a cross-sectional view of a transistor including an oxide semiconductor. [Figure 3] Energy band diagram (schematic diagram) at the A-A' cross section in Figure 2. [Figure 4] (A) shows the state where a positive potential (VG>0) is applied to the gate (GE1), and (B) shows the state where a negative potential (VG<0) is applied to the gate (GE1). [Figure 5] A diagram showing the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). [Figure 6] 1A to 1C illustrate a semiconductor device according to an embodiment; [Figure 7] 1A to 1C illustrate a manufacturing method of a semiconductor device according to an embodiment; [Figure 8] 1A to 1C are diagrams illustrating terminals of a semiconductor device according to an embodiment; [Figure 9] 1A and 1B are diagrams illustrating an inverter circuit according to an embodiment; [Figure 10] FIG. 1 is a block diagram illustrating a display device. [Figure 11] FIG. 2 illustrates a configuration of a signal line driver circuit. [Figure 12] FIG. 2 is a diagram illustrating the configuration of a shift register. [Figure 13] 1A and 1B are a circuit diagram and a timing chart illustrating the operation of a shift register; [Figure 14] 1A to 1C illustrate a semiconductor device according to an embodiment; [Figure 15] 1A to 1C illustrate a semiconductor device according to an embodiment; [Figure 16] 1A and 1B are diagrams illustrating pixel equivalent circuits of a semiconductor device according to an embodiment; [Figure 17] 1A to 1C illustrate a semiconductor device according to an embodiment; [Figure 18] 1A to 1C illustrate a semiconductor device according to an embodiment; [Figure 19] 1A to 1C illustrate a semiconductor device according to an embodiment; [Figure 20] 1A and 1B are diagrams illustrating examples of usage of electronic paper. [Figure 21] FIG. 1 is an external view showing an example of an electronic book. [Figure 22] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 23] FIG. 1 is an external view showing an example of a gaming machine. [Figure 24] FIG. 1 is an external view showing an example of a mobile phone. DETAILED DESCRIPTION OF THE INVENTION

[0045] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiments, and various changes and modifications may be made in the form and details thereof without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be achieved by the following embodiments. It should not be construed as being limited to the contents of the description. The same reference numerals are used in different drawings to denote the same parts or parts having similar functions. A repeated explanation will be omitted.

[0046] (Embodiment 1) In this embodiment, a bottom-gate transistor that transmits visible light is used as one mode of a semiconductor device. Regarding the register, Figure 1(A-1), Figure 1(A-2), Figure 1(B-1), and Figure 1(B-2) ) will be used to explain.

[0047] 1A-1 and 1A-2 show a transistor using a light-transmitting conductive film. 10A and 10B are diagrams illustrating an example of forming an electrode and a wiring connected to the transistor.

[0048] In addition, FIG. 1(B-1) and FIG. 1(B-2) show a transistor formed using a light-transmitting conductive film. In this example, an electrode of a transistor is formed, and a wiring connected to the transistor is formed using a conductive film containing metal. FIG.

[0049] One embodiment of the structure of a bottom-gate transistor that transmits visible light is shown in FIG. 1(A-1), and FIG. 1(A-1) is a top view showing the planar structure of a transistor. FIG. 1(A-2) is a cross-sectional view showing a layered structure of a transistor. The chain line P1-P2 in the figure corresponds to the cross section P1-P2 in FIG. 1(A-2).

[0050] The cross section P1-P2 shows the stacked structure of the transistor 151. A gate electrode 1 formed of a first conductive layer having light-transmitting properties on a substrate 100 having light-transmitting properties. 11a, a first insulating layer 102 having light-transmitting properties on the gate electrode 111a, and a gate electrode 1 A transparent oxide semiconductor including a channel forming region is in contact with the first insulating layer 102 on the substrate 11a. and a conductor layer 123.

[0051] Further, an end portion of the gate electrode 111a is overlapped with the second conductive layer having light transmitting properties. The device has a first electrode 115a and a second electrode 115b. The first electrode 115a is a barrier electrode. The second electrode 115b is an oxide semiconductor via the layer 114a, and the second electrode 115b is an oxide semiconductor via the barrier layer 114b. The first electrode 115a and the second electrode 115b are electrically connected to the conductive layer 123. It functions as the source electrode or drain electrode of the transistor 151 .

[0052] The transistor 151 includes a first electrode 115a, a second electrode 115b, a first insulating layer The second insulating layer 107 is provided over the oxide semiconductor layer 102 and the oxide semiconductor layer 123 .

[0053] Since all layers constituting the transistor 151 have a light-transmitting property, the transistor 151 is transparent. It has photosensitivity.

[0054] Another embodiment of the structure of a bottom-gate transistor that transmits visible light is shown in FIG. 1(B-1) and 1(B-2). FIG. 1(B-1) is a top view showing the planar structure of a transistor. 1(B-2) is a cross-sectional view showing the stacked structure of a transistor. The dashed line Q1-Q2 in Figure 1(B-1) corresponds to the cross section Q1-Q2 in Figure 1(B-2). do.

[0055] Cross section Q1-Q2 shows the stacked structure of transistor 152. The gate electrode 111a has a light-transmitting property on a light-transmitting substrate 100. The electrode 111a is connected to a gate wiring layer containing metal (not shown). a first insulating layer 102 having light-transmitting properties on the gate electrode 111a; a light-transmitting oxide semiconductor layer 123 including a channel formation region and in contact with the oxide semiconductor layer 102; .

[0056] The first electrode 115a and the second electrode 115b are formed on the gate electrode 111a, and the ends of the first electrode 115a and the second electrode 115b are overlapped on the gate electrode 111a. The first electrode 115a is connected to the barrier layer 114a via the barrier layer 114a. The second electrode 115b is electrically connected to the oxide semiconductor layer 123 via the barrier layer 114b. The first electrode 115a and the second electrode 115b are connected to the source electrode of the transistor 152. It functions as a positive or drain electrode.

[0057] In addition, the first electrode 115a, the second electrode 115b, the oxide semiconductor layer 123, and the first A second insulating layer 107 is provided on the insulating layer 102. The signal line 116a is connected to the second insulating layer 107. The signal line 116b is connected to the first electrode 115a through an opening 127a formed in the The insulating layer 107 is connected to the second electrode 115b through an opening 127b formed therein.

[0058] The transistor 152 is connected to the signal line 116a, the signal line 116b, and the second insulating layer 116b. A third insulating layer 108 is provided on the insulating layer 107. A conductive layer 129 is provided on the third insulating layer 108. It is okay to do so.

[0059] The first insulating layer 107 is exposed through the openings 126a and 126b formed in the second insulating layer 107. The insulating layer 102a, which is a part of the first insulating layer, and the third insulating layer 108 are in contact with each other. By using the same type of insulating layer as the third insulating layer 108, the insulating layers 102a and 108 are in close contact with each other. The transistor 152 is surrounded and in contact with the transistor 152 .

[0060] Note that all layers constituting the transistor 152 have light-transmitting properties. The electrode of the transistor 152 is formed using a conductive film containing metal. Since the transistor is connected to the wiring, it is possible to configure a semiconductor device with reduced wiring resistance. The transistor 152 is surrounded by an insulating layer of the same type, which prevents the diffusion of impurities from the outside. It is controlled and has excellent reliability.

[0061] In addition, the conductive layer 129 is provided so as to overlap with a channel formation region of the oxide semiconductor layer 123. By this, the transistor in the bias-thermal stress test (hereinafter referred to as BT test) The amount of change in the threshold voltage of 152 can be reduced. The test conditions were 85°C, 2 x 10 6 V / cm for 12 hours.

[0062] In this embodiment, the oxide semiconductor layer 123 has a carrier concentration of 1×10 14 / cm 3 Not yet Highly purified In-Ga-Zn-O oxide with fully suppressed and wide band gap A compound semiconductor is used.

[0063] Highly purified, with a carrier concentration of 1×10 14 / cm 3 preferably less than 1 x 10 12 / cm 3 The band gap is suppressed to be less than 2 eV, and a wide band gap (specifically, 2 eV or more, preferably 2.5 eV) is required. An oxide semiconductor layer having a conductivity of 100 eV or more, more preferably 3 eV or more, is used for a channel formation region. A transistor is in an off state when the potential of its gate electrode is 0 (normally off characteristic). A transistor manufactured using such an oxide semiconductor has a low off-state current. .

[0064] In addition, the carrier concentration in the semiconductor layer where the transistor channel is formed is 1×10 14 / c m 3 Less than 1 x 10 12 / cm 3 It is highly purified and has a wide band gap. The significance of using an oxide semiconductor having such a structure will be described in detail at the end of this embodiment.

[0065] The oxide semiconductor layer may be an In-Sn-Ga-Zn-O based layer, which is a quaternary metal oxide, or Ternary metal oxide layers: In-Ga-Zn-O, In-Sn-Zn-O, and In- Al-Zn-O layer, Sn-Ga-Zn-O layer, Al-Ga-Zn-O layer, Sn-A l-Zn-O based layers, binary metal oxide In-Zn-O based layers, and Sn-Zn-O based layers , Al-Zn-O layer, Zn-Mg-O layer, Sn-Mg-O layer, In-Mg-O layer and oxides such as In-O based layers, Sn-O based layers, and Zn-O based layers, which are single-component metal oxides. The oxide semiconductor layer may contain SiO2.

[0066] InMO3(ZnO) m There are oxide semiconductor materials that are expressed as (m>0), where , M is gallium (Ga), aluminum (Al), iron (Fe), nickel (Ni), manganese (Mn) One or more metal elements selected from manganese (Mn), cobalt (Co), etc. For example, M may be Ga, Ga and Al, Ga and Fe, Ga and Ni, Ga and Mn, Ga, Co, etc. can be used. InGaO3(Z nO) m The oxide semiconductors represented by (m>0) are the In-Ga-Zn-O oxides mentioned above. It is a typical example of a semiconductor material. The above composition is derived from the crystal structure. It should be noted that this is merely an example.

[0067] In addition, the oxide semiconductor layer is subjected to RTA (Rapid Thermal Anneal). Use materials that have been dehydrated or dehydrogenated at high temperature for a short time using methods such as hot thermal annealing. In the oxide semiconductor layer, oxygen vacancies occur during the dehydration or dehydrogenation process. Oxygen must be supplied to the oxygen vacancies. The carrier concentration of the highly purified oxide semiconductor layer is 1×10 14 / cm 3 Less than, good Preferably 1 x 10 12 / cm 3 It is suppressed as follows:

[0068] In this embodiment, the first conductive layer including the gate electrode 111a, the first electrode 115a, and The second conductive layer including the second electrode 115b is formed using a light-transmitting conductive film.

[0069] The light-transmitting conductive film has a thickness that allows visible light transmittance of 75 to 100%. Alternatively, a conductive film that is semi-transparent to visible light may be used. This refers to a transmittance of 50 to 75%.

[0070] In addition, the electrode of the light-transmitting conductive film used as the gate electrode, the first electrode, and the second electrode The air resistivity is 200 x 10 -6 Ω cm or more 2000×10 -6 Ω·cm or less, preferably 250×10 -6 Ω cm or more 2000×10 -6 Ω·cm or less.

[0071] As the light-transmitting conductive film, a conductive oxide film is suitable. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium dioxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide with silicon oxide added Indium tin oxide with silicon oxide added can be used. The crystallinity is suppressed, resulting in an amorphous film with excellent processability. Zinc oxide doped with zinc, zinc oxide doped with gallium, etc. can be used. uses indium tin oxide (ITO).

[0072] The light-transmitting oxide conductive layer can be made conductive depending on its composition, the impurities added, and the film-forming conditions. For example, the oxide conductive film formed in a reducing atmosphere and having oxygen deficiency can be The layer has improved conductivity. In addition, impurities (e.g., compounds containing hydrogen) can be added. This makes the oxide conductive layer amorphous, improving not only the processability but also the conductivity.

[0073] In this embodiment, the barrier layer 114a and the barrier layer 114b are made of titanium nitride. The thickness of the barrier layer is 1 nm or more and 50 nm or less, preferably 2 nm or more and 10 nm or less. It has photosensitivity.

[0074] The barrier layer 114a is formed between the highly purified oxide semiconductor layer 123 and the first electrode 115a. The barrier layer 114b is formed between the highly purified oxide semiconductor layer 123 and the second electrode 11. The barrier layer 114a and the barrier layer 114b are provided between the first and second electrodes 114a and 114b. This is the layer that inhibits

[0075] The barrier layer 114a and the barrier layer 114b are formed to prevent impurities (e.g., hydrogen) contained in the oxide conductive layer. The barrier layer 114 prevents impurities (including atoms) from diffusing into the oxide semiconductor layer. The barrier layer 114a and the barrier layer 114b prevent oxygen atoms contained in the oxide semiconductor layer from diffusing into the oxide conductive layer. Suppress the phenomenon.

[0076] The barrier layer 114a and the barrier layer 114b may be a titanium nitride layer or a titanium nitride layer. Conductive nitride layers such as tungsten nitride, molybdenum nitride, and ultra-thin nitride layers A nitride layer having barrier properties, such as a silicon layer or an aluminum nitride layer, can be used.

[0077] In this embodiment, the first insulating layer 102 is made of silicon nitride (SiN y (y>0) on silicon oxide The second insulating layer 107 is made of silicon oxide and silicon nitride (S iN y (y>0)) is used.

[0078] By using a silicon nitride layer, the oxide semiconductor layer 123 provided in the transistor 151 This can prevent impurities from diffusing from the outside.

[0079] In addition, the first insulating layer 102 on the side in contact with the oxide semiconductor layer 123 and the oxide semiconductor layer 12 By using silicon oxide for the second insulating layer 107 on the side in contact with the oxide semiconductor layer 12 The oxygen deficiency that occurs in 3 can be compensated for by oxygen.

[0080] The silicon oxide and silicon nitride constituting the first insulating layer 102 and the second insulating layer 107 are transparent. It has photosensitivity.

[0081] The first insulating layer 102 may be a silicon nitride oxide layer, a silicon oxynitride layer, a silicon nitride layer, or a silicon nitride layer. In addition to the silicon oxide layer, the oxide of aluminum, tantalum, yttrium, or hafnium , nitride, oxynitride, or oxynitride, or at least two or more of these compounds The compound layer containing the compound may be used as a single layer or as a laminate.

[0082] In particular, when an insulating layer having a higher dielectric constant than silicon oxide is used for the first insulating layer 102, the gate This is preferable because the properties as an insulating layer are improved.

[0083] The substrate 100 is transparent to visible light and has an insulating surface. For example, a glass substrate is used. In addition to plates and ceramic substrates, plastics that have heat resistance enough to withstand the processing temperatures in the manufacturing process A block substrate or the like can be used.

[0084] The glass substrate may be, for example, barium borosilicate glass, aluminoborosilicate glass, or Alternatively, a non-alkali glass substrate such as an aluminosilicate glass substrate may be used. In this embodiment, the substrate 100 is made of alumina. Borosilicate glass is used.

[0085] The size of the substrate may be determined appropriately taking into consideration the purpose of use, manufacturing equipment, etc. 3.5th generation (550mm x 650mm), 3.5th generation (600mm x 720mm, or 62 0mm x 750mm), 4th generation (680mm x 880mm, or 730mm x 920 mm), 5th generation (1100mm x 1300mm), 6th generation (1500mm x 1850 mm), 7th generation (1870mm x 2200mm), 8th generation (2200mm x 2400 mm), 9th generation (2400mm x 2800mm, 2450mm x 3050mm), 1st A glass substrate such as 0th generation (2950 mm x 3400 mm) can be used.

[0086] On the substrate 100, a silicon nitride film or a silicon nitride oxide film is formed as a single layer or a laminated layer as an underlayer. The undercoat film can be formed by a method such as sputtering, CVD, coating, or printing. It should be noted that even if the film is doped with phosphorus (P) or boron (B), good.

[0087] Here, the semiconductor layer in which the transistor channel is formed has a carrier concentration of 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 Highly purified and wide band gap The significance of using an oxide semiconductor having a gate electrode will be described.

[0088] <Intrinsic oxide semiconductor> There has been much research into the properties of oxide semiconductors, such as DOS (density of state). However, these studies do not include the idea of ​​sufficiently reducing the localized levels themselves. In one embodiment of the disclosed invention, water or hydrogen, which may cause localized levels, is removed from an oxide semiconductor. By removing the oxide semiconductor, a highly purified and intrinsic (i-type) oxide semiconductor is produced. This is based on the idea of ​​sufficiently reducing the localized level itself. This makes it possible to manufacture extremely excellent industrial products.

[0089] When removing hydrogen and water, oxygen may also be removed at the same time. Therefore, oxygen is supplied to the dangling bonds of the metal that are generated due to oxygen deficiency, and the localization caused by oxygen vacancies By reducing the intrinsic level, oxide semiconductors can be further purified and made intrinsic (i-type). For example, it is preferable to form a channel formation region including an oxide semiconductor in close proximity to the channel formation region. An oxide film is formed and heat treatment is carried out at temperatures between 200°C and 400°C, typically around 250°C. By doing this, oxygen is supplied from the oxide film to the oxide semiconductor, and the localized levels due to oxygen defects are eliminated. It is possible to reduce the

[0090] The cause of deterioration in the characteristics of oxide semiconductors is the 0.1 eV to 0.2 eV below the conduction band caused by excess hydrogen. This is thought to be due to shallow levels of 100 eV and deep levels due to oxygen deficiency. To eliminate defects, hydrogen is thoroughly removed and oxygen is supplied in sufficient quantities.

[0091] Note that oxide semiconductors are generally n-type. However, in one embodiment of the disclosed invention, By removing impurities such as i and supplying oxygen, which is a constituent element of oxide semiconductors, In this respect, unlike silicon, which is made i-type by adding impurity elements, It can be said that this technology contains a technological concept that has never been seen before.

[0092] <Conduction mechanism of transistors using oxide semiconductors> Here, the conduction mechanism of a transistor using an oxide semiconductor will be explained with reference to FIGS. 2 to 5. In the following explanation, an ideal situation is assumed for ease of understanding. Not all of the information provided reflects the actual situation. It is noted that this is merely an inventive step and does not affect the validity of the invention.

[0093] FIG. 2 is a cross-sectional view of a transistor using an oxide semiconductor. An oxide semiconductor layer (OS) is provided via a gate insulating layer (GI), and a source electrode is provided on top of it. (S) and a drain electrode (D).

[0094] FIG. 3 shows an energy band diagram (schematic diagram) in the cross section A-A' of FIG. The black circles (●) in 3 represent electrons, and the white circles (○) represent holes, each with a charge (-q, +q ) and a positive voltage (VD >0) is applied, and the dashed line indicates the gate voltage When no voltage is applied to the electrode (V G =0), the solid line indicates a positive voltage (V G >0) When no voltage is applied to the gate electrode, the high potential barrier This indicates an off state in which no carriers (electrons) are injected from the electrode to the oxide semiconductor, and no current flows. On the other hand, when a positive voltage is applied to the gate, the potential barrier decreases, and the on-state in which current flows is established. Indicates the state.

[0095] FIG. 4 shows an energy band diagram (schematic diagram) between B-B' in FIG. 4(A) applies a positive potential (V G >0) is a given state, The figure shows the on-state where carriers (electrons) flow between the source and drain. B) applies a negative potential (V G <0) is applied, and the off state ( This shows the case where minority carriers do not flow.

[0096] Figure 5 shows the relationship between the vacuum level and the work function (φ M ) and the electron affinity (χ) of the oxide semiconductor. show.

[0097] At room temperature, electrons in metals are degenerate, and the Fermi level is located within the conduction band. The oxide semiconductor is n-type, and its Fermi level (E f ) is located in the center of the band gap. The intrinsic Fermi level (E i ) and is located closer to the conduction band. It is known that hydrogen acts as a donor in the body and is one of the factors that causes n-type formation.

[0098] In contrast, an oxide semiconductor according to one embodiment of the disclosed invention can convert hydrogen, which is a factor in making the oxide semiconductor n-type, into an oxide. The oxide semiconductor is made of a material that contains as few impurity elements as possible, other than the main components of the oxide semiconductor. By purifying it to such a high level, it becomes genuine (type i) or is intended to become genuine. In other words, instead of adding impurity elements to make it i-type, impurities such as hydrogen and water are removed as much as possible. By doing so, it is highly purified, resulting in true (i-type) or close to true. This results in the Fermi level (E f ) is the intrinsic Fermi level (E i ) It is possible.

[0099] The band gap (E g ) is 3.15 eV, and the electron affinity (χ) is 4.3 V It is said that the work function of titanium (Ti) that constitutes the source and drain electrodes is The electron affinity (χ) of the oxide semiconductor is approximately equal to the electron affinity (χ) of the metal-oxide semiconductor interface. In this case, no Schottky barrier is formed for electrons.

[0100] At this time, the electrons are transported between the gate insulating layer and the highly purified oxide semiconductor, as shown in FIG. The electrons move near the interface with the oxide semiconductor (the lowest energetically stable part of the oxide semiconductor).

[0101] Also, as shown in FIG. 4(B), when a negative potential is applied to the gate electrode (GE1), Since the number of holes, which are carriers, is substantially zero, the current is a value that is infinitely close to zero.

[0102] In this way, high purity oxide semiconductors are used to minimize the inclusion of elements (impurity elements) other than the main components of the oxide semiconductor. By this, the gate insulating layer becomes intrinsic (i-type) or substantially intrinsic. Therefore, the gate insulating layer must have a good interface with the oxide semiconductor. Specifically, for example, power frequencies from the VHF band to the microwave band are required. Insulating layers are produced by CVD using high-density plasma generated by a large number of processes, and by sputtering. It is preferable to use an insulating layer manufactured by a method such as the above.

[0103] The oxide semiconductor is highly purified while the interface between the oxide semiconductor and the gate insulating layer is improved. For example, the channel width W of a transistor is 1×10 4 μm, channel length L In the case of 3 μm, at room temperature, -13 Off-state current of less than A, sub- A threshold swing value (S value) (gate insulating layer thickness: 100 nm) can be achieved.

[0104] In this way, the oxide semiconductor is highly oxidized so that elements other than the main components (impurity elements) are not included as much as possible. Purification can improve the operation of the transistor.

[0105] The transistor of this embodiment, which is formed using a light-transmitting material, has a light-transmitting property. .

[0106] The transistor of this embodiment contains oxygen vacancies and impurities (for example, hydrogen) and has high conductivity. Since the source and drain electrodes are formed using the oxide conductive layer, There is little current loss.

[0107] It has a wide band gap and a carrier concentration of 1×10 14 / cm 3 Less than 1x, preferably 10 12 / cm 3 Since the oxide semiconductor having the following characteristics is used, the transistor of this embodiment The transistor exhibits normally-off behavior and its off-current is low. The off-state current at room temperature per m is 1×10 -16 A / μm or less, even 1aA / μm (1 x10 -18 It is possible to reduce the resistance to less than 1 / μm.

[0108] The difficulty in flowing an off-state current through a transistor can be expressed as an off-state resistivity. Resistivity is the resistivity of the channel formation region when the transistor is off, and the off resistivity is It can be calculated from the off-state current.

[0109] Specifically, if the values ​​of the off-state current and drain voltage are known, the transistor can be calculated from Ohm's law. The resistance value when the transistor is off (off resistance R) can be calculated. The cross-sectional area A and the length of the channel formation region (corresponding to the distance between the source and drain electrodes) L are Then, the off-resistivity ρ can be calculated from the formula ρ=RA / L (R is the off-resistance).

[0110] Here, the cross-sectional area A is defined as follows: A = dW. The length L of the channel forming region is the channel length L. As described above, the off-state resistivity can be calculated from the off-state current.

[0111] The off-state resistivity of the transistor including the oxide semiconductor layer of this embodiment is 1×10 9 Ω m It shows excellent values ​​above.

[0112] In the transistor of this embodiment, the oxide conductive layer and the highly purified oxide semiconductor layer Since a barrier layer that prevents the diffusion of hydrogen and oxygen is provided between the oxide conductive layer and the conductive layer, impurities contained in the oxide conductive layer can be prevented. This suppresses the phenomenon in which impurities (for example, impurities containing hydrogen atoms) diffuse into the oxide semiconductor layer. In addition, the barrier layer prevents the phenomenon in which oxygen atoms contained in the oxide semiconductor layer diffuse into the oxide conductive layer. be suppressed.

[0113] The light-transmitting transistor described in this embodiment has a highly purified oxide semiconductor layer. is protected by a barrier layer, resulting in normally-off characteristics and reduced off-current. These properties are also resistant to change over time, making them highly reliable.

[0114] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0115] (Embodiment 2) In this embodiment, a bottom-gate transistor that transmits visible light is used as one mode of a semiconductor device. A display device using a transistor will be explained with reference to FIG. A manufacturing method of a multi-gate transistor will be described with reference to FIGS.

[0116] In addition, a channel-protected type that can be fabricated together with a bottom-gate type transistor that transmits visible light A manufacturing method of the transistor will also be described with reference to FIGS.

[0117] FIG. 6A shows an image of a display device to which a bottom-gate transistor that transmits visible light is applied. FIG. 6(B) shows a bottom-gate transistor that transmits visible light. 6A is a cross-sectional view showing a stacked structure of a pixel portion of a display device to which a photoresist is applied. The dashed line A1-A2 in FIG. 6(B) corresponds to the cross section A1-A2 in FIG. 6(A). The chain line B1-B2 in FIG. 6(B) corresponds to the cross section B1-B2 in FIG. 6(A). The chain line C1-C2 in FIG. 6(B) corresponds to the cross section C1-C2 in FIG. 6(A). The chain line D1-D2 in the figure corresponds to the cross section D1-D2 in FIG. 6(B).

[0118] The cross section A1-A2 is a diagram illustrating the stacked structure of the transistor 153. D2 is a diagram illustrating the stacked structure of the transistor 153 from a cross section different from the cross section A1-A2. be.

[0119] The transistor 153 has a gate electrode 111a over a light-transmitting substrate 100. The gate electrode 111a is electrically connected to the gate wiring 111c. The first insulating layer 102 is formed on the electrode 111a, and the first insulating layer 102 is formed on the gate electrode 111a. The oxide semiconductor layer 123 is in contact with the gate electrode 111a. The first electrode 115a and the second electrode 115b are connected to each other. The barrier layer 114a is provided between the second electrode 115b and the oxide semiconductor layer 123. A barrier layer 114b is provided between the conductor layers 123.

[0120] a region where the oxide semiconductor layer 123 and the first electrode 115a overlap on the gate electrode 111a; The second insulating layer 10 is formed between the oxide semiconductor layer 123 and the second electrode 115b. The second insulating layer 107 is in contact with the oxide semiconductor layer 123. An opening 127 is formed in the second insulating layer 107. A third insulating layer 108 is formed on the signal line 116a and the second insulating layer 107. The fourth insulating layer 109 is disposed on the third insulating layer 108. The second insulating layer 107, The second electrode is formed through an opening 128 formed in the third insulating layer 108 and the fourth insulating layer 109. A pixel electrode 120 electrically connected to the electrode 115b is provided on the fourth insulating layer 109.

[0121] The cross section B1-B2 is a diagram illustrating the laminated structure of the capacitance section.

[0122] The capacitance section is formed by forming a first capacitance electrode 111b on the substrate 100 and a first insulating layer 102 and a A second electrode 115b of the transistor 153 is formed extending across the barrier layer 114b. The first capacitor electrode 111b is connected to the gate electrode 111a of the transistor 153. The first insulating layer 102, the barrier layer 114b, and the second electrode 115b form a transistor. Can be crafted together with Star 153.

[0123] Since the first capacitor electrode 111b and the second electrode 115b are light-transmitting, the capacitor portion is light-transmitting. The aperture ratio of the pixel does not decrease. The narrow spacing of 5b allows for a large capacitance.

[0124] The cross section C1-C2 is a diagram illustrating the cross-sectional structure of the intersection of the gate wiring 111c and the signal line 116a. is.

[0125] A first insulating layer 102 and an oxide semiconductor layer 111c are formed on a gate wiring 111c provided on a substrate 100. 113c, and the signal line 116a crosses with the second insulating layer 107 sandwiched therebetween. is connected to the gate electrode of transistor 153.

[0126] At the intersection of the gate wiring 111c and the signal line 116a, the gap between them is widened. , the wiring capacitance is reduced.

[0127] Next, a method for manufacturing a bottom-gate transistor 153 that transmits visible light will be described with reference to FIG. This will be used to explain.

[0128] The transistor 153 shown in FIG. 7D is a visible light emitting diode (VLED) applied to the pixel portion of the display device shown in FIG. It has the same structure as a light-transmitting bottom-gate transistor.

[0129] Note that the transistor 15 in FIG. 7D has a different structure from the transistor 153. Also shown is a transistor 154 that can be fabricated in parallel with 3 on the same substrate.

[0130] The transistor 154 has a gate electrode 111d made of the same material as the gate wiring 111c. The third electrode 116c and the fourth electrode 116b are made of the same material as the signal line 116a. The transistor 154 has a channel formation region 16d in the oxide semiconductor layer 113c. An insulating layer 107c is provided on the region, and the insulating layer 107c functions as a channel protection layer.

[0131] In this embodiment, "B made of the same material as A" means that A and B are made in the same process. This refers to the fact that the parts are made of the same material.

[0132] In this embodiment, aluminoborosilicate glass is used for the substrate 100 .

[0133] First, the gate electrode 111a, the gate electrode 111d, and the gate electrode electrically connected In this embodiment, a conductive layer that becomes the gate electrode 111a and a gate wiring are formed. The conductive layer including the gate wiring is collectively referred to as the first conductive layer. It has not been done.

[0134] In this embodiment, the gate wiring and the gate electrode 111d are made of a titanium layer, an aluminum layer, and a titanium film. A three-layer conductive layer is formed by stacking a metal layer and a gate electrode 111a that transmits visible light. Indium tin oxide (ITO) is used for the conductive layer.

[0135] A titanium layer, an aluminum layer, and another titanium layer are stacked on the substrate 100 by sputtering. Next, a conductive layer having a three-layer structure is formed. The gate electrode 111d and the gate wiring are formed by selective etching using a resist mask. The gate electrode 111d is formed from the same material as the gate wiring. This serves as the gate electrode of the gate electrode 154.

[0136] Next, indium tin oxide (ITO) is deposited and then formed in a second photolithography step. The resist mask is used to selectively etch the gate electrode 111a, which is transparent to light. The light-transmitting gate electrode 111a is formed as the gate electrode of the transistor 153. This becomes:

[0137] The conductive film that forms the gate wiring may be made of Al, Cu, Cr, Ta, Ti, Mo, W, etc. It is made of a metal material or an alloy material containing the metal material as a component. A high melting point metal film such as Cr, Ta, Ti, Mo, or W is laminated on one or both of the metal films. Also, Si, Ti, Ta, W, Mo, Cr, Nd, Sc, Y, etc. The Al material contains elements that prevent the formation of hillocks and whiskers in the film. This makes it possible to improve heat resistance.

[0138] In this embodiment mode, a gate electrode having a light-transmitting property is formed after forming a gate wiring. However, even if a gate wiring is formed after forming a gate electrode having light transmission properties, good.

[0139] Next, a first insulating layer 102 is formed. In this embodiment, silicon oxide is stacked on a silicon nitride layer. The first insulating layer 102 is formed by layering.

[0140] The first insulating layer 102 may be a silicon oxide layer, a silicon oxynitride layer, a silicon nitride oxide layer, a silicon nitride layer, or an oxide layer. A single layer or a laminated layer such as an aluminum layer or a tantalum oxide layer can be used. The film thickness is set to 50 nm or more and 250 nm or less, and is formed by a CVD method, a sputtering method, or the like. The film may be doped with phosphorus (P) or boron (B).

[0141] Note that the first insulating layer 102 preferably has an oxide insulating layer on the side in contact with the oxide semiconductor layer. In addition, the i-type or substantially i-type silicon dioxide used in this embodiment can be obtained by removing impurities. The i-type oxide semiconductor (highly purified oxide semiconductor) has a high resistance to the interface state and interface charge. Since the oxide is extremely sensitive to the temperature, the interface with the insulating layer is important. The insulating layer in contact with the semiconductor is required to be of high quality.

[0142] Next, an oxide semiconductor layer is formed. In this embodiment, an In—Ga—Zn—O-based oxide In-Ga-Zn-O non-single crystal film formed by sputtering a semiconductor film formation target An oxide semiconductor layer is formed from the film.

[0143] The thickness of the oxide semiconductor layer is 5 nm to 200 nm, preferably 10 nm to 20 nm. The bottom is, for example, 15 nm.

[0144] Before forming the oxide semiconductor layer, a reverse process in which argon gas is introduced to generate plasma is performed. It is preferable to perform sputtering to remove dust adhering to the surface of the first insulating layer 102. stomach.

[0145] Reverse sputtering is a method of generating plasma by applying voltage to a substrate using an RF power supply in an argon atmosphere. It is a method of forming a thin film and modifying the surface. Note that nitrogen, helium, etc. can be used instead of argon atmosphere. Alternatively, the treatment may be carried out in an argon atmosphere to which oxygen, N2O, etc. has been added. Alternatively, the treatment may be carried out in an argon atmosphere to which Cl2, CF4, etc. have been added.

[0146] In addition, by forming an oxide semiconductor film without exposing it to the air after the reverse sputtering treatment, Dust and moisture can be prevented from adhering to the interface between the first insulating layer 102 and the oxide semiconductor layer. do.

[0147] The oxide semiconductor film is formed under a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or Formed by sputtering in a mixed atmosphere of rare gas (typically argon) and oxygen. In addition, when the sputtering method is used, SiO2 is contained in an amount of 2% by weight or more and 10% by weight or less. The oxide semiconductor film is deposited using a target containing SiOx(X> 0) may be included.

[0148] Here, a target for forming an oxide semiconductor film containing In, Ga, and Zn (the molar ratio of In 2O3:Ga2O3:ZnO=1:1:1 [molar ratio], or In2O3:Ga2O 3:ZnO=1:1:2 [molar ratio]) and set the distance between the substrate and the target at 1 00mm, pressure 0.6Pa, direct current (DC) power supply 0.5kW, oxygen (oxygen flow rate 100%) The film is formed under a ) atmosphere. If a pulsed direct current (DC) power supply is used, dust can be reduced and the film This is preferable because the thickness distribution is uniform.

[0149] In this case, it is preferable to form the oxide semiconductor film while removing residual moisture in the treatment chamber. This is preferable in order to prevent hydrogen, a hydroxyl group, or moisture from being contained in the oxide semiconductor film.

[0150] The multi-chamber sputtering apparatus used in this embodiment is a silicon or silicon oxide sputtering apparatus. It is equipped with a silicon (artificial quartz) target and a target for oxide semiconductor film formation, and However, the deposition chamber equipped with the oxide semiconductor deposition target uses a cryopump as an exhaust means. It should be noted that a turbo molecular pump is used instead of a cryopump, and the turbo component A cold trap can also be installed on the intake of the sub-pump to absorb moisture. good.

[0151] The deposition chamber evacuated using a cryopump contains, for example, hydrogen atoms and hydrogen atoms such as H2O. Since compounds containing carbon atoms and compounds containing carbon atoms are exhausted, the film formation chamber The concentration of impurities contained in the oxide semiconductor film can be reduced.

[0152] Note that the oxide semiconductor film is preferably formed successively over the first insulating layer 102.

[0153] The sputtering gas used in forming the oxide semiconductor film is hydrogen, water, a hydroxyl group, a hydride, or the like. High-purity gas is used, in which impurities have been removed to a concentration of approximately 1 ppm or 10 ppb. It is preferable that

[0154] The oxide semiconductor film may be formed while the substrate is heated. The temperature is set to 200°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor film, the concentration of impurities contained in the formed oxide semiconductor film can be reduced. do.

[0155] Next, selective etching is performed using a resist mask formed in the third photolithography process. island-shaped oxide semiconductor layers 113a made of In—Ga—Zn—O-based non-single crystals; An oxide semiconductor layer 113c is formed.

[0156] For etching, an organic acid such as citric acid or oxalic acid is used as an etching solution. By etching the edge portions of the island-shaped oxide semiconductor layer into a tapered shape, a step can be formed. This prevents the wiring from being cut off due to the shape. The method is not limited to etching, and dry etching may also be used.

[0157] Next, a first insulating film was formed on the substrate on which the island-shaped oxide semiconductor layer 113a and the island-shaped oxide semiconductor layer 113c were provided. The island-shaped oxide semiconductor layer is subjected to the heat treatment in step 1 to be dehydrated or dehydrogenated.

[0158] In this specification, the heat treatment under an inert gas atmosphere such as nitrogen or a rare gas is referred to as dehydration. This is also called heat treatment for dehydrogenation. Dehydrogenation does not only mean that H, hydroxyl groups, etc. are eliminated. For convenience, this process is referred to as dehydration or dehydrogenation.

[0159] In this embodiment, the first heat treatment is performed by increasing the substrate temperature of the substrate on which the island-shaped oxide semiconductor layer is provided. The temperature is heated to a temperature T below 700°C (or below the distortion point of the glass substrate). Preferably, the RTA (rapid annealing) is performed at 350°C or higher and 500°C or lower for 1 minute or longer and 10 minutes or shorter. Thermal Anneal process

[0160] The inert gas atmosphere used in the first heat treatment is nitrogen or a rare gas (helium, neon, etc.). The atmosphere is mainly composed of oxygen (carbon, argon, etc.), and the atmosphere does not contain water, hydrogen, etc. Alternatively, the purity of the inert gas introduced into the heat treatment device is preferably 6N (99 0.9999%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration It is preferable to set the concentration to 1 ppm or less, preferably 0.1 ppm or less.

[0161] When the oxide semiconductor layer is dehydrated or dehydrogenated, the oxide semiconductor layer is It is important not to expose it to the atmosphere and not recontaminate it with water or hydrogen.

[0162] The heat treatment device for the first heat treatment is an electric furnace or a heat treatment device for the first heat treatment. It may also be a device that heats the workpiece by conduction or thermal radiation. For example, a GRT A (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid Thermal Anneal (RTA) equipment The LRTA device uses a halogen lamp, Thallium halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps The material to be treated is heated by the radiation of light (electromagnetic waves) emitted from lamps such as high-pressure mercury lamps. It is a heating device.

[0163] By using the RTA method, dehydration or dehydrogenation can be carried out in a short time, so the strain point of the glass substrate can be reduced. The GRTA device can also process at temperatures exceeding 10 ... It is a device that performs processing.

[0164] The heat treatment is not limited to this timing, but can be performed before or after the photolithography process or film formation process. This may be done multiple times.

[0165] The oxide semiconductor layer that has been sufficiently dehydrated or dehydrogenated under the above conditions is analyzed by thermal desorption spectroscopy. (TDS: Thermal Desorption Spectroscopy) 45 When the temperature was raised to 0°C and the measurement was performed, the spectrum showed two peaks indicating the desorption of water. At least one peak appearing around 250 to 300°C is not detected.

[0166] Note that the oxide semiconductor layer is amorphous and has many dangling bonds when it is formed. By carrying out the first heat treatment of the dehydration or dehydrogenation treatment, dangling bonds in close proximity are dissociated. The molecules bond together to form an ordered amorphous structure. When the temperature is increased, a mixture of amorphous and microcrystalline regions is formed, with microcrystalline regions interspersed with amorphous regions.

[0167] Note that the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the substrate is removed from the heating device. The substrate is taken out and subjected to a photolithography step for processing into an island-shaped oxide semiconductor layer.

[0168] A cross-sectional view at this stage is shown in FIG.

[0169] Next, the barrier layer 114a, the barrier layer 114b, and the first electrode 115a, and The second electrode 115b is formed.

[0170] In this embodiment, titanium nitride is used for the barrier layer 114a and the barrier layer 114b. The second conductive film to be the first electrode 115a and the second electrode 115b is made of indium tin oxide. (ITO) is used.

[0171] The insulating layer 102 covers the island-shaped oxide semiconductor layer 113a formed on the first insulating layer 102 and serves as a barrier layer. A titanium nitride film is formed, and an indium tin film, which is a conductive film that transmits visible light, is formed on the titanium nitride film. The titanium nitride film and the indium tin oxide (ITO) film are formed. The SiO 2 film can be formed by sputtering.

[0172] Indium tin oxide (ITO) films are formed in a reducing atmosphere. In2O3) and tin oxide (SnO2) in a weight ratio of 85:15 (=In2O3:SnO2) A mixed and sintered target with a diameter of 302 mm was used, and the pressure in the chamber was set to 0.4 Pa. The film can be formed by DC sputtering with a power of 1 kW. For example, a mixture of argon, oxygen, and hydrogen gas, or a mixture of argon, oxygen, and water vapor Specifically, the volume of argon, oxygen, and hydrogen at standard conditions can be calculated as follows: A gas mixture in a ratio of 50:1:10 (=Ar:O2:H2) can be used. Argon, oxygen, and water vapor were mixed in a volume ratio of 50:1:1 (= Ar:O:H 2O) can be used.

[0173] By using gases containing hydrogen or water vapor, the indium tin oxide (ITO) film can be In addition, the oxygen deficiency caused by film formation in a reducing atmosphere and the amount of added The conductivity is improved by the impurities (for example, hydrogen, compounds containing hydrogen, etc.) that are added.

[0174] The dehydrated or dehydrogenated oxide semiconductor layer 113a is a titanium nitride film that serves as a barrier layer. Since the conductive film is covered with a transparent conductive film, it is exposed to a reducing atmosphere to increase the conductivity of the conductive film. It can never be done.

[0175] Next, the resist mask formed in the fourth photolithography step is used to selectively etch the By this, the barrier layer 114a, the barrier layer 114b and the first electrode 115a, and The second electrode 115b is formed.

[0176] The cross section at this stage is shown in FIG. 7(B).

[0177] In addition, the barrier layer 114a, the barrier layer 114b, the first electrode 115a, and the second electrode Before forming the electrode 115b, the first insulating layer 102 is selectively etched to form the gate wiring. Alternatively, a contact hole reaching the gate electrode may be formed. After forming a contact hole that reaches the gate electrode, a titanium nitride film that becomes a barrier layer and a transparent When a conductive film having the above structure is formed, a gate wiring or a gate electrode can be formed without any other conductive layer therebetween. The electrode, the titanium nitride film, and the light-transmitting conductive film can be directly connected. This reduces the number of contact holes required for connection. Reducing the number of contact holes not only reduces the electrical resistance but also reduces the space occupied by the contact holes. The area required can also be reduced.

[0178] Next, the second insulating layer 107 is formed on the first insulating layer 102, the oxide semiconductor layer 113a, and the oxide semiconductor layer 113b. It is formed on the semiconductor layer 113c, the first electrode 115a, and the second electrode 115b. The insulating layer 107 includes an inorganic insulating layer, such as a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, Alternatively, an aluminum oxynitride film or the like is used. The thickness is 1 nm or more, and impurities such as water and hydrogen are mixed into the oxide insulating layer by sputtering or the like. At this stage, the oxide semiconductor layer and the second The insulating layer 107 is in contact with the insulating layer 107.

[0179] An oxide film overlapping the gate electrode and sandwiched between the second insulating layer 107 and the first insulating layer 102 The second insulating layer 107 is a region of the semiconductor layer that serves as a channel formation region. It is provided on and in contact with the region that will become the channel formation region and functions as a channel protection layer.

[0180] The second insulating layer 107 is made of a compound containing a hydrogen atom, such as H2O, or a compound containing a carbon atom. or an oxide semiconductor layer containing a small amount of impurities such as hydrogen atoms or carbon atoms. The second insulating layer 107 is formed by removing impurities such as moisture, hydrogen ions, and hydroxyl groups. It does not contain any malware and blocks them from entering from outside.

[0181] In this embodiment, the second insulating layer 107 is made of silicon oxide.

[0182] The silicon oxide film that becomes the second insulating layer 107 is formed by sputtering. The plate temperature should be between room temperature and 600°C, preferably between 200°C and 400°C. In this embodiment, the temperature is set to 100° C. The silicon oxide film is formed by sputtering using a rare gas ( In an atmosphere of oxygen, or in a rare gas atmosphere (typically argon) The oxide insulating film formed by the sputtering method can be formed in an atmosphere containing oxygen. The layer is particularly dense and is a single layer that acts as a protective film to suppress the phenomenon of impurities diffusing into adjacent layers. It can also be used with targets doped with phosphorus (P) or boron (B). It is also possible to use an oxide insulating layer containing phosphorus (P) or boron (B).

[0183] In addition, a silicon oxide target or a silicon target can be used as the target, A silicon target is particularly preferred. When a silicon target is used, oxygen and a rare gas mixture atmosphere is used. The silicon oxide film formed by sputtering under the above conditions has dangling bonds between silicon atoms or oxygen atoms. It contains a lot of dangling bonds.

[0184] The second insulating layer 107 using silicon oxide as an example in this embodiment contains many dangling bonds. The impurities remaining in the oxide semiconductor layer 113a and the oxide semiconductor layer 113c are This facilitates diffusion into the second insulating layer 107 via the interface where the first insulating layer and the second insulating layer 107 come into contact. Specifically, hydrogen atoms contained in the oxide semiconductor layer and compounds containing hydrogen atoms such as H2O This facilitates diffusion and migration into the second insulating layer 107.

[0185] In this embodiment, a columnar polycrystalline B-doped silicon target (resistivity 0 The distance between the substrate and the target (TS distance) was 89 mm, and the pressure was Pulse was measured under an oxygen atmosphere (oxygen flow rate 100%) with a pressure of 0.4 Pa and a direct current (DC) power of 6 kW. The film is formed by DC sputtering, and the film thickness is 300 nm.

[0186] Next, a resist mask formed in a fifth photolithography step is used to selectively etch the By etching, openings 126a, 126b, and 127a are formed in the second insulating layer. .

[0187] Next, the signal line 116a, the third electrode 116c, and the fourth electrode 116d are formed. First, the signal line 116a, the third electrode 116c, and the third conductor that will become the fourth electrode 116d are connected. An electrical layer is deposited.

[0188] The third conductive layer may be made of a metal material such as Al, Cu, Cr, Ta, Ti, Mo, or W, or The metal film is made of an alloy material containing the metal material as a component. Alternatively, a high melting point metal film such as Cr, Ta, Ti, Mo, or W may be laminated on both surfaces. In addition, Si, Ti, Ta, W, Mo, Cr, Nd, Sc, Y, etc., which form on the Al film, Heat resistance is achieved by using Al material that contains elements that prevent the generation of cracks and whiskers. It is possible to improve

[0189] As the third conductive layer, a conductive film with a three-layer structure in which a titanium layer, an aluminum layer, and another titanium layer are stacked. is used.

[0190] A titanium layer and an aluminum layer are formed over the second insulating layer 107, the insulating layer 107c, and the opening. A conductive film having a three-layer structure in which a titanium layer and a silicon layer are stacked is formed by sputtering. Then, the resist mask formed in the sixth photolithography step is used to selectively etch the This forms the signal line 116a, the third electrode 116c, and the fourth electrode 116d. , a third electrode 116c and a fourth electrode 116d formed from the same material as the signal line 116a. serves as the source or drain electrode of transistor 154.

[0191] The cross section at this stage is shown in FIG. 7(C).

[0192] Next, a third insulating layer 108 is formed on the second insulating layer 107. The film 8 may be a silicon nitride film, a silicon nitride oxide film, or an aluminum nitride film. This can be done.

[0193] In this embodiment, silicon nitride is used as the third insulating layer 108. It can be formed by RF sputtering.

[0194] After the second insulating layer 107 is formed, a second heat treatment (preferably at 200° C. or higher and 400° C. or lower, For example, the temperature is between 250°C and 350°C in a rare gas atmosphere or a nitrogen gas atmosphere. Good too.

[0195] For example, the second heat treatment is performed at 250° C. for 1 hour in a nitrogen gas atmosphere. As a result, the oxide semiconductor layer 113a and the oxide semiconductor layer 113c are partially covered with the second insulating layer. 107, and another part of the oxide semiconductor layer 113a is heated to form a barrier layer ( 114a and 114b), and another part of the oxide semiconductor layer 113c is in contact with the signal line (116a , and 116b).

[0196] The oxide semiconductor layer that has been dehydrated or dehydrogenated by the first heat treatment also has oxygen vacancies. This means that the N-type - cation, N + (e.g., to convert into a new product).

[0197] N-type (N - cation, N + The oxide semiconductor layer is then in contact with the oxide insulating layer. When heat treatment is applied, the oxygen vacancies are eliminated and the material becomes highly resistive (i-type).

[0198] Through these steps, the oxide semiconductor layer is highly purified. A transistor fabricated using a conductor layer is in an off state (so-called This makes it possible to realize a switching element with normally-off characteristics.

[0199] Among the electrical characteristics of a transistor, the threshold voltage (Vth) is particularly important. Even if the effective mobility is high, the threshold voltage is high, or the threshold voltage is negative. It is difficult to control the threshold voltage as a circuit. In this case, the switching function of a transistor can be performed when the driving voltage is low. This may cause a burden.

[0200] In the case of an n-channel transistor, the channel is opened only when a positive voltage is applied to the gate. The transistor in which the drain current flows out is desirable. There are transistors in which a channel is not formed under negative voltage conditions, and transistors in which a channel is formed under negative voltage conditions and a drain A transistor through which an in-current flows is unsuitable for use in a circuit. If the threshold voltage of a transistor is negative, the source voltage will be Therefore, a current flows between the gate and drain electrodes, which is called a normally-on characteristic.

[0201] In active matrix display devices, the electrical characteristics of the transistors that make up the circuit These electrical characteristics are important and determine the performance of the display device. If a positive threshold voltage as close as possible to 0V is applied to the gate, a channel is formed. It is desirable for the display device to have this.

[0202] In this embodiment, the oxide semiconductor layers 113a and 113c are The panel formation region is heated in contact with the second insulating layer 107, and becomes highly resistive (i-type). As a result, the transistor 153 including the oxide semiconductor layer 113a and the oxide semiconductor layer 1 The transistor 154 having the 13c exhibits normally-off characteristics.

[0203] In addition, when a metal conductive layer having a high oxygen affinity is in contact with the oxide semiconductor layer, the second heat treatment is performed. When the oxide semiconductor layer is heated, oxygen moves easily to the metal conductive layer side, and the metal conductive layer contacts the oxide semiconductor layer. The region becomes N-type.

[0204] In this embodiment, the region of the oxide semiconductor layer 113c in contact with the third electrode 116c and The region in contact with the fourth electrode 116d is converted to N-type by heating.

[0205] The timing for performing the second heat treatment is immediately after the end of the sixth photolithography process. There are no particular limitations on the process, as long as it is a process subsequent to the fifth photolithography process.

[0206] Through the above steps, the transistor 153 and the transistor 154 can be manufactured. do.

[0207] According to the manufacturing method of the semiconductor element of this embodiment, the oxide conductive layer and the highly purified oxide semiconductor A barrier layer that prevents diffusion of hydrogen and oxygen is provided between the conductor layers, and the impurities contained in the oxide conductive layer are removed. The phenomenon in which impurities (for example, impurities containing hydrogen atoms) diffuse into the oxide semiconductor layer is suppressed. In addition, the barrier layer prevents oxygen atoms contained in the oxide semiconductor layer from being oxidized. A semiconductor device can be fabricated in which the phenomenon of diffusion into the compound conductive layer is suppressed.

[0208] Furthermore, according to the manufacturing method of the semiconductor element exemplified in this embodiment, a highly purified oxide semiconductor The conductor layer is protected by a barrier layer, resulting in normally-off characteristics and reduced off-current. The present invention provides a semiconductor element having excellent reliability and light transmission, and the characteristics of which are unlikely to change over time. It can be manufactured.

[0209] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0210] (Embodiment 3) In this embodiment, an example of the configuration of a terminal portion provided on the same substrate as the semiconductor device is shown in FIG. In addition, in Fig. 8, the same parts as in Fig. 1 will be described using the same reference numerals.

[0211] 8(A-1) and 8(A-2) are a top view and a cross-sectional view of the gate line terminal portion, respectively. FIG. 8(A-1) corresponds to a cross-sectional view taken along line jk in FIG. 8(A-2).

[0212] In FIG. 8(A-1), the first terminal 411 is a connection terminal that functions as an input terminal. The first terminal 411 is made up of a conductive layer 111e made of the same material as the gate wiring, and a second A conductive layer 115e made of the same material as the conductive layer 114e is laminated on the barrier layer 114e. Although not shown, the conductive layer 111e is electrically connected to the gate wiring. There are.

[0213] 8(B-1) and 8(B-2) are a top view and a cross-sectional view of the gate wiring terminal portion, respectively. FIG. 8(B-1) corresponds to a cross-sectional view taken along line jk in FIG. 8(B-2). do.

[0214] In FIG. 8(B-1), the second terminal 412 is a connection terminal that functions as an input terminal. The second terminal 412 is made up of a conductive layer 111f made of the same material as the gate wiring, and a second A conductive layer 115f made of the same material as the conductive layer 114f is laminated on the barrier layer 114f. The conductive layer 111f is electrically connected to the conductive layer 116, which is made of the same material as the third conductive layer. Although not shown, the conductive layer 116 is electrically connected to a signal line. It is being done.

[0215] A plurality of gate lines, signal lines, common potential lines, and power supply lines are provided according to the pixel density. In addition, in the terminal section, a first terminal has the same potential as the gate wiring, a second terminal has the same potential as the signal wiring, and a third terminal has the same potential as the signal wiring. a second terminal at the same potential as the power supply line, a third terminal at the same potential as the power supply line, and a fourth terminal at the same potential as the common potential line. The number of each terminal may be any number. The implementer should decide as appropriate.

[0216] This embodiment mode can be freely combined with other embodiment modes.

[0217] (Fourth embodiment) In this embodiment, a pair of electrodes is provided above and below a channel formation region of an oxide semiconductor layer with an insulating layer interposed therebetween. An example of configuring an inverter circuit using two four-terminal transistors with polar layers is shown below. The transistor shown in FIG. 9A is the same as that shown in FIG. 1 of Embodiment 1. The inverter of this embodiment can be fabricated in the same manner as the transistor 152. The circuit can be used as a driver circuit for driving a pixel portion.

[0218] The driving circuit for driving the pixel unit is arranged, for example, around the pixel unit, and includes an inverter circuit, It is constructed using capacitance, resistance, etc. One type of inverter circuit has two n-channel type For example, enhancement transistors are used. A transistor formed by combining a depletion-type transistor and a non-depletion-type transistor (hereinafter referred to as EDMOS circuits) and those formed by enhancement-type transistors (hereinafter referred to as , called EEMOS circuits).

[0219] FIG. 9A shows a cross-sectional structure of the inverter circuit of the driver circuit.

[0220] The first transistor 440A has a gate electrode 441 formed of a first conductive layer on a substrate 400. 21a, and a channel forming region is formed on the gate electrode 421a in contact with the first insulating layer 402. The gate electrode 42 is formed using the second conductive layer. The first electrode 4 is placed on the oxide semiconductor layer 404a with the end portion overlapping the oxide semiconductor layer 404a via a barrier layer. The first electrode 455a and the second electrode 455b serves as a source electrode or a drain electrode of the first transistor 440A. The first electrode 455a, the second electrode 455b, the first insulating layer 402, and the oxide semiconductor layer A second insulating layer 428 is formed on the insulating layer 428, and a third conductive layer is formed on the insulating layer 428. The electrode 422a is connected to the electrode 422a.

[0221] The second transistor 440B has a gate electrode 441 formed of a first conductive layer on the substrate 400. 21b, and a channel forming region is formed on the gate electrode 421b in contact with the first insulating layer 402. The gate electrode 42 is formed using the second conductive layer. The third electrode 4 is disposed on the oxide semiconductor layer 404b, and the end of the third electrode 4 is overlapped on the oxide semiconductor layer 404b, and the third electrode 4 is in contact with the oxide semiconductor layer 404b via a barrier layer. The third electrode 455c and the fourth electrode 455d serves as a source electrode or a drain electrode of the second transistor 440B. The third electrode 455c, the fourth electrode 455d, the first insulating layer 402, and the oxide semiconductor layer 404b has a second insulating layer 428, and a third conductive layer on the second insulating layer 428. The electrode 422b is connected to the electrode 422a.

[0222] The first transistor 440A and the second transistor 440B are formed using the same conductive film. The second electrode 455b and the third electrode 455c are electrically connected to each other. The electrode 455c is connected to the gate of the second transistor 440B through a contact hole 408. It is connected to the output electrode 421b.

[0223] The first transistor 440A and the second transistor 440B are the same as those described in the second embodiment. The first insulating layer 402 can be fabricated by the same method, and detailed description thereof will be omitted. After forming the contact hole 408, a second conductive layer is provided and then the second conductive layer is formed through the contact hole 408. The second wiring 410b connected to the third electrode 455c is directly connected to the second electrode 455b. Since the number of contact holes required for connection is small, electrical resistance can be reduced. Not only can the size be reduced, but the area occupied by the contact holes can also be reduced.

[0224] A first wiring 410a connected to a first electrode 455a of the first transistor 440A is a power supply line (negative power supply line) to which a negative voltage VDL is applied. This power supply line is connected to the ground potential. It may also be a power supply line (ground power supply line).

[0225] In addition, the third wiring 444 is connected to the fourth electrode 455d of the second transistor 440B. 10c is a power supply line (positive power supply line) to which a positive voltage VDH is applied.

[0226] 9(C) shows a top view of the inverter circuit of the driver circuit. The cross section taken along line Z1-Z2 corresponds to FIG. 9(A).

[0227] The equivalent circuit of the EDMOS circuit is shown in Figure 9(B). 9(B), and the first transistor 440A is an enhancement type n-channel transistor. The first transistor 440B is a depletion-type n-channel transistor. This is an example of a register.

[0228] In this embodiment, the threshold voltages of the first transistor 440A and the second transistor 440B are In order to control the value, an insulating layer is formed on the channel formation region of the highly purified oxide semiconductor layer. An electrode made of a third conductive layer formed as a second conductive layer is used. A is an enhancement type and the second transistor 440B is a depletion type. A voltage may be applied to each of the electrodes 422a and 422b.

[0229] In addition, in FIG. 9(A) and FIG. 9(C), the second wiring 410b is formed in the first insulating layer 402. 408, which is directly connected to the gate electrode 421b through the contact hole 408. However, there is no particular limitation, and a connecting electrode may be separately provided to connect the second wiring 410b and the gate electrode 421b. may be electrically connected.

[0230] As described above, an electrode layer is disposed on the channel formation region of the oxide semiconductor layer via an insulating layer. By using this, the threshold value of the transistor can be controlled and an inverter circuit can be constructed. By controlling the threshold voltage of the transistor, it is possible to achieve enhancement without forming separate oxide semiconductor films. Since both pent-type and depletion-type transistors can be fabricated on the same substrate, The process is simple.

[0231] In addition, a transistor having high field-effect mobility due to a highly purified oxide semiconductor is used. This makes it possible to provide an inverter circuit with excellent dynamic characteristics.

[0232] This embodiment mode can be freely combined with other embodiment modes.

[0233] (Embodiment 5) In this embodiment mode, a light-transmitting transistor is formed over the same substrate and in the same process as a light-transmitting transistor in a pixel portion. Driving circuit having transistors that can be fabricated in parallel and driving method for display device using the same An example of this will be described below.

[0234] The transistors arranged in the pixel portion are formed according to the first or second embodiment. The transistor described in Embodiment 1 or 2 is an n-channel transistor. Therefore, among the driver circuits, driver circuits that can be configured with n-channel transistors A part of the path is formed on the same substrate as the transistor of the pixel portion.

[0235] An example of a block diagram of an active matrix display device is shown in FIG. A pixel portion 5301, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, and a third scanning line driver circuit 5304 are provided on a substrate 5300. The pixel portion 5301 has a signal line driver circuit 5303 and a signal line driver circuit 5304. are arranged extending from the signal line driver circuit 5304, and a plurality of scanning lines are arranged in the first scanning line driver circuit The scanning line driver circuit 5302 and the second scanning line driver circuit 5303 are arranged to extend from each other. In the intersections of the signal lines and the wiring, pixels each having a display element are arranged in a matrix. The substrate 5300 of the display device is made of FPC (Flexible Printed Circuit). A timing control circuit 5305 (controller, control I) is connected to the timing control circuit 5305 via a connection part such as a C).

[0236] In FIG. 10A, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a signal The signal line driver circuit 5304 is formed on the same substrate 5300 as the pixel portion 5301. This reduces the number of externally provided components such as drive circuits, thereby reducing costs. In addition, when a driving circuit is provided outside the substrate 5300, it becomes necessary to extend the wiring, and the wiring The number of connections increases. If a driver circuit is installed on the same board 5300, the number of connections between the wiring can be reduced. This can reduce the number of defects, thereby improving reliability and yield.

[0237] The timing control circuit 5305 controls the first scanning line driver circuit 5302 as follows: The first scanning line driving circuit start signal (GSP1) (the start signal is a start pulse Also referred to as a timing signal, it supplies a clock signal (GCK1) for the scanning line driver circuit. The control circuit 5305 controls the second scanning line driver circuit 5303 to control the second scanning line It provides the start signal (GSP2) for the driver circuit and the clock signal (GCK2) for the scanning line driver circuit. A signal line driver circuit 5304 receives a start signal (SSP) for the signal line driver circuit, Clock signal for driver circuit (SCK), data for video signal (DATA) (simply video signal Each clock signal has a period of It may be a plurality of clock signals with different timings, or an inverted clock signal (CKB) and The first scanning line driver circuit 5302 and the second scanning line driver circuit 5303 may be supplied together. It is possible to omit one of the line driver circuit 5302 and the line driver circuit 5303 .

[0238] In FIG. 10B, circuits with low driving frequencies (for example, the first scanning line driving circuit 5302, the The second scanning line driver circuit 5303 is formed on the same substrate 5300 as the pixel portion 5301, and the signal line driver The configuration in which the driving circuit 5304 is formed on a substrate different from that of the pixel portion 5301 is shown. Due to the structure, the field-effect mobility of the transistor is lower than that of a transistor using a single crystal semiconductor. The transistors can be used to configure the driving circuits formed on the substrate 5300. This allows for the enlargement of display devices, reduction in the number of processes, cost reduction, and improvement of yield. It is possible.

[0239] The transistor described in Embodiment 1 or 2 is an n-channel transistor. In Figure 11(A) and Figure 11(B), the signal line is made up of n-channel transistors. An example of the configuration and operation of the drive circuit will be described below.

[0240] The signal line driver circuit includes a shift register 5601 and a switching circuit 5602 . The switching circuit 5602 is composed of switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each have a plurality of circuits. , a plurality of transistors 5603_1 to 5603_k (k is a natural number) The transistors 5603_1 to 5603_k are N-channel transistors. An example will be described.

[0241] The connection relationship of the signal line driver circuit will be described using the switching circuit 5602_1 as an example. The first terminals of the transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. The second terminals of the transistors 5603_1 to 5603_k are connected to , and are connected to signal lines S1 to Sk. The gates of the transistors 5603_1 to 5603_k are , and is connected to the wiring 5605_1.

[0242] The shift register 5601 sequentially outputs H level (H signal) to the wirings 5605_1 to 5605_N. , also referred to as a high power supply potential level), and the switching circuits 5602_1 to 56 It has the function of selecting 02_N in order.

[0243] The switching circuit 5602_1 is connected to the wirings 5604_1 to 5604_k and the signal lines S1 to Sk. The function of controlling the conduction state (conduction between the first terminal and the second terminal) with the wiring 5604_ The switches have the function of controlling whether or not the potentials of 1 to 5604_k are supplied to the signal lines S1 to Sk. In this way, the switching circuit 5602_1 has a function as a selector. The transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. A function for controlling the conduction state between the lines S1 to Sk, that is, the potential of the wirings 5604_1 to 5604_k to the signal lines S1 to Sk. Each of the switches 5603_k functions as a switch.

[0244] The wirings 5604_1 to 5604_k each carry video signal data (DATA). The video signal data (DATA) is an analog signal corresponding to the image information or image signal. This is often a signal.

[0245] Next, the operation of the signal line driver circuit of FIG. 11(A) will be explained with reference to the timing chart of FIG. 11(B). 11B shows signals Sout_1 to Sout_N and An example of Vdata_1 to Vdata_k is shown. are examples of output signals of the shift register 5601, and signals Vdata_1 to Vdata _k are examples of signals input to the wirings 5604_1 to 5604_k, respectively. One operation period of the signal line driving circuit corresponds to one gate selection period in the display device. The selection period is divided into periods T1 to TN, for example. This is the period for writing video signal data (DATA) to the pixels belonging to the selected row. be.

[0246] During the period T1 to the period TN, the shift register 5601 outputs a high-level signal to the wiring 560 For example, in the period T1, the shift registers 5 601 outputs a high-level signal to the wiring 5605_1. 03_1~5603_k will be turned on, so wires 5604_1~5604_k and signal line At this time, the wirings 5604_1 to 5604_k are connected to Da ta(S1)~Data(Sk) is input. Data(S1)~Data(Sk) is , each of which is connected to a pixel belonging to a selected row via a transistor 5603_1 to 5603_k. In this way, during the periods T1 to TN, the selected pixels are written to the pixels in the first to k-th columns. The video signal data (DATA) is written to the pixels in the selected row in order of k columns. can be.

[0247] As described above, video signal data (DATA) is written to pixels in multiple columns. This makes it possible to reduce the number of video signal data (DATA) or the number of wirings. This reduces the number of connections to external circuits. By writing directly to the memory, the writing time can be increased, and the video signal can be written This can prevent under-crowding.

[0248] The shift register 5601 and the switching circuit 5602 are the same as those in Embodiment 1 and 2. Alternatively, a circuit including the transistor described in Embodiment 2 can be used. In this case, the polarity of all the transistors in the shift register 5601 is set to N-channel type, or It can be constructed with only one polarity of the P-channel type.

[0249] The configuration of the scanning line driver circuit will be described. The scanning line driver circuit has a shift register. In some cases, a level shifter or a buffer may be included. In the operation circuit, a clock signal (CLK) and a start pulse signal (S) are input to the shift register. P) is input, the selection signal is generated. The generated selection signal is The signal is buffered and amplified in the scanning line, and then supplied to the corresponding scanning line. The gate electrodes of the transistors are connected. must be turned on all at once, so the buffer must be able to pass a large current. is used.

[0250] The shift registers of the scanning line driver circuit and the signal line driver circuit are shown in FIGS. 12 and 13. The shift register includes the first pulse output circuit 10_1 to the Nth pulse output circuit 10_2. The path 10_N (N is a natural number equal to or greater than 3) is shown in FIG. 12(A). The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N of the shift register shown in FIG. A first clock signal CK1 is transmitted from a first wiring 11, a second clock signal CK2 is transmitted from a second wiring 12, and so on. a third clock signal CK2 from the third wiring 13; a fourth clock signal CK3 from the fourth wiring 14; The clock signal CK4 is supplied to the first pulse output circuit 10_1. A start pulse SP1 (first start pulse) is input from line 15. In the subsequent n-th pulse output circuit 10_n (n is a natural number between 2 and N), Signal from the pulse output circuit (called the previous signal OUT(n-1)) (n is a natural number greater than or equal to 2) In addition, in the first pulse output circuit 10_1, the third pulse output circuit, which is two stages later, Similarly, the signal from the n-th pulse output circuit 10_2 in the second stage or later is input. In the nth stage, the signal from the (n+2)th pulse output circuit 10_(n+2) in the second stage (nth stage signal) Therefore, the pulse output circuit of each stage outputs the following: A first output signal (OUT( 1) (SR) to OUT(N) (SR)), a second output signal (OU) input to another circuit, etc. As shown in FIG. 12(A), the shift register The last two stages of the star do not receive the next stage signal OUT(n+2). A second start pulse SP2 is separately sent from the sixth wiring 16, and a third start pulse SP3 is sent from the seventh wiring 17. Alternatively, a separate shift register may be used. For example, a signal generated inside the pixel section may be used. The (N+1)th pulse output circuit 10_(N+1), the (N+2)th pulse output circuit 10_( N+2) (also called a dummy stage), and a second start pulse (SP2 ) and a signal corresponding to the third start pulse (SP3).

[0251] The clock signal (CK) alternates between H level and L level (L signal, low power supply potential) at regular intervals. Here, the first clock signal (CK1) to the second clock signal (CK2) are signals that repeat a cycle of 1 / 2 levels. The fourth clock signal (CK4) is delayed by 1 / 4 cycle in order. The first clock signal (CK1) to the fourth clock signal (CK4) are used to generate a pulse output circuit. The clock signal is controlled by the GCK It is sometimes called SCK, but here we will explain it as CK.

[0252] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11 to It is electrically connected to any one of the fourth wirings 14. For example, in FIG. The first pulse output circuit 10_1 has a first input terminal 21 electrically connected to the first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is The second pulse output circuit 10_2 is electrically connected to the third wiring 13. The first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring The third input terminal 23 is electrically connected to the fourth wiring 14. There are.

[0253] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 12B, the input terminal 25, the first output terminal 26, and the second output terminal 27. In the first pulse output circuit 10_1, a first clock signal is input to a first input terminal 21. A first clock signal CK1 is input to the first input terminal 21, a second clock signal CK2 is input to the second input terminal 22, and a third clock signal CK3 is input to the third input terminal 23. A third clock signal CK3 is input to the input terminal 23 of the clock generator 10, and a start signal CK4 is input to the fourth input terminal 24 of the clock generator 10. A pulse is input, the subsequent signal OUT(3) is input to the fifth input terminal 25, and the first output The first output signal OUT(1)(SR) is output from the terminal 26, and the second output signal OUT(1)(SR) is output from the second output terminal 27. The second output signal OUT(1) is output. The pulse output circuit is connected to a power supply line 51, a power supply line 52, and a power supply line 53.

[0254] Next, an example of a specific circuit configuration of the pulse output circuit will be described with reference to FIG.

[0255] The first pulse output circuit 10_1 includes a first transistor 31 to an eleventh transistor 41. (See FIG. 12(C)). In addition, the first input terminal 21 to the fifth input terminal a first output terminal 25, a first output terminal 26, a second output terminal 27, and a first high power supply potential VDD a power supply line 51 to which a second high power supply potential VCC is supplied, a power supply line 52 to which a low power supply potential The first transistor 31 to the eleventh transistor 4 are connected to the power supply line 53 to which VSS is supplied. A signal or a power supply potential is supplied to the power supply line 1. Here, the magnitude of the power supply potential of each power supply line in FIG. The minor relationship is: first high power supply potential VDD>second high power supply potential VCC>low power supply potential VSS (VC C is lower than VDD, and VSS is lower than VCC. The first clock signal (CK1) to the fourth clock signal (CK4) go to H level at regular intervals. This is a signal that repeats L level, but when it is H level it is VDD and when it is L level it is VSS. By setting the potential VCC of the power supply line 52 lower than the potential VDD of the power supply line 51, This allows the potential applied to the gate electrode of the transistor to be kept low without affecting its operation. This can reduce the shift in the threshold voltage of the transistor and suppress degradation. do.

[0256] In FIG. 12C, the first terminal of the first transistor 31 is electrically connected to the power supply line 51. the second terminal of the ninth transistor 39 is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode of the The second transistor 32 has a first terminal electrically connected to the fourth input terminal 24. The second terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first terminal of the ninth transistor 39. and a gate electrode electrically connected to the gate electrode of the fourth transistor 34. The third transistor 33 has a first terminal electrically connected to the first input terminal 21 and a second terminal electrically connected to the first input terminal 21. The second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 One terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 has a first terminal electrically connected to the power supply line 53 and a second terminal electrically connected to the power supply line 53. The two terminals are the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. and the gate electrode is electrically connected to the fourth input terminal 24. The transistor 36 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the second transistor 36. The gate electrode of the fourth transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to each other. The seventh transistor 3 has a gate electrode electrically connected to the fifth input terminal 25. The first terminal of the transistor 7 is electrically connected to the power supply line 52, and the second terminal of the transistor 38 is electrically connected to the power supply line 52. The gate electrode is electrically connected to the second terminal and the gate electrode is electrically connected to the third input terminal 23. The eighth transistor 38 has a first terminal connected to the gate electrode of the second transistor 32 and a second terminal connected to the gate electrode of the second transistor 32. 4, and the gate electrode is electrically connected to the second input terminal 2 The ninth transistor 39 has a first terminal electrically connected to the first transistor 2. The second terminal is electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32. The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are supplied with a voltage. The gate electrode is electrically connected to the power supply line 52. The first terminal of the sigma 40 is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the second output terminal 22. the gate electrode of the ninth transistor 39 is electrically connected to the second terminal of the ninth transistor 39. The eleventh transistor 41 has a first terminal electrically connected to the power supply line 53. The second terminal is electrically connected to the second output terminal 27, and the gate electrode is The gate electrode of the fourth transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to each other. do.

[0257] In FIG. 12C, the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 4 The connection point of the gate electrode of the ninth transistor 30 and the second terminal of the ninth transistor 39 is referred to as node A. The gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point of the first terminal of the eleventh transistor 38 and the gate electrode of the eleventh transistor 41 is node B. (See FIG. 13(A)).

[0258] A transistor is a device having at least three terminals including a gate, a drain, and a source. The element has a channel region between the drain region and the source region, A current can flow through the in-region, the channel region, and the source region. The source and drain depend on the transistor structure and operating conditions, so it is difficult to know which is the source or drain. Therefore, it is difficult to define whether the source or drain is the In some cases, the region that functions as a source or drain is not called a source or drain. In this case, they may be referred to as the first terminal and the second terminal, respectively.

[0259] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. A shift chart is shown in FIG. 13(B). In this case, the period 61 in FIG. 13(B) corresponds to the vertical blanking period, and the period 62 corresponds to the gate selection period. do.

[0260] As shown in FIG. 13A, the second high power supply potential VCC is applied to the gate electrode. By providing the transistor 39 of 9, before and after the bootstrap operation, The advantages are as follows:

[0261] If the ninth transistor 39, to whose gate electrode the second high power supply potential VCC is applied, is not present, When the potential of the node A rises due to the bootstrap operation, the first transistor 31 The potential of the source, which is the second terminal, rises and becomes higher than the first high power supply potential VDD. As a result, the source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, the gate and the source, the gate and the drain During this period, a large bias voltage is applied, which causes a large stress on the transistor. Therefore, the second high power supply potential VCC is applied to the gate electrode. By providing the ninth transistor 39, the node Although the potential of A rises, the potential of the second terminal of the first transistor 31 does not rise. That is, by providing the ninth transistor 39, Decrease the value of the negative bias voltage applied between the gate and source of transistor 31 Therefore, by using the circuit configuration of this embodiment, the first transistor The negative bias voltage applied between the gate and source of 31 can also be reduced, reducing stress. This can suppress the deterioration of the first transistor 31 due to the temperature rise.

[0262] The ninth transistor 39 is provided at a location corresponding to the second gate of the first transistor 31. and a gate of the third transistor 33 via a first terminal and a second terminal. In this embodiment, a system having a plurality of pulse output circuits may be provided. In the case of a soft register, the signal line driver circuit has more stages than the scanning line driver circuit. The resistor 39 may be omitted, which has the advantage of reducing the number of transistors.

[0263] Note that the semiconductor layers of the first to eleventh transistors 31 to 41 are made of oxide semiconductor. By using a conductor, the off-state current of the transistor is reduced, and the on-state current and the electric field It is possible to increase the effective mobility. In addition, it is possible to reduce the degree of deterioration, In addition, a transistor using an oxide semiconductor can reduce malfunctions in an ammonia Compared to transistors using ruthenium silicon, a high potential is applied to the gate electrode. Therefore, the second high power supply potential VCC is supplied. The same operation can be obtained by supplying the first high power supply potential VDD to the power supply line, and the power supply line can be connected to the circuit. Since the number of power supply lines can be reduced, the circuit can be made smaller.

[0264] The gate electrode of the seventh transistor 37 is connected to the clock signal supplied from the third input terminal 23. A lock signal, supplied by the second input terminal 22 to the gate electrode of the eighth transistor 38 The clock signal to be input is provided by the second input terminal 22 to the gate electrode of the seventh transistor. The clock signal supplied to the eighth gate electrode is supplied by the third input terminal 23. The same effect can be achieved by changing the wiring relationship so that the signal becomes a clock signal. In the shift register shown in are both on, the seventh transistor 37 is off, and the eighth transistor 38 is on. Then the seventh transistor 37 is turned off and the eighth transistor 38 is turned off. By doing so, the potentials of the second input terminal 22 and the third input terminal 23 decrease. The resulting drop in the potential of node B causes a drop in the potential of the gate electrode of the seventh transistor 37, and This occurs twice due to the drop in the potential of the gate electrode of the eighth transistor 38 and the second transistor 39. On the other hand, in the shift register shown in FIG. 13A, the seventh transistor 37 and the eighth transistor The seventh transistor 37 is turned on, and the eighth transistor 38 is turned on. Then the seventh transistor 37 is off, and the eighth transistor 38 is off. By turning off the input terminal 38, the voltages of the second input terminal 22 and the third input terminal 23 are The potential drop at node B caused by the potential drop is compensated by the gate voltage of the eighth transistor 38. Therefore, the seventh transistor 37 A clock signal CK3 is supplied to the gate electrode of the eighth transistor from the third input terminal 23. The gate electrode of the clock signal CK2 is connected to the second input terminal 22. This is because the number of fluctuations in the potential of node B is reduced, and noise is reduced. This is because it can be reduced.

[0265] In this way, the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level. By configuring the node B to periodically receive a high-level signal during this period, the pulse output This can suppress malfunction of the power circuit.

[0266] (Sixth embodiment) In this embodiment, as an example of the semiconductor device of the present invention, the semiconductor device according to the first embodiment or the second embodiment is The transistor formed in the same manner is used in the pixel portion and further in the driver circuit to form a semiconductor device having a display function. A semiconductor device (also called a display device) can be manufactured. A part or the whole of a driver circuit using a transistor formed in the same manner as in the second embodiment is connected to a pixel portion. They can be integrally formed on the same substrate to form a system-on-panel.

[0267] The display device includes a display element. The display element includes a liquid crystal element (also called a liquid crystal display element), a light-emitting element, A light-emitting element (also called a light-emitting display element) can be used. This category includes elements whose brightness is controlled by the light emitted from the light source, specifically inorganic EL (Electroluminescent) luminescence elements, organic EL elements, etc. Also, electronic ink A display medium whose contrast changes due to an electrical effect can also be applied.

[0268] The display device also includes a panel in which a display element is sealed, and a controller for the panel. Furthermore, one aspect of the present invention is a module in which an IC or the like including the above-mentioned is mounted. In the process of manufacturing a display device, the element substrate corresponds to one form before the display element is completed. The element substrate includes a means for supplying a current to each of the plurality of pixels. Specifically, the substrate may be in a state where only the pixel electrode layer of the display element is formed, or After forming the conductive film that will become the pixel electrode layer and before etching to form the pixel electrode layer It can be a state, and any form applies.

[0269] In this specification, the term "display device" refers to an image display device, a display device, or an optical device. It also refers to connectors, such as FPC (Flexible Printed Circuit) integrated circuit) or TAB (Tape Automated Bon ding) tape or TCP (Tape Carrier Package) Modules with printed wiring boards attached to the end of TAB tape or TCP or the display element is mounted on an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which the display device (circuit) is directly mounted.

[0270] In this embodiment mode, the appearance and cross section of a liquid crystal display panel, which is one mode of a semiconductor device of the present invention, will be described. The surface will be described with reference to FIG. 14. FIG. 14 shows a surface of the second embodiment on a first substrate 4001. The transistors 4010 and 4011 and the liquid crystal element 4013 formed in the same manner as above were used as the first substrate. The panel is sealed between the plate 4001 and the second substrate 4006 by a sealant 4005. 14(A1) and 14(A2) are cross-sectional views taken along line MN. do.

[0271] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this way, a sealing material 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealing material 4005, and a second substrate 4006. The first substrate 4001 is sealed together with the liquid crystal layer 4008 by the sealing material. In a region different from the region surrounded by 4005, a single crystal semiconductor is placed on a separately prepared substrate. A signal line driver circuit 4003 formed of a conductor film or a polycrystalline semiconductor film is mounted.

[0272] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, a wire The ear bonding method, the TAB method, etc. can be used. This is an example of mounting the signal line driver circuit 4003 by the OG method, and FIG. 14(A2) is an example of mounting the signal line driver circuit 4003 by the TAB method. This is an example in which the signal line driver circuit 4003 is implemented by the above.

[0273] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 14B, the transistor included in the pixel portion 4002 is 4004 and a transistor 4010 included in the scanning line driver circuit 4004. Insulating layers 4020 and 4021 are provided on the transistors 4010 and 4011. do.

[0274] The transistors 4010 and 4011 are, for example, the transistors shown in Embodiment 1 or 2. In this embodiment, the transistors 4010 and 40 11 is an n-channel transistor.

[0275] In addition, a pixel electrode layer 4030 of the liquid crystal element 4013 is electrically connected to the transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is connected to the second substrate 4006. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are overlapped. The portion where the pixel electrode layer 4030 and the counter electrode 4031 are formed corresponds to the liquid crystal element 4013. The layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. The liquid crystal layer 4008 is sandwiched between layers 4032 and 4033 .

[0276] The first substrate 4001 and the second substrate 4006 may be made of glass or metal (typically, stainless steel). Stainless steel, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film Aluminum foil can also be used with PVF film or polyester film. A sheet sandwiched between films can also be used.

[0277] The spacers 4035 are columnar spacers obtained by selectively etching the insulating film. and the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 is controlled. A spherical spacer may be used. 4031 is a common potential line and conductive particles provided on the same substrate as the transistor 4010. The conductive particles are contained in the sealing material 4005.

[0278] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. In order to achieve this, the liquid crystal layer 4008 is formed using a liquid crystal composition containing 5% by weight or more of a chiral agent. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of 10 μs It is short (approximately 100 μs), has optical isotropy so alignment treatment is not required, and has little viewing angle dependency. Sai.

[0279] Note that this embodiment mode is an example of a transmissive liquid crystal display device, but one embodiment of the present invention is a reflective liquid crystal display device. The present invention can be applied to both a liquid crystal display device and a semi-transmissive liquid crystal display device.

[0280] In the liquid crystal display device of this embodiment, a polarizing plate is provided on the outer side (viewing side) of the substrate, and a polarizing plate is provided on the inner side. An example is shown in which a colored layer and an electrode layer used for a display element are provided in this order, but the polarizing plate is provided on the inner side of the substrate. The laminated structure of the polarizing plate and the colored layer is not limited to that of the present embodiment. The coloring layer may be appropriately selected depending on the material and manufacturing process conditions of the coloring layer. A light-shielding film that functions as a light-shielding film may be provided.

[0281] In this embodiment, in order to reduce the surface irregularities caused by the transistor, In order to improve the reliability of the transistor obtained in the first or second embodiment, The insulating layer 4020 and the insulating layer 4021 function as a protective film and a planarizing insulating film. The protective film is made up of organic matter, metal matter, water vapor, etc. The purpose of the protective film is to prevent the intrusion of contaminating impurities, and a dense film is preferable. Using the above, silicon oxide film, silicon nitride film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide film Aluminum nitride film, aluminum oxynitride film, or aluminum oxynitride film In this embodiment mode, an example in which the protective film is formed by sputtering is shown. However, there is no particular limitation and various methods may be used for forming the layer.

[0282] After the protective film is formed, the oxide semiconductor layer containing indium, gallium, and zinc is Annealing (300°C to 400°C) may also be performed.

[0283] An insulating layer 4021 is formed as a planarization insulating film. Heat-resistant resins such as amide, acrylic resin, benzocyclobutene resin, polyamide, epoxy resin, etc. In addition to the above organic materials, low dielectric constant materials (L low-k materials), siloxane resin, PSG (phosphor glass), BPSG (phosphor boron glass) Siloxane-based resins may have organic groups (e.g., arsenic) as substituents. Alternatively, an alkyl group or an aryl group, or a fluoro group may be used. In addition, by laminating a plurality of insulating films made of these materials, the insulating layer 4 021 may be formed.

[0284] Siloxane-based resin is a Si-OS compound formed using siloxane-based materials as starting materials. Corresponds to resins containing i bonds.

[0285] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife When the insulating layer 4021 is formed using a material liquid, In the step of annealing, the oxide semiconductor layer containing indium, gallium, and zinc is annealed at the same time. The baking process of the insulating layer 4021 and the baking process of the indium and gallium may be performed. By combining this with annealing of the oxide semiconductor layer containing sodium and zinc, a semiconductor device can be efficiently manufactured. It becomes possible to manufacture it.

[0286] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material can be used.

[0287] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer (conductive polymer The conductive composition can be used to form the conductive film. The resulting pixel electrode layer has a sheet resistance of 10,000 Ω / □ or less and is transparent at a wavelength of 550 nm. The resistance of the conductive polymer contained in the conductive composition is preferably 70% or more. The resistivity is preferably 0.1 Ω·cm or less.

[0288] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0289] A signal line driver circuit 4003, a scanning line driver circuit 4004, and a pixel section 40 Various signals and potentials applied to O2 are supplied from FPC4018.

[0290] In this embodiment, the connection terminal electrode 4015 is connected to the pixel electrode layer 40 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the same conductive film as the transistor 4011. The electrode layer is formed of the same conductive film as the drain electrode layer.

[0291] The connection terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected.

[0292] In FIG. 14, a signal line driver circuit 4003 is separately formed and mounted on a first substrate 4001. However, this embodiment is not limited to this configuration. Alternatively, a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed separately and mounted. Alternatively, the circuit board may be formed separately and mounted.

[0293] FIG. 15 shows a semiconductor device using a transistor substrate 2600 manufactured according to one embodiment of the present invention. 1 shows an example in which a liquid crystal display module is configured as the body device.

[0294] FIG. 15 shows an example of a liquid crystal display module, which includes a transistor substrate 2600 and an opposing substrate 260. 1 is fixed by a sealing material 2602, and a pixel portion 2603 including a transistor and the like is provided between them. A display element 2604 including a liquid crystal layer and a colored layer 2605 are provided to form a display area. The color layer 2605 is necessary for color display. In the case of the RGB method, it is red, green, and blue. A colored layer corresponding to each color is provided for each pixel. On the outer side of the counter substrate 2601, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged. The light source is composed of a cold cathode fluorescent lamp 2610 and a reflector 2611, and is mounted on a circuit board 2612. The wiring circuit section 260 of the transistor substrate 2600 is connected to the flexible wiring substrate 2609. 8 and incorporates external circuits such as a control circuit and a power supply circuit. The optical plate and the liquid crystal layer may be laminated with a retardation plate between them.

[0295] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-Plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) Switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optically Compensated) Birefringence mode, FLC (Ferroelectric Liquid Crystal uid Crystal) mode, AFLC(AntiFerroelectric L You can use modes such as IQID Crystal.

[0296] Through the above steps, a display device including a transistor with excellent operational stability can be manufactured. The liquid crystal display device of this embodiment is equipped with a transistor having excellent operational stability. Highly reliable.

[0297] The display device of this embodiment mode has a light-transmitting transistor in a pixel portion and has a high aperture ratio. In addition, an oxide conductive layer containing oxygen deficiency and impurities (e.g., hydrogen) and having increased conductivity is formed. Since the source electrode and the drain electrode are formed using the same, the loss of the on-current is small.

[0298] In addition, the transistors provided in the pixel portion and the driver circuit of the display device of this embodiment mode have a wide band. It has a wide gap and a carrier concentration of 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3Since the oxide semiconductor used is suppressed to below 100%, it exhibits normally-off behavior, and The off-state current is low. Specifically, the off-state current at room temperature per 1 μm of channel width is 1×10 -16 A / μm or less, and even 1aA / μm (1×10 -18 A / μm) or less is possible.

[0299] As a result, a display device can be provided that suppresses leakage current and saves power. A display device with a large off-state current ratio can be provided. In addition, the display device has excellent contrast and high display quality. This makes it possible to provide a display device that is easy to use.

[0300] In addition, the display device of this embodiment uses a field-effect transfer element (FET) that uses a highly purified oxide semiconductor layer. It is equipped with high-performance transistors, which allows it to operate at high speed and has excellent video display characteristics and high-definition It is possible to display.

[0301] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0302] (Embodiment 7) In this embodiment mode, a light-emitting display device will be described as an example of a semiconductor device of the present invention. In this embodiment, a light-emitting element utilizing electroluminescence is used as the display element. The light-emitting element that utilizes electroluminescence is an organic compound Generally, the former are organic EL elements, and the latter are inorganic compounds. are called inorganic EL elements.

[0303] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. These carriers are then injected into a layer containing a light-emitting organic compound, causing a current to flow. The recombination of electrons and holes causes the light-emitting organic compound to form an excited state, When the excited state returns to the ground state, light is emitted. The optical element is called a current-excited light-emitting element.

[0304] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this embodiment, organic EL elements are used as light-emitting elements. I will explain.

[0305] FIG. 16 shows an example of a semiconductor device to which digital time gray scale driving is applied. FIG. 1 is a diagram illustrating an example of a possible pixel configuration. Note that OS in the diagram represents an oxide semiconductor (Oxide This indicates that the transistor is made of a silicon nitride semiconductor.

[0306] The configuration and operation of a pixel to which digital time gray scale driving can be applied will be described. In this embodiment, the oxide semiconductor layer (In—Ga—Zn Two n-channel transistors using a silicon dioxide film (SiO2-based film) in the channel formation region are placed in one pixel. Here is an example of its use.

[0307] The pixel 6400 includes a switching transistor 6401, a driving transistor 6402, It has a light emitting element 6404 and a capacitor element 6403. 01 has a gate connected to a scanning line 6406 and a first electrode (one of the source and drain electrodes) The first electrode (the other of the source electrode and the drain electrode) is connected to a signal line 6405, and the second electrode (the other of the source electrode and the drain electrode) is connected to a drive The driving transistor 6402 is connected to the gate of the driving transistor 6402. The gate is connected to a power supply line 6407 via a capacitor element 6403, and the first electrode is connected to a power supply line 640 7, and the second electrode is connected to the first electrode (pixel electrode layer) of the light-emitting element 6404. The second electrode of the light emitting element 6404 corresponds to a common electrode 6408. It is electrically connected to a common potential line formed on one substrate.

[0308] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. The low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. Then, in order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or greater than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0309] The capacitor element 6403 is omitted by substituting the gate capacitance of the driving transistor 6402. The gate capacitance of the driving transistor 6402 is determined by the channel region A capacitance may be formed between the gate electrode layer and the gate electrode layer. Since the off-state current of the transistor is extremely low, the capacitance of the capacitor 6403 can be reduced. Alternatively, a configuration without a capacitor element may be employed.

[0310] In the case of a voltage input voltage driving method, the gate of the driving transistor 6402 is connected to The driving transistor 6402 is either fully on or off. A video signal is input, that is, the driving transistor 6402 is operated in a linear region. The driving transistor 6402 is operated in a linear region, so that the voltage of the driving transistor 6402 is higher than the voltage of the power supply line 6407. A high voltage is applied to the gate of the driving transistor 6402. The signal line 6405 is connected to A voltage equal to or greater than (power supply line voltage+Vth of the driving transistor 6402) is applied.

[0311] Furthermore, when analog grayscale driving is performed instead of digital time grayscale driving, the input of the signal is different. By doing so, the same pixel configuration as in FIG. 16 can be used.

[0312] When analog gradation driving is performed, a light emitting element 6404 is connected to the gate of a driving transistor 6402. A voltage equal to or greater than the forward voltage of the light emitting element 64 and the Vth of the driving transistor 6402 is applied. The forward voltage in 04 refers to the voltage required to achieve the desired brightness, and It should be noted that the driving transistor 6402 is designed to operate in the saturation region. By inputting an optical signal, a current can be passed through the light emitting element 6404. In order to operate the transistor 6402 in the saturation region, the potential of the power supply line 6407 is The potential of the light emitting element is made higher than the gate potential of the capacitor 6402. A current corresponding to a video signal is passed through 6404, enabling analog gradation driving.

[0313] Note that the pixel configuration shown in Fig. 16 is not limited to this. For example, A switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be added.

[0314] Next, the structure of the light-emitting element will be described with reference to FIG. 17. In this embodiment, The cross-sectional structure of a pixel will be explained using an example in which the transistor is n-type. (B) and (C) driving transistors 7001, 7011, and 702 used in the semiconductor device The transistor 1 can be manufactured in a manner similar to that of the transistor described in Embodiment 1 or 2.

[0315] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a transistor and a light emitting element are formed on the substrate, and light is extracted from the surface opposite to the substrate. There are two types of emission: top emission, which emits light from the surface on the substrate side, bottom emission, which emits light from the surface on the substrate side, and emission from the surface on the opposite side to the substrate. There is a light-emitting element having a dual emission structure in which light is extracted from the side surface. It can be applied to any light emitting element with any emission structure.

[0316] A light emitting element with a bottom emission structure will be described with reference to FIG.

[0317] The driving transistor 7011 is an n-type transistor, and light emitted from the light emitting element 7012 is incident on the first electrode 7013. FIG. 17(A) shows a cross-sectional view of a pixel when light is emitted to the driving transistor 7013 side. A light-transmitting conductive material electrically connected to the source electrode or drain electrode of the transistor 7011 A first electrode 7013 of the light-emitting element 7012 is formed on the film 7017. On the layer 7013, an EL layer 7014 and a second electrode 7015 are laminated in this order.

[0318] The light-transmitting conductive film 7017 may be formed of indium oxide containing tungsten oxide, Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Titanium-containing indium tin oxide, indium tin oxide, indium zinc oxide, oxide ketone A light-transmitting conductive film such as indium tin oxide to which indium is added can be used.

[0319] In addition, various materials can be used for the first electrode 7013 of the light-emitting element. When the electrode 7013 is used as a cathode, a material having a small work function, specifically, For example, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr, In addition to alloys containing these metals (Mg:Ag, Al:Li, etc.), rare earth metals such as Yb and Er are preferred. In FIG. 17A, the first electrode 7013 has a thickness that is thick enough to transmit visible light (preferably For example, an aluminum film having a thickness of 20 nm is used. is used as the first electrode 7013 .

[0320] After a light-transmitting conductive film and an aluminum film are stacked, the film is selectively etched. The light-transmitting conductive film 7017 and the first electrode 7013 may be formed by the same method. This is preferable because etching can be performed using the same mask.

[0321] The partition wall 7019 is formed by the protective insulating layer 7035, the overcoat layer 7034, and the insulating layer 70 32 and a light-transmitting layer is formed on the contact hole that reaches the drain electrode layer. The first electrode 7013 is disposed with a conductive film 7017 interposed therebetween. Note that the periphery of the first electrode 7013 is covered with a partition wall. The partition wall 7019 may be made of a material such as polyimide, acrylic resin, polyamide, or epoxy resin. The partition wall 7019 is formed by using an organic resin film, an inorganic insulating film, or an organic polysiloxane. A photosensitive resin material is used to form an opening on the first electrode 7013, and the sidewall of the opening It is preferable that the partition wall 7 is formed to have an inclined surface having a continuous curvature. When a photosensitive resin material is used as the 019, the step of forming a resist mask can be omitted. It is possible.

[0322] The EL layer 7014 formed on the first electrode 7013 and the partition wall 7019 is made of at least It is sufficient to include a light-emitting layer, and it may be composed of a single layer or a plurality of layers stacked. The EL layer 7014 is made up of a plurality of layers, and the first electrode 7013 is made up of a When used as a cathode, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole transport layer are formed on the first electrode 7013. The hole transport layer and the hole injection layer are laminated in this order. There is no need to.

[0323] Furthermore, the stacking order is not limited to the above. When the first electrode 7013 is used as an anode, On the electrode 7013, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer are formed in this order. However, when comparing power consumption, the first electrode 7013 functions as a cathode. The first electrode 7013 is then coated with an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole transport layer. By stacking the layer in this order, it is possible to suppress the voltage rise in the drive circuit section and reduce power consumption. This is preferable because it can be done easily.

[0324] In addition, various materials can be used for the second electrode 7015 formed on the EL layer 7014. For example, when the second electrode 7015 is used as an anode, a material with a large work function can be used. Materials such as ZrN, Ti, W, Ni, Pt, Cr, ITO, IZO, ZnO, etc. A transparent conductive material is preferable. In addition, a shielding film 7016, for example, a film for blocking light, is provided on the second electrode 7015. A light-shielding metal, a light-reflecting metal, or the like is used. In this embodiment mode, the second electrode 7015 and An ITO film is used as the shielding film 7016, and a Ti film is used as the shielding film 7017.

[0325] An EL layer 7014 including a light-emitting layer is sandwiched between a first electrode 7013 and a second electrode 7015. In the case of the element structure shown in FIG. 17(A), the light-emitting element Light emitted from 7012 is emitted to the first electrode 7013 side as shown by the arrow.

[0326] In FIG. 17A, the light emitted from the light emitting element 7012 is reflected by the color filter layer. 7033, through the insulating layer 7032, the gate insulating layer 7030, and the substrate 7010. and eject it.

[0327] The color filter layer 7033 can be formed by a droplet discharge method such as an ink jet method, a printing method, or a photolithography method. Each is formed by an etching method using graphic technology.

[0328] The color filter layer 7033 is covered with an overcoat layer 7034, which is further provided with a protective insulating layer. In FIG. 17(A), the overcoat layer 7034 is thin. As shown in the figure, the overcoat layer 7034 is made of a resin material such as acrylic resin, and is colored. It has the function of flattening the unevenness caused by the filter layer 7033.

[0329] Next, a light emitting element with a dual emission structure will be described with reference to FIG.

[0330] In FIG. 17B, the source electrode or the drain electrode of the driving transistor 7021 is electrically connected to The first electrode 70 of the light-emitting element 7022 is formed on the light-transmitting conductive film 7027 that is electrically connected to the first electrode 70 of the light-emitting element 7022. 23 is formed, and an EL layer 7024 and a second electrode 7025 are formed on the first electrode 7023. They are stacked in order.

[0331] The light-transmitting conductive film 7027 may be formed of indium oxide containing tungsten oxide, Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Titanium-containing indium tin oxide, indium tin oxide, indium zinc oxide, oxide ketone A light-transmitting conductive film such as indium tin oxide to which indium is added can be used.

[0332] In addition, various materials can be used for the first electrode 7023. For example, When 23 is used as a cathode, a material with a small work function, specifically, for example, Li or Cs Alkali metals such as Mg, Ca, Sr, and alkaline earth metals, and alloys containing these metals In addition to (Mg:Ag, Al:Li, etc.), rare earth metals such as Yb and Er are preferred. When the first electrode 7023 is made of a material having a thickness that allows light to pass through (preferably, 5 nm or less), For example, when the first electrode 7023 is used as a cathode, the thickness is set to about 20 nm. An aluminum film having a thickness can be applied.

[0333] After the light-transmitting conductive film and the light-transmitting metal film are stacked, the conductive film and the metal film are selectively etched. The light-transmitting conductive film 7027 and the first electrode 7023 may be formed by etching. In this case, etching can be preferably performed using the same mask.

[0334] The partition wall 7029 is formed by the protective insulating layer 7045, the overcoat layer 7044, and the insulating layer 70 A light-transmitting conductive film is formed on the contact hole 42 and reaches the drain electrode layer. The first electrode 7023 is disposed with a conductive film 7027 interposed therebetween. The periphery of the first electrode 7023 may be covered with a partition wall. The partition wall 7029 is made of an organic material such as polyimide, acrylic resin, polyamide, or epoxy resin. The partition wall 7029 is formed using a resin film, an inorganic insulating film, or organic polysiloxane. An opening is formed on the first electrode 7023 using a photosensitive resin material, and the sidewall of the opening is It is preferable to form the partition wall 70 so as to have an inclined surface formed with a continuous curvature. When a photosensitive resin material is used as 29, the step of forming a resist mask can be omitted. This can be done.

[0335] The EL layer 7024 formed over the first electrode 7023 and the partition wall 7029 includes a light-emitting layer. It can be made up of a single layer or multiple layers stacked together. The EL layer 7024 is made up of multiple layers, and the first electrode 7023 is used as a cathode. When used, the electron injection layer, electron transport layer, light emitting layer, hole transport layer, and hole injection layer are stacked in this order. It is not necessary to provide all of these layers.

[0336] Furthermore, the stacking order is not limited to the above. When the first electrode 7023 is used as an anode, On the electrode 7023, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer are formed in this order. However, when comparing power consumption, the first electrode 7023 is used as a cathode. On the first electrode 7023, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, a hole injection layer, It is preferable to stack the layers in the order of the incoming layers, as this can suppress the voltage rise in the drive circuit section and reduces power consumption. It's nice.

[0337] In addition, various materials can be used for the second electrode 7025 formed on the EL layer 7024. For example, when the second electrode 7025 is used as an anode, a material with a large work function can be used. A transparent conductive material such as ITO, IZO, or ZnO can be preferably used. In this embodiment mode, the second electrode 7025 is used as an anode, and an ITO film containing silicon oxide is used as an anode. Form.

[0338] An EL layer 7024 including a light-emitting layer is sandwiched between a first electrode 7023 and a second electrode 7025. In the case of the element structure shown in FIG. 17(B), the light-emitting element The light emitted from 7022 travels between the second electrode 7025 and the first electrode 70 as shown by the arrows. 23It is fired on both sides.

[0339] In FIG. 17B, light emitted from the light-emitting element 7022 toward the first electrode 7023 One light passes through the color filter layer 7043 and enters the insulating layer 7042 and the gate insulating layer 704 0 and passes through the substrate 7020.

[0340] The color filter layer 7043 can be formed by a droplet discharge method such as an ink jet method, a printing method, or a photolithography method. Each is formed by an etching method using graphic technology.

[0341] The color filter layer 7043 is covered with an overcoat layer 7044, which is further provided with a protective insulating layer. Covered by layer 7045.

[0342] However, if a light-emitting element with a dual-side emission structure is used and both display surfaces are full color, Since light from the second electrode 7025 side does not pass through the color filter layer 7043, a separate color filter is required. It is preferable to provide a sealing substrate with a filter layer above the second electrode 7025.

[0343] Next, a light emitting element with a top emission structure will be described with reference to FIG.

[0344] In FIG. 17(C), a driving transistor 7001 is an n-type transistor, and a light emitting element 7002 emits light. FIG. 17(C) shows a cross-sectional view of a pixel in the case where light passes through the second electrode 7005. A light-emitting element electrically connected to the source electrode or the drain electrode of the driving transistor 7001 A first electrode 7003 of the element 7002 is formed, and an EL layer 7 004 and a second electrode 7005 are laminated in this order.

[0345] In addition, various materials can be used for the first electrode 7003. For example, When using 03 as a cathode, a material with a small work function, specifically, Li or Cs, Alkali metals such as Mg, Ca, Sr, and alkaline earth metals, and alloys containing these metals In addition to (Mg:Ag, Al:Li, etc.), rare earth metals such as Yb and Er are preferred.

[0346] The partition wall 7009 is formed on the protective insulating layer 7052 and the insulating layer 7055, and The first electrode 7003 is placed on the contact hole that reaches the inner electrode layer. The periphery of the first electrode 7003 may be covered with a partition wall. The partition wall 7009 may be made of polyimide, Organic resin films such as acrylic resin, polyamide, and epoxy resin, inorganic insulating films, or organic polymer films The partition wall 7009 is formed by using a photosensitive resin material, and the first electrode An opening is formed on 7003, and the sidewall of the opening has a continuous curvature. It is preferable to form the partition wall 7009 so that it has a flat surface. In this case, the step of forming a resist mask can be omitted.

[0347] The EL layer 7004 formed on the first electrode 7003 and the partition wall 7009 is It is sufficient to include a light-emitting layer, and it may be composed of a single layer or a plurality of layers stacked. The EL layer 7004 is made up of a plurality of layers, and the first electrode 7003 is made up of a When used as a cathode, it is used as an electron injection layer, an electron transport layer, an emitting layer, a hole transport layer, a hole injection layer, The layers are laminated in this order. It is not necessary to provide all of these layers.

[0348] Furthermore, the stacking order is not limited to the above. When the first electrode 7003 is used as an anode, On the electrode 7003, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer are formed in this order. Layers may be stacked one upon the other.

[0349] For example, the first electrode 7003, which is a laminate of a Ti film, an aluminum film, and a Ti film, is used as an anode. On the first electrode 7003, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer The above are laminated in this order, and then a laminate of an Mg:Ag alloy thin film and ITO is formed on top of that.

[0350] When the driving transistor 7001 is an n-type, an electron injection layer, Stacking the electron transport layer, light emitting layer, hole transport layer, and hole injection layer in this order is advantageous in the drive circuit. This is preferable because it can suppress the voltage rise during the heating and reduce power consumption.

[0351] The second electrode 7005 is formed using a conductive material that transmits visible light. For example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide oxides, indium oxides containing titanium oxide, indium tin oxides containing titanium oxide, indium Indium tin oxide, indium zinc oxide, indium tin oxide with silicon oxide added, etc. A light-transmitting conductive film such as the above may be used.

[0352] An EL layer 7004 including a light-emitting layer is sandwiched between a first electrode 7003 and a second electrode 7005. In the case of the pixel shown in FIG. 17(C), the light emitting element 700 Light emitted from 2 is emitted to the second electrode 7005 side as shown by the arrow.

[0353] The planarization insulating layer 7053 is made of polyimide, acrylic resin, benzocyclobutene resin, poly Resin materials such as amide and epoxy resins can be used. Dielectric constant materials (low-k materials), siloxane resins, PSG (phosphor glass), BPSG ( In addition, the insulating film formed from these materials can be The planarization insulating layer 7053 may be formed by stacking a plurality of layers. The method for forming the layer is not particularly limited, and may be a sputtering method, an SOG method, a spin coating method, or the like, depending on the material. , dip, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. It can be used.

[0354] In the structure of FIG. 17C, when full color display is performed, for example, the light emitting element 70 02 is a green light emitting element, one of the adjacent light emitting elements is a red light emitting element, and the other The light-emitting element is a blue light-emitting element. In addition to the three types of light-emitting elements, a white element is also included, making a total of four A light-emitting display device capable of full-color display may be manufactured using a variety of light-emitting elements.

[0355] In the structure of FIG. 17(C), all the light emitting elements are white light emitting elements. A sealing substrate having a color filter or the like is disposed above the light emitting element 7002. A light-emitting display device capable of full color display may be manufactured. By combining a color filter and a color conversion layer, a full color display is achieved. It is possible.

[0356] Of course, a single-color display may be performed. For example, a lighting device may be formed using white light. Alternatively, a monochromatic light emitting device may be used to form an area color type light emitting device.

[0357] If necessary, an optical film such as a polarizing film, eg, a circular polarizing plate, may be provided.

[0358] Although organic EL elements have been described as light-emitting elements here, inorganic EL elements can also be used as light-emitting elements. It is also possible to provide an L element.

[0359] The transistor that controls the driving of the light-emitting element (drive transistor) and the light-emitting element are electrically However, a current control transistor may be connected between the driving transistor and the light emitting element. A transistor may be connected.

[0360] Note that the semiconductor device described in this embodiment mode is not limited to the configuration shown in FIG. Various modifications based on the technical concept of the present invention are possible.

[0361] Next, one example of a semiconductor device to which the transistor described in Embodiment 1 or 2 is applied will be described. The appearance and cross section of the light-emitting display panel (also called the light-emitting panel) corresponding to the above state are shown in FIG. 18 shows a transistor and a light-emitting element formed on a first substrate. 18(B) is a top view of a panel sealed between two substrates by a sealing material, and FIG. This corresponds to a cross-sectional view taken along line HI in FIG. 18(A).

[0362] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. 3b and the scanning line driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealing material 4505, and a second substrate 4506. The seal is sealed together with the filler 4507 by the sealant. Highly airtight protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the product in a protective film (such as a film) or a cover material.

[0363] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of transistors. 18B, a transistor 4510 included in a pixel portion 4502 and a signal line driver A transistor 4509 included in the circuit 4503a is illustrated.

[0364] The transistors 4509 and 4510 include an oxide semiconductor layer (In-Ga-Zn-O based film). The transistor described in Embodiment 1 or 2 can be used to achieve high reliability. In this embodiment, the transistors 4509 and 4510 are n-channel transistors. It is a star.

[0365] The channel of the oxide semiconductor layer of the transistor 4509 for the driver circuit is formed over the insulating layer 4544. A conductive layer 4540 is provided in a position overlapping the hole formation region. By placing the conductive layer at a position that overlaps the channel formation region, The amount of change in the threshold voltage of the transistor 4509 can be reduced. The potential of the gate electrode layer of the transistor 4509 may be the same as or different from that of the gate electrode layer of the transistor 4509. Alternatively, the conductive layer 4540 may function as a second gate electrode layer. may be GND, 0V, or floating.

[0366] Further, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the transistor 4510. The light-emitting element 4511 is configured with a first electrode layer 4517, an electroluminescent layer 45 12, the stacked structure of the second electrode layer 4513 is not limited to the structure shown in this embodiment mode. The configuration of the light emitting element 4511 is adjusted according to the direction of the light to be extracted from the light emitting element 4511. can be changed appropriately.

[0367] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable to form the inclined surface so that the inclined surface has a continuous curvature.

[0368] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's done or not.

[0369] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511. A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be a silicon nitride film, A silicon nitride oxide film, a DLC film, or the like can be formed.

[0370] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are transmitted through the FPC 4518a, 4518b, and It is supplied by b.

[0371] In this embodiment, the connection terminal electrode 4515 is connected to the first electrode layer 4 The terminal electrode 4516 is formed from the same conductive film as the transistor 4509. The source electrode layer and the drain electrode layer are formed from the same conductive film.

[0372] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. are electrically connected to each other.

[0373] The second substrate located in the direction of light extraction from the light emitting element 4511 must be transparent. In that case, use a glass plate, plastic plate, polyester film or acrylic A light-transmitting material such as a resin film is used.

[0374] In addition to inert gases such as nitrogen and argon, filler 4507 can also be used as UV-curable resin. It can be made of PVC (polyvinyl chloride), acrylic resin or thermosetting resin. Oil, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. Nitrogen is used.

[0375] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0376] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Alternatively, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and mounted. In this embodiment, the structure shown in FIG. Not limited.

[0377] Through the above steps, a display device including a transistor with excellent operational stability can be manufactured. The light-emitting display device of this embodiment mode is equipped with a transistor having excellent operational stability. Highly reliable.

[0378] In addition, the transistors provided in the pixel portion and the driver circuit of the display device of this embodiment mode have a wide band. It has a wide gap and a carrier concentration of 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 Since the oxide semiconductor used is suppressed to below 100%, it exhibits normally-off behavior, and The off-state current is low. Specifically, the off-state current at room temperature per 1 μm of channel width is 1×10 -16 A / μm or less, and even 1aA / μm (1×10 -18 A / μm) or less is possible.

[0379] As a result, a display device can be provided that suppresses leakage current and saves power. A display device with a large off-state current ratio can be provided. In addition, the display device has excellent contrast and high display quality. This makes it possible to provide a display device that is easy to use.

[0380] In addition, the display device of this embodiment uses a field-effect transfer element (FET) that uses a highly purified oxide semiconductor layer. It is equipped with high-performance transistors, which allows it to operate at high speed and has excellent video display characteristics and high-definition It is possible to display.

[0381] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so.

[0382] (Embodiment 8) In this embodiment, an example of an electronic paper is used as a display device, which is an example of a semiconductor device of the present invention. show.

[0383] FIG. 19 shows an active matrix electronic display device as an example of a display device to which one embodiment of the present invention is applied. The transistor 581 used in the display device is the same as that described in Embodiment 1 or can be fabricated in the same manner as in the second embodiment.

[0384] The electronic paper in Figure 19 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. and a potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying by controlling the orientation of spherical particles by generating a magnetic field.

[0385] The source electrode layer or the drain electrode layer of the transistor 581 is formed by the first electrode layer 587 and the insulating layer The first electrode layer 587 is electrically connected to the first electrode layer 585 through an opening formed in the first electrode layer 587. Between the first electrode layer 588 and the second electrode layer 589, there are black areas 590a and white areas 590b. 90a and a cavity 594 filled with liquid provided around the white area 590b. The spherical particles 589 are surrounded by a filler 595 such as a resin. In FIG. 19, 580 is a substrate, 583 is an interlayer, The insulating film, 584 is a protective film, and 596 is a substrate.

[0386] Also, instead of the twist ball, an electrophoretic element can be used. and a diameter of 10 μm to 20 μm that contains positively charged white particles and negatively charged black particles. Microcapsules of about 0 μm in size are used. When an electric field is applied by the first and second electrode layers, the microcapsules turn white. White particles and black particles move in opposite directions, allowing the display to be white or black. The display element that applies this principle is an electrophoretic display element, and devices that use electrophoretic display elements Electrophoretic display elements are generally called electronic paper. High reflectance means no auxiliary light is required, and the low power consumption means it can be displayed even in dimly lit areas. Even if the display unit is not powered, the Therefore, for example, the radio wave source that supplies power can be used From the semiconductor device with a display function (also simply referred to as a display device or a semiconductor device equipped with a display device) Even if the user moves away from the camera, the displayed image can be saved.

[0387] Through the above process, we were able to create electronic paper equipped with transistors that have excellent operational stability. The electronic paper of this example is equipped with transistors that have excellent operational stability. Highly reliable.

[0388] In addition, the transistors provided in the pixel portion and the driver circuit of the display device of this embodiment mode have a wide band. It has a wide gap and a carrier concentration of 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 Since the oxide semiconductor used is suppressed to below 100%, it exhibits normally-off behavior, and The off-state current is low. Specifically, the off-state current at room temperature per 1 μm of channel width is 1×10 -16 A / μm or less, and even 1aA / μm (1×10 -18 A / μm) or less is possible.

[0389] As a result, a display device can be provided that suppresses leakage current and saves power. A display device with a large off-state current ratio can be provided. In addition, the display device has excellent contrast and high display quality. This makes it possible to provide a display device that is easy to use.

[0390] In addition, the display device of this embodiment uses a field-effect transfer element (FET) that uses a highly purified oxide semiconductor layer. It is equipped with high-performance transistors, which allows it to operate at high speed and has excellent video display characteristics and high-definition It is possible to display.

[0391] This embodiment is implemented by appropriately combining with the configuration described in the first or second embodiment. It is possible to implement this.

[0392] (Embodiment 9) The display device of one embodiment of the present invention can be used as electronic paper. It can be used in any electronic device that displays information. For example, electronic paper can be used for electronic books, posters, and on trains and other vehicles. It can be used for in-car advertising, display on various cards such as credit cards, etc. An example of a slave device is shown in FIG. 20 and FIG.

[0393] FIG. 20(A) shows a poster 2631 made of electronic paper. In the case of printed matter, the advertisements are exchanged manually. By using electronic paper, the display of advertisements can be changed in a short time. The poster is designed to be able to send and receive information wirelessly. It may also be possible to use the following.

[0394] FIG. 20(B) shows an advertisement 2632 inside a vehicle such as a train. In the case of paper printouts, the advertisements are exchanged manually. By using electronic paper, it is possible to change the display of advertisements in a short time without requiring much manpower. In addition, stable images can be displayed without any distortion. It may be configured to be able to send and receive information.

[0395] 21 also shows an electronic book 2700. For example, the electronic book 2700 has a housing 2 The housing 2701 and the housing 2703 are two housings. are integrated by a shaft portion 2711, and the opening and closing operation is performed around the shaft portion 2711. With this configuration, it is possible to operate like a paper book.

[0396] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are also configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, if a sentence is displayed on the right display (display 2705 in FIG. 21) and In FIG. 21, an image can be displayed on the display unit 2707).

[0397] 21 shows an example in which the housing 2701 is provided with an operation unit. 701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. It may also be configured to include a touch panel, a pointing device, etc. On the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB cable). The configuration includes a terminal that can be connected to various cables such as a cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have the function of an electronic dictionary. Good too.

[0398] The electronic book 2700 may also be configured to be able to send and receive information wirelessly. The desired book data can be purchased and downloaded from the e-book server. is also possible.

[0399] The transistor described in the above embodiment is used to provide a transistor with excellent operational stability. A display device equipped with a transistor having excellent operational stability can be manufactured. Highly reliable.

[0400] (Embodiment 10) A semiconductor device according to one embodiment of the present invention can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television (also called digital receivers), computer monitors, digital cameras, digital video cameras digital photo frames, mobile phones (also called mobile phones or mobile phone devices), Examples include large game machines such as small game machines, mobile information terminals, sound reproduction devices, and pachinko machines. can be.

[0401] FIG. 22(A) shows a television device 9600. The television device 9600 A display portion 9603 is incorporated in the housing 9601. The display portion 9603 displays images. In this embodiment, the housing 960 can be supported by a stand 9605. This shows a configuration that supports 1.

[0402] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the information displayed on the display 9603 is In addition, the remote control operation device 9610 can operate the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0403] The television device 9600 is configured to include a receiver, a modem, and the like. It can receive more general TV broadcasts and can also receive them via wired or wireless modems. By connecting to a communication network, it can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0404] FIG. 22(B) shows a digital photo frame 9700. For example, The display frame 9700 has a display unit 9703 built into a housing 9701. 03 can display various images, such as images taken with a digital camera. By displaying image data, it can function like a regular photo frame.

[0405] The Digital Photo Frame 9700 has an operation panel, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section. These components may be incorporated on the same surface as the display unit, but they may be incorporated on the side or back. It is preferable to have a recording medium for a digital photo frame as it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section. The image data can be captured and the captured image data can be displayed on the display portion 9703 .

[0406] The digital photo frame 9700 may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to configure the device so that desired image data can be wirelessly acquired and displayed.

[0407] FIG. 23(A) shows a portable gaming machine, which is composed of two cabinets, a cabinet 9881 and a cabinet 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in 23(A) also includes a speaker unit 9884, a recording medium insertion unit 988 6, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration (including functions for measuring movement, smell, or infrared rays), microphone 9889) Of course, the configuration of the portable gaming machine is not limited to the above, and It is sufficient if the semiconductor device according to one aspect is included, and other auxiliary equipment is appropriately provided. The portable gaming machine shown in FIG. 23(A) can be configured as It has the function of reading out programs or data and displaying them on the display, as well as wireless communication with other portable gaming machines. The portable gaming machine shown in FIG. 23(A) has the function of communicating with the user and sharing information. The functions are not limited to these, and various other functions may be provided.

[0408] FIG. 23(B) shows a slot machine 9900, which is a large gaming machine. 9900 has a display unit 9903 built into a housing 9901. The 9900 also has other controls such as a start lever and stop switch, and a coin slot. , speakers, etc. Of course, the configuration of the slot machine 9900 is the same as that described above. There are no limitations, and it is sufficient that the semiconductor device according to at least one embodiment of the present invention is included. Other auxiliary equipment may be provided as appropriate.

[0409] FIG. 24 shows a mobile phone 1000. The mobile phone 1000 is assembled in a housing 1001. In addition to the built-in display 1002, operation buttons 1003, external connection port 1004, speaker It is equipped with a camera 1005, a microphone 1006, etc.

[0410] The mobile phone 1000 shown in FIG. 24 allows users to input information by touching the display unit 1002 with a finger or the like. In addition, operations such as making a phone call or sending an email can be performed using the display unit 1. This can be done by touching 002 with a finger or the like.

[0411] The screen of the display unit 1002 has three main modes. The first is a display mode that mainly displays images. The first mode is a display mode, and the second mode is an input mode that mainly inputs information such as characters. This is a display + input mode that combines two modes: display mode and input mode.

[0412] For example, when making a call or creating an email, the display unit 1002 is used to input characters. This is the main character input mode, and you can input characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002. I wish.

[0413] In addition, the mobile phone 1000 may include a sensor for detecting tilt, such as a gyro or an acceleration sensor. By providing a detection device having the above configuration, the orientation of the mobile phone 1000 (portrait or landscape) can be determined and the display The screen display of the display unit 1002 can be automatically switched.

[0414] The screen mode can be switched by touching the display unit 1002 or by operating the housing 1001. This is done by operating the button 1003. Also, depending on the type of image displayed on the display unit 1002, For example, if the image signal to be displayed on the display unit is a video signal, If it is data, the display mode is switched to, and if it is text data, the input mode is switched to.

[0415] In the input mode, the optical sensor of the display unit 1002 detects a signal and displays it. If there is no input by touch operation of the part 1002 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0416] The display unit 1002 can also function as an image sensor. By touching the palm or fingers to the sensor 02, the palm print, fingerprint, etc. can be captured and identity authentication can be performed. In addition, the display unit may be equipped with a backlight that emits near-infrared light or a sensor that emits near-infrared light. By using a scanning light source, it is also possible to capture images of finger veins, palm veins, etc.

[0417] The transistor described in the above embodiment is used to provide a transistor with excellent operational stability. The above electronic devices are equipped with transistors that have excellent operational stability. It is highly reliable because it is included. [Explanation of symbols]

[0418] 10 Pulse output circuit 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 16 Wiring 17 Wiring 21 Input terminal 22 Input terminal 23 Input terminal 24 input terminals 25 Input terminals 26 Output terminal 27 Output terminal 31 Transistor 32 transistors 33 Transistor 34 transistors 35 transistors 36 transistors 37 Transistor 38 transistors 39 Transistor 40 transistors 41 Transistor 51 Power line 52 Power line 53 Power line 61 period 62 period 100 boards 102 Insulating layer 102a Insulating layer 107 Insulating layer 107c Insulating layer 108 Insulating layer 109 Insulating Layer 111a Gate electrode 111b Capacitive electrode 111c gate wiring 111d Gate electrode 111e Conductive layer 111f conductive layer 113a Oxide semiconductor layer 113c Oxide semiconductor layer 114a Barrier layer 114b Barrier layer 114e Barrier layer 114f Barrier layer 115a electrode 115b electrode 115e conductive layer 115f conductive layer 116 Conductive layer 116a signal line 116b signal line 116c electrode 116d electrode 120 pixel electrode 123 Oxide semiconductor layer 126a opening 126b opening 127 Opening 127a opening 127b opening 128 Opening 129 Conductive Layer 151 transistors 152 transistors 153 Transistor 154 transistors 400 boards 402 Insulating layer 404a Oxide semiconductor layer 404b Oxide semiconductor layer 408 Contact Hole 410a wiring 410b wiring 410c wiring 411 terminal 412 terminal 421a Gate electrode 421b Gate electrode 422a electrode 422b electrode 428 Insulating Layer 440A transistor 440B transistor 455a electrode 455b electrode 455c electrode 455d electrode 580 board 581 Transistor 583 Interlayer insulating film 584 Protective film 585 Insulation Layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 590a black area 590b White area 594 Cavity 595 Filling material 596 PCB 1000 mobile phones 1001 Case 1002 Display section 1003 Operation button 1004 External connection port 1005 Speaker 1006 Mike 2600 Transistor Board 2601 Opposing substrate 2602 Sealing material 2603 Pixel section 2604 Display element 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible wiring board 2610 cold cathode tube 2611 Reflector 2612 Circuit Board 2613 Diffuser 2631 Poster 2632 In-car advertising 2700 e-books 2701 Housing 2703 Housing 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation Key 2725 Speaker 4001 board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 board 4008 Liquid crystal layer 4010 transistor 4011 transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulation layer 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4033 Insulation layer 4035 Spacer 4501 Circuit Board 4502 Pixel section 4503a Signal line driver circuit 4503b Signal line driver circuit 4504a Scanning line driver circuit 4504b Scanning line driver circuit 4505 Sealing material 4506 board 4507 Filling material 4509 Transistor 4510 transistor 4511 Light-emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4518a FPC 4519 Anisotropic conductive film 4520 Bulkhead 4540 Conductive layer 4544 Insulation layer 5300 board 5301 Pixel unit 5302 Scanning line driver circuit 5303 Scanning line driver circuit 5304 Signal line driver circuit 5305 Timing control circuit 5601 Shift Register 5602 Switching Circuit 5603 Transistor 5604 Wiring 5605 Wiring 6400 pixels 6401 Switching transistor 6402 Drive transistor 6403 Capacitor element 6404 Light-emitting element 6405 signal line 6406 scan lines 6407 Power line 6408 Common electrode 7001 Drive transistor 7002 Light-emitting element 7003 Electrode 7004 EL layer 7005 Electrode 7009 Bulkhead 7010 board 7011 Drive transistor 7012 Light-emitting element 7013 Electrode 7014 EL layer 7015 Electrode 7016 Shielding membrane 7017 Conductive film 7019 Bulkhead 7020 board 7021 Drive transistor 7022 Light-emitting element 7023 Electrode 7024 EL layer 7025 Electrode 7027 Conductive film 7029 Bulkhead 7030 Gate insulating layer 7032 Insulation layer 7033 Color filter layer 7034 Overcoat layer 7035 Protective insulation layer 7040 Gate insulating layer 7042 Insulation layer 7043 Color filter layer 7044 Overcoat layer 7045 Protective insulation layer 7052 Protective insulation layer 7053 Planarization insulating layer 7055 Insulation layer 9600 Television Equipment 9601 Housing 9603 Display section 9605 Stand 9607 Display section 9609 Operation Key 9610 Remote Control Machine 9700 Digital Photo Frame 9701 Housing 9703 Display section 9881 Case 9882 Display section 9883 Display section 9884 Speaker section 9885 Operation Key 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Case 9893 Connection section 9900 slot machine 9901 Housing 9903 Display section

Claims

[Claim 1] a light-transmitting gate electrode on an insulating surface of a light-transmitting substrate; a first insulating layer on the gate electrode; a highly purified oxide semiconductor layer on the first insulating layer; a first electrode and a second electrode on the oxide semiconductor layer, the first electrode and the second electrode overlapping the gate electrode at their ends; a light-transmitting barrier layer between the oxide semiconductor layer and the first electrode and between the oxide semiconductor layer and the second electrode; a second insulating layer in contact with a surface of the oxide semiconductor layer opposite to a region where a channel is formed, The carrier concentration of the oxide semiconductor layer is 1×10 １４ / cm ３ is less than The first electrode and the second electrode are light-transmitting and have a resistivity of 2000×10 －６ an oxide conductive layer having a resistivity of Ω cm or less; The semiconductor device wherein the barrier layer comprises a nitride.

Images