Input circuit and semiconductor device

Abstract

To provide an input circuit that can reduce an input offset voltage while suppressing a change in response of a semiconductor device, and a semiconductor device comprising such an input circuit.SOLUTION: An input circuit has a first differential transistor portion having a plurality of first transistors connected in parallel to each other, a second differential transistor portion having a plurality of second transistors connected in parallel to each other, and a cutoff selectable portion. An output circuit has a first current path portion and a second current path portion disposed in parallel to each other. A first terminal of each of the plurality of first transistors is connected to the first current path portion. A first terminal of each of the plurality of second transistors is connected to the second current path portion. The cutoff selectable portion is connected in series to at least one transistor among the plurality of first transistors and the plurality of second transistors. The cutoff selectable portion is selected to be in one of a state that allows a current to flow and a state that cuts off the current.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to an input circuit and a semiconductor device. [Background technology]

[0002] Circuits such as comparator circuits are known that generate an output based on the difference between two input voltages. In such circuits, the output value changes in response to changes in the two input voltages. However, due to variations in the impedance of the circuit's components, the output value may not change in response to changes in the two input voltages, resulting in an input offset voltage. Trimming techniques for adjusting this input offset voltage include, for example, adding a current source to increase or decrease the amount of current flowing through the circuit. However, this change in the amount of current can cause fluctuations in the time it takes for the transistors included in the circuit to charge, resulting in changes in the circuit's responsiveness. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2007-531459 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to provide an input circuit that can reduce input offset voltage while suppressing changes in the responsiveness of a semiconductor device, and a semiconductor device including such an input circuit. [Means for solving the problem]

[0005] An input circuit according to an embodiment is connected to an output circuit that outputs an output value based on a first voltage and a second voltage, and to which the first voltage and the second voltage are applied. The input circuit according to an embodiment includes a first differential transistor section having a plurality of first transistors connected in parallel, a second differential transistor section having a plurality of second transistors connected in parallel, and a cutoff selectable section that selects a current cutoff state. The output circuit includes a first current path section and a second current path section that are arranged in parallel between a power supply voltage wiring to which a power supply voltage is applied and ground. The first differential transistor section and the second differential transistor section are arranged in parallel between the power supply voltage wiring and the ground. The first voltage is applied to drive terminals of the plurality of first transistors. The second voltage is applied to drive terminals of the plurality of second transistors. First terminals of the plurality of first transistors are connected to the first current path section. First terminals of the plurality of second transistors are connected to the second current path section. Second terminals of the plurality of first transistors and second terminals of the plurality of second transistors are connected to each other. The selectable cutoff unit is connected in series to at least one of the plurality of first transistors and the plurality of second transistors, and the selectable cutoff unit is set to one of a state in which a current is allowed to flow and a state in which a current is cut off. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a circuit diagram showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of the operation of the semiconductor device according to the first embodiment. [Figure 3] FIG. 4 is a circuit diagram showing another example of the operation of the semiconductor device according to the first embodiment. [Figure 4] 4 is a graph showing the relationship between input voltage and output voltage in the first embodiment. [Figure 5] FIG. 10 is a circuit diagram showing a semiconductor device according to a second embodiment. [Figure 6] FIG. 10 is a circuit diagram showing a semiconductor device according to a third embodiment. [Figure 7] FIG. 10 is a circuit diagram showing a semiconductor device according to a fourth embodiment. [Figure 8] FIG. 10 is a circuit diagram showing a semiconductor device according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, an input circuit and a semiconductor device according to an embodiment will be described with reference to the drawings.

[0008] (First embodiment) FIG. 1 is a circuit diagram showing a semiconductor device 100 according to a first embodiment. The semiconductor device 100 according to the first embodiment shown in FIG. 1 is a comparator. The semiconductor device 100 outputs a single output voltage VOUT as an output value in response to two input voltages VIN, a first voltage V1 and a second voltage V2. As shown in FIG. 1, the semiconductor device 100 includes an input circuit 10 and an output circuit 20.

[0009] The input circuit 10 is connected to the output circuit 20. A first voltage V1 and a second voltage V2 are applied to the input circuit 10. The input circuit 10 includes a first input terminal 11, a second input terminal 12, a first differential transistor section 50a, a second differential transistor section 50b, and a current source 13. The first voltage V1 is applied to the first input terminal 11 as an input voltage VIN. The second voltage V2 is applied to the second input terminal 12 as an input voltage VIN. The first differential transistor section 50a and the second differential transistor section 50b form a differential pair. The first differential transistor section 50a and the second differential transistor section 50b are arranged in parallel between a power supply voltage wiring 60 to which a power supply voltage VDD is applied and ground GND. The ground GND has a reference potential. The reference potential is, for example, 0 V. The reference potential is not particularly limited and may be a potential other than 0 V. Note that the voltages described in each embodiment are voltages relative to the reference potential of ground GND. That is, the voltage of the ground GND is 0 V. The first differential transistor section 50a includes a plurality of first transistors 51. The second differential transistor section 50b includes a plurality of second transistors 52.

[0010] In the first embodiment, the plurality of first transistors 51 and the plurality of second transistors 52 are field effect transistors (FETs). More specifically, the plurality of first transistors 51 and the plurality of second transistors 52 are N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs). The plurality of first transistors 51 are connected in parallel to one another. The first input terminal 11 is connected to each of the gate terminals 51g of the plurality of first transistors 51. As a result, a first voltage V1 is applied to the gate terminals 51g of the plurality of first transistors 51. The plurality of second transistors 52 are connected in parallel to one another. The second input terminal 12 is connected to each of the gate terminals 52g of the plurality of second transistors 52. As a result, a second voltage V2 is applied to the gate terminals 52g of the plurality of second transistors 52.

[0011] Drain terminals 51d of the plurality of first transistors 51 are connected to a first current path portion 30a (described later) of the output circuit 20. Drain terminals 52d of the plurality of second transistors 52 are connected to a second current path portion 30b (described later) of the output circuit 20. Source terminals 51s of the plurality of first transistors 51 and source terminals 52s of the plurality of second transistors 52 are connected to each other. In the first embodiment, two first transistors 51 and two second transistors 52 are provided.

[0012] The ratio W / L of the channel width W to the channel length L of the first transistor 51 and the ratio W / L of the channel width W to the channel length L of the second transistor 52 are larger than the ratios W / L of the channel width W to the channel length L of the other transistors in the semiconductor device 100.

[0013] In the present disclosure, the gate terminal of a field-effect transistor corresponds to a "drive terminal." The drive terminal of a transistor is a terminal to which a voltage is applied to drive the transistor. In the first embodiment, the drain terminal 51d of the first transistor 51 and the drain terminal 52d of the second transistor 52 correspond to a "first terminal." The source terminal 51s of the first transistor 51 and the source terminal 52s of the second transistor 52 correspond to a "second terminal."

[0014] The current source 13 is configured to pass a constant current. In the first embodiment, the current source 13 is configured by one transistor 13a. The current source 13 is not particularly limited as long as it is configured to pass a constant current, and may include, for example, a plurality of transistors. In the first embodiment, the transistor 13a is a field-effect transistor. More specifically, the transistor 13a is an N-channel MOSFET. A drain terminal 13d of the transistor 13a is connected to source terminals 51s of the plurality of first transistors 51 and source terminals 52s of the plurality of second transistors 52. The source terminal 13s of the transistor 13a is connected to ground GND.

[0015] A predetermined voltage V3 is applied to the gate terminal 13g of the transistor 13a. When the predetermined voltage V3 is applied to the gate terminal 13g, the transistor 13a is turned on. The amount of current that can flow through the transistor 13a is determined according to the magnitude of the predetermined voltage V3. Therefore, when the predetermined voltage V3 is applied to the gate terminal 13g, the transistor 13a functions as a current source 13 that supplies a constant current.

[0016] The input circuit 10 includes a cutoff selectable unit 14. The cutoff selectable unit 14 is a unit that can select a state in which a current is cut off. The cutoff selectable unit 14 is connected in series to at least one of the plurality of first transistors 51 and the plurality of second transistors 52. In the first embodiment, the cutoff selectable unit 14 is connected in series to each of one first transistor 51 and one second transistor 52. The cutoff selectable unit 14 connected in series to the first transistor 51 is connected to the drain terminal 51d of the first transistor 51. The cutoff selectable unit 14 connected in series to the second transistor 52 is connected to the drain terminal 52d of the second transistor 52. The cutoff selectable unit 14 connected in series to the first transistor 51 may be connected to the source terminal 51s of the first transistor 51. The cutoff selectable unit 14 connected in series to the second transistor 52 may be connected to the source terminal 52s of the second transistor 52.

[0017] The selectable interruption unit 14 selects either a state in which it allows current to flow or a state in which it blocks current. In the example of FIG. 1, the selectable interruption unit 14 connected in series to the first transistor 51 selects a state in which it allows current to flow. The selectable interruption unit 14 connected in series to the second transistor 52 selects a state in which it blocks current. In the following description, the state of the selectable interruption unit 14 in which it allows current to flow is referred to as the "conducting state," and the state of the selectable interruption unit 14 in which it blocks current is referred to as the "blocking state."

[0018] In the first embodiment, the selectable cutoff unit 14 is a fuse. A state in which the selectable cutoff unit 14, which is a fuse, is not cut off is a conducting state. A state in which the selectable cutoff unit 14, which is a fuse, is cut off is a cut-off state. During manufacturing of the input circuit 10, a selection is made between leaving the selectable cutoff unit 14, which is a fuse, uncut or cutting the selectable cut-off unit 14, thereby selecting the state of the selectable cut-off unit 14 to be either the conducting state or the cut-off state.

[0019] The output circuit 20 is connected to the input circuit 10. The output circuit 20 outputs an output voltage VOUT as an output value based on a first voltage V1 and a second voltage V2. In the first embodiment, the output circuit 20 has a first amplifier circuit section 30 and a second amplifier circuit section 40.

[0020] The first amplifier circuit section 30 is connected to the input circuit 10. The first amplifier circuit section 30 amplifies the voltage difference between a first voltage V1 and a second voltage V2 input to the input circuit 10 and outputs the amplified voltage to the second amplifier circuit section 40. The first amplifier circuit section 30 has a first current path section 30a, a second current path section 30b, a current source circuit section 31, a first auxiliary circuit section 32, a first current mirror circuit section 33, and a second auxiliary circuit section 34.

[0021] The first current path portion 30a and the second current path portion 30b are arranged in parallel with each other between a power supply voltage wiring 60 to which a power supply voltage VDD is applied and ground GND. One end of the first current path portion 30a and one end of the second current path portion 30b are connected to the power supply voltage wiring 60. The other end of the first current path portion 30a and the other end of the second current path portion 30b are connected to ground GND. In the first embodiment, the first current path portion 30a is configured by a transistor 31a, a transistor 32a, a transistor 34a, and a transistor 33a (described later) connected in series in this order between the power supply voltage wiring 60 and ground GND. In the first embodiment, the second current path portion 30b is configured by a transistor 31b, a transistor 32b, a transistor 34b, and a transistor 33b (described later) connected in series in this order between the power supply voltage wiring 60 and ground GND.

[0022] The current source circuit unit 31 is a circuit configured to pass a constant current. In the first embodiment, the current source circuit unit 31 is configured by a pair of transistors 31a and 31b. In the first embodiment, the pair of transistors 31a and 31b are field-effect transistors. More specifically, the pair of transistors 31a and 31b are P-channel MOSFETs. The gate terminals of the pair of transistors 31a and 31b are connected to each other. The transistor 31a is provided in the first current path unit 30a. The transistor 31b is provided in the second current path unit 30b. The source terminals of the pair of transistors 31a and 31b are connected to a power supply voltage wiring 60. A predetermined voltage V4 is applied to the gate terminals of the pair of transistors 31a and 31b. This turns the pair of transistors 31a and 31b into an ON state. In the first embodiment, the pair of transistors 31a and 31b are transistors having the same parameters, such as the ratio W / L of the channel width W to the channel length L, and have the same characteristics. Therefore, when the pair of transistors 31a and 31b are turned on, they function as current sources that pass currents of the same magnitude. The magnitude of the current passed by each of the pair of transistors 31a and 31b is the same as the magnitude of the current passed by the current source 13, for example. In other words, the total amount of current passed by the current source circuit unit 31 is, for example, twice the amount of current passed by the current source 13. Note that variations in the characteristics of the pair of transistors 31a and 31b may cause variations in the magnitude of the current passed by the pair of transistors 31a and 31b.

[0023] The first auxiliary circuit section 32 is a circuit that assists the current source circuit section 31. In the first embodiment, the first auxiliary circuit section 32 is configured by a pair of transistors 32a and 32b. In the first embodiment, the pair of transistors 32a and 32b are field-effect transistors. More specifically, the pair of transistors 32a and 32b are P-channel MOSFETs. The gate terminals of the pair of transistors 32a and 32b are connected to each other. The transistor 32a is provided in the first current path section 30a. The transistor 32b is provided in the second current path section 30b. The source terminal of the transistor 32a is connected to the drain terminal of the transistor 31a. The source terminal of the transistor 32b is connected to the drain terminal of the transistor 31b. A predetermined voltage V5 is applied to the gate terminals of the pair of transistors 32a and 32b. This turns the pair of transistors 32a and 32b into an ON state. In the first embodiment, the pair of transistors 32a and 32b have the same parameters, such as the ratio W / L of the channel width W to the channel length L, and therefore have the same characteristics. Therefore, by applying the same predetermined voltage V5 to the gate terminals of the pair of transistors 32a and 32b, the voltages at the source terminals of the pair of transistors 32a and 32b become the same. This allows the voltages at the drain terminals of the pair of transistors 31a and 31b, which are connected to the source terminals of the pair of transistors 32a and 32b, respectively, to be the same. Since the voltages at the drain terminals of the pair of transistors 31a and 31b constituting the current source circuit unit 31 can be stabilized to the same voltage, it is easier to stabilize and maintain the currents flowing through the pair of transistors 31a and 31b at the same magnitude. Note that variations in the voltages at the source terminals of the pair of transistors 32a and 32b may occur due to variations in the characteristics of the pair of transistors 32a and 32b.

[0024] The first current mirror circuit unit 33 is composed of a pair of transistors 33a and 33b. The first current mirror circuit unit 33 is a circuit configured to pass currents of the same magnitude through the pair of transistors 33a and 33b. The second auxiliary circuit unit 34 is composed of a pair of transistors 34a and 34b. The second auxiliary circuit unit 34 is a circuit that assists the first current mirror circuit unit 33.

[0025] In the first embodiment, the transistors 33a, 33b, 34a, and 34b are field-effect transistors. More specifically, the transistors 33a, 33b, 34a, and 34b are N-channel MOSFETs. The transistors 33a and 34a are provided in the first current path portion 30a. The transistors 33b and 34b are provided in the second current path portion 30b. In the first embodiment, the pair of transistors 33a and 33b are transistors having the same parameters, such as the ratio W / L of the channel width W to the channel length L, and have the same characteristics. In the first embodiment, the pair of transistors 34a and 34b are transistors having the same parameters, such as the ratio W / L of the channel width W to the channel length L, and have the same characteristics.

[0026] The transistors 33a and 34a are connected in series. The drain terminal of the transistor 33a is connected to the source terminal of the transistor 34a of the second auxiliary circuit section 34. The source terminal of the transistor 33a is connected to ground GND. The drain terminal of the transistor 34a is connected to the drain terminal of the transistor 32a of the first auxiliary circuit section 32.

[0027] The transistors 33b and 34b are connected in series. The drain terminal of the transistor 33b is connected to the source terminal of the transistor 34b. The source terminal of the transistor 33b is connected to ground GND. The drain terminal of the transistor 34b is connected to the drain terminal of the transistor 32b of the first auxiliary circuit section 32.

[0028] The gate terminals of the pair of transistors 33a, 33b in the first current mirror circuit section 33 are connected to each other. The gate terminals of the pair of transistors 33a, 33b are connected to the drain terminal of the transistor 32a and the drain terminal of the transistor 34a. The gate terminals of the pair of transistors 34a, 34b in the second auxiliary circuit section 34 are connected to each other. A predetermined voltage V6 is applied to the gate terminals of the pair of transistors 34a, 34b. This switches the pair of transistors 34a, 34b to an ON state. Since the pair of transistors 34a, 34b have identical characteristics, the application of the same predetermined voltage V6 to the gate terminals of the pair of transistors 34a, 34b causes the voltages of the source terminals of the pair of transistors 34a, 34b to be the same. Note that variations in the characteristics of the pair of transistors 34a, 34b may cause variations in the voltages of the source terminals of the pair of transistors 34a, 34b.

[0029] The first current mirror circuit 33 is configured such that the pair of transistors 33a and 33b have identical characteristics, causing a current of the same magnitude as the current flowing through the transistor 33a in the first current path section 30a to flow through the transistor 33b in the second current path section 30b. In the first embodiment, the voltages at the source terminals of the pair of transistors 34a and 34b in the second auxiliary circuit section 34 are the same, and therefore the voltages at the drain terminals of the pair of transistors 33a and 33b connected to the source terminals of the pair of transistors 34a and 34b, respectively, are also the same. This allows the voltages at the drain terminals of the pair of transistors 33a and 33b to be stably made the same. Therefore, the magnitudes of the currents flowing through the transistors 33a and 33b can be easily stably made the same. Note that variations in the characteristics of the pair of transistors 33a and 33b may cause variations in the magnitudes of the currents flowing through the pair of transistors 33a and 33b.

[0030] One end of a first differential transistor section 50a in the input circuit 10 is connected to a portion of the first current path section 30a between the transistor 31a and the transistor 32a. More specifically, drain terminals 51d of a plurality of first transistors 51 in the input circuit 10 are connected to a portion of the first current path section 30a between the transistor 31a and the transistor 32a. The drain terminals 51d of the plurality of first transistors 51 are connected to the drain terminal of the transistor 31a in the current source circuit section 31 and the source terminal of the transistor 32a in the first auxiliary circuit section 32. In the first embodiment, the drain terminal 51d of one first transistor 51 is connected to the first current path section 30a via a selectable interruption section 14 that is in a conductive state.

[0031] One end of the second differential transistor section 50b in the input circuit 10 is connected to a portion of the second current path section 30b between the transistor 31b and the transistor 32b. More specifically, the drain terminals 52d of the plurality of second transistors 52 in the input circuit 10 are connected to a portion of the second current path section 30b between the transistor 31b and the transistor 32b. The drain terminals 52d of the plurality of second transistors 52 are connected to the drain terminal of the transistor 31b in the current source circuit section 31 and the source terminal of the transistor 32b in the first auxiliary circuit section 32. In the first embodiment, the drain terminal 52d of one second transistor 52 is connected to the second current path section 30b via the selectable interruption section 14, which is in an interrupted state. Therefore, the drain terminal 52d of the one second transistor 52 and the second current path section 30b are interrupted by the selectable interruption section 14.

[0032] In the circuits disclosed herein, "another element is disposed between a certain element and another element" means that the other element is disposed on the circuit between the certain element and the other element, tracing from one to the other.

[0033] The second amplifier circuit unit 40 is connected to the first amplifier circuit unit 30. The second amplifier circuit unit 40 outputs an output voltage VOUT as an output value. The second amplifier circuit unit 40 has a current source 43, a third transistor 41, a fourth transistor 42, a second current mirror circuit unit 44, and an output terminal 45.

[0034] The current source 43 is configured to supply a constant current. In the first embodiment, the current source 43 is configured by one transistor 43a. The current source 43 is not particularly limited as long as it is configured to supply a constant current, and may include, for example, a plurality of transistors. In the first embodiment, the transistor 43a is a field-effect transistor. More specifically, the transistor 43a is a P-channel MOSFET. A source terminal 43s of the transistor 43a is connected to the power supply voltage wiring 60. A predetermined voltage V8 is applied to a gate terminal 43g of the transistor 43a. This turns the transistor 43a on and functions as the current source 43 supplying a constant current. The predetermined voltages V3, V4, V5, V6, and V8 are not particularly limited and may be voltages of the same magnitude or different magnitudes.

[0035] The third transistor 41 and the fourth transistor 42 are arranged in parallel with each other between the current source 43 and the second current mirror circuit section 44. The third transistor 41 and the fourth transistor 42 form a differential pair. In the first embodiment, the third transistor 41 and the fourth transistor 42 are field-effect transistors. More specifically, the third transistor 41 and the fourth transistor 42 are P-channel MOSFETs. A source terminal 41s of the third transistor 41 and a source terminal 42s of the fourth transistor 42 are connected to each other. The source terminal 41s of the third transistor 41 and the source terminal 42s of the fourth transistor 42 are connected to a drain terminal 43d of the transistor 43a of the current source 43.

[0036] The gate terminal 41g of the third transistor 41 is connected to the first current path portion 30a. More specifically, the gate terminal 41g of the third transistor 41 is connected to a portion of the first current path portion 30a between the transistor 32a of the first auxiliary circuit portion 32 and the transistor 34a of the second auxiliary circuit portion 34. The gate terminal 41g of the third transistor 41 is connected to the drain terminal of the transistor 32a and the drain terminal of the transistor 34a.

[0037] The gate terminal 42g of the fourth transistor 42 is connected to the second current path portion 30b. More specifically, the gate terminal 42g of the fourth transistor 42 is connected to a portion of the second current path portion 30b between the transistor 32b of the first auxiliary circuit portion 32 and the transistor 34b of the second auxiliary circuit portion 34. The gate terminal 42g of the fourth transistor 42 is connected to the drain terminal of the transistor 32b and the drain terminal of the transistor 34b.

[0038] In the first embodiment, the second current mirror circuit unit 44 is configured by a pair of transistors 44a and 44b. In the first embodiment, the pair of transistors 44a and 44b are field-effect transistors. More specifically, the pair of transistors 44a and 44b are N-channel MOSFETs. The drain terminal of the transistor 44a is connected to the drain terminal 41d of the third transistor 41. The source terminal of the transistor 44a is connected to ground GND. The drain terminal of the transistor 44b is connected to the drain terminal 42d of the fourth transistor 42. The source terminal of the transistor 44b is connected to ground GND. The gate terminals of the pair of transistors 44a and 44b are connected to each other. The gate terminals of the pair of transistors 44a and 44b are connected to the drain terminal of the transistor 44a and the drain terminal 41d of the third transistor 41. The second current mirror circuit section 44 is a circuit that attempts to pass a current of the same magnitude through a transistor 44a connected in series with the third transistor 41 to a transistor 44b connected in series with the fourth transistor 42.

[0039] The output terminal 45 is a terminal from which the output voltage VOUT is output as an output value. The output terminal 45 is connected to the drain terminal 42d of the fourth transistor 42 and the drain terminal of the transistor 44b in the second current mirror circuit portion 44.

[0040] Next, the operation of the semiconductor device 100 will be described. Fig. 2 is a circuit diagram showing an example of the operation of the semiconductor device 100. Fig. 3 is a circuit diagram showing another example of the operation of the semiconductor device 100. Fig. 2 shows a case where the first voltage V1 is higher than the second voltage V2. Fig. 3 shows a case where the first voltage V1 is lower than the second voltage V2.

[0041] 2 and 3, when a first voltage V1 is applied to the gate terminal 51g of each first transistor 51 and a second voltage V2 is applied to the gate terminal 52g of each second transistor 52, each transistor is turned on, allowing current to flow. Each first transistor 51 and each second transistor 52 is normally driven in a non-saturation region. When each first transistor 51 and each second transistor 52 is turned on, a portion of the current output from the current source circuit section 31 flows through each of the first differential transistor section 50a and the second differential transistor section 50b.

[0042] A current Ia1, which is a portion of the current Ia flowing through the transistor 31a of the current source circuit unit 31, flows to the first differential transistor unit 50a. In the first embodiment, the selectable interruption unit 14 connected in series to one first transistor 51 is in a conducting state, so the current Ia1 flowing through the first differential transistor unit 50a branches and flows to the two first transistors 51. A current Ib1, which is a portion of the current Ib flowing through the transistor 31b of the current source circuit unit 31, flows to the second differential transistor unit 50b. In the first embodiment, the selectable interruption unit 14 connected in series to one second transistor 52 is in a cutoff state, so the current Ib1 flowing through the second differential transistor unit 50b flows to one second transistor 52. The current Ia1 flowing to the first differential transistor unit 50a and the current Ib1 flowing to the second differential transistor unit 50b join together and flow from the current source 13 to ground GND. The sum of the magnitude of the current Ia1 and the magnitude of the current Ib1 is equal to the magnitude of the current flowed by the current source 13.

[0043] Since the current source circuit section 31 is a circuit that makes the magnitude of the currents flowing through the pair of transistors 31a and 31b equal to each other, the magnitude of the current Ia flowing through transistor 31a and the magnitude of the current Ib flowing through transistor 31b are equal to each other.

[0044] In the first embodiment, the first transistor 51 and the second transistor 52 are N-channel field-effect transistors. Therefore, in the non-saturation region (linear region), the larger the voltage applied to the gate terminal, the larger the current that flows. Therefore, as shown in FIG. 2, when the first voltage V1 is higher than the second voltage V2, the magnitude of the current Ia1 flowing to the first differential transistor unit 50a is larger than the current Ib1 flowing to the second differential transistor unit 50b. In this case, the magnitude of the current Ia2 remaining after the current Ia1 branches in the first current path unit 30a is smaller than the magnitude of the current Ib2 remaining after the current Ib1 branches in the second current path unit 30b. The current Ia2 flows through the first current path unit 30a toward ground GND and attempts to flow to the transistor 33a of the first current mirror circuit unit 33. The current Ib2 flows through the second current path unit 30b toward ground GND and attempts to flow to the transistor 33b of the first current mirror circuit unit 33.

[0045] Here, the first current mirror circuit unit 33 attempts to make the magnitude of the current flowing through transistor 33b equal to the magnitude of the current flowing through transistor 33a. Therefore, even if the current Ib2 flowing through the second current path unit 30b attempts to flow through transistor 33b, it can only flow up to the magnitude of the current flowing through transistor 33a in the first current path unit 30a. As a result, the voltage in the portion of the second current path unit 30b upstream of transistor 33b of the first current mirror circuit unit 33 becomes higher than the voltage in the portion of the first current path unit 30a upstream of transistor 33a of the first current mirror circuit unit 33. As a result, the voltage Vb applied to the gate terminal 42g of the fourth transistor 42 becomes higher than the voltage Va applied to the gate terminal 41g of the third transistor 41. As a result, the voltage Va becomes relatively lower than the voltage Vb.

[0046] On the other hand, as shown in FIG. 3, when the first voltage V1 is lower than the second voltage V2, the magnitude of the current Ia1 flowing to the first differential transistor section 50a is smaller than the current Ib1 flowing to the second differential transistor section 50b. In this case, the magnitude of the current Ia2 remaining after the current Ia1 branches in the first current path section 30a is larger than the magnitude of the current Ib2 remaining after the current Ib1 branches in the second current path section 30b. In this case, the current that can flow through the transistor 33a of the first current mirror circuit section 33 is larger, but because the current Ib2 flowing through the second current path section 30b is smaller than the current Ia2, the transistor 33b cannot pass as much current as it can through the transistor 33a. As a result, the voltage Vb is lower than the voltage Va.

[0047] The higher of voltages Va and Vb becomes the power supply voltage VDD when the difference between the first voltage V1 and the second voltage V2 is sufficiently large. When the difference between the first voltage V1 and the second voltage V2 is small, the higher of voltages Va and Vb may not rise to the power supply voltage VDD and may become lower than the power supply voltage VDD. Even in this case, the difference between voltages Va and Vb is greater than the difference between the first voltage V1 and the second voltage V2. This is because the drain current flowing through a MOSFET is proportional to the square of the gate voltage, and therefore the difference between the current Ia2 flowing through the first current path portion 30a and the current Ib2 flowing through the second current path portion 30b is greater than the difference between the first voltage V1 and the second voltage V2. Furthermore, the first transistor 51 and the second transistor 52 have a larger ratio W / L of their channel width W to their channel length L than the other transistors included in the semiconductor device 100, and therefore output a larger drain current for an applied gate voltage than the other transistors. Therefore, the difference between the current Ia2 flowing through the first current path portion 30a and the current Ib2 flowing through the second current path portion 30b can be more suitably increased, and the difference between the voltages Va and Vb can be more suitably increased.

[0048] In the first embodiment, the third transistor 41 and the fourth transistor 42 are P-channel field-effect transistors, and therefore, the lower the voltage applied to the gate terminals 41g and 42g, the more easily current flows through the third transistor 41 and the fourth transistor 42. Therefore, as shown in FIG. 2, when the voltage Va is lower than the voltage Vb, the current Ica flowing through the third transistor 41 is larger than the current Icb flowing through the fourth transistor 42. On the other hand, as shown in FIG. 3, when the voltage Vb is lower than the voltage Va, the current Icb flowing through the fourth transistor 42 is larger than the current Ica flowing through the third transistor 41. The currents Ica and Icb are currents branched from the current Ic flowing from the current source 43. The sum of the magnitude of the current Ica and the magnitude of the current Icb is equal to the magnitude of the current Ic.

[0049] As shown in FIG. 2, when the current Ica is greater than the current Icb, the current that can flow through the transistor 44b of the second current mirror circuit 44 increases in accordance with the current flowing through the transistor 44a of the second current mirror circuit 44. However, the current Icb flowing from the fourth transistor 42 to the transistor 44b is smaller than the current that can flow through the transistor 44b. Therefore, the voltage upstream of the transistor 44b, i.e., the voltage at the drain terminal of the transistor 44b, becomes lower than the voltage at the drain terminal of the transistor 44a. When the current Ica flows through the third transistor 41, the voltage at the source terminal 41s of the third transistor 41 decreases, and the voltage at the source terminal 42s of the fourth transistor 42 connected to the source terminal 41s also decreases. Because the voltage Vb applied to the gate terminal 42g of the fourth transistor 42 is higher than the voltage Va applied to the gate terminal 41g of the third transistor 41, the fourth transistor 42 approaches an OFF state as the voltage at the source terminal 42s decreases. When the fourth transistor 42 is turned off in this way, the output terminal 45 is shorted to the ground GND, and the output voltage OUT of the output terminal 45 becomes the voltage of the ground GND, that is, 0V.

[0050] 3, when the current Icb is greater than the current Ica, only a portion of the current Icb can flow through the transistor 44b of the second current mirror circuit 44, causing the voltage between the fourth transistor 42 and the transistor 44b, i.e., the output voltage VOUT, to rise. Because the difference between the voltages Va and Vb applied to the third transistor 41 and the fourth transistor 42 of the second amplifier circuit 40 is greater than the difference between the first voltage V1 and the second voltage V2, the difference between the current Ica and the current Icb is sufficiently large. As a result, the portion of the current Icb that cannot flow through the transistor 44b can be used to effectively raise the output voltage VOUT to the power supply voltage VDD.

[0051] As described above, in the first embodiment, when the first voltage V1 is higher than the second voltage V2, 0 V is output as the output voltage VOUT, and when the first voltage V1 is lower than the second voltage V2, the power supply voltage VDD is output as the output voltage VOUT. FIG. 4 is a graph showing the relationship between the input voltage VIN and the output voltage VOUT. The upper graph in FIG. 4 is a graph showing the first voltage V1 and the second voltage V2, which are the input voltage VIN. The lower graph in FIG. 4 is a graph showing the output voltage VOUT. FIG. 4 shows a case where the second voltage V2 is a constant voltage value and the first voltage V1 is changed linearly with time t from a voltage value higher than the second voltage V2 to a voltage value lower than the second voltage V2.

[0052] In the lower graph of FIG. 4, the dashed-dotted line indicates the ideal change in the output voltage VOUT. In the lower graph of FIG. 4, the dashed line indicates the change in the conventional output voltage VOUT. In the lower graph of FIG. 4, the solid line indicates an example of the change in the output voltage VOUT in the first embodiment. As shown by the dashed-dotted line in FIG. 4, ideally, the output voltage VOUT should switch between 0 V and the power supply voltage VDD when the first voltage V1 and the second voltage V2 are the same value. However, in reality, as shown by the dashed line in FIG. 4, due to variations in the impedance of each element, the point at which the output voltage VOUT switches is shifted by the input offset voltage VOF from the point at which the first voltage V1 and the second voltage V2 are the same value. In this case, the output voltage VOUT may not be switched properly in a region where the difference between the first voltage V1 and the second voltage V2 is small.

[0053] In the semiconductor device 100 according to the first embodiment, the input offset voltage VOF described above occurs when there is a difference between the current Ia2 flowing through the first current mirror circuit portion 33 in the first current path portion 30a and the current Ib2 flowing through the first current mirror circuit portion 33 in the second current path portion 30b, even when the first voltage V1 and the second voltage V2 have the same voltage value. To address this issue, for example, a current source may be provided separately to increase or decrease the currents Ia and Ib flowing from the pair of transistors 31a and 31b of the current source circuit portion 31, respectively, to adjust the amounts of the currents. In this case, the separately provided current source can bring the magnitude of the current Ia2 in the first current path portion 30a and the magnitude of the current Ib2 in the second current path portion 30b closer together, thereby reducing the input offset voltage VOF. However, in this case, the total amount of current flowing in the first amplifier circuit section 30 changes, and the time required to charge the gate terminals 41g, 42g of the third transistor 41 and the fourth transistor 42 in the second amplifier circuit section 40 changes. This changes the response time of the change in the output voltage VOUT to the change in the first voltage V1 and the second voltage V2, which causes a problem of changing the responsiveness of the semiconductor device 100.

[0054] Alternatively, for example, without providing a new current source, it is possible to connect at least one of the pair of transistors 33a, 33b in the first current mirror circuit unit 33 of the first amplifier circuit unit 30 in parallel to adjust the magnitude of the current Ia2 in the first current path unit 30a and the magnitude of the current Ib2 in the second current path unit 30b. However, in this case, the parasitic capacitance of the transistors provided in the first current mirror circuit unit 33 increases, changing the time it takes for the gates of the transistors in the first current mirror circuit unit 33 to be charged. This changes the time it takes for the voltages Va and Vb output to the third transistor 41 and the fourth transistor 42 to change, which causes a problem of changing the responsiveness of the semiconductor device 100.

[0055] To address the above problem, according to a first embodiment, an input circuit 10 is connected to an output circuit 20 that outputs an output voltage VOUT (output value) based on a first voltage V1 and a second voltage V2. The input circuit 10 is an input circuit to which the first voltage V1 and the second voltage V2 are applied, and includes a first differential transistor section 50a having a plurality of first transistors 51 connected in parallel, a second differential transistor section 50b having a plurality of second transistors 52 connected in parallel, and a cutoff selectable section 14 that can select a current cutoff state. The output circuit 20 includes a first current path section 30a and a second current path section 30b that are arranged in parallel between a power supply voltage wiring 60 to which a power supply voltage VDD is applied and ground GND. The first differential transistor section 50a and the second differential transistor section 50b are arranged in parallel between the power supply voltage wiring 60 and ground GND. A first voltage V1 is applied to gate terminals 51g (drive terminals) of the plurality of first transistors 51. A second voltage V2 is applied to gate terminals 52g (drive terminals) of the plurality of second transistors 52. Drain terminals 51d (first terminals) of the plurality of first transistors 51 are connected to the first current path portion 30a. Drain terminals 52d (first terminals) of the plurality of second transistors 52 are connected to the second current path portion 30b. Source terminals 51s (second terminals) of the plurality of first transistors 51 and source terminals 52s (second terminals) of the plurality of second transistors 52 are connected to each other. A selectable cutoff unit 14 is connected in series to at least one of the plurality of first transistors 51 and the plurality of second transistors 52. The selectable cutoff unit 14 selects either a conducting state in which current is allowed to flow or a cutoff state in which current is cut off. Therefore, by selecting either the conductive state or the cut-off state as the state of the cut-off selectable section 14, it is possible to adjust at least one of the ease of current flow in the first differential transistor section 50a and the ease of current flow in the second differential transistor section 50b.

[0056] Specifically, for example, when both of the above-described two selectable interruption units 14 are in a conducting state, and the first voltage V1 and the second voltage V2 are set to the same voltage value, the total current flowing through the second differential transistor unit 50b is greater than the total current flowing through the first differential transistor unit 50a. In this case, even if the first voltage V1 and the second voltage V2 are the same voltage value, a difference occurs between the current Ia2 flowing through the first current path unit 30a and the current Ib2 flowing through the second current path unit 30b, resulting in an input offset voltage VOF. In this case, when a selectable interruption unit 14 connected in series to one second transistor 52 is cut off, no current flows through that one second transistor 52, and the total current flowing through the second differential transistor unit 50b decreases compared to when the selectable interruption unit 14 is in a conducting state. This allows the total current flowing through the second differential transistor unit 50b to approach the total current flowing through the first differential transistor unit 50a. Therefore, the input offset voltage VOF can be reduced. Therefore, even if the difference between the first voltage V1 and the second voltage V2 is small, the semiconductor device 100 can be made to operate normally.

[0057] Furthermore, since the input offset voltage VOF can be reduced by adjusting the ease with which a current flows in the first differential transistor section 50a and the ease with which a current flows in the second differential transistor section 50b, it is possible to suppress changes in the total amount of current flowing in the first amplifier circuit section 30. Furthermore, there is no change in the parasitic capacitance in the first amplifier circuit section 30. Therefore, it is possible to suppress changes in the responsiveness of the semiconductor device 100. As described above, according to the first embodiment, it is possible to reduce the input offset voltage VOF while suppressing changes in the responsiveness of the semiconductor device 100.

[0058] 4, the output voltage VOUT in the first embodiment is in a state where a slight input offset voltage VOF remains, but this is not limited to this. The input offset voltage VOF may be completely trimmed by selecting the state of the cutoff selectable unit 14.

[0059] The ratio W / L of the channel width W to the channel length L of the first transistor 51 connected to the selectable interruption unit 14 and the ratio W / L of the channel width W to the channel length L of the second transistor 52 connected to the selectable interruption unit 14 are determined based on, for example, the average value of the input offset voltage VOF that occurs when the selectable interruption unit 14 is not provided. For example, the ratio W / L of each transistor connected to the selectable interruption unit 14 is determined so that the input offset voltage VOF can be reduced to a predetermined range or below by changing the state of the selectable interruption unit 14 connected to at least one transistor. The predetermined range is not particularly limited.

[0060] According to the first embodiment, the selectable cutoff section 14 is connected in series to at least one first transistor 51. The selectable cutoff section 14 is connected in series to at least one second transistor 52. Therefore, in both the first differential transistor section 50a and the second differential transistor section 50b, the ease of current flow can be adjusted by selecting the state of the selectable cutoff section 14. This makes it easier to make the amount of current flowing through the first differential transistor section 50a and the amount of current flowing through the second differential transistor section 50b suitably close to each other. This allows the input offset voltage VOF to be further reduced.

[0061] According to the first embodiment, the selectable interruption unit 14 is a fuse. Therefore, the selectable interruption unit 14 can be provided inexpensively. Furthermore, when changing the state of the selectable interruption unit 14 from a conducting state to a cut-off state, the fuse can be blown, making it easy to select the state of the selectable interruption unit 14.

[0062] According to the first embodiment, the output circuit 20 includes a first amplifier circuit unit 30 having a first current path portion 30a and a second current path portion 30b, and a second amplifier circuit unit 40 connected to the first amplifier circuit unit 30 and outputting an output voltage VOUT (output value). Therefore, the two amplifier circuit units can appropriately increase the difference between the first voltage V1 and the second voltage V2 and output the resulting output voltage VOUT. Furthermore, the first amplifier circuit unit 30 can increase the current generated based on the difference between the first voltage V1 and the second voltage V2 input to the input circuit 10. That is, the current gain for the input of the first voltage V1 and the second voltage V2 can be increased. This shortens the time it takes for the gate terminals 41g and 42g of the third transistor 41 and the fourth transistor 42, which are operated to generate the output voltage VOUT, to be charged. This improves the switching speed of the output voltage VOUT when the first voltage V1 and the second voltage V2 change. Consequently, the responsiveness of the semiconductor device 100 can be improved.

[0063] As described above, in the first embodiment, the selectively cutoff unit 14 reduces the input offset voltage VOF while suppressing a decrease in the responsiveness of the semiconductor device 100. Therefore, the input offset voltage VOF can be reduced while suppressing changes in the responsiveness of the semiconductor device 100, which was improved by providing two amplifier circuits, the first amplifier circuit 30 and the second amplifier circuit 40. Furthermore, since the difference between the input voltages V IN can be suitably amplified by the two amplifier circuits while reducing the input offset voltage VOF, the semiconductor device 100 can operate normally even if the difference between the input voltages V IN is small. Therefore, according to the first embodiment, the selectively cutoff unit 14 capable of trimming the input offset voltage VOF is provided in the input circuit 10, and the output circuit 20 is configured to have two amplifier circuits, thereby achieving a semiconductor device 100 with high response speed and high sensitivity.

[0064] (Second embodiment) The second embodiment differs from the first embodiment in the configuration of the input circuit 210. In the following description, the same components as those in the above-described embodiments may be denoted by the same reference numerals as appropriate, and the description thereof may be omitted.

[0065] FIG. 5 is a circuit diagram showing a semiconductor device 200 according to a second embodiment. As shown in FIG. 5, in an input circuit 210, a current source 213 is configured with a transistor 213a, which is a P-channel MOSFET. A source terminal 213s of the transistor 213a is connected to a power supply voltage line 60. A predetermined voltage V7 is applied to a gate terminal 213g of the transistor 213a. The current source 213 is configured to supply a constant current based on the predetermined voltage V7. The predetermined voltage V7 may be a voltage having the same magnitude as the above-described predetermined voltages V3, V4, V5, V6, and V8, or may be a voltage having a magnitude different from the predetermined voltages V3, V4, V5, V6, and V8.

[0066] One end of the first differential transistor section 250a and one end of the second differential transistor section 250b are connected to the drain terminal 213d of the transistor 213a of the current source 213. The other end of the first differential transistor section 250a is connected to a portion of the first current path section 30a between the transistor 33a of the first current mirror circuit section 33 and the transistor 34a of the second auxiliary circuit section 34. The other end of the second differential transistor section 250b is connected to a portion of the second current path section 30b between the transistor 33b of the first current mirror circuit section 33 and the transistor 34b of the second auxiliary circuit section 34.

[0067] In the second embodiment, the plurality of first transistors 251 in the first differential transistor section 250a and the plurality of second transistors 252 in the second differential transistor section 250b are P-channel MOSFETs. A first voltage V1 is applied to gate terminals 251g of the plurality of first transistors 251. A second voltage V2 is applied to gate terminals 252g of the plurality of second transistors 252. Source terminals 251s of the plurality of first transistors 251 and source terminals 252s of the plurality of second transistors 252 are connected to each other. The source terminals 251s of the plurality of first transistors 251 and source terminals 252s of the plurality of second transistors 252 are connected to the drain terminal 213d of the transistor 213a of the current source 213. As in the first embodiment, a selectable cutoff unit 14 is connected in series to each of the first transistors 251 and the second transistor 252.

[0068] The drain terminals 251d of the multiple first transistors 251 are connected to the first current path portion 30a. More specifically, the drain terminals 251d of the multiple first transistors 251 are connected to a portion of the first current path portion 30a between the transistor 33a of the first current mirror circuit portion 33 and the transistor 34a of the second auxiliary circuit portion 34. The drain terminal 251d of one first transistor 251 is connected to the first current path portion 30a via the selectable interruption portion 14 that is in a conductive state.

[0069] The drain terminals 252d of the multiple second transistors 252 are connected to the second current path portion 30b. More specifically, the drain terminals 252d of the multiple second transistors 252 are connected to a portion of the second current path portion 30b between the transistor 33b of the first current mirror circuit portion 33 and the transistor 34b of the second auxiliary circuit portion 34. The drain terminal 252d of one second transistor 252 is connected to the second current path portion 30b via the selectable interruption portion 14 that is in the cut-off state. Therefore, the drain terminal 252d of that one second transistor 252 and the second current path portion 30b are cut off by the selectable interruption portion 14.

[0070] In the second embodiment, the drain terminal 251d of the first transistor 251 and the drain terminal 252d of the second transistor 252 correspond to the "first terminal." The source terminal 251s of the first transistor 251 and the source terminal 252s of the second transistor 252 correspond to the "second terminal."

[0071] In the second embodiment, the current output from the current source 213 is divided and flows into the first differential transistor section 250a and the second differential transistor section 250b based on the difference between the first voltage V1 and the second voltage V2. The current flowing through the first differential transistor section 250a flows into the first current path section 30a and merges with the current output from the current source circuit section 31 to the first current path section 30a. The current flowing through the second differential transistor section 250b flows into the second current path section 30b and merges with the current output from the current source circuit section 31 to the second current path section 30b. In the second embodiment as well, the voltages Va and Vb applied to the second amplifier circuit section 40 change depending on the difference between the current flowing to the first current mirror circuit section 33 in the first current path section 30a and the current flowing to the first current mirror circuit section 33 in the second current path section 30b. This changes the output voltage VOUT.

[0072] Other configurations of the input circuit 210 are similar to other configurations of the input circuit 10 in the first embodiment. Other configurations of the semiconductor device 200 are similar to other configurations of the semiconductor device 100 in the first embodiment.

[0073] According to the second embodiment, similarly to the first embodiment described above, the input offset voltage VOF can be reduced by providing the selectable cutoff unit 14 in the input circuit 210. Furthermore, even if the selectable cutoff unit 14 is provided, the total amount of current flowing in the first amplifier circuit unit 30 does not change, and the parasitic capacitance in the first amplifier circuit unit 30 does not change, so it is possible to suppress changes in the responsiveness of the semiconductor device 200. Therefore, also in the second embodiment, it is possible to reduce the input offset voltage VOF while suppressing changes in the responsiveness of the semiconductor device 200.

[0074] (Third embodiment) The third embodiment differs from the first embodiment in the configuration of the output circuit 320. In the following description, the same components as those in the above-described embodiments may be denoted by the same reference numerals as appropriate, and the description thereof may be omitted.

[0075] FIG. 6 is a circuit diagram showing a semiconductor device 300 according to a third embodiment. As shown in FIG. 6, in an output circuit 320 according to the third embodiment, a first amplifier circuit section 330 includes a diode 370. The anode of the diode 370 is connected to a portion of the second current path section 30b to which the gate terminal 42g of the fourth transistor 42 is connected. The anode of the diode 370 is connected to the drain terminal of the transistor 32b of the first auxiliary circuit section 32 and the drain terminal of the transistor 34b of the second auxiliary circuit section 34. The cathode of the diode 370 is connected to a portion of the first current path section 30a to which the gate terminal 41g of the third transistor 41 is connected. The cathode of the diode 370 is connected to the drain terminal of the transistor 32a of the first auxiliary circuit section 32, the drain terminal of the transistor 34a of the second auxiliary circuit section 34, and the gate terminals of the transistors 33a and 33b of the first current mirror circuit section 33.

[0076] Other configurations of the output circuit 320 are similar to other configurations of the output circuit 20 in the first embodiment. Other configurations of the semiconductor device 300 are similar to other configurations of the semiconductor device 100 in the first embodiment.

[0077] According to the third embodiment, the first amplifier circuit section 330 includes a diode 370. The anode of the diode 370 is connected to a portion of the second current path section 30b to which the gate terminal 42g (drive terminal) of the fourth transistor 42 is connected. The cathode of the diode 370 is connected to a portion of the first current path section 30a to which the gate terminal 41g (drive terminal) of the third transistor 41 is connected. Therefore, when the voltage Vb applied to the gate terminal 42g of the fourth transistor 42 becomes higher than the voltage Va applied to the gate terminal 41g of the third transistor 41, the difference between the voltages Va and Vb can be made the same magnitude as the forward voltage of the diode 370. As a result, for example, when the voltage Vb is switched from a state in which it is higher than the voltage Va to a state in which it is lower than the voltage Va, the amount of charge released until the voltage Vb becomes lower than the voltage Va can be reduced. Therefore, the time until the voltage Vb becomes lower than the voltage Va can be shortened compared to when the voltage Vb becomes the power supply voltage VDD. Therefore, the response of the semiconductor device 300 can be further improved.

[0078] Alternatively, the anode of the diode 370 may be connected to a portion of the first current path portion 30a to which the gate terminal 41g of the third transistor 41 is connected, and the cathode of the diode 370 may be connected to a portion of the second current path portion 30b to which the gate terminal 42g of the fourth transistor 42 is connected. In this case, when the voltage Va applied to the gate terminal 41g of the third transistor 41 is higher than the voltage Vb applied to the gate terminal 42g of the fourth transistor 42, the difference between the voltages Va and Vb can be made the same magnitude as the forward voltage of the diode 370. This increases the speed at which charge is released from the gate terminal 41g of the third transistor 41 when the voltage Va is switched from a state in which it is higher than the voltage Vb to a state in which it is lower than the voltage Vb, thereby improving the responsiveness of the semiconductor device 300.

[0079] (Fourth embodiment) The fourth embodiment differs from the first embodiment in the configuration of the input circuit 410. In the following description, the same components as those in the above-described embodiments may be denoted by the same reference numerals as appropriate, and the description thereof may be omitted.

[0080] FIG. 7 is a circuit diagram showing a semiconductor device 400 of the fourth embodiment. As shown in FIG. 7, in an input circuit 410 of the fourth embodiment, a first differential transistor section 450a has three first transistors 51. A second differential transistor section 450b has three second transistors 52. Two of the three first transistors 51 are connected in series to selectable interruption sections 14, respectively. Two of the three second transistors 52 are connected in series to selectable interruption sections 14, respectively. In the example of FIG. 7, both selectable interruption sections 14 provided for the two first transistors 51 are in a conducting state, and one of the selectable interruption sections 14 provided for the two second transistors 52 is in a conducting state and the other is in a cut-off state.

[0081] Other configurations of the input circuit 410 are similar to other configurations of the input circuit 10 in the first embodiment. Other configurations of the semiconductor device 400 are similar to other configurations of the semiconductor device 100 in the first embodiment.

[0082] According to the fourth embodiment, the selectable cutoff sections 14 are connected in series to two or more first transistors 51, and the selectable cutoff sections 14 are connected in series to two or more second transistors 52. This makes it possible to select the state of multiple selectable cutoff sections 14 in each of the first differential transistor section 450a and the second differential transistor section 450b, and more finely adjust the ease of current flow in the first differential transistor section 450a and the second differential transistor section 450b. This makes it easier to more effectively reduce the input offset voltage VOF.

[0083] (Fifth embodiment) The fifth embodiment differs from the first embodiment in the configuration of the input circuit 510. In the following description, the same components as those in the above-described embodiments may be denoted by the same reference numerals as appropriate, and the description thereof may be omitted.

[0084] 8 is a circuit diagram showing a semiconductor device 500 according to a fifth embodiment. As shown in FIG. 8, in the fifth embodiment, the selectable cutoff unit 514 is a transistor. More specifically, the selectable cutoff unit 514 is an N-channel MOSFET. The selectable cutoff unit 514 is connected in series with, for example, one first transistor 51 and one second transistor 52.

[0085] The input circuit 510 includes a control unit 515. The control unit 515 is connected to a gate terminal of the selectable cutoff unit 514. The control unit 515 applies a voltage to the gate terminal of the selectable cutoff unit 514 to switch the state of the selectable cutoff unit 514. When the selectable cutoff unit 514, which is a transistor, is in an ON state, the selectable cutoff unit 514 is in a conductive state. When the selectable cutoff unit 514, which is a transistor, is in an OFF state, the selectable cutoff unit 514 is in a cutoff state. The control unit 515 pre-stores information for determining whether the state of each selectable cutoff unit 514 should be a conductive state or a cutoff state. Based on the stored information, the control unit 515 sets the state of each selectable cutoff unit 514 to either the conductive state or the cutoff state. Note that the information regarding the state of the selectable cutoff unit 514 stored in the control unit 515 may be updated as appropriate, for example, in response to deterioration of the semiconductor device 500.

[0086] Other configurations of the input circuit 510 are similar to other configurations of the input circuit 10 in the first embodiment. Other configurations of the semiconductor device 500 are similar to other configurations of the semiconductor device 100 in the first embodiment.

[0087] According to the fifth embodiment, the selectable cutoff unit 514 is a transistor. Therefore, by changing the voltage applied to the selectable cutoff unit 514, the state of the selectable cutoff unit 514 can be switched between a conductive state and a cutoff state. As a result, even if, for example, the first transistor 51 and the second transistor 52 deteriorate and their characteristics with respect to the input voltage VIN change, causing the input offset voltage VOF to increase, the state of the selectable cutoff unit 514 can be switched to reduce the input offset voltage VOF.

[0088] According to at least one of the above-described embodiments, the input circuit is connected to an output circuit that outputs an output value based on a first voltage and a second voltage, and to which the first voltage and the second voltage are applied. The input circuit has a first differential transistor section having a plurality of first transistors connected in parallel, a second differential transistor section having a plurality of second transistors connected in parallel, and a cutoff selectable section that can select a current cutoff state. The output circuit has a first current path section and a second current path section that are arranged in parallel between a power supply voltage wiring to which a power supply voltage is applied and ground. The first differential transistor section and the second differential transistor section are arranged in parallel between the power supply voltage wiring and ground. A first voltage is applied to drive terminals of the plurality of first transistors, a second voltage is applied to drive terminals of the plurality of second transistors, and first terminals of the plurality of first transistors are connected to the first current path section. First terminals of the plurality of second transistors are connected to the second current path section, and second terminals of the plurality of first transistors and second terminals of the plurality of second transistors are connected to each other. A selectable cutoff unit is connected in series to at least one of the plurality of first transistors and the plurality of second transistors. The selectable cutoff unit is selected to be in either a state in which a current flows or a state in which a current is cut off. This makes it possible to reduce the input offset voltage while suppressing changes in the responsiveness of the semiconductor device.

[0089] The selectable interruption unit may have any configuration as long as it is a unit that can select either a state in which current is allowed to flow or a state in which current is interrupted. The selectable interruption unit may be a switch whose state can be mechanically switched. When the selectable interruption unit is a transistor, the transistor may be any type of transistor. When multiple selectable interruption units are provided, the multiple selectable interruption units may include selectable interruption units with different structures. The selectable interruption unit may be connected in series to each of all first transistors included in the first differential transistor unit. The selectable interruption unit may be connected in series to each of all second transistors included in the second differential transistor unit. The number of selectable interruption units provided in the first differential transistor unit and the number of selectable interruption units provided in the second differential transistor unit may be different. If a selectable interruption unit is connected in series to one or more first transistors, a selectable interruption unit connected in series to a second transistor may not be provided. If a selectable interruption unit is connected in series to one or more second transistors, a selectable interruption unit connected in series to a first transistor may not be provided.

[0090] The multiple first transistors may include first transistors having different ratios W / L of channel width W to channel length L. In this case, if selectable interruption units are connected to two or more first transistors, respectively, the ease of current flow in the first differential transistor unit can be more precisely adjusted by appropriately selecting which of the first transistors having different ratios W / L to change the state of the selectable interruption unit connected to that transistor. The same applies to a second differential transistor unit having multiple second transistors. The multiple first transistors may include first transistors having a ratio W / L different from that of the second transistors. The multiple second transistors may include second transistors having a ratio W / L different from that of the first transistors.

[0091] Each of the transistors in the above-described embodiments, including the first to fourth transistors, may be any type of transistor. Each of the transistors may be an N-channel field-effect transistor or a P-channel field-effect transistor. At least one of the transistors may be a bipolar transistor.

[0092] The output circuit may be a circuit having one amplifier circuit unit. The output circuit may be a circuit having three or more amplifier circuit units. The semiconductor device including the input circuit and the output circuit is not particularly limited as long as it is a device that outputs an output value based on the first voltage and the second voltage. The semiconductor device may be, for example, an operational amplifier.

[0093] The input circuit and the semiconductor device according to the embodiments include the following additional aspects. (Appendix 1) an input circuit connected to an output circuit that outputs an output value based on a first voltage and a second voltage, and to which the first voltage and the second voltage are applied, a first differential transistor section having a plurality of first transistors connected in parallel with each other; a second differential transistor section having a plurality of second transistors connected in parallel with each other; a cutoff selectable unit that can select a state in which a current is cut off; Equipped with the output circuit has a first current path portion and a second current path portion arranged in parallel with each other between a power supply voltage wiring to which a power supply voltage is applied and ground, the first differential transistor section and the second differential transistor section are arranged in parallel with each other between the power supply voltage wiring and the ground, the first voltage is applied to drive terminals of the plurality of first transistors; the second voltage is applied to drive terminals of the plurality of second transistors; first terminals of the plurality of first transistors are connected to the first current path portion; First terminals of the plurality of second transistors are connected to the second current path portion; second terminals of the plurality of first transistors and second terminals of the plurality of second transistors are connected to each other; the selectively cutoff unit is connected in series to at least one of the plurality of first transistors and the plurality of second transistors; The cutoff selectable portion selects one of a state in which a current is allowed to flow and a state in which a current is cut off. (Appendix 2) the cutoff selectable portion is connected in series with at least one of the first transistors; 2. The input circuit of claim 1, wherein the selectable cutoff portion is connected in series with at least one of the second transistors. (Appendix 3) the cutoff selectable portion is connected in series to two or more of the first transistors; 3. The input circuit according to claim 2, wherein the selectable cutoff portion is connected in series to two or more of the second transistors. (Appendix 4) 4. The input circuit according to claim 1, wherein the selectable cutoff component is a fuse. (Appendix 5) 4. The input circuit according to claim 1, wherein the selectable cutoff portion is a transistor. (Appendix 6) an input circuit according to any one of Supplementary Note 1 to Supplementary Note 5; the output circuit connected to the input circuit; A semiconductor device comprising: (Appendix 7) The output circuit a first amplifier circuit unit having the first current path portion and the second current path portion; a second amplifier circuit unit connected to the first amplifier circuit unit and outputting the output value; 7. The semiconductor device according to claim 6, (Appendix 8) The second amplifier circuit section a third transistor having a drive terminal connected to the first current path portion; a fourth transistor having a drive terminal connected to the second current path portion; and the first amplifier circuit unit has a diode, an anode of the diode is connected to one of a portion of the first current path section to which a drive terminal of the third transistor is connected and a portion of the second current path section to which a drive terminal of the fourth transistor is connected; 8. The semiconductor device according to claim 7, wherein the cathode of the diode is connected to the other of a portion of the first current path portion to which the drive terminal of the third transistor is connected and a portion of the second current path portion to which the drive terminal of the fourth transistor is connected.

[0094] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0095] 10,210,410,510...input circuit, 14,514...selectable cutoff section, 20,320...output circuit, 30,330...first amplifier circuit section, 30a...first current path section, 30b...second current path section, 40...second amplifier circuit section, 41...third transistor, 41g, 42g, 51g, 52g...gate terminal (drive terminal), 42...fourth transistor, 50a, 250a, 450a...first differential transistor section, 50b, 250b, 450b...second differential transistor Transistor section, 51, 251... first transistor, 51d, 52d, 251d, 252d... drain terminal (first terminal), 51s, 52s, 251s, 252s... source terminal (second terminal), 52, 252... second transistor, 60... power supply voltage wiring, 100, 200, 300, 400, 500... semiconductor device, 370... diode, GND... ground, V1... first voltage, V2... second voltage, VDD... power supply voltage, VOUT... output voltage (output value)

Claims

1. an input circuit connected to an output circuit that outputs an output value based on a first voltage and a second voltage, and to which the first voltage and the second voltage are applied, a first differential transistor section having a plurality of first transistors connected in parallel with each other; a second differential transistor section having a plurality of second transistors connected in parallel with each other; a cutoff selectable unit that can select a state in which a current is cut off; Equipped with the output circuit has a first current path portion and a second current path portion arranged in parallel with each other between a power supply voltage wiring to which a power supply voltage is applied and ground, the first differential transistor section and the second differential transistor section are arranged in parallel with each other between the power supply voltage wiring and the ground, the first voltage is applied to drive terminals of the plurality of first transistors; the second voltage is applied to drive terminals of the plurality of second transistors; First terminals of the plurality of first transistors are connected to the first current path portion; First terminals of the plurality of second transistors are connected to the second current path portion; second terminals of the plurality of first transistors and second terminals of the plurality of second transistors are connected to each other; the selectable cutoff unit is connected in series to at least one of the plurality of first transistors and the plurality of second transistors; The cutoff selectable portion selects one of a state in which a current is allowed to flow and a state in which a current is cut off.

2. the cutoff selectable portion is connected in series with at least one of the first transistors; 2. The input circuit of claim 1, wherein the selectable cutoff portion is connected in series with at least one of the second transistors.

3. the selectively cutoff portion is connected in series to two or more of the first transistors; 3. The input circuit according to claim 2, wherein the selectable cutoff portion is connected in series to two or more of the second transistors.

4. 2. The input circuit of claim 1, wherein the selectable interruption section is a fuse.

5. 2. The input circuit of claim 1, wherein the selectable cutoff portion is a transistor.

6. An input circuit according to any one of claims 1 to 5; the output circuit connected to the input circuit; A semiconductor device comprising:

7. The output circuit a first amplifier circuit unit having the first current path portion and the second current path portion; a second amplifier circuit unit connected to the first amplifier circuit unit and outputting the output value; The semiconductor device according to claim 6 , comprising:

8. The second amplifier circuit unit a third transistor having a drive terminal connected to the first current path portion; a fourth transistor having a drive terminal connected to the second current path portion; and the first amplifier circuit unit has a diode, an anode of the diode is connected to one of a portion of the first current path portion to which a drive terminal of the third transistor is connected and a portion of the second current path portion to which a drive terminal of the fourth transistor is connected; 8. The semiconductor device according to claim 7, wherein the cathode of the diode is connected to the other of a portion of the first current path portion to which a drive terminal of the third transistor is connected and a portion of the second current path portion to which a drive terminal of the fourth transistor is connected.

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