Standard cell library and semiconductor device

Abstract

To provide a standard cell library and a semiconductor device capable of suppressing repetition of work in a design process.SOLUTION: A standard cell library according to an embodiment has a first standard cell having a first internal power supply wiring disposed therein and a second standard cell having a second internal power supply wiring disposed therein. When the first standard cell and the second standard cell are disposed adjacent to each other in a second direction, the first internal power supply wiring is separated from the second internal power supply wiring. The first standard cell has a first wiring region where a first external power supply wiring can be disposed and which extends in the second direction, and a first connectable position where the first external power supply wiring and the first internal power supply wiring can be connected. The first standard cell further has a third wiring region where a second external power supply wiring can be disposed, and a third connectable position where the second external power supply wiring and the first internal power supply wiring can be connected.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a standard cell library and a semiconductor device. [Background technology]

[0002] The design of semiconductor integrated circuits has become increasingly automated, high-performance, and highly functional using computers. The layout design of semiconductor integrated circuits, in particular, employs standard cell placement and routing (P&R) techniques. This technique generates circuit layouts by placing standard cells and interconnecting them through a process called P&R. In recent years, the need for faster circuits and lower power consumption has led to the widespread use of multiple power supplies within a single P&R region. However, P&R tools lack the functionality to optimize the location, size, and number of power supply regions. Therefore, to achieve optimal electrical and area performance, repeated adjustments—adjusting the location, size, and shape of each power supply region and then re-running P&R—are required, which requires significant time and effort. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 6,903,389 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the embodiments is to provide a standard cell library and a semiconductor device that can reduce the repetition of work in the design process using design tools (P&R tools, layout design tools, etc.). [Means for solving the problem]

[0005] A standard cell library according to an embodiment includes first and second standard cells having the following characteristics: the first standard cell has a first internal power supply wiring disposed therein, and the second standard cell has a second internal power supply wiring disposed therein; the first standard cell and the second standard cell are configured such that the first internal power supply wiring is separated from the second internal power supply wiring when the first standard cell and the second standard cell are disposed adjacent to each other in a second direction; the first standard cell has a first wiring region extending in the second direction in which a first external power supply wiring can be disposed, and a first connectable position at which the first external power supply wiring and the first internal power supply wiring can be connected; the second standard cell has a second wiring region extending in the second direction in which the first external power supply wiring can be disposed, and a second connectable position at which the first external power supply wiring and the second internal power supply wiring can be connected; the first wiring region and the second wiring region are adjacent to each other and connectable.

[0006] The first standard cell has a third wiring region in which a second external power supply wiring can be arranged and extending in a second direction, and a third connectable position at which the second external power supply wiring and the first internal power supply wiring can be connected. The first standard cell has a fourth wiring region in which a third external power supply wiring can be arranged and extending in the second direction, a third internal power supply wiring, and a fourth connectable position at which the third external power supply wiring and the third internal power supply wiring can be connected. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a configuration diagram of a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a diagram showing the configuration of a standard cell according to the first embodiment. [Figure 3A] FIG. 3A is a cross-sectional configuration diagram of the standard cell according to the first embodiment. [Figure 3B] FIG. 3B is a cross-sectional view of the standard cell according to the first embodiment. [Figure 4] FIG. 4 is a first configuration diagram showing the arrangement of standard cells and power supply wiring according to the first embodiment. [Figure 5A] FIG. 5A is a cross-sectional view of a first configuration in which standard cells and power supply wiring according to the first embodiment are arranged. [Figure 5B] FIG. 5B is a cross-sectional view of a first configuration in which standard cells and power supply wiring according to the first embodiment are arranged. [Figure 6A] FIG. 6A is a second configuration diagram showing the arrangement of standard cells and power supply wiring according to the first embodiment. [Figure 6B] FIG. 6B is a third configuration diagram showing the arrangement of standard cells and power supply wiring according to the first embodiment. [Figure 7] FIG. 7 is a flowchart of the layout design method for the semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a schematic diagram of a layout design system for a semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a block diagram of the layout design system of FIG. [Figure 10] FIG. 10 is a configuration diagram of a semiconductor device according to the second embodiment. [Figure 11] FIG. 11 is a cross-sectional view of a configuration in which standard cells and power supply wiring according to the second embodiment are arranged. [Figure 12] FIG. 12 is a configuration diagram of a semiconductor device according to the third embodiment. [Figure 13A] FIG. 13A is a first configuration diagram showing the arrangement of standard cells and power supply wiring according to the third embodiment. [Figure 13B] FIG. 13B is a second configuration diagram showing the arrangement of standard cells and power supply wiring according to the third embodiment. [Figure 14A] FIG. 14A is a first configuration diagram showing the arrangement of standard cells and power supply wiring according to the fourth embodiment. [Figure 14B] FIG. 14B is a second configuration diagram showing the arrangement of standard cells and power supply wiring according to the fourth embodiment. [Figure 15] FIG. 15 is a first configuration diagram of a semiconductor device according to a comparative example. [Figure 16]FIG. 16 is a configuration diagram of a standard cell according to a comparative example. [Figure 17A] FIG. 17A is a cross-sectional configuration diagram of a standard cell according to a comparative example. [Figure 17B] FIG. 17B is a cross-sectional configuration diagram of a standard cell according to a comparative example. [Figure 18] FIG. 18 is a second configuration diagram of the semiconductor device according to the comparative example. [Figure 19] FIG. 19 is a flow diagram of a layout design method for a semiconductor device according to a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0008] The embodiments will be described with reference to the drawings. In the following description of the drawings, the same or similar parts will be denoted by the same or similar reference numerals, and the description thereof will be omitted. The drawings are schematic.

[0009] Furthermore, the embodiments shown below are merely examples of devices and methods for embodying the technical ideas, and do not specify the materials, shapes, structures, arrangements, etc. of each component part. Various modifications can be made to these embodiments within the scope of the claims.

[0010] [First embodiment] (Configuration of semiconductor device) In the following description, the semiconductor device is designed using a standard cell method. A first direction, which is the direction of the height hu of the standard cell 10, is defined as the Y direction, a second direction perpendicular to the direction of the height hu of the standard cell 10 on the paper surface is defined as the X direction, and a third direction perpendicular to the XY plane is defined as the Z direction.

[0011] 1 is a configuration diagram of a semiconductor device according to a first embodiment. A plurality of standard cells 10 are arranged two-dimensionally in the X and Y directions so that their boundaries contact each other, and wiring is connected between the arranged plurality of standard cells 10 to form a semiconductor device 100 having a larger-scale semiconductor integrated circuit. The semiconductor device 100 includes standard cell rows 20, 21, and 22, main power supply wiring 13a and 13b in the M2 layer, secondary power supply wiring 13c in the M2 layer, power supply wiring 14 in the M3 layer, extra-cell contacts 15a, 15b, and 15c, and a contact 16. The M1, M2, and M3 layers are the first, second, and third metal wiring layers, respectively.

[0012] A plurality of standard cells 10 are arranged in the X direction in standard cell placement rows 20, 21, and 22. Main power supply wiring 13a, 13b and sub-power supply wiring 13c are arranged in the X direction outside the standard cells 10 for each of the standard cell placement rows 20, 21, and 22. Here, "arranged outside the standard cells" means that they are not included in the components of the standard cells. Power supply wiring 14 is arranged in the Y direction. Extra-cell contacts 15a, 15b, and 15c are arranged outside the standard cells 10 and connect either of the intra-cell power supply wiring 12a, 12b in the M1 layer to either of the main power supply wiring 13a, 13b, or sub-power supply wiring 13c in the M2 layer. Contact 16 connects either of the main power supply wiring 13a, 13b, or sub-power supply wiring 13c in the M2 layer to the power supply wiring 14 in the M3 layer.

[0013] A plurality of standard cell placement rows arranged in the Y direction is called a standard cell placement group. In the standard cell placement group, standard cells 10 are arranged two-dimensionally in the X and Y directions.

[0014] Standard cells 10 are logic circuits that perform basic logical operations, and each logical operation is made into a cell to facilitate reuse. Examples of standard cells 10 include inverters, NANDs, NORs, EX-ORs, buffers, and D-type flip-flops.

[0015] Generally, a logic circuit uses a pair of power supplies, one high-potential power supply and one low-potential power supply. The standard cell 10 in Fig. 1 uses the first power supply VDD or a third power supply VDD2 separated from the first power supply VDD as the high-potential power supply of the logic circuit, and the second power supply VSS as the low-potential power supply of the logic circuit.

[0016] The third power supply VDD2 is, for example, a power supply with a lower potential than the first power supply VDD, and is used in logic circuits with ample operating speed to reduce power consumption. In another example, the third power supply VDD2 is a power supply that can cut off the supply to the logic circuits even while the first power supply VDD is being supplied, and is used to reduce standby power consumption by cutting off the supply to the logic circuits when the semiconductor device is in standby mode.

[0017] The main power supply wiring 13a that supplies the first power supply VDD is referred to as the main power supply wiring 13a(VDD), the main power supply wiring 13a that supplies the third power supply VDD2 is referred to as the main power supply wiring 13a(VDD2), and the sub-power supply wiring 13c that supplies the third power supply VDD2 is referred to as the sub-power supply wiring 13c(VDD2).

[0018] The configuration of the standard cell 10 is the same whether the first power supply VDD or the third power supply VDD2 is used, and when the standard cell 10 is placed, it is connected to the power supply used by the standard cell 10 outside the standard cell 10. When the standard cell 10 uses the first power supply VDD as the high-potential power supply, it is written as standard cell 10(VDD), and when it uses the third power supply VDD2, it is written as standard cell 10(VDD2).

[0019] 2 is a configuration diagram of a standard cell 10 according to the first embodiment. A two-input NAND circuit is shown as an example. The standard cell 10 is defined as a rectangular region and has boundary lines 11 surrounding it on all four sides. The dimension in the Y direction is the unit height hu, and the dimension in the X direction differs depending on the type of standard cell.

[0020] The standard cell 10 has internal power supply wiring, referred to as intra-cell power supply wiring. The standard cell 10 includes intra-cell power supply wiring 12a, 12b in the M1 layer, an element isolation boundary 36, gate layers 37a, 37b, contacts 38 connecting the M1 layer to the gate layer or the M1 layer to the diffusion layer, and signal wiring 39 in the M1 layer. Of the area surrounded by the element isolation boundary 36, the area where the gate layers 37a, 37b do not overlap when viewed from the Z direction is a P-type diffusion layer or an N-type diffusion layer. The standard cell 10 further includes a signal line wiring region 42 in the M2 layer, extra-cell wiring regions 43a, 43b, 43c, and 43d in the M2 layer, and power supply access points 45a, 45b, 45c, and 45d.

[0021] The extra-cell wiring regions 43a, 43b, 43c, and 43d of the M2 layer are regions where external power supply wiring or signal line wiring of the M2 layer can be placed outside the standard cells. The external power supply wiring placed in the extra-cell wiring regions 43a and 43b of the M2 layer is referred to as main power supply wiring 13a and 13b, and the external power supply wiring placed in the extra-cell wiring regions 43c and 43d of the M2 layer is referred to as sub-power supply wiring 13c and 13d.

[0022] The power access points 45a, 45b, 45c, and 45d indicate positions where extra-cell contacts 15a, 15b, 15c, and 15d can be placed outside the standard cell 10. The extra-cell contacts 15a, 15b, 15c, and 15d connect one of the intra-cell power wirings 12a and 12b on the M1 layer to one of the main power wirings 13a, 13b, and sub-power wirings 13c and 13d on the M2 layer. In other words, the power access points 45a, 45b, 45c, and 45d are positions where the intra-cell power wirings 12a and 12b on the M1 layer can be connected to the main power wirings 13a, 13b, and sub-power wirings 13c and 13d on the M2 layer. The power access points 45a, 45b, 45c, and 45d do not have physical entities but are represented in the data of the standard cell before placement.

[0023] The intracellular power supply wiring 12a, 12b in the M1 layer is formed by combining a first portion of the intracellular power supply wiring arranged in the Y direction and a second portion of the intracellular power supply wiring arranged in the X direction. The first portion of the intracellular power supply wiring arranged in the Y direction is connected to a P-type diffusion layer of a PMOS or an N-type diffusion layer of an NMOS, and is further connected to either the main power supply wiring 13a, 13b or the sub-power supply wiring 13c, 13d in the M2 layer. The second portion of the intracellular power supply wiring arranged in the X direction is located at a position overlapping the extracellular wiring region 43a or the extracellular wiring region 43b in the M2 layer when viewed from the Z direction. The second portion of the intracellular power supply wiring arranged in the X direction is connected to the main power supply wiring 13a or 13b in the M2 layer, or is not connected to either the main power supply wiring 13a, 13b or the sub-power supply wiring 13c, 13d.

[0024] The intra-cell power supply wiring 12a in the M1 layer can have power supply access points 45a in a portion of a first portion of the intra-cell power supply wiring arranged in the Y direction that overlaps with the extra-cell wiring region 43a in the M2 layer when viewed from the Z direction, and in a second portion of the intra-cell power supply wiring arranged in the X direction. Therefore, the number of power supply access points 45a is greater than the number of first portions of the intra-cell power supply wiring 12a arranged in the Y direction. Similarly, the number of power supply access points 45b is greater than the number of first portions of the intra-cell power supply wiring 12b arranged in the Y direction.

[0025] When the standard cell 10 is arranged, either one of the power supply access points 45a, 45c is exclusively arranged with the corresponding out-of-cell contact 15a or out-of-cell contact 15c. Also, either one of the power supply access points 45b, 45d is exclusively arranged with the corresponding out-of-cell contact 15b or out-of-cell contact 15d. When any one of the out-of-cell contacts 15a, 15b, 15c, 15d is arranged, the power supply access point 45a, 45b, 45c, 45d is replaced by any one of the out-of-cell contacts 15a, 15b, 15c, 15d or a physical entity on which an insulating film is arranged.

[0026] The positions of the extra-cell wiring regions 43a, 43b, 43c, and 43d of the M2 layer in the Y direction are substantially the same for multiple standard cells. Therefore, when the P&R process is performed and multiple standard cells 10 are arranged so that they are in contact with each other at their boundary lines 11 in the X direction, the extra-cell wiring regions 43a, 43b, 43c, and 43d of adjacent standard cells 10 are connected by being in contact with each other at their boundary lines 11. This allows the main power supply wirings 13a and 13b and the secondary power supply wirings 13c and 13d of the M2 layer in the X direction to be arranged outside the standard cells 10 so as to penetrate through substantially fixed positions in the Y direction of the standard cell arrangement row.

[0027] The area sandwiched between the outer wiring areas 43c and 43d of the M2 layer is called the signal line wiring area 42 of the M2 layer, and can be used to arrange the signal lines of the M2 layer in the X direction outside the standard cell 10.

[0028] 3A and 3B are cross-sectional views of the standard cell 10 according to the first embodiment. Fig. 3A shows a cross section taken along line IIIA-IIIA in Fig. 2, and Fig. 3B shows a cross section taken along line IIIB-IIIB in Fig. 2.

[0029] In the cross section taken along IIIA-IIIA in FIG. 3A, the standard cell 10 includes a P-type semiconductor substrate 31, an N-type well 32, an isolation 33, an insulating film 35, gate layers 37a and 37b, an M1-layer internal power supply wiring 12a, and a power supply access point 45a. The power supply access point 45a has no physical entity, but is shown in the cross section for convenience. The standard cell 10 also includes an M2-layer external wiring region 43a on top of the insulating film 35 and the power supply access point 45a.

[0030] In the cross section taken along line IIIB-IIIB in FIG. 3B, the standard cell 10 includes a P-type semiconductor substrate 31, an N-type well 32, an isolation 33, a P-type diffusion layer 34, an insulating film 35, an isolation boundary 36, and gate layers 37a and 37b. The standard cell 10 also includes an intra-cell power supply wiring 12a in the M1 layer, a signal wiring 39 in the M1 layer, and a power supply access point 45c. Although the power supply access point 45c does not have a physical entity, it is shown in the cross section for convenience. The standard cell 10 also includes an extra-cell wiring region 43c in the M2 layer on top of the insulating film 35 and the power supply access point 45c.

[0031] 2, 3A, and 3B are placed in the X and Y directions by performing P&R processing, with the standard cells 10 contacting each other at their boundary lines 11. Before placing the standard cells 10, high-potential power supply wiring for the M2 layer is placed in either or both of the extra-cell wiring regions 43a and 43c of the M2 layer. Furthermore, low-potential power supply wiring for the M2 layer is placed in either or both of the extra-cell wiring regions 43b and 43d of the M2 layer. The standard cells 10 are placed in the regions where the high-potential power supply wiring and the low-potential power supply wiring are placed.

[0032] There are multiple combinations of the method of arranging power supply wiring in the extra-cell wiring region of the M2 layer and the method of arranging extra-cell contacts at power supply access points. Among these combinations, the one used in the semiconductor device 100 according to the first embodiment shown in FIG. 1 will be described below.

[0033] FIG. 4 is a first configuration diagram showing the arrangement of standard cells and power supply wiring according to the first embodiment. The first configuration diagram shows a case where a standard cell 10 is arranged in an area where power supply wiring is arranged as follows: (1) Main power supply wiring 13a and 13b are arranged in the extra-cell wiring areas 43a and 43b of the M2 layer in FIG. 2, respectively. The main power supply wiring 13a is either the first power supply VDD or the third power supply VDD2. The main power supply wiring 13b is either the second power supply VSS or the fourth power supply VSS2. (2) No power supply wiring is arranged in the extra-cell wiring areas 43c and 43d of the M2 layer in FIG. 2.

[0034] The fourth power supply VSS2 is a power supply that can cut off the supply to the logic circuit, for example, even while the first power supply VDD and the second power supply VSS are being supplied, and is used for the purpose of reducing standby power consumption by cutting off the supply to the logic circuit when the semiconductor device is in standby mode.

[0035] The extra-cell wiring areas 43c and 43d of the M2 layer do not have power supply wiring, so they can be used to place signal lines on the M2 layer. The area sandwiched between the extra-cell wiring areas 43c and 43d of the M2 layer is the signal line wiring area 42 of the M2 layer.

[0036] The standard cell 10 uses the main power supply wiring 13a and the main power supply wiring 13b. When the standard cell 10 is placed by P&R, the following processes (a) to (g) are performed.

[0037] (a) The main power supply wirings 13a and 13b are selected as a pair of power supply wirings used by the standard cell 10.

[0038] (b) Of the power supply access points 45a and 45c in FIG. 2, the power supply access point 45a corresponding to the main power supply wiring 13a used by the standard cell 10 is selected.

[0039] (c) An extra-cell contact 15a is placed at the selected power access point 45a to connect the intra-cell power wiring 12a in the M1 layer and the main power wiring 13a in the M2 layer.

[0040] (d) An insulating film is disposed at the power access points 45c that are not selected, and the intra-cell power wiring 12a in the M1 layer is separated from the signal lines disposed in the extra-cell wiring region 43c in the M2 layer.

[0041] (e) Of the power supply access points 45b and 45d in FIG. 2, the power supply access point 45b corresponding to the main power supply wiring 13b used by the standard cell 10 is selected.

[0042] (f) An extra-cell contact 15b is placed at the selected power access point 45b to connect the intra-cell power wiring 12b on the M1 layer and the main power wiring 13b on the M2 layer.

[0043] (g) An insulating film is disposed at the power access points 45d that are not selected, and the intra-cell power wiring 12b in the M1 layer is separated from the signal lines disposed in the extra-cell wiring region 43d in the M2 layer.

[0044] In this way, either the main power supply wiring 13a or the sub-power supply wiring 13c is selected as the high-potential side power supply wiring and connected to the intra-cell power supply wiring 12a in the M1 layer at the corresponding power access point 45a or 45c. Also, either the main power supply wiring 13b or the sub-power supply wiring 13d is selected as the low-potential side power supply wiring and connected to the intra-cell power supply wiring 12b in the M1 layer at the corresponding power access point 45b or 45d.

[0045] The power supply access points 45a, 45b, 45c, and 45d are not shown in the drawing after the standard cells are placed, because they are replaced with physical entities by the placement of one of the extra-cell contacts 15a, 15b, 15c, and 15d, or an insulating film.

[0046] 5A and 5B are cross-sectional views corresponding to the first configuration in which standard cells and power supply wiring according to the first embodiment are arranged, as shown in Fig. 4. Fig. 5A shows a cross section taken along VA-VA in Fig. 4, and Fig. 5B shows a cross section taken along VB-VB in Fig. 4.

[0047] The cross-sectional view taken along line VA-VA in FIG. 5A differs from the cross-sectional configuration diagram of the standard cell 10 according to the first embodiment shown in FIG. 3A in the following respects: (1) The main power supply wiring 13a in the M2 layer is arranged in the extra-cell wiring region 43a in the M2 layer. (2) An extra-cell contact 15a is arranged at the position of the power access point 45a, and connects the intra-cell power supply wiring 12a in the M1 layer and the main power supply wiring 13a in the M2 layer. The rest of the configuration is the same as in the cross-sectional configuration diagram of the standard cell 10 shown in FIG. 3A, and therefore description thereof will be omitted.

[0048] In the cross section taken along VB-VB in FIG. 5B, the standard cell 10 after placement differs from the cross section of the standard cell 10 according to the first embodiment shown in FIG. 3B in the following respects: (1) An insulating film is disposed at the position of the power supply access point 45c. The rest of the configuration is the same as the cross section of the standard cell 10 shown in FIG. 3B, and therefore a description thereof will be omitted.

[0049] FIG. 6A is a second configuration diagram showing the arrangement of standard cells and power supply wiring according to the first embodiment. The second configuration diagram shows a case where a standard cell 10 is arranged in an area where power supply wiring is arranged as follows: (1) Main power supply wiring 13a and 13b are arranged in the extra-cell wiring areas 43a and 43b of the M2 layer in FIG. 2, respectively. The main power supply wiring 13a is either the first power supply VDD or the third power supply VDD2, and the main power supply wiring 13b is either the second power supply VSS or the fourth power supply VSS2. (2) Sub-power supply wiring 13c is arranged in the extra-cell wiring area 43c of the M2 layer in FIG. 2. The sub-power supply wiring 13c is a power supply wiring that supplies either the first power supply VDD or the third power supply VDD2, which is different from the power supply supplied by the main power supply wiring 13a. (3) No power supply wiring is arranged in the extra-cell wiring area 43d of the M2 layer in FIG. 2.

[0050] Since no power supply wiring is arranged in the extra-cell wiring area 43d of the M2 layer, it can be used to arrange signal lines in the M2 layer. In addition, the area sandwiched between the sub-power supply wiring 13c and the extra-cell wiring area 43d of the M2 layer is the signal line wiring area 42 of the M2 layer.

[0051] The standard cell 10 uses main power supply wiring 13a and main power supply wiring 13b. The second configuration diagram shown in FIG. 6A differs from the first configuration diagram shown in FIG. 4 in that not only the main power supply wiring 13a but also the sub-power supply wiring 13c is arranged as the high-potential side power supply wiring. In relation to this difference, the process (d) performed when the standard cell 10 is arranged in the first configuration diagram shown in FIG. 4 becomes a process of separating the intra-cell power supply wiring 12a and the sub-power supply wiring 13c in the M1 layer in the second configuration diagram shown in FIG. 6A. The rest is the same as the first configuration diagram shown in FIG. 4, and the description thereof will be omitted.

[0052] 6B is a third configuration diagram showing the arrangement of standard cells and power supply wiring according to the first embodiment. In the third configuration diagram, the configuration of the power supply wiring in the area where the standard cells 10 are arranged is the same as that in the second configuration diagram shown in FIG. 6A.

[0053] The third configuration diagram shown in Fig. 6B differs from the second configuration diagram shown in Fig. 6A in that the standard cell 10 uses the secondary power supply wiring 13c instead of the primary power supply wiring 13a as the high-potential side power supply wiring. In relation to this difference, the processes (a) to (d) performed when the standard cell 10 is placed in the first configuration diagram are as follows.

[0054] (a) The sub-power supply wiring 13c and the main power supply wiring 13b are selected as a pair of power supply wirings used by the standard cell 10.

[0055] (b) Of the power supply access points 45a and 45c in FIG. 2, the power supply access point 45c corresponding to the sub-power supply wiring 13c used by the standard cell 10 is selected.

[0056] (c) An extra-cell contact 15c is placed at the selected power access point 45c to connect the intra-cell power wiring 12a in the M1 layer and the sub-power wiring 13c in the M2 layer.

[0057] (d) An insulating film is placed at the unselected power supply access point 45a to separate the intra-cell power supply wiring 12a and the main power supply wiring 13a of the M1 layer.

[0058] The configuration diagram and cross-sectional diagram of the standard cell 10, and the configuration diagram and cross-sectional diagram of the arrangement of the standard cell 10 and power supply wiring have been described above. Based on these, the configuration diagram of the semiconductor device 100 according to the first embodiment shown in FIG. 1 will be described in detail.

[0059] 1, in standard cell placement rows 20 and 21, standard cells 10 are arranged in a state that is inverted in the Y direction relative to that in FIG. 2. This is generally done to reduce the layout area by sharing wells at the boundaries of standard cell placement rows that are adjacent in the Y direction, but they may also be arranged without being inverted.

[0060] The standard cell placement row 20 in FIG. 1 uses the first configuration of standard cells and power supply wiring shown in FIG. 4. Main power supply wiring 13a (VDD), 13b in the M2 layer are placed outside the standard cell 10 in the extra-cell wiring regions 43a, 43b in the M2 layer in FIG. 2. The standard cell 10 uses the first power supply VDD, so it is represented as standard cell 10(VDD). The standard cell placement row 20 includes a third standard cell 10(VDD).

[0061] In the standard cell 10 of the standard cell placement row 20, the high-potential side main power supply wiring 13a (VDD) is connected to the intra-cell power supply wiring 12a of the M1 layer. Therefore, an extra-cell contact 15a is placed outside the standard cell 10 at the position of the power supply access point 45a in FIG. 2. Also, the low-potential side main power supply wiring 13b is connected to the intra-cell power supply wiring 12b of the M1 layer. Therefore, outside the standard cell 10, an extra-cell contact 15b is placed at the position of the power supply access point 45b in FIG. 2. A contact 16 is placed at the intersection of the main power supply wiring 13a (VDD), 13b of the M2 layer and the power supply wiring 14 of the M3 layer placed in the Y direction.

[0062] The standard cell layout row 21 in Fig. 1 uses the first configuration in which standard cells and power supply wiring are arranged, as shown in Fig. 4. Since the standard cell 10 uses the main power supply wiring 13a (VDD2) that supplies the third power supply VDD2, it is written as the standard cell 10 (VDD2), and is therefore the same as the standard cell layout row 20, except that it is written as the standard cell 10 (VDD2).

[0063] 1, the standard cell placement rows 20 and 21 use the first configuration in which standard cells and power supply wiring are arranged as shown in Fig. 4, and a pair of power supply wirings consisting of one high-potential side main power supply wiring 13a and one low-potential side main power supply wiring 13b is arranged as the power supply wiring. The area in which the pair of power supply wirings is arranged as the power supply wirings is called a first block, and the standard cell placement rows 20 and 21 in Fig. 1 belong to the first block.

[0064] 1, the standard cell placement row 22 uses the second configuration in which standard cells and power supply wiring are arranged as shown in Fig. 6A and the third configuration in which standard cells and power supply wiring are arranged as shown in Fig. 6B. Main power supply wiring 13a (VDD), 13b and sub-power supply wiring 13c (VDD2) of the M2 layer are arranged outside the standard cells 10 in the extra-cell wiring regions 43a, 43b, 43c of the M2 layer in Fig. 2.

[0065] Of the four standard cells 10 arranged in the standard cell arrangement row 22, the standard cells 10(VDD)_1 and 10(VDD)_4 use the second configuration of arranging the standard cells and power supply wiring shown in FIG. 6A. In the standard cells 10(VDD)_1 and 10(VDD)_4, the high-potential main power supply wiring 13a(VDD) is connected to the intra-cell power supply wiring 12a in the M1 layer. For this purpose, an extra-cell contact 15a is arranged outside the standard cell 10 at the position of the power supply access point 45a in FIG. 2.

[0066] The first standard cell 10(VDD2)_2 and the second standard cell 10(VDD2)_3 use the third configuration of standard cells and power supply wiring shown in FIG. 6B. The first standard cell 10(VDD)_2 has a first intra-cell power supply wiring 12a, which is a first internal power supply wiring, and a third intra-cell power supply wiring 12b, which is a third internal power supply wiring. In the first standard cell 10(VDD2)_2, a high-potential sub-power supply wiring 13c(VDD2), which is located in the extra-cell wiring region 43c, which is a first wiring region extending in the X direction, is connected to the first intra-cell power supply wiring 12a in the M1 layer. To this end, an extra-cell contact 15c, which is a first contact, is located outside the first standard cell 10(VDD)_2 at the power supply access point 45c in FIG. 2, which is a first connectable position. In the first standard cell 10(VDD)_2, a high-potential main power supply wiring 13a(VDD) serving as a second external power supply wiring is arranged in an extra-cell wiring region 43a, which is a third wiring region. Outside the first standard cell 10(VDD)_2, an insulating film is arranged at the third connectable position, which is the power supply access point 45a in FIG. 2 . In the first standard cell 10(VDD)_2, a low-potential main power supply wiring 13b serving as a third external power supply wiring arranged in an extra-cell wiring region 43b, which is a fourth wiring region, is connected to the third intra-cell power supply wiring 12b in the M1 layer. To this end, an extra-cell contact 15b serving as a third contact is arranged outside the first standard cell 10(VDD)_2 at the fourth connectable position, which is the power supply access point 45b in FIG. 2 .

[0067] The second standard cell 10(VDD2)_3 has a second intra-cell power supply wiring 12a, which is a second internal power supply wiring. In the second standard cell 10(VDD2)_3, a high-potential sub-power supply wiring 13c(VDD2) arranged in an extra-cell wiring area 43c, which is a second wiring area extending in the X direction, is connected to the second intra-cell power supply wiring 12a in the M1 layer. To this end, an extra-cell contact 15c, which is a second contact, is arranged outside the second standard cell 10(VDD2)_3 at the position of the power supply access point 45c in FIG. 2, which is a second connectable position.

[0068] 1, a pair of power supply wirings is arranged, consisting of one high-potential side main power supply wiring 13a which is a second external power supply wiring and one low-potential side main power supply wiring 13b which is a third external power supply wiring. Also arranged in the standard cell placement row 22 is one high-potential side sub-power supply wiring 13c which is a first external power supply wiring. An area in which the pair of power supply wirings and one or more power supply wirings are arranged is called a second block, and the standard cell placement row 22 belongs to the second block.

[0069] Generally, each area divided according to the type of power supply used is called a power supply domain. In the semiconductor device 100 of Fig. 1, the standard cell placement row 20 is a VDD-VSS power supply domain area in which the power supply wiring for the first power supply VDD is placed as the high-potential side main power supply wiring 13a and the power supply wiring for the second power supply VSS is placed as the low-potential side main power supply wiring 13b. The standard cell placement row 21 is a VDD2-VSS power supply domain area in which the power supply wiring for the third power supply VDD2 is placed as the high-potential side main power supply wiring 13a and the power supply wiring for the second power supply VSS is placed as the low-potential side main power supply wiring 13b.

[0070] In a standard cell placement row 22 located on the boundary between standard cell placement row 20 and standard cell placement row 21, which are in different power domains, a power supply line for the first power supply VDD is placed as a main power supply line 13a, and a power supply line for the third power supply VDD2 is placed as a sub-power supply line 13c. Then, in the standard cell placement row 22, either the main power supply line 13a or the sub-power supply line 13c is selected as the power supply line to be used for each standard cell 10. Then, from the power supply access points 45a, 45c in FIG. 2, a power supply access point corresponding to either the main power supply line 13a or the sub-power supply line 13c used by the standard cell 10 is selected. Either the main power supply line 13a or the sub-power supply line 13c is connected to the intra-cell power supply line 12a by placing either the corresponding extra-cell contact 15a, 15c at the selected power supply access point 45a or the power supply access point 45c.

[0071] Standard cells that use either the first power supply VDD or the third power supply VDD2 can be placed in the standard cell placement row 22. The region where standard cells that use any of the multiple power supplies can be placed is called a buffer region of the power domain.

[0072] By using the standard cell placement row 22 as a buffer region for the power domains, standard cells 10 (VDD) that use the first power supply VDD can be placed in the region where the standard cell placement row 20 in the VDD-VSS power domain and the standard cell placement row 22 are combined. Also, standard cells 10 (VDD2) that use the third power supply VDD2 can be placed in the region where the standard cell placement row 21 in the VDD2-VSS power domain and the standard cell placement row 22 are combined. This improves the degree of freedom for P&R in each power domain. This allows the designer to reduce the frequency with which they have to redo P&R by readjusting the position, size, and shape of each power domain and relocating the power wiring.

[0073] [Layout design method] A layout design method for the semiconductor device 100 according to the first embodiment will be described.

[0074] FIG. 7 is a flow diagram of a layout design method for the semiconductor device 100 according to the first embodiment.

[0075] Before the layout design begins, the logic circuit composed of standard cells is logically synthesized using a logic synthesis tool and converted into circuit diagram information composed of elements such as NMOS or PMOS, and this circuit diagram information is input at the start of the layout design.

[0076] Layout design is performed in the following steps. First, in step S11, the designer determines the size and shape of the area to be laid out using P&R. Next, in step S12, the designer tentatively determines the position, size, and shape of each power domain and the area where sub-power wiring will be placed. Next, in step S13, the designer places power wiring in each power domain and the area where sub-power wiring will be placed.

[0077] Next, in step S14, automatic layout is performed by P&R processing. The P&R processing is broken down as follows:

[0078] First, in step S141, standard cells are placed in an area that combines the area of ​​the power domain to which the standard cells belong and the area in which the sub-power wiring is placed. Next, in step S142, for each standard cell, a main power wiring or a sub-power wiring to be used by the standard cell is selected, and a power access point corresponding to the selected main power wiring or sub-power wiring is selected. Then, an external contact is placed at the selected power access point to connect the intra-cell power wiring to the main power wiring or sub-power wiring. Next, in step S143, wiring is performed between the standard cells.

[0079] Next, in step S144, it is determined whether the quantity and quality of the wiring between the power supply wiring and the standard cells satisfy evaluation criteria, such as the degree of wiring congestion.

[0080] In step S144, if the quantity and quality of the wiring satisfy the evaluation criteria, the P&R process in step S14 ends and the process proceeds to step S 15. In step S15, the designer outputs layout information for the P&R area, and the layout design ends.

[0081] On the other hand, if it is determined in step S144 that the quantity or quality of the wiring does not satisfy the evaluation criteria, the process proceeds to step S145, where it is determined whether there is room for improvement in the placement of the standard cells.

[0082] In step S145, if the quantity and quality of the wiring, the number of times P&R has been performed, etc. do not exceed predetermined standards, it is determined that there is room for improvement in the placement of the standard cells. Then, the P&R process returns to step S141, and the placement and wiring of the standard cells are redone to improve the quantity and quality of the wiring.

[0083] On the other hand, if the amount or quality of the wiring, the number of times P&R has been performed, etc., exceed the predetermined standards in step S145, it is determined that there is no room for improvement in the placement of the standard cells, because even if the P&R process is redone, the amount and quality of the wiring are unlikely to satisfy the evaluation standards.Then, returning to step S12, the designer redoes the settings of the position, size, and shape of the areas where each power domain and sub-power wiring will be placed, based on the evaluation results in step S144, so as to improve the amount and quality of the wiring.Furthermore, the placement of the power wiring is redone in step S13, and the P&R process is performed again in step S14.

[0084] In the flow of the layout design method for the semiconductor device 100 according to the first embodiment shown in FIG. 7, in step S141, standard cells are placed in an area that combines the area of ​​the power domain to which the standard cells belong and the area in which the sub-power wiring is placed. Then, in step S142, for each standard cell, a main power wiring or sub-power wiring to be used by the standard cell is selected and connected to the intra-cell power wiring. In the area in which the sub-power wiring is placed, standard cells that use any of a plurality of power supplies can be placed. This improves the degree of freedom of P&R.

[0085] By increasing the degree of freedom in P&R, it is possible to reduce the frequency with which it is determined in step S145 that there is no room for improvement in the placement of standard cells. This also reduces the frequency with which the designer returns to step S12 and adjusts the position, size, and shape of each power domain to redo the placement of power wiring.

[0086] [Layout design system] A layout design system for a semiconductor device 100 according to the first embodiment will be described.

[0087] 8 is a schematic diagram of a layout design system 200 for the semiconductor device 100 according to the first embodiment, and FIG. 9 is a block diagram of the layout design system 200 of FIG.

[0088] 8, the layout design system 200 includes a central processing unit (CPU) server 61, a storage medium 62, a computer device 63, and a network 64. In the following description, the central processing unit server 61 will also be referred to as a CPU server 61.

[0089] The layout design system 200 connects a CPU server 61, a storage medium 62, and a computer device 63 operated by a user via a network 64. The CPU server 61 stores computer programs used in the layout design system 200. The storage medium 62 stores input information and output information required to execute the computer programs used in the layout design system 200. The computer device 63 is operated by a user.

[0090] The CPU server 61 may be, for example, an engineering workstation, a mainframe, or a supercomputer. The storage medium 62 may be, for example, an external storage device such as a hard disk, a semiconductor storage device such as a memory, or a storage medium (media). The computer device 63 may be, for example, a personal computer (PC), a thin client terminal, a mobile terminal, or a PDA (Personal Digital Assistant). The network 64 may be, for example, the Internet, an intranet, a LAN, a telephone network, or a dedicated line. However, in practice, it is not limited to these examples.

[0091] As shown in FIG. 9, the CPU server 61 includes a logic synthesis unit 81 and a layout design tool unit 82 that execute a computer program used in the layout design system 200.

[0092] The logic synthesis unit 81 and the layout design tool unit 82 may be processing units such as a CPU or a microprocessor, but are not limited to these examples.

[0093] The logic synthesis unit 81 logically synthesizes standard cell connection information 73 (gate netlist) based on the circuit description information 71 and the information of the standard cell library 72, and outputs the logically synthesized standard cell connection information 73 to the storage medium 62.

[0094] The layout design tool unit 82 includes a standard cell placement unit 821 , a standard cell wiring unit 822 , a wiring evaluation unit 823 , and a chip layout output unit 824 .

[0095] The storage medium 62 has circuit description information 71, a standard cell library 72, and standard cell connection information 73. The storage medium 62 further has power wiring layout information 74, standard cell layout information 75, power access point connection information 76, signal line layout information 77, and chip layout information 78. The standard cell library 72 includes a plurality of standard cells.

[0096] The designer provisionally determines the size and shape of the P&R area, and the position, size, and shape of the area where each power domain and sub-power wiring will be placed, places the power wiring, and outputs power wiring placement information 74 to storage medium 62.

[0097] The standard cell placement unit 821 places standard cells based on the standard cell library 72 , standard cell connection information 73 , and power supply wiring placement information 74 , and outputs standard cell placement information 75 and power supply access point connection information 76 to the storage medium 62 .

[0098] The standard cell wiring unit 822 wires and connects the standard cells based on the standard cell connection information 73 , power supply wiring layout information 74 , and standard cell layout information 75 , and outputs signal line layout information 77 to the storage medium 62 .

[0099] The wiring evaluation unit 823 evaluates the quantity and quality of the wiring based on the power supply wiring placement information 74 and the signal line placement information 77. If the quantity and quality of the wiring satisfy the evaluation criteria, the wiring evaluation unit 823 outputs a determination that the evaluation criteria have been satisfied to the computer device 63. If the quantity or quality of the wiring does not satisfy the evaluation criteria, or if it is determined that there is room for improvement in the placement of the standard cells, the wiring evaluation unit 823 transmits a redo command to the standard cell placement unit. If it is determined that there is no room for improvement in the placement of the standard cells, it outputs an error determination result to the computer device 63.

[0100] The chip layout output unit 824 outputs chip layout information 78 to the storage medium 62 based on instructions from the computer device 63, power wiring layout information 74, standard cell layout information 75, power access point connection information 76, and signal line layout information 77.

[0101] (Effects of the first embodiment) According to the first embodiment, in the layout design, in addition to the region where a pair of main power supply wirings is placed, a region where a pair of main power supply wirings and one or more high-potential side sub-power supply wirings are placed is partially provided. By partially providing the region where the sub-power supply wirings are placed, it is possible to suppress an increase in the wiring area. In the partially provided region, standard cells that use any of multiple power supplies can be placed. This improves the degree of freedom of P&R, and reduces the frequency with which a designer needs to readjust the position, size, and shape of each power domain, redo the power supply wiring placement, and perform P&R again, thereby suppressing repetitive work in the design process.

[0102] Here, to facilitate understanding of the features of the present invention, a semiconductor device of a comparative example will be described.

[0103] In the following description, as in the first embodiment of the present invention, a first direction, which is the direction of the height hu of the standard cell 90, is defined as the Y direction, a second direction perpendicular to the direction of the height hu of the standard cell 90 on the paper surface is defined as the X direction, and a third direction perpendicular to the XY plane is defined as the Z direction.

[0104] 15 is a first configuration diagram of a semiconductor device according to a comparative example. A semiconductor device 300 includes standard cell placement rows 110, 111, and 112, power supply wiring 14 in the M3 layer, and contacts 96 that connect the power supply wiring 14 to intra-cell power supply wiring 93a and 93b in the M2 layer. Standard cells 90 are placed in the standard cell placement rows 110, 111, and 112 in the X direction. The intra-cell power supply wiring 93a and 93b in the M2 layer are placed inside the standard cells in the X direction. Here, being placed inside the standard cells means being included in the components of the standard cells.

[0105] 16 is a configuration diagram of a standard cell 90 according to a comparative example. A two-input NAND circuit is shown as an example. The standard cell 90 is defined as a rectangular area and has boundary lines 91 surrounding it on the top, bottom, left, and right.

[0106] The standard cell 90 includes intra-cell power supply wiring 92a, 92b in the M1 layer, intra-cell power supply wiring 93a, 93b in the M2 layer, intra-cell contacts 95a, 95b, and a signal line wiring region 94 in the M2 layer. The intra-cell contacts 95a, 95b are disposed inside the standard cell 90 and connect the intra-cell power supply wiring 92a, 92b in the M1 layer to the intra-cell power supply wiring 93a, 93b in the M2 layer. The standard cell 90 further includes an element isolation boundary 36, gate layers 37a, 37b, contacts 38 connecting the M1 layer to the gate layer or the M1 layer to the diffusion layer, and a signal line 39 in the M1 layer. Within the region surrounded by the element isolation boundary 36, the region where the gate layers 37a, 37b do not overlap when viewed from the Z direction is a P-type diffusion layer or an N-type diffusion layer.

[0107] The positions of the intra-cell power supply wiring 93a, 93b of the M2 layer in the Y direction are substantially the same for multiple standard cells. Therefore, when multiple standard cells 90 are placed in the X direction by performing P&R processing so that they contact each other at their boundary lines 91, the intra-cell power supply wiring 93a, 93b of the M2 layer of adjacent standard cells 90 are connected by contacting each other at the boundary line 91.

[0108] 17A and 17B are cross-sectional views of a standard cell 90 according to a comparative example. Fig. 17A shows a cross section taken along line XVIIA-XVIIA in Fig. 16, and Fig. 17B shows a cross section taken along line XVIIB-XVIIB in Fig. 16, respectively.

[0109] 17A, the standard cell 90 includes a P-type semiconductor substrate 31, an N-type well 32, an isolation 33, an insulating film 35, and gate layers 37a and 37b. The standard cell 90 further includes an intra-cell power supply wiring 92a in the M1 layer, an intra-cell power supply wiring 93a in the M2 layer, and an intra-cell contact 95a connecting the intra-cell power supply wiring 92a in the M1 layer and the intra-cell power supply wiring 93a in the M2 layer.

[0110] 17B, ​​the standard cell 90 includes a P-type semiconductor substrate 31, an N-type well 32, an isolation 33, a P-type diffusion layer 34, an insulating film 35, an isolation boundary 36, and gate layers 37a and 37b. The standard cell 90 further includes an intra-cell power supply wiring 92a in the M1 layer, a signal wiring 39 in the M1 layer, and a signal wiring region 94 in the M2 layer.

[0111] 15, in standard cell placement rows 110 and 112, standard cells 90 (VDD) using the first power supply VDD are placed adjacent to each other in the X direction. As a result, the intra-cell power supply wiring 93a (VDD) in the M2 layer and the intra-cell power supply wiring 93b of the second power supply VSS are connected across the entire row. Also, in standard cell placement row 111, standard cells 90 (VDD2) using the third power supply VDD2 are placed adjacent to each other in the X direction. As a result, the intra-cell power supply wiring 93a (VDD2) in the M2 layer and the intra-cell power supply wiring 93b of the second power supply VSS are connected across the entire row.

[0112] 18 is a second configuration diagram of a semiconductor device according to a comparative example. A semiconductor device 301 includes standard cell placement rows 110, 111, and 113, power supply wiring 14 in the M3 layer, and contacts 96 connecting the power supply wiring 14 to the internal power supply wiring 93a and 93b in the M2 layer. In the standard cell placement row 113, a standard cell 90(VDD) and a standard cell 90(VDD2) are placed in the same standard cell placement row. If the standard cells 90(VDD) and 90(VDD2) were placed adjacent to each other in the X direction, the internal power supply wiring 93a(VDD) and the internal power supply wiring 93a(VDD2) in the M2 layer would be connected, resulting in a short circuit between the first power supply VDD and the third power supply VDD2. Therefore, the standard cells 90(VDD) and 90(VDD2) are placed with a gap in the X direction.

[0113] The standard cell placement row 110 and standard cells 90(VDD)_1 and 90(VDD)_4 in the standard cell placement row 113 form a VDD-VSS power supply domain. The standard cells 90(VDD2)_2 and 90(VDD2)_3 in the standard cell placement row 113 and the standard cell placement row 111 form a VDD2-VSS power supply domain.

[0114] The standard cell 10 according to the first embodiment of the present invention differs from the standard cell 90 according to the comparative example described above in the following points: (1) The standard cell 10 according to the first embodiment of the present invention does not have the intra-cell power supply wiring 93a, 93b and the intra-cell contacts 95a, 95b in the M2 layer. (2) The standard cell 10 according to the first embodiment of the present invention has power supply access points 45a, 45b, 45c, and 45d. (3) The standard cell 10 according to the present invention has portions in the X direction where the intra-cell power supply wiring 12a, 12b in the M1 layer overlap with the extra-cell wiring regions 43a, 43b in the M2 layer when viewed in the Z direction.

[0115] 19 is a flow diagram of a layout design method for the semiconductor devices 300 and 301 according to the comparative examples. This flow diagram is common to the first and second configuration diagrams of the semiconductor devices according to the comparative examples.

[0116] Layout design is performed in the following steps. First, in step S91, the designer determines the size and shape of the area to be laid out using P&R. Next, in step S92, the designer tentatively determines the position, size, and shape of each power domain. Next, in step S93, the designer places power wiring for each power domain.

[0117] Next, in step S94, automatic layout is performed by P&R processing.

[0118] The P&R process is broken down as follows: First, in step S941, standard cells are placed in each power domain, and then in step S942, wiring is performed between the standard cells.

[0119] Next, in step S943, it is determined whether the quantity and quality of the wiring between the power supply wiring and the standard cells satisfy evaluation criteria, such as the degree of wiring congestion.

[0120] If the quantity and quality of the wiring satisfy the evaluation criteria in step S943, the P&R process in step S94 ends and the process proceeds to step S95. In step S95, the designer outputs layout information for the P&R area, and the layout design ends.

[0121] On the other hand, if the quantity and quality of the wiring do not satisfy the evaluation criteria in step S943, the process proceeds to step S944, where it is determined whether there is room for improvement in the placement of the standard cells.

[0122] In step S944, if the amount and quality of wiring, the number of P&Rs, etc. do not exceed predetermined standards, it is determined that there is room for improvement in the placement of the standard cells. Then, the P&R process returns to step S941, and the placement and routing of the standard cells are redone to improve the amount and quality of wiring.

[0123] On the other hand, if the quantity or quality of the wiring, the number of times P&R has been performed, etc., exceed the predetermined standards in step S944, it is determined that there is no room for improvement in the placement of the standard cells, because even if the P&R process is redone, the quantity and quality of the wiring are unlikely to satisfy the evaluation standards.Then, returning to step S92, the designer redoes the settings of the position, size, and shape of each power domain based on the evaluation results in step S943 so as to improve the quantity and quality of the wiring.Furthermore, the power wiring placement is redone in step S93, and the P&R process is performed again in step S94.

[0124] Based on the flow of the layout design method for the semiconductor devices 300 and 301 according to the comparative example described above, let us return to the first configuration diagram of the semiconductor device according to the comparative example in Fig. 15 and the second configuration diagram of the semiconductor device according to the comparative example in Fig. 18. In the first and second configuration diagrams according to the comparative example, P&R is performed after the layout of the power supply domains of the first power supply VDD and the third power supply VDD2 has been determined in the stage prior to P&R, so the degree of freedom of P&R is limited.

[0125] 15, for example, the location where a standard cell 90 that uses VDD2 can be placed is limited to standard cell placement row 111, which is the VDD2-VSS power domain. Therefore, if the quantity or quality of the wiring for the standard cell 90 placed in standard cell placement row 111 does not satisfy the evaluation criteria in the evaluation after P&R, the degree of freedom for re-arranging the standard cell 90 is limited, and it is likely to be determined that there is no room for improvement. If it is determined that there is no room for improvement in the placement of the standard cell 90, the designer must adjust the size and shape of the power domain to expand the area of ​​the VDD2-VSS power domain and redo the placement of the power wiring.

[0126] As an example of adjusting the size and shape of the power domain, consider the case where part of the VDD-VSS power domain is replaced with a VDD2-VSS power domain, as in standard cell placement row 113 in the second configuration diagram of FIG.

[0127] To separate the intra-cell power wiring 93a(VDD) of the first power supply VDD and the intra-cell power wiring 93a(VDD2) of the third power supply VDD2 in the M2 layer in the X direction, the designer moves the power domain to which the standard cells 90(VDD)_1 and 90(VDD)_4 belong outward in the X direction. Then, gaps are inserted between the standard cells 90(VDD)_1 and 90(VDD2)_2 and between the standard cells 90(VDD2)_3 and 90(VDD)_4. The designer adjusts the placement of the power wiring 14 in the M3 layer in the Y direction to ensure the power supply capability to the separated intra-cell power wiring 93a(VDD) and 93a(VDD2) in the M2 layer.

[0128] If the layout area increases as a result of these adjustments by the designer, the position and shape of the power domain and the placement of the power wiring must be adjusted to fit within the specified area and shape. Then, the P&R must be redone.

[0129] In this way, adjusting the position, size, and shape of the power domain, arranging the power wiring, and repeating P&R requires a lot of time and work.

[0130] Compared to the semiconductor devices 300 and 301 according to the comparative examples described above, the semiconductor device 100 according to the first embodiment of the present invention has improved flexibility in P&R, and can reduce the need to repeatedly adjust the layout of the power domains and power wiring and redo the P&R.

[0131] Specifically, in addition to the area where a pair of main power supply wirings is placed, a partial area is provided where a pair of main power supply wirings and one or more high-potential secondary power supply wirings are placed. Then, for each standard cell, either the main power supply wiring or the secondary power supply wiring to be used by the standard cell is selected. Also, from among multiple power supply access points, a power supply access point corresponding to either the main power supply wiring or the secondary power supply wiring to be used by the standard cell is selected. Then, by placing a corresponding external contact at the selected power supply access point, either the main power supply wiring or the secondary power supply wiring is connected to the internal power supply wiring of the cell. In this way, standard cells that use any of multiple power supplies can be placed within the partial area, improving the flexibility of P&R.

[0132] [Second embodiment] (Configuration of semiconductor device) 10 is a configuration diagram of a semiconductor device according to the second embodiment. The semiconductor device 101 includes standard cell rows 20, 21, and 23, main power supply wiring 13a and 13b in the M2 layer, a sub-power supply wiring 13c in the M2 layer, a power supply wiring 14 in the M3 layer, extra-cell contacts 15a, 15b, and 15c, and a contact 16.

[0133] A plurality of standard cells 10 are arranged in the X direction in standard cell placement rows 20, 21, and 23. Main power supply wiring 13a, 13b and sub-power supply wiring 13c are arranged in the X direction outside the standard cells for each of standard cell placement rows 20, 21, and 23. Power supply wiring 14 is arranged in the Y direction. Extra-cell contacts 15a, 15b, and 15c are arranged outside the standard cells and connect either of the intra-cell power supply wiring 12a, 12b in the M1 layer to either of the main power supply wiring 13a, 13b, or sub-power supply wiring 13c in the M2 layer. Contact 16 connects either of the main power supply wiring 13a, 13b, or sub-power supply wiring 13c in the M2 layer to the power supply wiring 14 in the M3 layer.

[0134] FIG. 11 is a configuration diagram showing the arrangement of standard cells and power supply wiring according to the second embodiment. A two-input NAND circuit is shown as an example. The configuration diagram of the standard cell used is the same as that of the standard cell according to the first embodiment shown in FIG. 2. The configuration diagram of FIG. 11 shows a case where the standard cell 10 is arranged in an area where power supply wiring is arranged as follows: (1) A secondary power supply wiring 13c is arranged in the extra-cell wiring area 43c of the M2 layer in FIG. 2. The secondary power supply wiring 13c is either the first power supply VDD or the third power supply VDD2. (2) A main power supply wiring 13b is arranged in the extra-cell wiring area 43b of the M2 layer in FIG. 2. The main power supply wiring 13b is either the second power supply VSS or the fourth power supply VSS2. (3) No power supply wiring is arranged in the extra-cell wiring areas 43a and 43d of the M2 layer in FIG. 2.

[0135] The configuration diagram of the second embodiment shown in Fig. 11 differs from the first configuration diagram of the first embodiment shown in Fig. 4 in the following points: (1) Power supply wiring is not arranged in the extra-cell wiring area 43a of the M2 layer, and extra-cell contacts 15a are not arranged at the power supply access points 45a. (2) Sub-power supply wiring 13c is arranged in the extra-cell wiring area 43c of the M2 layer, and extra-cell contacts 15c are arranged at the power supply access points 45c.

[0136] In this way, the sub-power supply wiring 13c may be used as a power supply wiring on the high potential side in the standard cell 10. Similarly, the sub-power supply wiring 13d may be used as a power supply wiring on the low potential side.

[0137] The configuration diagram of the semiconductor device according to the second embodiment shown in Figure 10 differs from the configuration diagram of the semiconductor device according to the first embodiment shown in Figure 1 in the following respects: (1) In some standard cells 10(VDD2)_2 of the standard cell placement row 23, the main power supply wiring 13a(VDD) is not placed, and the M2 layer extra-cell wiring region 43a remains. (2) The sub-power supply wiring 13c(VDD2) is placed in some standard cells 10(VDD2)_2 and 10(VDD2)_3 of the standard cell placement row 23. The region of the standard cell placement row 23 where the sub-power supply wiring 13c(VDD2) is not placed remains the M2 layer extra-cell wiring region 43c.

[0138] In FIG. 10, standard cell placement rows 20 and 21 are provided with a pair of power supply wirings, each consisting of one high-potential side main power supply wiring 13a and one low-potential side main power supply wiring 13b, and belong to the first block.

[0139] The standard cells 10(VDD)_1 and 10(VDD)_4 in the standard cell placement row 23 are provided with a pair of power supply wirings consisting of one high-side main power supply wiring 13a and one low-side main power supply wiring 13b, and belong to the first block. The standard cell 10(VDD2)_2 in the standard cell placement row 23 is provided with a pair of power supply wirings consisting of one high-side sub-power supply wiring 13c and one low-side main power supply wiring 13b, and belong to the first block. The standard cell 10(VDD2)_3 in the standard cell placement row 23 is provided with a pair of power supply wirings consisting of one high-side main power supply wiring 13a and one low-side main power supply wiring 13b, and also with one high-side sub-power supply wiring 13c. The standard cell 10(VDD2)_3 in the standard cell placement row 23 belongs to the second block.

[0140] 10, the main power supply wiring 13a (VDD) or the sub-power supply wiring 13c (VDD2) is not arranged over the entire standard cell placement row 23. In the area where the main power supply wiring 13a (VDD) or the sub-power supply wiring 13c (VDD2) is not arranged, the signal line wiring of the M2 layer can be arranged in the extra-cell wiring areas 43a and 43c of the M2 layer, and more area can be secured in which the signal line wiring of the M2 layer can be arranged.

[0141] The flow of the layout design method for the semiconductor device 101 according to the second embodiment shown in Fig. 10 is similar to the flow of the layout design method for the semiconductor device 100 according to the first embodiment shown in Fig. 7. Furthermore, the layout design system for the semiconductor device 101 according to the second embodiment shown in Fig. 10 is similar to the layout design system 200 for the semiconductor device 100 according to the first embodiment shown in Figs. 8 and 9.

[0142] (Effects of the second embodiment) According to the second embodiment, in the layout design, in addition to the region where a pair of main power supply wirings are arranged, a region where a pair of main power supply wirings and one or more high-potential sub-power supply wirings are arranged is partially provided. By partially providing the region where the sub-power supply wirings are arranged, an increase in the wiring area can be suppressed. Furthermore, for some standard cells, the main power supply wiring is not arranged in the extra-cell wiring region of the M2 layer, but the sub-power supply wiring is arranged. Alternatively, in a standard cell placement row, the sub-power supply wiring is arranged in the extra-cell wiring region of some standard cells, and the sub-power supply wiring is not arranged in the extra-cell wiring region of the remaining standard cells. By not arranging the main power supply wiring or the sub-power supply wiring, more area can be secured for arranging the signal line wiring of the M2 layer. This improves the degree of freedom of the wiring between the P&R standard cells, reduces the frequency with which the designer adjusts the position, size, and shape of each power domain, redoes the power supply wiring placement, and performs the P&R again, and suppresses the repetition of work in the design process. From another perspective, the layout area required for arranging the signal line wiring can be reduced.

[0143] Furthermore, compared to the second configuration diagram of the semiconductor device according to the comparative example shown in FIG. 18, the second embodiment of the present invention can reduce the need to repeatedly adjust the placement of power domains and power wiring and redo P&R. Specifically, consider the case where a standard cell using the first power supply VDD and a standard cell using the third power supply VDD2 are placed adjacent to each other in the X direction. By placing the power wiring of the power domain to which either standard cell belongs as a sub-power wiring, it becomes unnecessary to insert a gap to separate the power wiring of the first power supply VDD and the third power supply VDD2 in the M2 layer in the X direction. This reduces the frequency with which designers need to adjust the position, size, and shape of the power domains.

[0144] [Third embodiment] (Configuration of semiconductor device) 12 is a configuration diagram of a semiconductor device according to the third embodiment. A semiconductor device 102 includes standard cell rows 20, 21, and 24, main power supply wirings 13a and 13b in the M2 layer, a sub-power supply wiring 13d in the M2 layer, a power supply wiring 14 in the M3 layer, extra-cell contacts 15a, 15b, and 15d, and a contact 16.

[0145] A plurality of standard cells 10 are arranged in the X direction in standard cell placement rows 20, 21, and 24. Main power supply wiring 13a, 13b and sub-power supply wiring 13d are arranged in the X direction outside the standard cells for each of standard cell placement rows 20, 21, and 24. Power supply wiring 14 is arranged in the Y direction. Extra-cell contacts 15a, 15b, and 15d are arranged outside the standard cells and connect either of the intra-cell power supply wiring 12a, 12b in the M1 layer to either of the main power supply wiring 13a, 13b, or sub-power supply wiring 13d in the M2 layer. Contact 16 connects either of the main power supply wiring 13a, 13b, or sub-power supply wiring 13d in the M2 layer to the power supply wiring 14 in the M3 layer.

[0146] The main power supply wiring 13b that supplies the second power supply VSS is referred to as the main power supply wiring 13b(VSS), the main power supply wiring 13b that supplies the fourth power supply VSS2 is referred to as the main power supply wiring 13b(VSS2), and the sub-power supply wiring 13d that supplies the fourth power supply VSS2 is referred to as the sub-power supply wiring 13d(VSS2).

[0147] The configuration of the standard cell 10 is common whether the second power supply VSS or the fourth power supply VSS2 is used, and when the standard cell 10 is placed, it is connected to the power supply used by the standard cell 10 outside the standard cell 10. When the standard cell 10 uses the second power supply VSS as the low-potential power supply, it is written as standard cell 10(VSS), and when it uses the fourth power supply VSS2, it is written as standard cell 10(VSS2).

[0148] FIG. 13A is a first configuration diagram showing the arrangement of standard cells and power supply wiring according to the third embodiment. The first configuration diagram shows a case where a standard cell 10 is arranged in an area where power supply wiring is arranged as follows: (1) Main power supply wiring 13a and 13b are arranged in the extra-cell wiring areas 43a and 43b of the M2 layer in FIG. 2, respectively. The main power supply wiring 13a is either the first power supply VDD or the third power supply VDD2, and the main power supply wiring 13b is either the second power supply VSS or the fourth power supply VSS2. (2) Sub-power supply wiring 13d is arranged in the extra-cell wiring area 43d of the M2 layer in FIG. 2. The sub-power supply wiring 13d is a power supply wiring that supplies either the second power supply VSS or the fourth power supply VSS2, which is different from the power supply supplied by the main power supply wiring 13b. (3) No power supply wiring is arranged in the extra-cell wiring area 43c of the M2 layer in FIG. 2.

[0149] The standard cell 10 uses main power supply wiring 13a and main power supply wiring 13b. The first configuration diagram of the third embodiment shown in FIG. 13A differs from the first configuration diagram of the first embodiment shown in FIG. 4 in that not only the main power supply wiring 13b but also the sub-power supply wiring 13d is arranged as the low-potential side power supply wiring. In relation to this difference, the process (g) performed when the standard cell 10 is arranged in the first configuration diagram of the first embodiment shown in FIG. 4 becomes a process of separating the intra-cell power supply wiring 12b and the sub-power supply wiring 13d in the first configuration diagram of the third embodiment shown in FIG. 13A. Other than that, the first configuration diagram is the same as FIG. 4, and a description thereof will be omitted.

[0150] 13B is a second configuration diagram showing the arrangement of standard cells and power supply wiring according to the third embodiment. In the second configuration diagram, the configuration of the power supply wiring in the area where the standard cells 10 are arranged is the same as that in the first configuration diagram shown in FIG.

[0151] The second configuration diagram shown in Fig. 13B differs from the first configuration diagram shown in Fig. 13A in that the standard cell 10 uses sub-power supply wiring 13d instead of main power supply wiring 13b as the low-potential side power supply wiring. In relation to this difference, the process (a) and processes (e) to (g) performed when the standard cell 10 is placed in the first configuration diagram according to the first embodiment shown in Fig. 4 are as follows.

[0152] (a) The main power supply wiring 13a and the sub-power supply wiring 13d are selected as a pair of power supply wirings used by the standard cell 10.

[0153] (e) Of the power supply access points 45b and 45d in FIG. 2, the power supply access point 45d corresponding to the sub-power supply wiring 13d used by the standard cell 10 is selected.

[0154] (f) An extra-cell contact 15d is placed at the selected power access point 45d to connect the intra-cell power wiring 12b and the sub-power wiring 13d on the M1 layer.

[0155] (g) An insulating film is disposed at the unselected power supply access point 45b to separate the intra-cell power supply wiring 12b and the main power supply wiring 13b of the M1 layer.

[0156] In the standard cell placement rows 20 and 21 in FIG. 12, the first configuration in which the standard cells and power supply wiring according to the first embodiment shown in FIG. 4 are placed is used.

[0157] 12, a first configuration in which standard cells and power supply wiring according to the third embodiment are arranged as shown in Fig. 13A, and a second configuration in which standard cells and power supply wiring according to the third embodiment are arranged as shown in Fig. 13B are used. Main power supply wiring 13a, 13b (VSS) and sub-power supply wiring 13d (VSS2) of the M2 layer are arranged outside the standard cells 10 in extra-cell wiring regions 43a, 43b, 43d of the M2 layer in Fig. 2.

[0158] Of the four standard cells 10 arranged in the standard cell arrangement row 24, the standard cells 10(VSS)_1 and 10(VSS)_4 use the first configuration shown in FIG. 13A. In the standard cells 10(VSS)_1 and 10(VSS)_4, the low-potential main power supply wiring 13b(VSS) is connected to the intra-cell power supply wiring 12b in the M1 layer. For this purpose, an extra-cell contact 15b is arranged outside the standard cell 10 at the position of the power supply access point 45b in FIG. 2.

[0159] The standard cells 10(VSS2)_2 and 10(VSS2)_3 use the second configuration shown in FIG. 13B. In the standard cells 10(VSS2)_2 and 10(VSS2)_3, the low-potential sub-power supply wiring 13d (VSS2) is connected to the intra-cell power supply wiring 12b in the M1 layer. For this purpose, an extra-cell contact 15d is arranged outside the standard cell 10 at the position of the power supply access point 45d in FIG. 2.

[0160] 12, a pair of power supply wirings consisting of one high-potential side main power supply wiring 13a and one low-potential side main power supply wiring 13b is arranged, and the standard cell placement rows 20 and 21 in Fig. 12 belong to a first block. Standard cell placement row 24 in Fig. 12 belongs to a second block.

[0161] The flow of the layout design method for the semiconductor device 102 according to the third embodiment shown in Fig. 12 is similar to the flow of the layout design method for the semiconductor device 100 according to the first embodiment shown in Fig. 7. Furthermore, the layout design system for the semiconductor device 102 according to the third embodiment is similar to the layout design system 200 for the semiconductor device 100 according to the first embodiment shown in Figs.

[0162] 12, similarly to the semiconductor device 101 according to the second embodiment shown in FIG. 10, the main power supply wiring 13b may not be arranged in the extra-cell wiring regions 43b, 43d of some of the standard cells 10, but the sub-power supply wiring 13d may be arranged therein. Alternatively, in the standard cell placement row 24, the sub-power supply wiring 13d may be arranged in the extra-cell wiring region 43d of some of the standard cells 10, and the sub-power supply wiring 13d may not be arranged in the extra-cell wiring region 43d of the remaining standard cells 10. Signal lines of the M2 layer can be arranged in the extra-cell wiring region 43d of the M2 layer where the sub-power supply wiring 13d is not arranged.

[0163] (Effects of the third embodiment) According to the third embodiment, in the layout design, in addition to the region where a pair of main power supply wirings is placed, a region where a pair of main power supply wirings and one or more low-potential side sub-power supply wirings are placed is partially provided. By partially providing the region where the sub-power supply wirings are placed, it is possible to suppress an increase in the wiring area. In the partially provided region, standard cells that use any of multiple power supplies can be placed. This improves the degree of freedom of P&R, and reduces the frequency with which a designer needs to readjust the position, size, and shape of each power domain, redo the power supply wiring placement, and perform P&R again, thereby suppressing repetitive work in the design process.

[0164] [Fourth embodiment] (Configuration of semiconductor device) 14A is a first configuration diagram showing the arrangement of standard cells and power supply wiring according to the fourth embodiment. The first configuration diagram shows a case where a standard cell 10 is arranged in an area where power supply wiring is arranged as follows: (1) Main power supply wiring 13a and 13b are arranged in the extra-cell wiring areas 43a and 43b of the M2 layer in FIG. 2, respectively. (2) Sub-power supply wiring 13c and 13d are arranged in the extra-cell wiring areas 43c and 43d of the M2 layer in FIG. 2, respectively.

[0165] The standard cell 10 uses main power supply wiring 13a and main power supply wiring 13b. The first configuration diagram of the fourth embodiment shown in FIG. 14A differs from the first configuration diagram of the first embodiment shown in FIG. 4 in that sub-power supply wiring 13c is also arranged as a high-potential side power supply wiring and sub-power supply wiring 13d is also arranged as a low-potential side power supply wiring. In relation to this difference, the processes (d) and (g) performed when the standard cell 10 is arranged in the first configuration diagram of the first embodiment shown in FIG. 4 are as follows in the first configuration diagram of the fourth embodiment shown in FIG. 14A.

[0166] (d) An insulating film is disposed at the unselected power access point 45c to separate the intra-cell power wiring 12a and the sub-power wiring 13c of the M1 layer.

[0167] (g) An insulating film is placed at the unselected power access point 45d to separate the intra-cell power supply wiring 12b and the sub-power supply wiring 13d in the M1 layer.

[0168] 14B is a second configuration diagram showing the arrangement of standard cells and power supply wiring according to the fourth embodiment. In the second configuration diagram, the configuration of the power supply wiring in the area where the standard cells 10 are arranged is the same as that in the first configuration diagram shown in FIG.

[0169] The second configuration diagram shown in Fig. 14B differs from the first configuration diagram shown in Fig. 14A in that the standard cell 10 uses sub-power supply wiring 13c as a high-potential side power supply wiring and sub-power supply wiring 13d as a low-potential side power supply wiring. In relation to this difference, the processes (a) to (g) performed when the standard cell 10 is placed in the first configuration diagram according to the first embodiment shown in Fig. 4 are as follows in the second configuration diagram according to the fourth embodiment shown in Fig. 14B.

[0170] (a) The sub-power supply wirings 13c and 13d are selected as a pair of power supply wirings used by the standard cell 10.

[0171] (b) Of the power supply access points 45a and 45c in FIG. 2, the power supply access point 45c corresponding to the sub-power supply wiring 13c used by the standard cell 10 is selected.

[0172] (c) An extra-cell contact 15c is placed at the selected power access point 45c to connect the intra-cell power wiring 12a and the sub-power wiring 13c on the M1 layer.

[0173] (d) An insulating film is placed at the unselected power supply access point 45a to separate the intra-cell power supply wiring 12a and the main power supply wiring 13a of the M1 layer.

[0174] (e) Of the power supply access points 45b and 45d in FIG. 2, the power supply access point 45d corresponding to the sub-power supply wiring 13d used by the standard cell 10 is selected.

[0175] (f) An extra-cell contact 15d is placed at the selected power access point 45d to connect the intra-cell power wiring 12b and the sub-power wiring 13d on the M1 layer.

[0176] (g) An insulating film is disposed at the unselected power supply access point 45b to separate the intra-cell power supply wiring 12b and the main power supply wiring 13b of the M1 layer.

[0177] The first configuration diagram in FIG. 14A shows a case where both the high-potential side power supply wiring and the low-potential side power supply wiring are main power supply wiring, while the second configuration diagram in FIG. 14B shows a case where both the high-potential side power supply wiring and the low-potential side power supply wiring are sub-power supply wiring. Another combination is where the main power supply wiring is used for the high-potential side power supply wiring and the sub-power supply wiring is used for the low-potential side power supply wiring. This corresponds to the case where the high-potential side sub-power supply wiring 13c is additionally placed in the extra-cell wiring region 43c in FIG. 13B, as shown in FIG. 6A. Since the configuration can be uniquely derived from FIG. 13B and FIG. 6A, the explanation is omitted.

[0178] Another possible combination is to use a secondary power supply wiring for the high-potential side power supply wiring and a primary power supply wiring for the low-potential side power supply wiring. This corresponds to the case where a secondary power supply wiring 13d for the low-potential side is additionally placed in the extra-cell wiring area 43d of FIG. 6B, as shown in FIG. 13A. The configuration can be uniquely derived from FIG. 6B and FIG. 13A, so a detailed explanation is omitted.

[0179] 14A and 14B are arranged in the X direction so that the boundaries 11 of the standard cell arrangement row are in contact with each other. In this standard cell arrangement row, for each standard cell 10, either the main power supply wiring 13a or the sub-power supply wiring 13c used by the standard cell 10 is selected as the high-potential side power supply wiring and connected to the intracellular power supply wiring 12a. Also, for each standard cell 10, either the main power supply wiring 13b or the sub-power supply wiring 13d used by the standard cell 10 is selected as the low-potential side power supply wiring and connected to the intracellular power supply wiring 12b. The configuration of this standard cell arrangement row can be derived by combining the configuration diagram of the semiconductor device 100 according to the first embodiment shown in FIG. 1 with the configuration diagram of the semiconductor device 102 according to the third embodiment shown in FIG. 12, and therefore a description thereof will be omitted.

[0180] (Effects of the fourth embodiment) According to the fourth embodiment, in the layout design, in addition to the region where a pair of main power supply wirings is arranged, a region where a pair of main power supply wirings, one or more high-potential side sub-power supply wirings, and one or more low-potential side sub-power supply wirings are arranged is partially provided. By partially providing the region where the sub-power supply wirings are arranged, an increase in the wiring area can be suppressed. In the partially provided region, standard cells that use any of multiple power supplies can be arranged. This improves the degree of freedom in P&R, and reduces the frequency with which a designer needs to adjust the position, size, and shape of each power supply domain, redo the power supply wiring arrangement, and perform P&R again, thereby suppressing repetitive work in the design process.

[0181] [Other embodiments] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims.

[0182] For example, in the configurations of the standard cells and semiconductor devices according to some embodiments of the present invention, a logic circuit, particularly a NAND circuit, using a pair of power supplies has been described. However, the logic circuit may also be a level shifter using a pair of power supplies and one or more power supplies that are boosted or stepped down. Furthermore, the logic circuit may also be a flip-flop that uses a pair of power supplies and one or more power supplies whose supply to the logic circuit is cut off during standby and retains its value even when the power is cut off.

[0183] For example, in the configurations of the standard cells and semiconductor devices according to some embodiments of the present invention, the Y-direction dimension of the standard cell has been described as a unit height hu. However, multi-height cells, which are included in multiple types of standard cells and whose Y-direction dimension is an integer multiple of the unit height hu, may also be used. Multi-height cells also use a pair of power supplies, and the Y-direction positions of their power supply wiring are the same as those of standard cells whose Y-direction dimension is the unit height hu, and therefore are within the scope and spirit of the present invention. For example, a first standard cell whose Y-direction dimension is a natural number m times the unit height hu and a second standard cell whose Y-direction dimension is a natural number n times the unit height hu, but different from the natural number m times the unit height hu, may be arranged.

[0184] For example, in the configurations of the standard cells and semiconductor devices according to some embodiments of the present invention, the main power supply wiring is arranged in the extra-cell wiring regions 43a and 43b of the M2 layer, and the secondary power supply wiring is arranged in the extra-cell wiring regions 43c and 43d of the M2 layer. However, the main power supply wiring may be arranged in the extra-cell wiring regions 43c and 43d of the M2 layer, and the secondary power supply wiring may be arranged in the extra-cell wiring regions 43a and 43b of the M2 layer. [Explanation of symbols]

[0185] 10 Standard Cells 11 Borderline 12a, 12b Intra-cell power wiring 13a, 13b Main power wiring 13c, 13d sub power wiring 14 Power wiring 15a, 15b, 15c, 15d Outer cell contacts 16 Contacts 20, 21, 22, 23, 24 Standard cell placement rows 31 P-type semiconductor substrate 32 N-type well 33 Element isolation 34 P-type diffusion layer 35 insulating film 36 Borderline 37a, 37b gate layer 38 Contacts 39 Signal wiring 42 Signal line wiring area 43a, 43b, 43c, 43d Out-of-cell wiring area 45a, 45b, 45c, 45d Power Access Points 100, 101, 102 Semiconductor device VDD 1st power supply VDD2 3rd power supply VSS 2nd power supply VSS2 4th power supply

Claims

1. A standard cell library including at least a first standard cell and a second standard cell used in a standard cell design in which standard cells are arranged to configure a semiconductor integrated circuit, a dimension of the first standard cell in a first direction is a natural number m times a unit height, and a first internal power supply wiring is disposed inside the first standard cell; the dimension of the second standard cell in the first direction is a natural number n times the unit height, and a second internal power supply wiring is disposed inside the second standard cell; the first standard cell and the second standard cell are configured such that, when the first standard cell and the second standard cell are arranged adjacent to each other in a second direction perpendicular to the first direction, the first internal power supply wiring is separated from the second internal power supply wiring; the first standard cell has a first wiring region in which a first external power supply wiring can be arranged and which extends in the second direction, and a first connectable position at which the first external power supply wiring and the first internal power supply wiring can be connected; the second standard cell has a second wiring region in which the first external power supply wiring can be arranged and which extends in the second direction, and a second connectable position at which the first external power supply wiring and the second internal power supply wiring can be connected; the first wiring region and the second wiring region are adjacent to each other and connectable to each other; Standard cell library.

2. the first wiring region of the first standard cell and the second wiring region of the second standard cell are at substantially equal positions in the first direction; The standard cell library of claim 1 .

3. a third standard cell that can be arranged adjacent to the first standard cell in the first direction; The standard cell library of claim 1 .

4. 2. The standard cell library according to claim 1, wherein the natural number m and the natural number n are different natural numbers.

5. The first standard cell a third internal power supply wiring separate from the first internal power supply wiring; a third wiring area in which a second external power supply wiring can be arranged and which extends in the second direction; a third connectable position at which the second external power supply wiring and a third internal power supply wiring can be connected; a fourth wiring area in which a third external power supply wiring can be arranged and which extends in the second direction; a fourth connectable position at which the third external power supply wiring and the third internal power supply wiring can be connected; having The standard cell library of claim 1 .

6. When the first standard cell is placed, the first connectable position or the second connectable position corresponding to the external power supply wiring used by the first standard cell is selected from the first external power supply wiring and the second external power supply wiring; the first external power supply wiring and the first internal power supply wiring are connected at the selected first connectable position, or the second external power supply wiring and the first internal power supply wiring are connected at the selected second connectable position; the third external power supply wiring is connected to the third internal power supply wiring at the fourth connectable position; 6. The standard cell library according to claim 5.

7. the first internal power supply wiring includes a first portion arranged along the first direction and a second portion arranged along the second direction; the number of the first connectable positions is greater than the number of the first portions; The standard cell library of claim 1 .

8. a first standard cell whose dimension in a first direction is a natural number m times the unit height and in which a first internal power supply wiring is disposed; a second standard cell whose dimension in the first direction is a natural number n times the unit height, in which a second internal power supply wiring separate from the first internal power supply wiring is disposed inside the second standard cell, and which is adjacent to the first standard cell in a second direction perpendicular to the first direction; a first external power supply wiring extending in the second direction; a first contact that connects the first internal power supply wiring and a first external power supply wiring at a first connectable position; a second contact that connects the second internal power supply wiring and the first external power supply wiring at a second connectable position; Equipped with Semiconductor device.

9. the first connectable position and the second connectable position are at substantially the same position in the first direction; The semiconductor device according to claim 8 .

10. a third standard cell that can be arranged adjacent to the first standard cell in the first direction; The semiconductor device according to claim 8 .

11. 9. The semiconductor device according to claim 8, wherein said natural number m and said natural number n are different natural numbers.

12. The first standard cell comprises: a third internal power supply wiring separate from the first internal power supply wiring and the second internal power supply wiring; a second external power supply wiring extending in the second direction; a third external power supply wiring extending in the second direction; a third contact that connects the third internal power supply wiring and the third external power supply wiring at a fourth connectable position; externally, The semiconductor device according to claim 8 .

13. the first internal power supply wiring includes a first portion arranged along the first direction and a second portion arranged along the second direction; the number of the first contacts is greater than the number of the first portions; The semiconductor device according to claim 8 .

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