Nonvolatile memory and method for controlling nonvolatile memory

Abstract

To provide a nonvolatile memory capable of improving a read speed.SOLUTION: A nonvolatile memory according to an embodiment includes a plurality of memory cells, word lines connected to the plurality of memory cells, and a controller, in which in a read process, the controller: reads data at a first timing, a second timing, and a third timing while a first voltage is being applied to the word lines; calculates a first difference between the numbers of memory cells based on the data read at the first timing and the second timing, a second difference between the numbers of memory cells based on the data read at the second timing and the third timing, and a first value obtained by subtracting the first difference from the second difference; and based on the first value, determines one of the data read at the first timing, the data read at the second timing, and the data read at the third timing as a plurality of first read data from a plurality of memory cells.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] SUMMARY OF THE INVENTION Embodiments relate to non-volatile memories and methods for controlling non-volatile memories. [Background technology]

[0002] NAND flash memories capable of storing data in a nonvolatile manner are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2021 / 0390986 [Patent Document 2] U.S. Patent Application Publication No. 2022 / 0301640 [Patent Document 3] US Patent Application Publication No. 2018 / 0294036 Summary of the Invention [Problem to be solved by the invention]

[0004] A nonvolatile memory capable of improving read speed is provided. [Means for solving the problem]

[0005] A nonvolatile memory according to an embodiment includes a plurality of memory cells, word lines connected to the plurality of memory cells, and a controller configured to read data from the plurality of memory cells by applying a voltage to the word lines, wherein the controller, in a read process for the plurality of memory cells, applies a first voltage to the word lines, reads data from the plurality of memory cells at a first timing while the first voltage is being applied to the word lines, reads data from the plurality of memory cells at a second timing that is later than the first timing, reads data from the plurality of memory cells at a third timing that is later than the second timing, and performs a write operation based on the data read from the plurality of memory cells at the first timing. a first difference between the number of memory cells and the number of memory cells based on the data read from the plurality of memory cells at the second timing, a second difference between the number of memory cells based on the data read from the plurality of memory cells at the second timing and the number of memory cells based on the data read from the plurality of memory cells at the third timing, and a first value obtained by subtracting the first difference from the second difference; and based on the first value, determine any one of the data read from the plurality of memory cells at the first timing, the data read from the plurality of memory cells at the second timing, and the data read from the plurality of memory cells at the third timing as a plurality of first read data from the plurality of memory cells. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of an information processing system including a memory system and a host device according to a first embodiment. [Figure 2] FIG. 1 is a block diagram showing an example of the configuration of a nonvolatile memory according to a first embodiment. [Figure 3] FIG. 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array included in the nonvolatile memory according to the first embodiment. [Figure 4]FIG. 2 is a diagram showing an example of threshold voltage distributions of memory cell transistors included in the nonvolatile memory according to the first embodiment. [Figure 5] FIG. 2 is a block diagram showing an example of the configuration of a sense amplifier module included in the nonvolatile memory according to the first embodiment. [Figure 6] FIG. 2 is a circuit diagram showing an example of the circuit configuration of a sense circuit included in the nonvolatile memory according to the first embodiment. [Figure 7] FIG. 2 is a diagram for explaining an outline of a tracking operation performed in the nonvolatile memory according to the first embodiment. [Figure 8] 6 is a flowchart for explaining a tracking operation in the nonvolatile memory according to the first embodiment. [Figure 9] FIG. 4 is a diagram for explaining an overview of a process for determining an optimal read voltage in a tracking operation in the nonvolatile memory according to the first embodiment. [Figure 10] 6 is a flowchart for explaining a process of determining an optimum read voltage in a tracking operation in the nonvolatile memory according to the first embodiment. [Figure 11] 6 is a timing chart for explaining a sensing operation in a read process during a process of determining an optimal read voltage executed in the nonvolatile memory according to the first embodiment. [Figure 12] 6 is a timing chart for explaining a read process during a process of determining an optimal read voltage in the nonvolatile memory according to the first embodiment. [Figure 13] FIG. 10 is a diagram for explaining an outline of a process for determining an optimum read voltage in a tracking operation in a nonvolatile memory according to a first modified example of the first embodiment. [Figure 14] 10 is a flowchart for explaining a process of determining an optimum read voltage in a tracking operation in a nonvolatile memory according to a first modified example of the first embodiment. [Figure 15] 10 is a timing chart for explaining a read process during a process of determining an optimum read voltage in a nonvolatile memory according to a second modification of the first embodiment. [Figure 16]FIG. 10 is a diagram showing an example of a shift amount table used in the memory system according to the second embodiment. [Figure 17] 10 is a flowchart for explaining a tracking operation in the nonvolatile memory according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration will be assigned the same reference numeral. Furthermore, when multiple components having the same reference numeral are to be distinguished from one another, a subscript will be added to the common reference numeral. Furthermore, when no particular distinction is required between multiple components, the multiple components will be assigned only the common reference numeral, without a subscript. Subscripts include, for example, lowercase letters added to the end of a reference numeral, and indexes indicating an array.

[0008] 1. First embodiment A memory system according to a first embodiment will be described.

[0009] 1.1 Configuration The configuration of the memory system according to the first embodiment will be described.

[0010] 1.1.1 Memory System The overall configuration of the memory system according to the first embodiment will be described with reference to Fig. 1. Fig. 1 is a block diagram showing an example of the configuration of an information processing system including the memory system according to the first embodiment and a host device.

[0011] The memory system 1 includes a nonvolatile memory 10, a memory controller 20, and a volatile memory 30. The nonvolatile memory 10, the memory controller 20, and the volatile memory 30 may be combined to form a single semiconductor device. The memory system 1 may be, for example, a solid state drive (SSD) or SD TM It is a card.

[0012] The memory system 1 communicates with, for example, an external host device 2. The memory system 1 stores data from the host device 2. The memory system 1 also reads data to the host device 2.

[0013] The nonvolatile memory 10 is, for example, a semiconductor memory. The nonvolatile memory 10 includes a plurality of memory cells. The nonvolatile memory 10 stores data in a nonvolatile manner. The nonvolatile memory 10 is, for example, a NAND flash memory. The nonvolatile memory 10 can also be called a memory device 10. The nonvolatile memory 10 is connected to a memory controller 20 by, for example, a NAND bus.

[0014] The NAND bus transmits and receives various signals conforming to the NAND interface via individual signal lines, including, for example, IO<7:0>, / CE, CLE, ALE, / WE, / RE, and / RB.

[0015] The signal IO<7:0> is, for example, an 8-bit signal. The signal IO<7:0> is transmitted and received between the nonvolatile memory 10 and the memory controller 20. The signal IO<7:0> includes an address, a command, and data. The command is a signal for controlling the entire nonvolatile memory 10. The data includes read data and write data. The signal / CE is a chip enable signal. The signal / CE is a signal for enabling the nonvolatile memory 10. The signal CLE is a command latch enable signal. The signal CLE notifies the nonvolatile memory 10 that the signal IO<7:0> sent to the nonvolatile memory 10 while the signal CLE is at an "H (High)" level is a command. The signal ALE is an address latch enable signal. The signal ALE notifies the nonvolatile memory 10 that the signal IO<7:0> sent to the nonvolatile memory 10 while the signal ALE is at an "H" level is an address. The signal / WE is a write enable signal. The signal / WE instructs the nonvolatile memory 10 to take in the signal IO<7:0>. The signal / RE is a read enable signal. The signal / RE instructs the nonvolatile memory 10 to output the signal IO<7:0>. The signal / RB is a ready / busy signal. The signal / RB indicates whether the nonvolatile memory 10 is in a ready state (a state in which it can accept commands from the outside) or a busy state (a state in which it cannot accept commands from the outside).

[0016] The memory controller 20 is configured by an integrated circuit such as an SoC (System-on-a-Chip). The memory controller 20 receives instructions from the host device 2. The functions of each part of the memory controller 20 can be realized by dedicated hardware, a processor that executes programs and firmware, or a combination of these. The memory controller 20 controls the nonvolatile memory 10 based on instructions received from the host device 2. Specifically, the memory controller 20 writes data that is instructed to be written to the nonvolatile memory 10 based on a write instruction received from the host device 2. Furthermore, the memory controller 20 reads data that is instructed to be read by the host device 2 from the nonvolatile memory 10 and transmits the data to the host device 2 based on a read instruction received from the host device 2.

[0017] The volatile memory 30 is, for example, a dynamic random access memory (DRAM). The volatile memory 30 stores firmware for managing the nonvolatile memory 10 and various management information. The volatile memory 30 stores, for example, a predetermined read voltage (default value) for a read process executed in the nonvolatile memory 10. The predetermined read voltage may also be stored in the nonvolatile memory 10.

[0018] 1.1.2 Memory Controller The configuration of the memory controller 20 of the memory system 1 according to the first embodiment will be described again with reference to FIG.

[0019] The memory controller 20 includes a processor (CPU: Central Processing Unit) 21, an internal memory 22, a buffer memory 23, a host I / F (host interface circuit) 24, a NAND I / F (NAND interface circuit) 25, and an ECC (Error Checking and Correcting) circuit 26.

[0020] The processor 21 controls the overall operation of the memory controller 20. The processor 21 issues commands to the nonvolatile memory 10 to instruct it to execute various processes including write processes, read processes, and erase processes, for example.

[0021] The built-in memory 22 is, for example, a semiconductor memory such as an SRAM (Static Random Access Memory). The built-in memory 22 is used as a working area for the processor 21. The built-in memory 22 stores firmware for managing the non-volatile memory 10, various management tables, and the like.

[0022] The buffer memory 23 is, for example, a semiconductor memory such as a DRAM (Dynamic Random Access Memory). The buffer memory 23 temporarily stores write data received from the host device 2, read data received by the memory controller 20 from the non-volatile memory 10, etc. The buffer memory 23 may be provided outside the memory controller 20.

[0023] The host interface circuit 24 is connected to the host device 2 via a host bus. The host bus is, for example, a PCI Express (PCI Express) TM (Peripheral component interconnect express)), UFS (Universal Flash Storage), SD TM Interface: SAS (Serial attached SCSI (small computer system interface)), SATA (Serial ATA (advanced technology attachment)), or NVMe (NVM EXPRESS TM(Non-volatile memory express) bus. The host interface circuit 24 manages communication between the memory controller 20 and the host device 2. For example, the host interface circuit 24 transfers commands and data received from the host device 2 to the processor 21 and buffer memory 23, respectively.

[0024] The NAND interface circuit 25 is connected to the nonvolatile memory 10 via a NAND bus. The NAND bus is a bus that complies with, for example, Toggle NAND (Toggle DDR) or ONFI (Open NAND Flash Interface). The NAND interface circuit 25 controls communication with the nonvolatile memory 10. The NAND interface circuit 25 transmits commands, addresses, and write data to the nonvolatile memory 10 in response to instructions from the processor 21. The NAND interface circuit 25 also receives read data from the nonvolatile memory 10.

[0025] The ECC circuit 26 performs error correction processing on data stored in the nonvolatile memory 10. More specifically, when writing data, the ECC circuit 26 generates parity of an error correction code and adds the parity of the error correction code to the written data. The error correction code is, for example, a hard-decision decoded code such as a BCH (Bose-Chaudhuri-Hocquenghem) code or an RS (Reed-Solomon) code, or a soft-decision decoded code such as an LDPC (Low-Density Parity-Check) code. Furthermore, when reading data, the ECC circuit 26 performs decoding processing of the error correction code and can correct fail bits.

[0026] 1.1.3 Non-volatile memory The configuration of the nonvolatile memory 10 of the memory system 1 according to the first embodiment will be described with reference to Fig. 2. Fig. 2 is a block diagram showing an example of the configuration of the nonvolatile memory according to the first embodiment.

[0027] The nonvolatile memory 10 includes a memory cell array 11, an input / output circuit 12, a logic circuit 13, a register 14, a sequencer 15, a voltage generation circuit 16, a row decoder module 17, a sense amplifier module 18, and an arithmetic circuit 19. Note that some or all of the elements of the register 14, the sequencer 15, the sense amplifier module 18, and the arithmetic circuit 19 may also be referred to as a controller (control circuit).

[0028] The memory cell array 11 includes a plurality of blocks BLK0, BLK1, ..., and BLK(m-1), where m is an integer equal to or greater than 2. Each block BLK is a collection of a plurality of memory cell transistors capable of storing data non-volatilely. Each block BLK is used, for example, as a data erasure unit. The memory cell array 11 is also provided with a plurality of bit lines and a plurality of word lines. One memory cell transistor is associated, for example, with one bit line and one word line.

[0029] The input / output circuit 12 transmits and receives signals IO<7:0> to and from the memory controller 20. The input / output circuit 12 transfers the command and address in the signals IO<7:0> to the register 14. The input / output circuit 12 also transmits and receives data DAT in the signals IO<7:0> to and from the sense amplifier module 18. The data DAT includes write data and read data.

[0030] The logic circuit 13 receives signals / CE, CLE, ALE, / WE, and / RE from the memory controller 20. The logic circuit 13 also transfers a signal / RB to the memory controller 20.

[0031] The register 14 holds commands and addresses. The addresses include a row address and a column address. The row address is used to select a block BLK. The column address is used to select a bit line. The register 14 transfers the row address to the row decoder module 17. The register 14 also transfers the column address to the sense amplifier module 18. The register 14 also transfers the command to the sequencer 15.

[0032] The sequencer 15 controls the entire nonvolatile memory 10 in accordance with a sequence based on the received command.

[0033] The voltage generation circuit 16 generates voltages necessary for operations such as write processing, read processing, and erase processing based on instructions from the sequencer 15. The voltage generation circuit 16 supplies the generated voltages to the memory cell array 11, the row decoder module 17, and the sense amplifier module 18.

[0034] The row decoder module 17 selects a block BLK based on the row address received from the register 14. A voltage is transferred from the voltage generating circuit 16 via the row decoder module 17 to the selected block BLK.

[0035] In a data read process, the sense amplifier module 18 senses the threshold voltage of the memory cell transistor to be read. Then, the sense amplifier module 18 transfers read data based on the sense result to the input / output circuit 12. In a write process, the sense amplifier module 18 transfers write data DAT to the memory cell array 11.

[0036] The arithmetic circuit 19 performs various calculations using data stored in the sense amplifier module 18, based on instructions from the sequencer 15, for example. Note that the above-mentioned various calculations may be executed by the sequencer 15. In this case, the nonvolatile memory 10 does not need to include the arithmetic circuit 19. Furthermore, the arithmetic circuit 19 may be configured within the sense amplifier module 18.

[0037] 1.1.4 Memory Cell Array The configuration of each block BLK included in the memory cell array 11 in the nonvolatile memory 10 will be described with reference to Fig. 3. Fig. 3 is a circuit diagram showing an example of the circuit configuration of the memory cell array included in the nonvolatile memory according to the first embodiment.

[0038] The block BLK includes, for example, four string units SU0, SU1, SU2, and SU3. Hereinafter, when the string units SU0, SU1, SU2, and SU3 are not distinguished from one another, each of the string units SU0, SU1, SU2, and SU3 will be simply referred to as a string unit SU. Each string unit SU includes a plurality of NAND strings NS.

[0039] Each NAND string NS includes, for example, eight memory cell transistors MT0 to MT7 and select transistors ST1 and ST2. Hereinafter, when the memory cell transistors MT0 to MT7 are not distinguished from one another, each of the memory cell transistors MT0 to MT7 will simply be referred to as a memory cell transistor MT. The number of memory cell transistors MT included in each NAND string NS is not limited. Each memory cell transistor MT has a stack gate including a control gate and a charge storage layer. Each memory cell transistor MT is connected in series between one end of the select transistor ST1 and one end of the select transistor ST2.

[0040] In each block BLK, the gates of the select transistors ST1 of the string units SU0 to SU3 are connected to select gate lines SGD0 to SGD3, respectively. That is, each select gate line SGD is connected to only one of the string units SU in the same block BLK. Also, the gates of the select transistors ST2 of all the string units SU in the block BLK are connected to a select gate line SGS. That is, the select gate line SGS is connected to all the string units SU in the same block BLK. Also, the control gates of the memory cell transistors MT0 to MT7 in each block BLK are connected to word lines WL0 to WL7, respectively. That is, word lines WL with the same address are connected to all the string units SU in the same block BLK.

[0041] The other end of the select transistor ST1 is connected to one of a plurality of bit lines BL0 to BL(n-1), where n is an integer equal to or greater than 2. Each bit line BL is connected to the NAND strings NS in the same column in each of a plurality of blocks BLK.

[0042] The other end of the select transistor ST2 is connected to a source line SL, which is shared by, for example, a plurality of blocks BLK.

[0043] As described above, data erasure is performed, for example, on memory cell transistors MT in the same block BLK all at once. In contrast, read and write operations can be performed, for example, on multiple memory cell transistors MT connected to any word line WL in any string unit SU in any block BLK all at once. Such a set of memory cell transistors MT sharing a word line WL in one string unit SU is called, for example, a cell unit CU. That is, a cell unit CU is a set of memory cell transistors MT on which a write or read operation is performed all at once. A cell unit CU corresponds, for example, to a set of one or more memory areas. A write or read operation for one cell unit CU is performed on one of the set of memory areas. Such a unit of memory area is called a "page."

[0044] 1.1.5 Threshold voltage distribution of memory cell transistors The threshold voltage distribution of the memory cell transistors MT included in the nonvolatile memory 10 will be described with reference to FIG. 4. FIG. 4 is a diagram showing an example of the threshold voltage distribution of the memory cell transistors included in the nonvolatile memory according to the first embodiment. In FIG. 4, the vertical axis of the threshold voltage distribution corresponds to the number of memory cell transistors MT, and the horizontal axis corresponds to the threshold voltage of the memory cell transistors MT. In the drawings used below, the number of memory cell transistors MT and the threshold voltage of the memory cell transistors MT are indicated as NMTs and Vth, respectively.

[0045] In the nonvolatile memory 10 according to the first embodiment, for example, eight states are formed depending on the threshold voltages of the multiple memory cell transistors MT. That is, each memory cell transistor MT can have eight states. Hereinafter, the eight states will be referred to as "Er" state, "A" state, "B" state, "C" state, "D" state, "E" state, "F" state, and "G" state, in order from lowest to highest threshold voltage.

[0046] The "Er" state corresponds to, for example, an erased state of data. The threshold voltage of the memory cell transistor MT included in the "Er" state is less than the voltage VA.

[0047] The "A" to "G" states correspond to states in which charges are injected into the charge storage layer of the memory cell transistor MT. The threshold voltage of the memory cell transistor MT in the "A" state is equal to or greater than voltage VA and less than voltage VB (VB>VA). The threshold voltage of the memory cell transistor MT in the "B" state is equal to or greater than voltage VB and less than voltage VC (VC>VB). The threshold voltage of the memory cell transistor MT in the "C" state is equal to or greater than voltage VC and less than voltage VD (VD>VC). The threshold voltage of the memory cell transistor MT in the "D" state is equal to or greater than voltage VD and less than voltage VE (VE>VD). The threshold voltage of the memory cell transistor MT in the "E" state is equal to or greater than voltage VE and less than voltage VF (VF>VE). The threshold voltage of the memory cell transistor MT in the "F" state is equal to or greater than voltage VF and less than voltage VG (VG>VF). The threshold voltage of the memory cell transistor MT in the "G" state is equal to or greater than voltage VG and less than voltage VREAD (VREAD>VG).

[0048] When a voltage is applied to the control gate of a memory cell transistor MT, the memory cell transistor MT is turned on if it has a threshold voltage less than the applied voltage. When a voltage is applied to the control gate of a memory cell transistor MT, the memory cell transistor MT is turned off if it has a threshold voltage equal to or greater than the applied voltage. When a voltage VREAD is applied to the control gate of a memory cell transistor MT, the memory cell transistor MT is turned on regardless of whether the state of the memory cell transistor MT is in the "Er" state to the "G" state.

[0049] Each of the eight states is assigned a different three-bit data. This allows each memory cell transistor MT to hold three bits of data. An example of how data is assigned to the eight states is given below. Below, the data assigned to each state is shown in the order of "high-order bit, middle-order bit, low-order bit" corresponding to the state.

[0050] “Er” state: “1, 1, 1” data, “A” state: “1, 1, 0” data, "B" state: "1, 0, 0" data, “C” state: “0, 0, 0” data, “D” state: “0, 1, 0” data, “E” state: “0, 1, 1” data, “F” state: “0, 0, 1” data, “G” state: “1, 0, 1” data.

[0051] When such data allocation is applied, one page of data (lower page data) made up of lower bits is determined by a read process using each of voltages VA and VE. One page of data (middle page data) made up of middle bits is determined by a read process using each of voltages VB, VD, and VF. One page of data (upper page data) made up of upper bits is determined by a read process using each of voltages VC and VG. Hereinafter, the voltages VA to VG are also referred to as read voltages.

[0052] 1.1.6 Sense Amplifier Module The configuration of the sense amplifier module 18 in the nonvolatile memory 10 will be described with reference to Fig. 5. Fig. 5 is a block diagram showing an example of the configuration of the sense amplifier module included in the nonvolatile memory according to the first embodiment.

[0053] The sense amplifier module 18 includes a plurality of sense amplifier units SAU connected to the plurality of bit lines BL, respectively.

[0054] Each sense amplifier unit SAU includes, for example, latch circuits SDL, ADL, BDL, CDL, TDL, and XDL, and a sense circuit SA. The latch circuits SDL, ADL, BDL, CDL, TDL, and XDL, and the sense circuit SA are connected via a bus LBUS. As a result, the latch circuits SDL, ADL, BDL, CDL, TDL, and XDL, and the sense circuit SA are connected so as to transmit and receive data to and from each other via the bus LBUS.

[0055] The latch circuit XDL is used for transmitting and receiving data DAT between the sense amplifier unit SAU and the input / output circuit 12, for example.

[0056] The latch circuits SDL, ADL, BDL, CDL, and TDL temporarily store, for example, write data or read data.

[0057] Although not shown, the latch circuit SDL includes a first inverter, a second inverter, a first transistor, and a second transistor. The first transistor and the second transistor are, for example, low-voltage N-type MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors). An input node of the first inverter is connected to a node LAT_S. An output node of the first inverter is connected to a node INV_S. An input node of the second inverter is connected to a node INV_S. An output node of the second inverter is connected to a node LAT_S. One end of the first transistor is connected to a bus LBUS. The other end of the first transistor is connected to a node INV_S. One end of the second transistor is connected to a bus LBUS. The other end of the second transistor is connected to a node LAT_S. The latch circuit SDL stores data at the node LAT_S. Meanwhile, the latch circuit SDL stores inverted data of the data stored at the node LAT_S at the node INV_S. The latch circuits ADL, BDL, CDL, and TDL have the same configuration as the latch circuit SDL, and therefore a description of these configurations will be omitted.

[0058] In a read process, the sense circuit SA senses the current flowing through the corresponding bit line BL or the voltage of the bit line BL to determine whether the read data is "0" or "1." The following description will be given of a case in which the sense circuit SA senses the current flowing through the bit line BL. The sense amplifier unit SAU determines the read data at a timing corresponding to, for example, a signal STB generated by the sequencer 15. In a write process, the sense circuit SA applies a voltage to the bit line BL based on the write data. The sense circuit SA controls the bit line BL according to, for example, the data held in the latch circuit SDL.

[0059] The bus LBUS of each sense amplifier unit SAU is connected to, for example, an arithmetic circuit 19. As a result, the arithmetic circuit 19 is configured to be able to perform arithmetic operations using data held in, for example, latch circuits SDL, ADL, BDL, CDL, and TDL in each sense amplifier unit SAU.

[0060] The configuration of the sense amplifier unit SAU is not limited to the above and can be modified in various ways. For example, the number of latch circuits included in the sense amplifier unit SAU can be designed according to the number of bits of data held by the memory cell transistor MT.

[0061] 1.1.7 Sense Circuit An example of the configuration of the sense circuit SA of the sense amplifier unit SAU included in the sense amplifier module 18 will be described with reference to Fig. 6. Fig. 6 is a circuit diagram showing an example of the circuit configuration of the sense amplifier circuit provided in the nonvolatile memory according to the first embodiment. In Fig. 6, the circuit configuration of the sense circuit SA is shown together with other configurations of the sense amplifier unit SAU.

[0062] The sense circuit SA includes, for example, transistors Tr0 to Tr7 and a capacitor CAE. The transistor Tr0 is, for example, a P-type MOSFET. The transistors Tr1 to Tr7 are, for example, N-type MOSFETs.

[0063] For example, a voltage VDD is applied to the source of the transistor Tr0. The drain of the transistor Tr0 is connected to the transistors Tr1 and Tr2. The gate of the transistor Tr0 is connected to the node INV_S in the latch circuit SDL, for example.

[0064] The drain of the transistor Tr1 is connected to the drain of the transistor Tr0, the source of the transistor Tr1 is connected to the transistors Tr3, Tr4, and Tr5, and the gate of the transistor Tr1 receives a signal BLX.

[0065] The drain of the transistor Tr2 is connected to the drain of the transistor Tr0 and the drain of the transistor Tr1, the source of the transistor Tr2 is connected to the node SEN, and the signal HLL is input to the gate of the transistor Tr2.

[0066] The drain of the transistor Tr3 is connected to the node SEN, the source of the transistor Tr3 is connected to the source of the transistor Tr1, and the gate of the transistor Tr3 receives the signal XXL.

[0067] The drain of the transistor Tr4 is connected to the source of the transistor Tr1 and the source of the transistor Tr3. The signal BLC is input to the gate of the transistor Tr4. The source of the transistor Tr4 is connected to the corresponding bit line BL. The transistor Tr4 functions as a clamp transistor that clamps the voltage of the bit line BL in response to the signal BLC.

[0068] The drain of transistor Tr5 is connected to the source of transistor Tr1, the source of transistor Tr3, and the drain of transistor Tr4. The source of transistor Tr5 is connected to node SRCGND. For example, voltage VSS is applied to node SRCGND. Voltage VSS is a ground voltage. The gate of transistor Tr5 is connected to node INV_S, for example.

[0069] The source of the transistor Tr6 is grounded, the gate of the transistor Tr6 is connected to the node SEN, and the transistor Tr6 functions as a sense transistor that senses the voltage of the node SEN.

[0070] The drain of the transistor Tr7 is connected to the bus LBUS, the source of the transistor Tr7 is connected to the drain of the transistor Tr6, and the signal STB is input to the gate of the transistor Tr7.

[0071] One electrode of the capacitor CAE is connected to the node SEN, and the other electrode of the capacitor CAE receives the clock signal CLK.

[0072] The signals BLX, HLL, XXL, BLC, and STB, and the clock signal CLK are each generated by, for example, a sequencer 15 .

[0073] In a read operation, for example, when node INV_S is set to the "L (Low)" level, transistor Tr0 is turned on. Furthermore, for example, when signals BLX and BLC are set to the "H" level, transistors Tr1 and Tr4 are turned on. As a result, the bit line BL is precharged to a voltage corresponding to signal BLC via transistors Tr0, Tr1, and Tr4. Furthermore, for example, when signal HLL is set to the "H" level, transistor Tr2 is turned on. As a result, node SEN is precharged to voltage VDD.

[0074] For example, when signal HLL is changed from "H" to "L", transistor Tr2 is changed from on to off. Then, when signal XXL is changed to "H", transistor Tr3 is changed to on. When the memory cell transistor MT to be read is turned on, current flows from bit line BL to source line SL, causing the voltage at node SEN to drop. When the voltage at node SEN drops below the threshold voltage of transistor Tr6, transistor Tr6 is turned off. On the other hand, when the memory cell transistor MT to be read is turned off, no current flows from bit line BL to source line SL, so the voltage at node SEN remains approximately constant. Furthermore, transistor Tr6 is turned on. Note that, hereinafter, the memory cell transistor MT to be read is also referred to as the selected memory cell transistor MT. Note that, hereinafter, the memory cell transistor MT not to be read is also referred to as the unselected memory cell transistor MT. Note that, hereinafter, the selected memory cell transistor MT that is turned on is also referred to as the on cell. Note that, hereinafter, the selected memory cell transistor MT that is turned off is also referred to as the off cell.

[0075] Then, for example, when the signal STB is changed from the "L" level to the "H" level, the transistor Tr7 is changed from the off state to the on state. As a result, a voltage corresponding to the on state and off state of the transistor Tr6 is transferred to the bus LBUS. When the transistor Tr6 is turned off, the bus LBUS is set to the "H" level. When the transistor Tr6 is turned on, the bus LBUS is set to the "L" level. When the bus LBUS is at the "H" level, the sense amplifier unit SAU holds "1" data in, for example, the latch circuit SDL. When the bus LBUS is at the "L" level, the sense amplifier unit SAU holds "0" data in, for example, the latch circuit SDL. The data held in the latch circuit SDL is transferred to, for example, the latch circuits ADL, BDL, CDL, or TDL.

[0076] 1.2 Operation The operation of the memory system 1 according to the first embodiment will be described below. The tracking operation executed in the nonvolatile memory 10 will be described below.

[0077] 1.2.1 Tracking behavior overview An overview of the tracking operation performed in the nonvolatile memory 10 according to the first embodiment will be described with reference to Fig. 7. Fig. 7 is a diagram for explaining the overview of the tracking operation performed in the nonvolatile memory according to the first embodiment. Note that, for simplicity of explanation, Fig. 7 shows only the "Er" state and the "A" state.

[0078] The tracking operation is performed, for example, when it is assumed that data cannot be read correctly with a default read voltage. Note that, hereinafter, when referring to a default read voltage, "def" is added to the end of each read voltage VA to VG. The read voltage is also simply referred to as the read voltage Vdef.

[0079] 7A, immediately after writing, the threshold voltage distributions of the "Er" state and the "A" state are different from each other. Therefore, correct data can be read by using a predetermined read voltage VAdef between the "Er" state and the "A" state as the read voltage VA.

[0080] However, the threshold voltage of a memory cell transistor MT can fluctuate due to various factors. For example, the charge injected into the charge storage layer of the memory cell transistor MT may escape from the charge storage layer over time. This may result in a decrease in the threshold voltage of the memory cell transistor MT. Furthermore, for example, when a read operation is repeatedly performed on a certain cell unit CU, as described below, the voltage VREAD is repeatedly applied to the gate of the memory cell transistor MT of a cell unit CU adjacent to the cell unit CU. This may result in an increase in the threshold voltage of the memory cell transistor MT. In other words, disturbance may occur. These factors may widen the distribution width of the threshold voltages for each state or change the most frequent value of the threshold voltage distribution for each state. As a result, as shown in Figure 7B, adjacent distributions may overlap. When adjacent distributions overlap, when a read operation is performed using the read voltage VAdef, data different from that read from the memory cell transistor MT corresponding to the shaded area in Figure 7B may be read. More specifically, in the "Er" state of the threshold voltage distribution, read data from memory cell transistors MT having a threshold voltage equal to or greater than the read voltage VAdef will be a fail bit. Also, in the "A" state of the threshold voltage distribution, read data from memory cell transistors MT having a threshold voltage less than the read voltage VAdef will be a fail bit. If the number of fail bits exceeds the number of error correctable bits of the ECC circuit 26, the data cannot be correctly corrected.

[0081] In such a case, the number of fail bits can be reduced by using read data at an optimal read voltage that is shifted by a certain voltage from the read voltage Vdef. In (B) of Figure 7, the optimal read voltage is shown as a read voltage VAopt.

[0082] In the first embodiment, the tracking operation is, for example, an operation of determining an optimal read voltage through a read process, and determining the data of the upper page, middle page, or lower page stored in the cell unit CU based on the read data at the determined optimal read voltage.

[0083] 1.2.2 Overall operation The overall operation of the tracking operation of the memory system 1 according to the first embodiment will be described with reference to FIG. 8. FIG. 8 is a flowchart for explaining the tracking operation in the nonvolatile memory according to the first embodiment. Note that, although an example in which the tracking operation is performed for the lower page will be described below, the present invention is not limited to this. The same applies to the case in which the tracking operation is performed for the upper page or the middle page.

[0084] The nonvolatile memory 10 receives a read command from the memory controller 20 to instruct the nonvolatile memory 10 to execute a read process (S1).

[0085] When the read command is received as described above, the nonvolatile memory 10 determines an optimum read voltage for each read voltage in the page (target page) that is the target of the tracking operation (S2). That is, a process of determining the optimum read voltage is executed. The process of determining the optimum read voltage will be described later.

[0086] Furthermore, the nonvolatile memory 10 determines the page data stored in the cell unit CU based on the read data at each of the determined optimum read voltages.

[0087] Then, the nonvolatile memory 10 outputs the determined page data to the memory controller 20 (S3).

[0088] 1.2.3 Determining the optimal read voltage An overview of the process of determining an optimal read voltage in a tracking operation in the nonvolatile memory 10 according to the first embodiment will be described with reference to Fig. 9. Fig. 9 is a diagram for explaining the overview of the process of determining an optimal read voltage in a tracking operation in the nonvolatile memory according to the first embodiment.

[0089] In the process of determining the optimal read voltage, the nonvolatile memory 10 executes a read process on the target page. In this read process, for each read voltage, read data is read at a reference read voltage, a read voltage obtained by subtracting a predetermined voltage from the reference read voltage, and a read voltage obtained by adding a predetermined voltage to the reference read voltage. The reference read voltage is, for example, a read voltage Vdef. The read process will be described later.

[0090] In the following, for each read voltage, a "2" is added to the end of the read voltage as a reference read voltage. This read voltage is also simply referred to as read voltage V2. For each read voltage, a "1" is added to the end of the read voltage (V2-ΔV) obtained by subtracting a predetermined voltage (ΔV) from the read voltage V2. This read voltage is also simply referred to as read voltage V1. For each read voltage, a "3" is added to the end of the read voltage (V2+ΔV) obtained by adding a predetermined voltage to the read voltage V2. This read voltage is also simply referred to as read voltage V3.

[0091] Furthermore, the calculation circuit 19 performs calculations on the number of ON cells when the read process is performed using each of the read voltages V1, V2, and V3 based on the read results. Note that, hereinafter, the number of ON cells when the read process is performed using each read voltage is also simply referred to as the number of ON cells at that read voltage.

[0092] In the calculation of the number of ON cells, the calculation circuit 19 calculates a difference Δ1 between the number of ON cells at read voltage V1 and the number of ON cells at read voltage V2, and a difference Δ2 between the number of ON cells at read voltage V2 and the number of ON cells at read voltage V3.

[0093] As will be described later, the arithmetic circuit 19 determines an optimum read voltage from the read voltages V1, V2, and V3 based on the calculated differences Δ1 and Δ2.

[0094] 1.2.4 Flowchart of optimal read voltage determination process The process of determining the optimum read voltage in the tracking operation in the nonvolatile memory 10 according to the first embodiment will be further described with reference to Fig. 10. Fig. 10 is a flowchart for explaining the process of determining the optimum read voltage in the tracking operation in the nonvolatile memory according to the first embodiment. The following describes a flowchart for one of the read voltages related to the target page.

[0095] In the process of determining the optimum read voltage, each sense amplifier unit SAU stores read data at the read voltage V1 for the selected memory cell transistor MT corresponding to the sense amplifier unit SAU in, for example, the latch circuit ADL (S11). Then, the process proceeds to S12.

[0096] Furthermore, each sense amplifier unit SAU stores the read data at the read voltage V2 for the selected memory cell transistor MT corresponding to that sense amplifier unit SAU in, for example, the latch circuit BDL (S12).Then, the process proceeds to S13.

[0097] Then, each sense amplifier unit SAU stores the read data at voltage V3 for the selected memory cell transistor MT corresponding to that sense amplifier unit SAU in, for example, the latch circuit CDL (S13).Then, the process proceeds to S14.

[0098] The arithmetic circuit 19 calculates the difference Δ1 based on the read data stored in the latch circuit ADL and the read data stored in the latch circuit BDL (S14). The arithmetic circuit 19 calculates the difference Δ1 based on, for example, an exclusive OR operation (XOR operation) of the two read data stored in the latch circuits ADL and BDL in each sense amplifier unit SAU. More specifically, the arithmetic circuit 19 calculates the difference Δ1 by, for example, counting the number of bits that are “1” data among the data obtained by the exclusive OR operation in each of the multiple sense amplifier units SAU. Then, the process proceeds to S15. Note that, although the flowchart in FIG. 10 shows an example in which the difference Δ1 is calculated after the read data at voltage V3 is stored in the latch circuit CDL, this is not limiting. The arithmetic circuit 19 may calculate the difference Δ1 after the read data at read voltages V1 and V2 are stored in the latch circuits ADL and BDL, respectively, and before the read data at voltage V3 is stored in the latch circuit CDL.

[0099] The arithmetic circuit 19 also calculates the difference Δ2 based on the read data stored in the latch circuit BDL and the read data stored in the latch circuit CDL (S15). The arithmetic circuit 19 calculates the difference Δ2 based on, for example, an exclusive OR operation of the two read data stored in the latch circuits BDL and CDL in each sense amplifier unit SAU. More specifically, the arithmetic circuit 19 calculates the difference Δ2 by, for example, counting the number of bits that are "1" data among the data obtained by the exclusive OR operation in each of the multiple sense amplifier units SAU. Then, the process proceeds to S16.

[0100] Then, the arithmetic circuit 19 determines whether the difference Δ2 is greater than the difference Δ1 (Δ1<Δ2) (S16). In the process of S16, the arithmetic circuit 19 calculates, for example, a value (Δ2-Δ1) by subtracting the difference Δ1 from the difference Δ2. Then, the arithmetic circuit 19 makes the above determination based on the value (Δ2-Δ1). That is, the arithmetic circuit 19 determines whether the value (Δ2-Δ1) is greater than 0. The value (Δ2-Δ1) can be said to be the second-order differential value of the number of ON cells at the read voltage V2. If the difference Δ2 is greater than the difference Δ1 (S16; YES), the process proceeds to S17. If the difference Δ2 is equal to or less than the difference Δ1 (S16; NO), the process proceeds to S18.

[0101] If the difference Δ2 is greater than the difference Δ1 (S16; YES), the calculation circuit 19 determines whether the value (Δ2-Δ1) is greater than the value Δth1 ((Δ2-Δ1)>Δth1) (S17). The value Δth1 is a positive value. The value Δth1 may be set according to the read voltage. If the value (Δ2-Δ1) is greater than the value Δth1 (S17; YES), the process proceeds to S19. If the value (Δ2-Δ1) is equal to or less than the value Δth1 (S17; NO), the process proceeds to S20.

[0102] If the difference Δ2 is less than or equal to the difference Δ1 (S16; NO), the arithmetic circuit 19 determines whether the value (Δ1-Δ2) (-(Δ2-Δ1)) obtained by subtracting the difference Δ2 from the difference Δ1 is greater than the value Δth2 ((Δ1-Δ2)>Δth2) (S18). The value Δth2 is a positive value. The value Δth2 is, for example, equal to the value Δth1. The value Δth2 may be set according to the read voltage. However, this is not a limitation, and the value Δth2 may be a value different from the value Δth1. If the value (Δ1-Δ2) is greater than the value Δth2 (S18; YES), the process proceeds to S21. If the value (Δ1-Δ2) is less than or equal to the value Δth2 (S18; NO), the process proceeds to S20.

[0103] If the value (Δ2−Δ1) is greater than the value Δth1 (S17; YES), the arithmetic circuit 19 determines the read voltage V1 as the optimum read voltage, and the process ends.

[0104] If the value (Δ2-Δ1) is equal to or less than the value Δth1 (S17; NO), and if the value (Δ1-Δ2) is equal to or less than the value Δth2 (S18; NO), the arithmetic circuit 19 determines the read voltage V2 to be the optimum read voltage. That is, if the value (Δ2-Δ1) is equal to or less than the value Δth1 and equal to or greater than the value (-Δth2) (-Δth2≦(Δ2-Δ1)≦Δth1), the arithmetic circuit 19 determines the read voltage V2 to be the optimum read voltage. Then, the process ends.

[0105] If the value (Δ1−Δ2) is greater than the value Δth2 (S18; YES), the arithmetic circuit 19 determines the voltage V3 as the optimum read voltage, and the process then ends.

[0106] In this manner, the optimum read voltage is determined for each read voltage.

[0107] In the process of determining the optimum read voltage, the optimum read voltage is determined for each of the plurality of read voltages of the target page in order. Then, the arithmetic circuit 19, for example, identifies read data corresponding to each of the plurality of read voltages and determines the page data.

[0108] In determining the page data, the sense amplifier unit SAU stores, in the latch circuit TDL, the read data at the optimal read voltage, among the read data stored in the latch circuits ADL, BDL, and CDL, for the first read voltage determined among the multiple read voltages for the target page. The arithmetic circuit 19 performs an exclusive NOR (XNOR) operation on the read data at the optimal read voltage, among the read data stored in the latch circuits ADL, BDL, and CDL, for the second or subsequent read voltages determined among the multiple read voltages for the target page, and the data stored in the latch circuit TDL. The sense amplifier unit SAU then stores the result of the exclusive NOR operation on the read data at the optimal read voltage determined last among the multiple read voltages for the target page and the data stored in the latch circuit TDL. Hereinafter, the data stored in the latch circuit TDL will also be referred to as data based on the read data at the optimal read voltage.

[0109] 1.2.5 Read process The read process executed in the process of determining the optimum read voltage will be described below: In this read process, read data for a plurality of read voltages in the target page is read out in order.

[0110] 1.2.5.1 Sense Operation The sense operation in the read process executed in the process of determining the optimum read voltage will be described with reference to Fig. 11. Fig. 11 is a timing chart for explaining the sense operation in the read process when the process of determining the optimum read voltage is executed in the nonvolatile memory according to the first embodiment. The vertical axis of Fig. 11 represents the voltage of the node SEN corresponding to the memory cell transistor MT to be read.

[0111] The sense operation is an operation that determines whether or not the threshold voltage Vth of the memory cell transistor MT has reached the determination level in the read process.

[0112] When the charge of the node SEN is transferred to the bit line BL during the sense period, the voltage of the node SEN decreases. At this time, the rate at which the voltage of the node SEN decreases varies depending on the threshold voltage Vth of the memory cell transistor MT. For example, a memory cell transistor MT whose threshold voltage Vth is less than or equal to the read voltage VL (Vth≦VL) becomes a strong on-state. As a result, the voltage of the node SEN decreases rapidly. Hereinafter, a memory cell transistor MT that has become on-state and whose threshold voltage Vth is less than or equal to the read voltage VL is also referred to as a first on-cell. Also, for example, a memory cell transistor MT whose threshold voltage Vth is higher than the read voltage VL and less than or equal to the voltage VM (VL<Vth≦VM) becomes a weaker on-state compared to the first on-cell. As a result, the voltage of the node SEN decreases more gently compared to the first on-cell. Hereinafter, a memory cell transistor MT that has become a weaker on-state compared to the first on-cell and whose threshold voltage Vth is higher than the read voltage VL and less than or equal to the voltage VM is also referred to as a second on-cell. Also, for example, a memory cell transistor MT whose threshold voltage Vth is higher than the voltage VM and less than or equal to the read voltage VH (VM<Vth≦VH) becomes a weaker on-state compared to the second on-cell. As a result, the voltage of the node SEN decreases more gently compared to the second on-cell. Hereinafter, a memory cell transistor MT that has become on-state and whose threshold voltage Vth is higher than the voltage VM and less than or equal to the read voltage VH is also referred to as a third on-cell. Also, for example, a memory cell transistor MT whose threshold voltage Vth is higher than the read voltage VH (VH<Vth) becomes an off-state. As a result, the voltage of the node SEN hardly decreases. Hereinafter, a memory cell transistor MT that has become off-state and whose threshold voltage Vth is higher than the read voltage VH is also referred to as an off-cell.

[0113] Based on the above relationship, a sense period Tsen1 is set to sense whether the threshold voltage Vth is equal to or less than the read voltage VL. The length of the sense period Tsen1 is set so that the voltage at the node SEN corresponding to the memory cell transistor MT whose threshold voltage Vth is equal to or less than the read voltage VL falls below the determination level, and the voltage at the node SEN corresponding to the memory cell transistor MT whose threshold voltage Vth is higher than the read voltage VL rises above the determination level. The sense period Tsen1 is the period from time t0 when the charge at the node SEN starts to be transferred to the bit line BL to time t1.

[0114] At the end of the sense period Tsen1, the sense amplifier module 18 determines whether the voltage at the node SEN falls below the determination level, thereby determining whether the threshold voltage Vth of the memory cell transistor MT is equal to or lower than the read voltage VL.

[0115] In addition, a sense period Tsen2 is set to sense whether the threshold voltage Vth is equal to or less than the read voltage VM. The length of the sense period Tsen2 is set so that the voltage of the node SEN corresponding to the memory cell transistor MT whose threshold voltage Vth is equal to or less than the voltage VM falls below the determination level, and the voltage of the node SEN corresponding to the memory cell transistor MT whose threshold voltage Vth is higher than the voltage VM rises above the determination level. The sense period Tsen2 is the period from time t0 to time t2. Time t2 is a time after time t1.

[0116] At the end of the sense period Tsen2, the sense amplifier module 18 determines whether the voltage at the node SEN is below the determination level, thereby determining whether the threshold voltage Vth of the memory cell transistor MT is equal to or lower than the voltage VM.

[0117] Furthermore, a sense period Tsen3 is set to sense whether the threshold voltage Vth is equal to or less than the read voltage VH. The length of the sense period Tsen3 is set so that the voltage at the node SEN corresponding to the memory cell transistor MT whose threshold voltage Vth is equal to or less than the read voltage VH falls below the determination level, and the voltage at the node SEN corresponding to the memory cell transistor MT whose threshold voltage Vth is higher than the read voltage VH rises above the determination level. The sense period Tsen3 is the period from time t0 to time t3. Time t3 is a time after time t2.

[0118] At the end of the sense period Tsen3, the sense amplifier module 18 determines whether the voltage at the node SEN is below the determination level, thereby determining whether the threshold voltage Vth of the memory cell transistor MT is equal to or lower than the read voltage VH.

[0119] In the first embodiment, in a read process, for example, a voltage V2 is applied to the word line WL. Also, the read VL, VM, and VH are set to read voltages V1, V2, and V3, respectively. Then, it is determined whether the threshold voltage Vth of the memory cell transistor MT is equal to or lower than the read voltage V1, whether the threshold voltage Vth of the memory cell transistor MT is equal to or lower than the read voltage V2, and whether the threshold voltage Vth of the memory cell transistor MT is equal to or lower than the read voltage V1.

[0120] 1.2.5.2 Timing chart for read processing The voltage of each wiring during a read process will be described with reference to FIG. 12. FIG. 12 is a timing chart for explaining a read process during a process for determining an optimal read voltage in the nonvolatile memory according to the first embodiment. FIG. 12 shows a timing chart for when the target page is a lower page. Note that, hereinafter, a word line WL corresponding to a selected memory cell transistor MT will be referred to as a selected word line WL. Also, hereinafter, a word line WL corresponding to an unselected memory cell transistor MT will be referred to as an unselected word line WL.

[0121] At time t11, the row decoder module 17 applies the voltage VREAD to the selected word line WL and the unselected word lines WL.

[0122] At time t12, the row decoder module 17 applies a voltage VE2 to the selected word line WL.

[0123] At time t13, the sense amplifier module 18 applies the voltage VBL to the bit line BL. That is, the bit line BL is precharged. Also, the voltage generation circuit 16 applies the voltage VSL to the source line SL.

[0124] At time t14, the sequencer 15 changes the signal HLL from the "L" level to the "H" level to turn on the transistor Tr2, thereby precharging the node SEN with the voltage VDD in the sense amplifier unit SAU.

[0125] At time t15, the sequencer 15 changes the signal XXL from “L” level to “H” level to turn on transistor Tr3. Then, during a sense period Tsen1 from time t15 to time t16, it is determined whether the threshold voltage Vth is equal to or lower than the read voltage V1. More specifically, if the threshold voltage of the selected memory cell transistor MT is higher than the read voltage V1 and lower than the voltage V2 (second ON cell), higher than the voltage V2 and lower than the read voltage V3 (third ON cell), or higher than the read voltage V3 (off cell), the voltage of node SEN is maintained at “H” level, which turns on transistor Tr6, at time t16. If the threshold voltage of the selected memory cell transistor MT is lower than the read voltage V1 (first ON cell), the voltage of node SEN drops to “L” level, which turns off transistor Tr6, at time t16.

[0126] At time t16, the sequencer 15 changes the signal STB from the "L" level to the "H" level voltage. Then, the sequencer 15 maintains the signal STB at the "H" level voltage for a predetermined period. This causes the transistor Tr7 in the sense amplifier unit SAU to be turned on. As a result, when the transistor Tr6 is off, the voltage of the bus LBUS is set to the "H" level. On the other hand, when the transistor Tr6 is on, the voltage of the bus LBUS is set to the "L" level. When the bus LBUS is at the "H" level, "1" data is stored in the latch circuit ADL. Also, when the bus LBUS is at the "L" level, "0" data is stored in the latch circuit ADL. That is, the read data is stored in S11.

[0127] During the sense period Tsen2 from time t15 to time t17, it is determined whether the threshold voltage Vth is equal to or lower than voltage V2. More specifically, if the threshold voltage of the selected memory cell transistor MT is higher than voltage V2 and equal to or lower than read voltage V3 (if it is a third ON cell), or if it is higher than read voltage V3 (if it is an OFF cell), the voltage of node SEN is maintained at an "H" level voltage that turns on transistor Tr6 at time t17. If the threshold voltage of the selected memory cell transistor MT is equal to or lower than read voltage V1 (if it is a first ON cell), or if it is higher than read voltage V1 and equal to or lower than voltage V2 (if it is a second ON cell), the voltage of node SEN drops to an "L" level voltage that turns off transistor Tr6 at time t17.

[0128] At time t17, the sequencer 15 changes the signal STB from the "L" level to the "H" level. Then, the sequencer 15 maintains the signal STB at the "H" level for a predetermined period. As a result, when the transistor Tr6 is in the off state, the voltage of the bus LBUS is set to the "H" level. On the other hand, when the transistor Tr6 is in the on state, the voltage of the bus LBUS is set to the "L" level. When the bus LBUS is at the "H" level, "1" data is stored in the latch circuit BDL. Also, when the bus LBUS is at the "L" level, "0" data is stored in the latch circuit BDL. In other words, the read data is stored in S12.

[0129] During the sense period Tsen3 from time t15 to time t18, it is determined whether the threshold voltage Vth is equal to or lower than the read voltage V3. More specifically, if the threshold voltage of the selected memory cell transistor MT is higher than the read voltage V3 (if it is an off cell), the voltage of the node SEN is maintained at an "H" level voltage that turns on the transistor Tr6 at time t18. If the threshold voltage of the selected memory cell transistor MT is equal to or lower than the read voltage V1 (if it is a first on cell), higher than the read voltage V1 and lower than or equal to the voltage V2 (if it is a second on cell), or higher than the voltage V2 and lower than or equal to the read voltage V3 (if it is a third on cell), the voltage of the node SEN drops to an "L" level voltage that turns off the transistor Tr6 at time t18.

[0130] At time t18, the sequencer 15 changes the signal STB from the "L" level to the "H" level. Then, the sequencer 15 maintains the signal STB at the "H" level for a predetermined period. As a result, when the transistor Tr6 is in the off state, the voltage of the bus LBUS is set to the "H" level. On the other hand, when the transistor Tr6 is in the on state, the voltage of the bus LBUS is set to the "L" level. When the bus LBUS is at the "H" level, "1" data is stored in the latch circuit CDL. Also, when the bus LBUS is at the "L" level, "0" data is stored in the latch circuit CDL. In other words, the read data is stored in S13.

[0131] At time t19, the sequencer 15 changes the signal XXL from "H" level to "L" level to turn off the transistor Tr3.

[0132] In this manner, read data is acquired at the read voltages VE1, VE2, and VE3.

[0133] The calculation of the difference Δ1 (processing of S14), the calculation of the difference Δ2 (processing of S15), and the storage of the data based on the read data at the optimum read voltage in the latch circuit TDL are performed, for example, before the time (time t23) when the read data at the next read voltage V1 (voltage VA1) is stored in the latch circuit ADL.

[0134] At time t20, the row decoder module 17 applies a voltage VA2 to the selected word line WL, and the voltage of the node SEN is set to the voltage VSS.

[0135] The operation from time t21 to time t26 is substantially the same as the operation from time t14 to time t19, except that read data at read voltages VA1, VA2, and VA3 are obtained instead of read data at read voltages VE1, VE2, and VE3, respectively.

[0136] At time t27, the row decoder module 17 applies voltage VSS to the selected word line WL and unselected word lines WL. The sense amplifier module 18 applies voltage VSS to the bit line BL. The voltage generation circuit 16 applies voltage VSS to the source line SL. The voltage of node SEN is set to voltage VSS.

[0137] In this manner, the read process for the read voltages VE and VA is executed.

[0138] 1.3 Effects According to the first embodiment, it is possible to improve the read speed of the nonvolatile memory 10. The effects of the first embodiment will be described below.

[0139] The nonvolatile memory 10 according to the first embodiment includes a memory cell array 11, an input / output circuit 12, a logic circuit 13, a register 14, a sequencer 15, a voltage generation circuit 16, a row decoder module 17, a sense amplifier module 18, and an arithmetic circuit 19. During a read process in a tracking operation, the sense amplifier module 18 senses whether the threshold voltage of the memory cell transistor MT is equal to or lower than voltage V1, whether the threshold voltage of the memory cell transistor MT is equal to or lower than voltage V2, and whether the threshold voltage of the memory cell transistor MT is equal to or lower than voltage V3. Based on the results of these senses, the arithmetic circuit 19 calculates a difference Δ1 between the number of memory cell transistors MT whose threshold voltages fall within the range equal to or lower than voltage V1 and the number of memory cell transistors whose threshold voltages fall within the range equal to or lower than voltage V2, and a difference Δ2 between the number of memory cell transistors MT whose threshold voltages fall within the range equal to or lower than voltage V2 and the number of memory cell transistors whose threshold voltages fall within the range equal to or lower than voltage V3. The arithmetic circuit 19 then determines an optimal read voltage based on the value (Δ2-Δ1). Then, the arithmetic circuit 19 determines the data based on the optimum read voltage. With the above configuration, when reading data from the nonvolatile memory 10, it is possible to improve the read speed while ensuring accuracy.

[0140] To further elaborate, when determining the optimal read voltage, the nonvolatile memory selects two read voltages that are estimated to be optimal read voltages from, for example, three or more optimal read voltage options. When determining which of the two selected read voltages is the optimal read voltage, the nonvolatile memory may determine the lower read voltage or the higher read voltage as the optimal read voltage. In this case, whether to select the lower read voltage or the higher read voltage of the two selected read voltages is preset. However, in this case, the read voltage that results in the most failed bits may be determined as the optimal read voltage, which may result in a decrease in the accuracy of the read process.

[0141] To improve the accuracy of the read process, the nonvolatile memory further searches for an optimal read voltage by, for example, estimating the threshold voltage distribution by interpolation between the two selected read voltages. However, in this case, the read speed is slowed down by performing the further search operation and the read process (read-back) using the determined optimal read voltage.

[0142] According to the first embodiment, the nonvolatile memory 10 determines one of the read voltages V1, V2, and V3 as the optimal read voltage based on the difference between the difference Δ1 in the number of ON cells at the read voltages V1 and V2 and the difference Δ2 in the number of ON cells at the read voltages V2 and V3. In other words, the nonvolatile memory 10 can determine the read voltage closest to the true optimal read voltage among the read voltages V1, V2, and V3 as the optimal read voltage. This allows the nonvolatile memory 10 according to the first embodiment to suppress delays due to the search for the optimal read voltage and to suppress degradation in the accuracy of the read process. Therefore, the nonvolatile memory 10 according to the first embodiment can improve the read speed.

[0143] Furthermore, according to the first embodiment, when determining the optimal read voltage for each read voltage, the nonvolatile memory 10 senses the threshold voltage Vth of the memory cell transistor MT in multiple different sense periods Tsen1, Tsen2, and Tsen3 while maintaining the voltage applied to the selected word line WL at read voltage V2. This makes it possible to obtain data equivalent to the read data obtained when a read process is performed by applying different read voltages V1, V2, and V3 to the selected word line WL. This also allows the nonvolatile memory 10 according to the first embodiment to improve the read speed.

[0144] 2. Modification of the First Embodiment A modification of the first embodiment will be described.

[0145] 2.1 First Modification of the First Embodiment In the first modification of the first embodiment, the optimum read voltage can be determined based on the difference between the number of ON cells at a read voltage obtained by adding a predetermined voltage to the read voltage V3, as well as the difference between the differences Δ1 and Δ2, and the number of ON cells at the read voltage V3. The configuration of the memory system according to the first modification of the first embodiment is the same as the configuration of the memory system according to the first embodiment. Below, the operation of the memory system according to the first modification of the first embodiment will be described, focusing mainly on the differences from the configuration and operation of the memory system according to the first embodiment.

[0146] 2.1.1 Determining the optimal read voltage An overview of the process of determining an optimal read voltage in a tracking operation in the nonvolatile memory 10 according to the first embodiment will be described with reference to Fig. 13. Fig. 13 is a diagram for explaining the overview of the process of determining an optimal read voltage in a tracking operation in the nonvolatile memory according to a first modified example of the first embodiment.

[0147] In the process of determining the optimal read voltage, if the value (Δ2-Δ1) is smaller than the value Δth1, the calculation circuit 19 calculates a difference Δ3 between the number of ON cells at a read voltage obtained by adding a predetermined voltage to the read voltage V3 based on the read process and the number of ON cells at the read voltage V3. In this case, the calculation circuit 19 determines the optimal read voltage based on the differences Δ2 and Δ3. Hereinafter, the read voltage obtained by adding a predetermined voltage to the read voltage V3 is referred to as (V3+ΔV), and the read voltage is suffixed with "4". This read voltage will also be simply referred to as read voltage V4.

[0148] 2.1.2 Flowchart of the process for determining the optimum read voltage The process of determining the optimum read voltage in the tracking operation in the nonvolatile memory 10 according to the first modified example of the first embodiment will be further described with reference to Fig. 14. Fig. 14 is a flowchart for explaining the process of determining the optimum read voltage in the tracking operation in the nonvolatile memory according to the first modified example of the first embodiment. The flowchart for one of the read voltages related to the target page will be described below.

[0149] The nonvolatile memory 10 stores the read data at the read voltages V1 to V3 and calculates the differences Δ1 and Δ2 through the same processes as S11 to S15 in the first embodiment (S31).

[0150] The arithmetic circuit 19 also determines whether the difference Δ2 is greater than the difference Δ1 (Δ1<Δ2) (S32) by the same process as S16. If the difference Δ2 is greater than the difference Δ1 (S32; YES), the process proceeds to S33. If the difference Δ2 is equal to or less than the difference Δ1 (S32; NO), the process proceeds to S34.

[0151] If the difference Δ2 is greater than the difference Δ1 (S32; YES), the arithmetic circuit 19 determines whether the value (Δ2-Δ1) is greater than the value Δth1 ((Δ2-Δ1)>Δth1) by the same process as S17 (S33). If the value (Δ2-Δ1) is greater than the value Δth1 (S33; YES), the process proceeds to S39. If the value (Δ2-Δ1) is equal to or less than the value Δth1 (S33; NO), the process proceeds to S34.

[0152] If the difference Δ2 is equal to or smaller than the difference Δ1 (S32; NO), and if the value (Δ2-Δ1) is equal to or smaller than the value Δth1 (S33; NO), each sense amplifier unit SAU stores the read data at the read voltage V4 for the selected memory cell transistor MT corresponding to that sense amplifier unit SAU, for example, in the latch circuit ADL (S34). That is, if the value (Δ2-Δ1) is equal to or smaller than the value Δth1, the process of S34 is executed. In the process of S34, the sense amplifier unit SAU uses the latch circuits ADL, BDL, and CDL like a ring buffer, as described above. Note that the acquisition of the read data at the read voltage V4 will be described later. Then, the process proceeds to S35.

[0153] Then, the arithmetic circuit 19 calculates a difference Δ3 based on the read data stored in the latch circuit ADL and the read data stored in the latch circuit CDL (S35). The difference Δ3 is calculated, for example, based on an exclusive OR operation (XOR operation) of the two read data stored in the latch circuits ADL and CDL in each sense amplifier unit SAU. Then, the process proceeds to S36.

[0154] The arithmetic circuit 19 also determines whether the difference Δ3 is greater than the difference Δ2 (Δ2<Δ3) (S36). In the process of S36, the arithmetic circuit 19 calculates, for example, a value (Δ3-Δ2) by subtracting the difference Δ2 from the difference Δ3. Then, the arithmetic circuit 19 makes the above determination based on the value (Δ3-Δ2). That is, the arithmetic circuit 19 determines whether the value (Δ3-Δ2) is greater than 0. The value (Δ3-Δ2) can be said to be the second-order differential value of the number of ON cells at the read voltage V3. If the difference Δ3 is greater than the difference Δ2 (S36; YES), the process proceeds to S37. If the difference Δ3 is equal to or less than the difference Δ2 (S36; NO), the process proceeds to S38.

[0155] If the difference Δ3 is greater than the difference Δ2 (S36; YES), the arithmetic circuit 19 determines whether the value (Δ3-Δ2) is greater than the value Δth3 ((Δ3-Δ2)>Δth3) (S37). Δth3 is a positive value. The value Δth3 may be set according to the read voltage. Δth3 is equal to, for example, Δth1. If the value (Δ3-Δ2) is greater than the value Δth3 (S37; YES), the process proceeds to S40. If the value (Δ3-Δ2) is equal to or less than the value Δth3 (S37; NO), the process proceeds to S41.

[0156] If the difference Δ3 is less than or equal to the difference Δ2 (S36; NO), the arithmetic circuit 19 determines whether the value (Δ2-Δ3) (-(Δ3-Δ2)) obtained by subtracting the difference Δ3 from the difference Δ2 is greater than the value Δth4 ((Δ2-Δ3)>Δth4) (S38). Δth4 is a positive value. Δth4 is equal to, for example, Δth2. The value Δth4 may be set according to the read voltage. If the value (Δ2-Δ3) is greater than the value Δth4 (S38; YES), the process proceeds to S42. If the value (Δ2-Δ3) is less than or equal to the value Δth4 (S38; NO), the process proceeds to S41.

[0157] If the value (Δ2−Δ1) is greater than the value Δth1 (S33; YES), the arithmetic circuit 19 determines the read voltage V1 as the optimum read voltage (S39), and the process then ends.

[0158] If the value (Δ3−Δ2) is greater than the value Δth3 (S37; YES), the arithmetic circuit 19 determines the voltage V2 as the optimum read voltage (S40), and the process then ends.

[0159] If the value (Δ3-Δ2) is equal to or less than the value Δth3 (S37; NO), and if the value (Δ2-Δ3) is equal to or less than the value Δth4 (S38; NO), the arithmetic circuit 19 determines the read voltage V3 to be the optimum read voltage (S41). That is, if the value (Δ3-Δ2) is equal to or less than the value Δth3 and equal to or greater than the value (-Δth4) (-Δth4≦(Δ3-Δ2)≦Δth3), the arithmetic circuit 19 determines the read voltage V3 to be the optimum read voltage. Then, the process ends.

[0160] If the value (Δ2−Δ3) is greater than the value Δth4 (S38; YES), the arithmetic circuit 19 determines the read voltage V4 as the optimum read voltage (S42), and the process then ends.

[0161] In this manner, the optimum read voltage is determined for each read voltage.

[0162] Acquisition of read data at read voltage V4 will be described.

[0163] In the read process in the tracking operation according to the first modification of the first embodiment, a sense period Tsen4 is set to sense whether the threshold voltage Vth is equal to or less than a read voltage V4. The length of the sense period Tsen4 is set so that the voltage at the node SEN corresponding to the memory cell transistor MT whose threshold voltage Vth is equal to or less than the voltage V4 falls below the determination level, and the voltage at the node SEN corresponding to the memory cell transistor MT whose threshold voltage Vth is higher than the voltage V4 exceeds the determination level. In FIG. 11, the sense period Tsen4 is the period from time t0 to a time after time t3. In this case, the memory cell transistor MT whose threshold voltage Vth is higher than the read voltage V4 is set as an off cell.

[0164] Although a timing chart for explaining the read process during the process of determining the optimal read voltage in the nonvolatile memory according to the first modification of the first embodiment is not shown, the nonvolatile memory 10 determines whether the difference Δ2 is greater than the difference Δ1 (S32) and whether the value (Δ2−Δ1) is greater than the value Δth1 (S33) after the sequencer 15 changes the signal XXL from the “L” level to the “H” level (after the times corresponding to times t15 and t22 in the first embodiment) and before the sense period Tsen4 has elapsed. If the difference Δ2 is equal to or less than the difference Δ1 (S32; NO) and if the value (Δ2−Δ1) is equal to or less than the value Δth1 (S33; NO), the read data at the read voltage V4 is stored in the latch circuit ADL at the timing when the sense period Tsen4 has elapsed, similar to the read data at the read voltage V1 in the first embodiment.

[0165] The first modification of the first embodiment also provides the same effects as the first embodiment.

[0166] Furthermore, according to the first variant of the first embodiment, instead of determining the optimum read voltage from the read voltages V1, V2, V3, and V3, the optimum read voltage is determined from the read voltages V1, V2, V3, and V4, thereby improving the accuracy of the read process.

[0167] 2.2 Second Modification of the First Embodiment In the second modification of the first embodiment, in the read process, a shift read is performed instead of setting the sense periods Tsen1, Tsen2, and Tsen3.

[0168] The configuration of the memory system according to the second modified example of the first embodiment is the same as the configuration of the memory system according to the first embodiment. Below, the operation of the memory system according to the second modified example of the first embodiment will be described, focusing mainly on the differences from the configuration and operation of the memory system according to the first embodiment.

[0169] In the second modification of the first embodiment, the shift read operation is a read process using read voltages V1 and V3 that are shifted by a predetermined voltage from the default read voltage V2.

[0170] The read process during the process of determining the optimal read voltage in the nonvolatile memory according to the second modified example of the first embodiment will be described with reference to FIG. 15. FIG. 15 is a timing chart for explaining the read process during the process of determining the optimal read voltage in the nonvolatile memory according to the second modified example of the first embodiment. FIG. 15 shows the read process for the voltage VE of the lower page. That is, the case where the read process is performed using voltages VE1, VE2, and VE3 is shown.

[0171] At time t31, similar to the operation at time t11, the voltage VREAD is applied to the selected word line WL and the unselected word lines WL.

[0172] At time t32, the row decoder module 17 applies a voltage VE1 to the selected word line WL.

[0173] At time t33, similar to the operation at time t13, voltages VBL and VSL are applied to the bit line BL and source line SL, respectively.

[0174] At time t34, similar to the operation at time t14, in the sense amplifier unit SAU, the node SEN is precharged to the voltage VDD.

[0175] At time t35, similar to the operation at time t15, the sequencer 15 changes the signal XXL from "L" level to "H" level to turn on transistor Tr3. Then, during the period from time t35 to time t36, it is determined whether the threshold voltage Vth is equal to or lower than the read voltage VE1. More specifically, if the threshold voltage of the selected memory cell transistor MT is higher than the read voltage VE1 (if it is an off cell), at time t36 the voltage of node SEN is maintained at "H" level, which turns on transistor Tr6. On the other hand, if the threshold voltage of the selected memory cell transistor MT is equal to or lower than the read voltage VE1 (if it is an on cell), at time t36 the voltage of node SEN drops to "L" level, which turns off transistor Tr6.

[0176] At time t36, the sequencer 15 changes the signal STB from the "L" level to the "H" level voltage. Then, the sequencer 15 maintains the signal STB at the "H" level voltage for a predetermined period. As a result, when the bus LBUS is at the "H" level, "1" data is stored in the latch circuit ADL. Also, when the bus LBUS is at the "L" level, "0" data is stored in the latch circuit ADL. In other words, the read data is stored in S11.

[0177] At time t37, similar to the operation at time t19, the sequencer 15 changes the signal XXL from "H" level to "L" level to turn off the transistor Tr3.

[0178] In this manner, the read process using the read voltage VE1 is executed, and read data at the read voltage VE1 is acquired.

[0179] At time t38, the row decoder module 17 applies, for example, a voltage VE2 to the selected word line WL, and the voltage of the node SEN is set to the voltage VSS.

[0180] The operation from time t39 to time t42 is substantially the same as the operation from time t34 to time t37, except that read voltage VE2 is used instead of read voltage VE1. As a result, a read process using read voltage VE2 is executed. Also, storage of the read data in S12 is executed.

[0181] At time t44, the row decoder module 17 applies, for example, a voltage VE3 to the selected word line WL, and the voltage of the node SEN is set to the voltage VSS.

[0182] The operation from time t45 to time t47 is substantially the same as the operation from time t34 to time t37 or the operation from time t39 to time t42, except that read voltage VE3 is used instead of read voltage VE1 or VE2. As a result, a read process using read voltage VE3 is executed. Also, the read data is stored in S13.

[0183] At time t48, the row decoder module 17 applies, for example, voltage VA1 to the selected word line WL. The voltage of node SEN is set to voltage VSS. Then, similar to the read operation using read voltages VE1, VE2, and VE3, a read operation using read voltages VA1, VA2, and VA3 is executed.

[0184] In this manner, the read process for determining the optimum read voltage is completed.

[0185] The second modified example of the first embodiment also provides the same effects as the first embodiment.

[0186] 3 Second embodiment In the first embodiment, the first modification of the first embodiment, and the second modification of the first embodiment described above, the nonvolatile memory 10 performs a tracking operation using the read voltage Vdef as the read voltage V2, but this is not limiting. The nonvolatile memory 10 may perform a tracking operation using a read voltage V2 that is shifted from a specified read voltage depending on the previous tracking operation.

[0187] The following describes the configuration and operation of the memory system 1 according to the second embodiment that differ from the memory system according to the first embodiment.

[0188] The configuration of the memory system 1 according to the second embodiment can be the same as that of the memory system 1 according to the first embodiment, except that the volatile memory 30 stores a shift amount table relating to the shift amount for each read voltage. The shift amount table will be described below with reference to FIG. 16. FIG. 16 is a diagram showing an example of a shift amount table used in the memory system according to the second embodiment.

[0189] In the tracking operation according to the second embodiment, the nonvolatile memory 10 sets the read voltage Vdef or a voltage obtained by adding a shift amount to the read voltage Vdef as the read voltage V2 for each read voltage of the target page, for example, based on a tracking operation command. The read voltage V2 is selected or specified, for example, based on an address included in the command. The shift amount is a value calculated for each read voltage based on the sum of the difference between the optimal read voltage in a tracking operation already performed and the read voltage V2. More specifically, when a tracking operation is performed, the shift amount is updated to a value obtained by adding the current shift amount to a value obtained by subtracting the read voltage V2 from the optimal read voltage in the tracking operation. For example, if the optimal read voltage in the tracking operation is determined to be read voltage V1, the shift amount is updated to a value obtained by subtracting the difference between read voltages V2 and V1 from the current shift amount. Furthermore, if the optimal read voltage in the tracking operation is determined to be read voltage V2, for example, the shift amount is maintained. Furthermore, for example, in a tracking operation, if the optimum read voltage is determined to be read voltage V3, the shift amount is updated to a value obtained by adding the difference between read voltages V3 and V2 to the current shift amount. Furthermore, if read voltage Vdef is selected as read voltage V2 for each read voltage based on a tracking operation command, the shift amount is reset. That is, the shift amount corresponding to the read voltage is set to zero. Note that the updating and resetting of the shift amount is performed, for example, by the sequencer 15 and the arithmetic circuit 19.

[0190] The shift amount table stores, for example, a read voltage Vdef and shift amounts CVA to CVG for each read voltage. All or part of the information included in the shift amount table may also be stored in the nonvolatile memory 10. As will be described later, the shift amount table may be configured to store only shift amounts related to a predetermined number of read voltages. In the following, when the shift amounts CVA to CVG are not distinguished from one another, each of the shift amounts CVA to CVG will simply be referred to as a shift amount CV.

[0191] The overall operation of the tracking operation of the memory system 1 according to the second embodiment will be described with reference to Fig. 17. Fig. 17 is a flowchart for explaining the tracking operation in the nonvolatile memory according to the second embodiment.

[0192] The nonvolatile memory 10 receives a read command from the memory controller 20 to instruct the execution of a tracking operation and to execute a read process (S51).

[0193] When receiving the read command as described above, the sequencer 15 selects, for example, the read voltage Vdef or a voltage obtained by adding a shift amount CV to the read voltage Vdef as the read voltage V2 for each read voltage of the target page, based on, for example, a command for the tracking operation (S52). When the read voltage Vdef is selected as the read voltage V2, the read voltage shift amount CV is reset.

[0194] Then, the nonvolatile memory 10 determines the optimum read voltage for each read voltage based on the selected read voltage V2, in the same manner as in the first embodiment (S53).

[0195] Then, the nonvolatile memory 10 outputs the page data determined based on the read data at the optimum read voltage determined in S53 to the memory controller 20 (S54).

[0196] Also, for example, before the next tracking operation is performed, based on the information of the selected latch circuit stored in the calculation circuit 19, the shift amount CV is updated to a value obtained by subtracting the read voltage V2 from the optimum read voltage and adding the result to the current shift amount CV.

[0197] 16 shows an example in which the shift amount table stores shift amounts CV for all read voltages, but this is not limiting. In the second embodiment, multiple tracking operations for the same page among the upper page, middle page, and lower page are executed, for example, consecutively. Then, among the read voltages VA to VG, the shift amount CV for the read voltage for the page is updated. As a result, the shift amount table may be configured to store shift amounts CV for, for example, the maximum number of read voltages for each page. For example, since the maximum number of read voltages for each of the upper page, middle page, and lower page is three, the shift amount table may be configured to be able to store three shift amounts CV in association with the read voltages.

[0198] The second embodiment also provides the same effects as the first embodiment.

[0199] Furthermore, the accuracy of the read process can be improved by performing a tracking operation based on the read voltage V2 according to the shift amount CV of each read voltage.

[0200] 4. Other In the above-described first embodiment, first modification of the first embodiment, second modification of the first embodiment, and second embodiment, the tracking operation is performed within the nonvolatile memory 10, but this is not limiting. For example, in these embodiments, various calculations performed by the arithmetic circuit 19 using data held in the latch circuits, calculations of the differences Δ1, Δ2, and Δ3 in the number of ON cells, and various processes for determining an optimal read voltage based on the calculations may be performed by a configuration included in the memory controller 20 in the memory system 1, for example.

[0201] In the above-described first embodiment, first modification of the first embodiment, second modification of the first embodiment, and second embodiment, eight states are formed by the threshold voltages of the memory cell transistors MT in the nonvolatile memory. However, this is not limited to this. For example, the nonvolatile memory may form two states, four states, or sixteen states by the threshold voltages of the memory cell transistors MT. Note that, for example, when two states are formed by the threshold voltages of the memory cell transistors MT, page data may be determined using one read voltage between the two states. When page data is determined using one read voltage in this way, the nonvolatile memory outputs the read data at the optimal read voltage determined as shown in FIG. 10 or the read data at the optimal read voltage determined as shown in FIG. 14 to the memory controller as page data.

[0202] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0203] 1...memory system, 2...host device, 10...non-volatile memory, 20...memory controller, 30...volatile memory, 11...memory cell array, 12...input / output circuit, 13...logic circuit, 14...register, 15...sequencer, 16...voltage generation circuit, 17...row decoder module, 18...sense amplifier module, BLK...block, SU...string unit, NS...NAND string, MT...memory cell transistor, ST1, ST2...select transistor, BL...bit line, WL...word line, SGS, SGD...select gate line, ADL, BDL, CDL, TDL, SDL...latch circuit.

Claims

1. a plurality of memory cells; a word line connected to the plurality of memory cells; a controller configured to read data from the plurality of memory cells by applying voltages to the word lines; Equipped with The controller, in a read process for the plurality of memory cells, applying a first voltage to the word line; While the first voltage is being applied to the word line, data is read from the plurality of memory cells at a first timing, data is read from the plurality of memory cells at a second timing that is later than the first timing, and data is read from the plurality of memory cells at a third timing that is later than the second timing; a first difference between the number of memory cells based on the data read from the plurality of memory cells at the first timing and the number of memory cells based on the data read from the plurality of memory cells at the second timing; a second difference between the number of memory cells based on the data read from the plurality of memory cells at the second timing and the number of memory cells based on the data read from the plurality of memory cells at the third timing; a first value obtained by subtracting the first difference from the second difference; Calculate, determining, based on the first value, any one of the data read from the plurality of memory cells at the first timing, the data read from the plurality of memory cells at the second timing, and the data read from the plurality of memory cells at the third timing as a plurality of first read data from the plurality of memory cells; Non-volatile memory.

2. The controller If the first value is a positive value and is greater than a first threshold value, determining the data read from the plurality of memory cells at the first timing as the plurality of first read data; when the first value is a positive value and is equal to or less than the first threshold value, and when the first value is equal to or less than 0 and a second value obtained by subtracting the second difference from the first difference is equal to or less than a second threshold value, determining the data read from the plurality of memory cells at the second timing as the plurality of first read data; When the first value is equal to or less than 0 and the second value is greater than the second threshold value, the data read from the memory cells at the third timing is determined as the first read data. It is configured as follows: The nonvolatile memory of claim 1 .

3. further comprising an input / output circuit; The nonvolatile memory is connectable to an external memory controller via the input / output circuit; The controller transmits the plurality of first read data to the memory controller in response to a read command received from the memory controller via the input / output circuit. The nonvolatile memory of claim 1 .

4. further comprising a word line adjacent to the word line; While the first voltage is being applied to the word line, the controller applies a second voltage higher than the first voltage to the adjacent word line. The nonvolatile memory of claim 1 .

5. The controller performing an exclusive OR operation on a plurality of first data, which are data read from the plurality of memory cells at the first timing, and a plurality of second data, which are data read from the plurality of memory cells at the second timing, for each of the plurality of memory cells; The number of bits that are 1 in the data obtained by performing an exclusive OR operation on the plurality of first data and the plurality of second data is set as the first difference. The nonvolatile memory of claim 1 .

6. The controller performing an exclusive OR operation on the plurality of second data and the plurality of third data which are data read from the plurality of memory cells at the third timing for each of the plurality of memory cells; The number of bits that are 1 in the data obtained by performing an exclusive OR operation on the plurality of second data and the plurality of third data is set as the second difference.

6. The nonvolatile memory according to claim 5.

7. The controller a plurality of first latch circuits, a plurality of second latch circuits, a plurality of third latch circuits, and a plurality of fourth latch circuits, each corresponding to one of the plurality of memory cells; storing the plurality of first data in the plurality of first latch circuits, respectively; storing the plurality of second data in the plurality of second latch circuits, respectively; storing the plurality of third data in the plurality of third latch circuits, respectively; storing the plurality of first read data in the plurality of fourth latch circuits, respectively; each of the plurality of first latch circuits corresponds to read data from each of the plurality of memory cells; each of the plurality of second latch circuits corresponds to read data from each of the plurality of memory cells; Each of the plurality of third latch circuits corresponds to read data from each of the plurality of memory cells.

7. The nonvolatile memory of claim 6.

8. Each of the plurality of memory cells is capable of storing two or more bits of data; The controller, in the read process for the plurality of memory cells, After the first read data is determined, a third voltage different from the first voltage is applied to the word line; While the third voltage is being applied to the word line, data is read from the plurality of memory cells at a fourth timing, data is read from the plurality of memory cells at a fifth timing that is later than the fourth timing, and data is read from the plurality of memory cells at a sixth timing that is later than the fifth timing; a third difference between the number of memory cells based on the data read from the plurality of memory cells at the fourth timing and the number of memory cells based on the data read from the plurality of memory cells at the fifth timing; a fourth difference between the number of memory cells based on the data read from the plurality of memory cells at the fifth timing and the number of memory cells based on the data read from the plurality of memory cells at the sixth timing; a second value obtained by subtracting the third difference from the fourth difference; Calculate, Based on the second value, any one of the data read from the plurality of memory cells at the fourth timing, the data read from the plurality of memory cells at the fifth timing, and the data read from the plurality of memory cells at the sixth timing is determined as a plurality of second read data of the plurality of memory cells. The nonvolatile memory of claim 7.

9. The controller If the first value is a positive value and is greater than a first threshold value, determining the data read from the plurality of memory cells at the first timing as the plurality of first read data; when the first value is a positive value and is equal to or less than the first threshold value, when the first value is equal to or less than 0 and a third value obtained by subtracting the second difference from the first difference is equal to or less than a second threshold value, determining the data read from the plurality of memory cells at the second timing as the plurality of first read data; When the first value is equal to or less than 0 and the third value is greater than the second threshold value, the data read from the memory cells at the third timing is determined as the first read data. It is configured as follows:

9. The nonvolatile memory of claim 8.

10. The controller When the second value is a positive value and is greater than the first threshold value, the data read from the plurality of memory cells at the fourth timing is determined as the plurality of second read data; when the second value is a positive value and is equal to or less than the first threshold value, when the second value is equal to or less than 0 and a fourth value obtained by subtracting the fourth difference from the third difference is equal to or less than the second threshold value, determining the data read from the plurality of memory cells at the fifth timing as the plurality of second read data; When the second value is equal to or less than 0 and the fourth value is greater than the second threshold value, the data read from the plurality of memory cells at the sixth timing is determined as the plurality of second read data. It is configured as follows:

10. The non-volatile memory of claim 9.

11. further comprising an input / output circuit; The nonvolatile memory is connectable to an external memory controller via the input / output circuit; The controller transmits data based on the first read data and the plurality of second read data to the memory controller in response to a read command received from the memory controller via the input / output circuit.

9. The nonvolatile memory of claim 8.

12. The data based on the plurality of first read data and the plurality of second read data is a result of a logical operation of the plurality of first read data and the plurality of second read data.

9. The nonvolatile memory of claim 8.

13. further comprising a word line adjacent to the word line; While the first voltage and the third voltage are applied to the word line, the controller applies a fourth voltage higher than the first voltage and the third voltage to the adjacent word line. The nonvolatile memory of claim 8.

14. The nonvolatile memory of claim 8 , wherein the third voltage is lower than the first voltage.

15. The nonvolatile memory of claim 8 , wherein the first voltage is lower than the third voltage.

16. The controller performing an exclusive OR operation on a plurality of fourth data which are data read from the plurality of memory cells at the fourth timing and a plurality of fifth data which are data read from the plurality of memory cells at the fifth timing for each of the plurality of memory cells; the number of bits that are 1 in the data obtained by performing an exclusive OR operation on the plurality of fourth data and the plurality of fifth data is set to the third difference; performing an exclusive OR operation on the plurality of fifth data and the plurality of sixth data which are data read from the plurality of memory cells at the sixth timing for each of the plurality of memory cells; The number of bits that are 1 in the data obtained by performing an exclusive OR operation on the plurality of fifth data and the plurality of sixth data is set as the fourth difference. The nonvolatile memory of claim 8.

17. The controller a plurality of first latch circuits, a plurality of second latch circuits, a plurality of third latch circuits, and a plurality of fourth latch circuits; storing the plurality of fourth data in the plurality of first latch circuits, respectively; storing the plurality of fifth data in the plurality of second latch circuits, respectively; storing the plurality of sixth data in the plurality of third latch circuits, respectively; For each of the plurality of memory cells, an exclusive NOR operation is performed on the plurality of first read data and the plurality of second read data stored in the plurality of fourth latch circuits, and the data obtained by the exclusive NOR operation is stored in the plurality of fourth latch circuits.

17. The non-volatile memory of claim 16.

18. 1. A method for controlling a non-volatile memory comprising a plurality of memory cells and word lines connected to the plurality of memory cells, the method comprising: the method includes reading data from the plurality of memory cells by applying a voltage to the word lines; Reading data from the plurality of memory cells includes: applying a first voltage to the word line; While the first voltage is being applied to the word line, reading data from the plurality of memory cells at a first timing, reading data from the plurality of memory cells at a second timing that is later than the first timing, and reading data from the plurality of memory cells at a third timing that is later than the second timing; a first difference between the number of memory cells based on the data read from the plurality of memory cells at the first timing and the number of memory cells based on the data read from the plurality of memory cells at the second timing; a second difference between the number of memory cells based on the data read from the plurality of memory cells at the second timing and the number of memory cells based on the data read from the plurality of memory cells at the third timing; a first value obtained by subtracting the first difference from the second difference; Calculating and determining, based on the first value, any one of data read from the plurality of memory cells at the first timing, data read from the plurality of memory cells at the second timing, and data read from the plurality of memory cells at the third timing as a plurality of first read data from the plurality of memory cells; A method comprising:

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