Semiconductor storage device and memory system

Abstract

To provide a semiconductor storage device that can improve bus utilization efficiency.SOLUTION: A semiconductor storage device includes a data holding part, a data transfer circuit, and a control part. The data holding part temporarily holds data read from a memory cell array. The data transfer circuit is provided between the data holding part and a pad part and transfers the data held in the data holding part to an input / output pad. The data transfer circuit is provided with a blocking part capable of blocking a current supply to the data transfer circuit. When a predetermined time has elapsed without data transfer to a memory controller after the data has been transferred to the data transfer circuit from the memory cell array via the data holding part, the control part blocks the current supply to the data transfer circuit by means of the blocking part. The predetermined time is changeable.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor memory device and a memory system. [Background technology]

[0002] NAND flash memory is known as a semiconductor memory device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2023-137230 Summary of the Invention [Problem to be solved by the invention]

[0004] According to the embodiments, a semiconductor memory device and a memory system capable of improving the bus usage efficiency are provided. [Means for solving the problem]

[0005] A semiconductor memory device according to an embodiment includes a memory cell array, a data holding unit, a pad unit, a data transfer circuit, and a control unit. The data holding unit temporarily holds data read from the memory cell array. The pad unit transmits and receives signals to and from the memory controller. The data transfer circuit is provided between the data holding unit and the pad unit and transfers data held in the data holding unit to an input / output pad. The control unit controls the data transfer circuit. The data transfer circuit is provided with a cutoff unit capable of cutting off the supply of current to the data transfer circuit. When a predetermined time has elapsed since data was transferred from the memory cell array to the data transfer circuit via the data holding unit without data transfer to the memory controller being started, the control unit cuts off the supply of current to the data transfer circuit using the cutoff unit. The predetermined time is variable.

[0006] A memory system according to an embodiment includes a semiconductor memory device and a memory controller that controls the semiconductor memory device based on a request from a host. The memory controller outputs a recommended value for the predetermined time to the host. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram showing a schematic configuration of a memory system according to an embodiment. [Figure 2] FIG. 1 is a block diagram showing a schematic configuration of a semiconductor memory device according to an embodiment. [Figure 3] 1 is a circuit diagram showing a configuration of a semiconductor memory device according to an embodiment; [Figure 4] 1 is a cross-sectional view showing a cross-sectional structure of a semiconductor memory device according to an embodiment; [Figure 5] FIG. 2 is a block diagram showing the configuration of a sense amplifier unit according to the embodiment. [Figure 6] FIG. 10 is a diagram showing an example of a threshold distribution of a memory cell transistor. [Figure 7] FIG. 10 is a diagram showing potential changes of each wiring during a program operation. [Figure 8] FIG. 10 is a diagram showing potential changes in each wiring during a read operation. [Figure 9] 2 is a diagram showing the configuration of a circuit for outputting data from a memory cell array to a memory controller in the memory system of the embodiment. FIG. [Figure 10] FIG. 2 is a block diagram showing a configuration for supplying current to a holding unit and an input / output circuit according to the embodiment. [Figure 11] 2 is a diagram showing an example of the transition of signals transmitted and received between the semiconductor memory device and the memory controller according to the embodiment; [Figure 12] 2 is a diagram showing an example of the transition of signals transmitted and received between the semiconductor memory device and the memory controller according to the embodiment; [Figure 13] 2 is a diagram showing an example of the transition of signals transmitted and received between the semiconductor memory device and the memory controller according to the embodiment; [Figure 14] 2 is a diagram showing an example of the transition of signals transmitted and received between the semiconductor memory device and the memory controller according to the embodiment; [Figure 15] 4 is a sequence chart showing an example of the operation of the memory system according to the embodiment. [Figure 16] FIG. 10 is a block diagram showing a schematic configuration for supplying current to a holding unit and an input / output circuit according to a modified example of the embodiment. [Figure 17] 10 is a sequence chart showing an example of the operation of a memory system according to another embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described with reference to the drawings. To facilitate understanding of the description, the same components in the drawings will be denoted by the same reference numerals as much as possible, and duplicated descriptions will be omitted.

[0009] 1. Embodiment A semiconductor memory device according to an embodiment will be described. The semiconductor memory device according to this embodiment is a nonvolatile memory device configured as a NAND flash memory.

[0010] 1.1 Memory system configuration First, the configuration of the memory system of this embodiment will be described.

[0011] 1, a memory system 3 of this embodiment includes a memory controller 1 and semiconductor memory devices 2a to 2d. The semiconductor memory devices 2a to 2d are nonvolatile memory devices configured as NAND-type flash memories. The memory system 3 can be connected to a host 4. The host 4 is, for example, an electronic device such as a personal computer or a mobile terminal.

[0012] The memory controller 1 controls writing of data to the semiconductor memory devices 2a to 2d in accordance with a write request from the host 4. The memory controller 1 also controls reading of data from the semiconductor memory devices 2a to 2d in accordance with a read request from the host 4.

[0013] The following signals are transmitted and received between the memory controller 1 and the semiconductor memory devices 2a to 2d: chip enable signal / CE, ready / busy signal R / B, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signals / RE, RE, write protect signal / WP, signal DQ<7:0>, and data strobe signals DQS, / DQS.

[0014] The chip enable signal / CE is a signal for enabling the semiconductor memory devices 2a to 2d. The ready / busy signal R / B is a signal for indicating whether the semiconductor memory devices 2a to 2d are in a ready state or a busy state. A "ready state" is a state in which an external command is accepted. A "busy state" is a state in which an external command is not accepted.

[0015] 1, a chip enable signal / CE is individually transmitted to each of the semiconductor memory devices 2a to 2d. In Fig. 1, a number is added to the end of each chip enable signal / CE, for example, " / CE0", so that each chip enable signal / CE can be distinguished from each other.

[0016] Similarly, each of the semiconductor memory devices 2a to 2d individually transmits a ready / busy signal R / B. In Fig. 1, the ready / busy signals R / B are each assigned a number at the end, such as "R / B0," so that they can be distinguished from one another.

[0017] Signals other than the chip enable signal / CE and the ready / busy signal R / B (such as the command latch enable signal CLE) are transmitted and received between the memory controller 1 and the semiconductor memory devices 2a to 2d via signal lines shared by the semiconductor memory devices 2a to 2d. The memory controller 1 uses an individual chip enable signal / CE to identify the semiconductor memory devices 2a to 2d with which to communicate.

[0018] The command latch enable signal CLE is a signal indicating that the signal DQ<7:0> is a command. The address latch enable signal ALE is a signal indicating that the signal DQ<7:0> is an address. The write enable signal / WE is a signal for loading the received signal into the semiconductor memory devices 2a to 2d, and is asserted by the memory controller 1 each time a command, address, and data are received. The memory controller 1 instructs the semiconductor memory devices 2a to 2d to load the signal DQ<7:0> while the signal / WE is at the "L (Low)" level.

[0019] The read enable signals / RE and / RE are signals that allow the memory controller 1 to read data from the semiconductor memory devices 2a to 2d. The read enable signals RE and / RE are used to control the operation timing of the semiconductor memory devices 2a to 2d when outputting, for example, the signal DQ<7:0>. The write protect signal / WP is a signal that instructs the semiconductor memory devices 2a to 2d to prohibit data writing and erasure. The signal DQ<7:0> is the entity of data exchanged between the semiconductor memory devices 2a to 2d and the memory controller 1, and includes a command, address, and data. The data strobe signals DQS and / DQS are signals that control the timing of input and output of the signal DQ<7:0>.

[0020] The memory controller 1 includes a RAM 11, a processor 12, a host interface 13, an ECC circuit 14, and a memory interface 15. These are connected to one another by an internal bus 16.

[0021] The host interface 13 outputs requests and user data (write data) received from the host 4 to the internal bus 16. The host interface 13 also transmits user data read from the semiconductor memory devices 2a to 2d, responses from the processor 12, and the like to the host.

[0022] Based on instructions from the processor 12, the memory interface 15 controls the process of writing user data and the like to the semiconductor storage devices 2a to 2d and the process of reading user data and the like from the semiconductor storage devices 2a to 2d.

[0023] The processor 12 performs overall control of the memory controller 1. The processor 12 is a CPU, an MPU, or the like. When the processor 12 receives a request from the host 4 via the host interface 13, the processor 12 performs control in accordance with the request. For example, in accordance with the request from the host 4, the processor 12 instructs the memory interface 15 to write user data and parity to the semiconductor memory devices 2a to 2d. In addition, in accordance with the request from the host 4, the processor 12 instructs the memory interface 15 to read user data and parity from the semiconductor memory devices 2a to 2d.

[0024] The processor 12 determines a storage area (memory area) on the semiconductor storage devices 2a to 2d for user data accumulated in the RAM 11. The user data is stored in the RAM 11 via the internal bus 16. The processor 12 determines the memory area for data (page data) in units of pages, which are write units. User data stored in one page of the semiconductor storage devices 2a to 2d is also referred to as "unit data" below. The unit data is generally encoded and stored in the semiconductor storage devices 2a to 2d as a code word. In this embodiment, encoding is not essential. The memory controller 1 may store the unit data in the semiconductor storage devices 2a to 2d without encoding it, but FIG. 1 shows a configuration in which encoding is performed as an example. When the memory controller 1 does not perform encoding, the page data matches the unit data. Furthermore, one code word may be generated based on one unit data, or one code word may be generated based on divided data obtained by dividing the unit data. Furthermore, one code word may be generated using multiple unit data.

[0025] The processor 12 determines the memory area of ​​the semiconductor storage devices 2a to 2d to which the unit data is to be written for each unit data. A physical address is assigned to the memory area of ​​the semiconductor storage devices 2a to 2d. The processor 12 manages the memory area to which the unit data is to be written using the physical address. The processor 12 instructs the memory interface 15 to write the user data to the semiconductor storage devices 2a to 2d by specifying the determined memory area (physical address). The processor 12 manages the correspondence between the logical address of the user data (logical address managed by the host 4) and the physical address. When the processor 12 receives a read request including a logical address from the host 4, it identifies the physical address corresponding to the logical address and instructs the memory interface 15 to read the user data by specifying the physical address.

[0026] The ECC circuit 14 generates code words by encoding the user data stored in the RAM 11. The ECC circuit 14 also decodes code words read from the semiconductor memory devices 2a to 2d.

[0027] The RAM 11 temporarily stores user data received from the host 4 before storing it in the semiconductor storage devices 2a to 2d, and temporarily stores data read from the semiconductor storage devices 2a to 2d before transmitting it to the host 4. The RAM 11 is a general-purpose memory such as an SRAM or a DRAM.

[0028] 1 shows a configuration example in which the memory controller 1 includes an ECC circuit 14 and a memory interface 15. However, the ECC circuit 14 may be built into the memory interface 15. Alternatively, the ECC circuit 14 may be built into the semiconductor memory devices 2a to 2d. The specific configuration and arrangement of the elements shown in FIG. 1 are not particularly limited.

[0029] When a write request is received from the host 4, the memory system 3 of FIG. 1 operates as follows: The processor 12 temporarily stores the data to be written in the RAM 11. The processor 12 reads the data stored in the RAM 11 and inputs it to the ECC circuit 14. The ECC circuit 14 encodes the input data and inputs the codeword to the memory interface 15. The memory interface 15 writes the input codeword to the semiconductor memory devices 2a to 2d.

[0030] 1 operates as follows when a read request is received from the host 4. The memory interface 15 inputs the codeword read from the semiconductor memory devices 2a to 2d to the ECC circuit 14. The ECC circuit 14 decodes the input codeword and stores the decoded data in the RAM 11. The processor 12 transmits the data stored in the RAM 11 to the host 4 via the host interface 13.

[0031] 1.2 Overview of semiconductor memory device Next, the schematic configuration of the semiconductor memory devices 2a to 2d will be described. Note that since the semiconductor memory devices 2a to 2d have the same structure, the structure of the semiconductor memory device 2a will be described below as a representative.

[0032] As shown in FIG. 2, the semiconductor memory device 2a includes two planes PL1 and PL2, an input / output circuit 21, a logic control circuit 22, a sequencer 41, a register 42, a voltage generation circuit 43, a group of input / output pads 31, a group of logic control pads 32, and a group of power input terminals 33.

[0033] The plane PL1 includes a memory cell array 110, a sense amplifier 120, and a row decoder 130. The plane PL2 includes a memory cell array 210, a sense amplifier 220, and a row decoder 230. The configuration of the plane PL1 is the same as the configuration of the plane PL2. That is, the configuration of the memory cell array 110 is the same as the configuration of the memory cell array 210, the configuration of the sense amplifier 120 is the same as the configuration of the sense amplifier 220, and the configuration of the row decoder 130 is the same as the configuration of the row decoder 230. The number of planes provided in the semiconductor memory device 2a may be two as in this embodiment, or may be one, or three or more.

[0034] The memory cell arrays 110 and 210 are sections for storing data, and each of the memory cell arrays 110 and 210 includes a plurality of memory cell transistors associated with word lines and bit lines.

[0035] The row decoders 130 and 230 are circuits configured with a group of switches for applying voltages to the multiple word lines of the memory cell arrays 110 and 210, respectively. The row decoders 130 and 230 receive a block address and a row address from the register 42, select a block based on the block address, and select a word line based on the row address. The row decoders 130 and 230 switch the open / close states of the group of switches so that a voltage from the voltage generation circuit 43 is applied to the selected word line. The operation of the row decoder 230 is controlled by the sequencer 41.

[0036] The sense amplifiers 120 and 220 are circuits for adjusting the voltages applied to the bit lines of the memory cell arrays 110 and 210, and for reading the voltages of the bit lines and converting them into data. When reading data, the sense amplifiers 120 and 220 acquire data read from the memory cell transistors of the memory cell arrays 110 and 210 to the bit lines, and transfer the acquired read data to the input / output circuit 21. When writing data, the sense amplifiers 120 and 220 transfer the data to be written to the memory cell transistors via the bit lines. The operation of the sense amplifiers 120 and 220 is controlled by the sequencer 41.

[0037] The input / output circuit 21 transmits and receives signals DQ<7:0> and data strobe signals DQS, / DQS to and from the memory controller 1. The input / output circuit 21 transfers the command and address in the signal DQ<7:0> to the register 42. The input / output circuit 21 also transmits and receives write data and read data to and from the sense amplifier 120 and the sense amplifier 220. The input / output circuit 21 functions as both an "input circuit" that receives commands and the like from the memory controller 1 and an "output circuit" that outputs data to the memory controller 1. Alternatively, the input circuit and the output circuit may be configured as separate circuits.

[0038] The logic control circuit 22 receives a chip enable signal / CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal / WE, read enable signals / RE, RE, and a write protect signal / WP from the memory controller 1. The logic control circuit 22 also transfers a ready / busy signal R / B to the memory controller 1 to notify the outside of the state of the semiconductor memory device 2a.

[0039] The input / output circuit 21 and the logic control circuit 22 are both circuits configured as parts through which signals are input and output to and from the memory controller 1. That is, the input / output circuit 21 and the logic control circuit 22 are provided as interface circuits for the semiconductor memory device 2a.

[0040] The sequencer 41 controls the operation of each part, such as the planes PL1 and PL2 and the voltage generation circuit 43, based on control signals input from the memory controller 1 to the semiconductor memory device 2a. The sequencer 41 is a part that controls the operation of the memory cell arrays 110 and 210. In this embodiment, the sequencer 41 is an example of a control part of the semiconductor memory device 2a. Note that both the sequencer 41 and the logic control circuit 22 can also be considered as a control part.

[0041] The sequencer 41 has a feature register 41a. The feature register 41a is a section that holds the operating parameters of the semiconductor memory device 2a. The operating parameters can be set by a SetFeature operation, which will be described later.

[0042] The register 42 includes a command register 42a, an address register 42b, and a status register 42c. The command register 42a temporarily holds commands. The address register 42b temporarily holds addresses. The status register 42c holds status information indicating the state of the semiconductor memory device 2a. More specifically, the status register 42c holds status information indicating the respective states of the planes PL1 and PL2. The status information is output as a status signal from the input / output circuit 21 to the memory controller 1 in response to a request from the memory controller 1.

[0043] The voltage generation circuit 43 generates voltages required for data write, read, and erase operations in the memory cell arrays 110 and 210 based on instructions from the sequencer 41. Such voltages include, for example, voltages applied to the word lines and bit lines of the memory cell arrays 110 and 210. The voltage generation circuit 43 can apply voltages individually to each of the word lines and bit lines so that the planes PL1 and PL2 can operate in parallel with each other.

[0044] The input / output pad group 31 is a portion provided with a plurality of terminals (pads) for transmitting and receiving signals between the memory controller 1 and the input / output circuit 21. Each terminal is provided individually corresponding to the signal DQ<7:0> and the data strobe signals DQS, / DQS. In this embodiment, the input / output pad group 31 is an example of a pad section.

[0045] The logic control pad group 32 is a portion provided with a plurality of terminals (pads) for transmitting and receiving various signals between the memory controller 1 and the logic control circuit 22. The terminals are individually provided corresponding to the chip enable signal / CE, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signals / RE, RE, write protect signal / WP, and ready / busy signal R / B, respectively.

[0046] The power input terminal group 33 is a section provided with a plurality of terminals for receiving the voltages required for the operation of the semiconductor memory device 2a. The voltages applied to the respective terminals include power supply voltages VCC, VCCQ, VPP, and ground voltage VSS. The power supply voltage VCC is a circuit power supply voltage provided externally as an operating power supply, and is, for example, a voltage of about 2.5V. The power supply voltage VCC is, for example, a voltage for generating voltage VDD, which is an internal power supply voltage of the semiconductor memory device 2a. The power supply voltage VDD is, for example, a voltage of about 1.5V. The power supply voltage VCCQ is a power supply voltage lower than the power supply voltage VCC, and is, for example, a voltage of 1.2V. The power supply voltage VCCQ is an input / output power supply voltage used when transmitting and receiving signals between the memory controller 1 and the semiconductor memory device 2a.

[0047] 1.3 Memory cell array circuit configuration Next, the circuit configuration of the memory cell array 110 will be described.

[0048] As shown in Fig. 3, the memory cell array 110 is composed of multiple blocks BLK. Only one of the multiple blocks BLK is shown in Fig. 3. The configurations of the other blocks BLK in the memory cell array 110 are similar to that shown in Fig. 3.

[0049] 3, the block BLK includes, for example, four string units SU (SU0 to SU3). Each string unit SU includes a plurality of NAND strings NS. Each of the NAND strings NS includes, for example, eight memory cell transistors MT (MT0 to MT7) and select transistors ST1 and ST2.

[0050] The memory cell transistors MT are arranged so as to be connected in series between the select transistors ST1 and ST2. The memory cell transistor MT7 on one end is connected to the source of the select transistor ST1, and the memory cell transistor MT0 on the other end is connected to the drain of the select transistor ST2.

[0051] The gates of the select transistors ST1 in the string units SU0 to SU3 are commonly connected to select gate lines SGD0 to SGD3, respectively. The gates of the select transistors ST2 are commonly connected to the same select gate line SGS across multiple string units SU in the same block BLK. The gates of the memory cell transistors MT0 to MT7 in the same block BLK are commonly connected to word lines WL0 to WL7, respectively. That is, while the word lines WL0 to WL7 and the select gate line SGS are common to multiple string units SU0 to SU3 in the same block BLK, the select gate line SGD is provided individually for each string unit SU0 to SU3, even within the same block BLK.

[0052] The memory cell array 110 is provided with m bit lines BL (BL0, BL1, ..., BL(m-1)). "m" is an integer corresponding to the number of NAND strings NS included in one string unit SU. The drain of each select transistor ST1 of the NAND string NS is connected to the corresponding bit line BL. The source of each select transistor ST2 of the NAND string NS is connected to a source line SL. The source line SL is common to the sources of the multiple select transistors ST2 of the block BLK.

[0053] Data stored in multiple memory cell transistors MT in the same block BLK is erased collectively. On the other hand, data is read and written collectively from multiple memory cell transistors MT connected to one word line WL and belonging to one string unit SU. Each memory cell can hold three bits of data: an upper bit, a middle bit, and a lower bit.

[0054] That is, the semiconductor memory device 2a of this embodiment employs the TLC method for writing data to the memory cell transistors MT, in which 3-bit data is stored in one memory cell transistor MT. Alternatively, the method for writing data to the memory cell transistors MT may employ the MLC method, in which 2-bit data is stored in one memory cell transistor MT. The number of bits of data stored in one memory cell transistor MT is not particularly limited.

[0055] In the following description, a set of 1-bit data stored in multiple memory cell transistors MT connected to one word line WL and belonging to one string unit SU is referred to as a "page." In Figure 3, one of the sets of multiple memory cell transistors MT described above is denoted by the symbol "MG."

[0056] In the present embodiment, when three bits of data are stored in one memory cell transistor MT, a set of memory cell transistors MT connected to a common word line WL in one string unit SU can store three pages of data. A page consisting of a set of lower-order bit data will be referred to below as a "lower page," and the data on the lower page will be referred to below as "lower page data." Similarly, a page consisting of a set of middle-order bit data will be referred to below as a "middle page," and the data on the middle page will be referred to below as "middle page data." A page consisting of a set of upper-order bit data will be referred to below as an "upper page," and the data on the upper page will be referred to below as "upper page data."

[0057] 1.4 Cross-sectional structure of semiconductor memory device Next, the structure of the memory cell array 110 and its periphery will be described.

[0058] 4, in the memory cell array 110, a plurality of NAND strings NS are formed on a conductive layer 320. The conductive layer 320 is also called a buried source line (BSL), and corresponds to the source line SL shown in FIG.

[0059] A plurality of wiring layers 333 functioning as select gate lines SGS, a plurality of wiring layers 332 functioning as word lines WL, and a plurality of wiring layers 331 functioning as select gate lines SGD are stacked above the conductive layer 320. Insulating layers (not shown) are disposed between each of the stacked wiring layers 333, 332, and 331.

[0060] A plurality of memory holes 334 are formed in the memory cell array 110. The memory holes 334 are holes that vertically penetrate the above-mentioned wiring layers 333, 332, and 331 and the insulating layers (not shown) between them, and reach the conductive layer 320. A block insulating film 335, a charge storage layer 336, and a gate insulating film 337 are sequentially formed on the side surfaces of the memory holes 334, and a conductive pillar 338 is further embedded inside the memory holes 334. The conductive pillar 338 is made of, for example, polysilicon and functions as a region where a channel is formed during operation of the memory cell transistors MT and select transistors ST1 and ST2 included in the NAND string NS. In this way, a pillar-shaped body made of the block insulating film 335, the charge storage layer 336, the gate insulating film 337, and the conductive pillar 338 is formed inside the memory holes 334.

[0061] Of the pillars formed inside the memory holes 334, the portions that intersect with the stacked wiring layers 333, 332, and 331 function as transistors. Of these multiple transistors, the portion that intersects with the wiring layer 331 functions as a select transistor ST1. Of the multiple transistors, the portion that intersects with the wiring layer 332 functions as a memory cell transistor MT (MT0 to MT7). Of the multiple transistors, the portion that intersects with the wiring layer 333 functions as a select transistor ST2. With this configuration, each of the pillars formed inside each memory hole 334 functions as a NAND string NS shown in FIG. 3. The conductive pillars 338 inside the pillars function as channels of the memory cell transistors MT and the select transistors ST1 and ST2.

[0062] A wiring layer that functions as a bit line BL is formed above the conductor pillar 338. A contact plug 339 that connects the conductor pillar 338 and the bit line BL is formed at the upper end of the conductor pillar 338.

[0063] A plurality of configurations similar to the configuration shown in Fig. 4 are arranged in the depth direction of the paper of Fig. 4. A set of a plurality of NAND strings NS aligned in a row in the depth direction of the paper of Fig. 4 forms one string unit SU.

[0064] In the semiconductor memory device 2a of this embodiment, a peripheral circuit PER is provided below the memory cell array 110, i.e., between the memory cell array 110 and the semiconductor substrate 300. The peripheral circuit PER is a circuit provided to perform data write, read, and erase operations in the memory cell array 110. The sense amplifier 120, row decoder 130, and voltage generation circuit 43 shown in FIG. 2 are part of the peripheral circuit PER. The peripheral circuit PER includes various transistors, RC circuits, and the like. In the example shown in FIG. 4, a transistor TR formed on the semiconductor substrate 300 is electrically connected to a bit line BL located above the memory cell array 110 via a contact 924.

[0065] 1.5 Sense amplifier configuration Next, the circuit configuration of the sense amplifier 120 will be described.

[0066] The sense amplifier 120 includes a plurality of sense amplifier units associated with the plurality of bit lines BL, respectively. Fig. 5 shows an extracted circuit configuration of one of these sense amplifier units SAU.

[0067] 5, the sense amplifier unit SAU includes a sense amplifier section SA and latch circuits SDL, ADL, BDL, CDL, and XDL. The sense amplifier section SA and the latch circuits SDL, ADL, BDL, CDL, and XDL are connected by a bus LBUS so as to be able to transmit and receive data to and from each other.

[0068] For example, in a read operation, the sense amplifier unit SA senses data read onto the corresponding bit line BL and determines whether the read data is “0” or “1.” The sense amplifier unit SA includes, for example, a transistor TR1 which is a p-channel MOS transistor, transistors TR2 to TR9 which are n-channel MOS transistors, and a capacitor C10.

[0069] One end of transistor TR1 is connected to the power supply line, and the other end of transistor TR1 is connected to transistor TR2. The gate of transistor TR1 is connected to node INV in latch circuit SDL. One end of transistor TR2 is connected to transistor TR1, and the other end of transistor TR2 is connected to node COM. A signal BLX is input to the gate of transistor TR2. One end of transistor TR3 is connected to node COM, and the other end of transistor TR3 is connected to transistor TR4. A signal BLC is input to the gate of transistor TR3. Transistor TR4 is a high-voltage MOS transistor. One end of transistor TR4 is connected to transistor TR3. The other end of transistor TR4 is connected to the corresponding bit line BL. A signal BLS is input to the gate of transistor TR4.

[0070] One end of transistor TR5 is connected to node COM, and the other end of transistor TR5 is connected to node SRC. The gate of transistor TR5 is connected to node INV. One end of transistor TR6 is connected between transistor TR1 and transistor TR2, and the other end of transistor TR6 is connected to node SEN. A signal HLL is input to the gate of transistor TR6. One end of transistor TR7 is connected to node SEN, and the other end of transistor TR7 is connected to node COM. A signal XXL is input to the gate of transistor TR7.

[0071] One end of transistor TR8 is grounded, and the other end of transistor TR8 is connected to transistor TR9. The gate of transistor TR8 is connected to node SEN. One end of transistor TR9 is connected to transistor TR8, and the other end of transistor TR9 is connected to bus LBUS. A signal STB is input to the gate of transistor TR9. One end of capacitor C10 is connected to node SEN. The other end of capacitor C10 receives clock CLK.

[0072] The signals BLX, BLC, BLS, HLL, XXL, and STB are generated by, for example, a sequencer 41. A voltage VDD, which is, for example, the internal power supply voltage of the semiconductor memory device 2a, is applied to a power supply line connected to one end of the transistor TR1, and a voltage VSS, which is, for example, the ground voltage of the semiconductor memory device 2a, is applied to the node SRC.

[0073] The latch circuits SDL, ADL, BDL, CDL, and XDL temporarily hold read data. The latch circuit XDL is connected to the input / output circuit 21 and is used for inputting and outputting data between the sense amplifier unit SAU and the input / output circuit 21. By being held in the latch circuit XDL, the read data becomes available for output from the input / output circuit 21 to the memory controller 1. For example, data read by the sense amplifier unit SAU is stored in one of the latch circuits ADL, BDL, and CDL, then transferred to the latch circuit XDL, and output from the latch circuit XDL to the input / output circuit 21. Also, for example, data input from the memory controller 1 to the input / output circuit 21 is transferred from the input / output circuit 21 to the latch circuit XDL, and then transferred from the latch circuit XDL to one of the latch circuits ADL, BDL, and CDL. In this embodiment, the latch circuit XDL is an example of a data holding unit.

[0074] The latch circuit SDL includes, for example, inverters IV11 and IV12 and n-channel MOS transistors TR13 and TR14. The input node of the inverter IV11 is connected to a node LAT. The output node of the inverter IV11 is connected to a node INV. The input node of the inverter IV12 is connected to the node INV. The output node of the inverter IV12 is connected to the node LAT. One end of the transistor TR13 is connected to the node INV, and the other end of the transistor TR13 is connected to the bus LBUS. A signal STI is input to the gate of the transistor TR13. One end of the transistor TR14 is connected to the node LAT, and the other end of the transistor TR14 is connected to the bus LBUS. A signal STL is input to the gate of the transistor TR14. For example, the data held at the node LAT corresponds to the data held in the latch circuit SDL. The data held at the node INV corresponds to the inverted data of the data held at the node LAT. The circuit configuration of the latch circuits ADL, BDL, CDL, and XDL is similar to that of the latch circuit SDL, for example, and therefore description thereof will be omitted.

[0075] 1.6 Threshold voltage distribution of memory cell transistors Next, the threshold distribution of the memory cell transistor MT will be described.

[0076] 6 is a diagram showing a schematic diagram of the threshold distribution of the memory cell transistors MT, etc. The diagram in the middle of Fig. 6 shows the correspondence relationship between the threshold voltage of the memory cell transistors MT (horizontal axis) and the number of memory cell transistors MT (vertical axis).

[0077] When the TLC method is adopted as in this embodiment, the multiple memory cell transistors MT form eight threshold distributions, as shown in the middle of Figure 6. These eight threshold distributions (write levels) are referred to as the "ER" level, "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level, in order from lowest to highest threshold voltage. The table in the top of Figure 6 shows an example of 3-bit data assigned to each threshold voltage level.

[0078] In this way, the threshold voltage of the memory cell transistor MT in this embodiment can take one of eight preset candidate levels, and data is assigned as described above corresponding to each candidate level.

[0079] Between adjacent threshold distributions, a read voltage is set to be used in a read operation. The "read voltage" is the voltage applied to the word line WL connected to the memory cell transistor MT to be read, i.e., the selected word line, during a read operation. In a read operation, data is determined based on whether the threshold voltage of the memory cell transistor MT to be read is higher than the applied read voltage. For example, as shown in the lower diagram of Figure 6, the read voltage VrA, which determines whether the threshold voltage of the memory cell transistor MT is included in the "ER" level or the "A" level, is set between the maximum threshold voltage at the "ER" level and the minimum threshold voltage at the "A" level. The other read voltages VrB, VrC, VrD, VrE, VrF, and VrG are set in the same way as the read voltage VrA.

[0080] A read pass voltage VPASS_READ is set to a voltage higher than the maximum threshold voltage of the highest threshold distribution (for example, the “G” level). A memory cell transistor MT with the read pass voltage VPASS_READ applied to its gate is turned on regardless of the data stored therein.

[0081] When the data allocation described above is applied, in a read operation, one page of data of the lower bits (lower page data) can be determined by the read result using read voltages VrA and VrE. One page of data of the middle bits (middle page data) can be determined by the read result using read voltages VrB, VrD, and VrF. One page of data of the upper bits (upper page data) can be determined by the read result using read voltages VrC and VrG.

[0082] 1.7 Programming of semiconductor memory devices Next, a program operation of the semiconductor memory device 2a will be described. In the following, an example in which the target of the program operation is the plane PL1 will be described, but the same applies to the case in which the target of the program operation is the plane PL2.

[0083] FIG. 7 shows the potential changes of each wiring during a program operation. During a program operation, the sense amplifier 120 changes the potential of each bit line BL in accordance with the program data. A ground voltage VSS (0V), for example, is applied as an "L" level to the bit line BL connected to the memory cell transistor MT to be programmed (whose threshold voltage should be increased). A voltage of 2.5V, for example, is applied as an "H" level to the bit line BL connected to the memory cell transistor MT not to be programmed (whose threshold voltage should be maintained). The former bit line BL is denoted as "BL(0)" in FIG. 7. The latter bit line BL is denoted as "BL(1)" in FIG. 7.

[0084] The row decoder 130 selects one of the blocks BLK as a target for the write operation, and further selects one of the string units SU. More specifically, a voltage of, for example, 5 V is applied to the select gate line SGD (selected select gate line SGDsel) in the selected string unit SU from the voltage generation circuit 43 via the row decoder 130. This turns on the select transistor ST1. On the other hand, a voltage of, for example, VSS is applied to the select gate line SGS from the voltage generation circuit 43 via the row decoder 130. This turns off the select transistor ST2.

[0085] Furthermore, a voltage of, for example, 5V is applied to the select gate line SGD (unselected select gate line SGDusel) of the unselected string unit SU in the selected block BLK from the voltage generating circuit 43 via the row decoder 130. This turns on the select transistor ST1. Note that the select gate line SGS is commonly connected in the string units SU included in each block BLK. Therefore, the select transistor ST2 is also turned off in the unselected string units SU.

[0086] Furthermore, the voltage VSS, for example, is applied to the select gate lines SGD and SGS in the unselected block BLK from the voltage generating circuit 43 via the row decoder 130. This turns off the select transistors ST1 and ST2.

[0087] The source line SL is set to a potential higher than the potential of the select gate line SGS, for example, 1V.

[0088] Thereafter, the potential of the selected select gate line SGDsel in the selected block BLK is set to, for example, 2.5V. This potential is a voltage that can turn on the select transistor ST1 corresponding to the bit line BL(0) to which 0V is applied in the above example, and cut off the select transistor ST1 corresponding to the bit line BL(1) to which 2.5V is applied. As a result, in the selected string unit SU, the select transistor ST1 corresponding to the bit line BL(0) is turned on, and the select transistor ST1 corresponding to the bit line BL(1) to which 2.5V is applied is cut off. Meanwhile, the potential of the unselected select gate lines SGDusel is set to, for example, voltage VSS. As a result, in the unselected string units SU, the select transistor ST1 is cut off regardless of the potentials of the bit lines BL(0) and BL(1).

[0089] The row decoder 130 then selects one of the word lines WL in the selected block BLK as the target of the write operation. A voltage VPGM, for example, is applied to the word line WL to be the target of the write operation (selected word line WLsel) from the voltage generation circuit 43 via the row decoder 130. On the other hand, a voltage VPASS_PGM, for example, is applied to the other word lines WL (unselected word lines WLusel) from the voltage generation circuit 43 via the row decoder 130. The voltage VPGM is a high voltage for injecting electrons into the charge storage layer 336 by the tunneling phenomenon. The voltage VPASS_PGM is a voltage that turns on the memory cell transistors MT connected to the word line WL while not changing the threshold voltage. The voltage VPGM is a voltage higher than VPASS_PGM.

[0090] In the NAND string NS corresponding to the bit line BL(0) to be programmed, the select transistor ST1 is turned on. Therefore, the channel potential of the memory cell transistor MT connected to the selected word line WLsel becomes 0 V. The potential difference between the control gate and the channel increases, and as a result, electrons are injected into the charge storage layer 336, increasing the threshold voltage of the memory cell transistor MT.

[0091] In the NAND string NS corresponding to the bit line BL(1) that is not the programming target, the select transistor ST1 is cut off. As a result, the channel of the memory cell transistor MT connected to the selected word line WLsel is electrically floating, and the channel potential rises to near the voltage VPGM due to capacitive coupling with the word line WL. The potential difference between the control gate and the channel becomes small, and as a result, electrons are not injected into the charge storage layer 336, so the threshold voltage of the memory cell transistor MT is maintained. To be precise, the threshold voltage does not change enough to transition the threshold distribution level to a higher distribution.

[0092] 1.8 Read operation of semiconductor memory device Next, the read operation of the semiconductor memory device 2a will be described. The following describes an example in which the target of the read operation is plane PL1, but the same applies to the case of plane PL2. The verify operation performed following the program operation is the same as the read operation described below.

[0093] 8 shows the potential changes of each wiring during a read operation. In a read operation, a NAND string NS including a memory cell transistor MT to be read is selected. Alternatively, a string unit SU including a page to be read is selected.

[0094] First, a voltage of, for example, 5 V is applied to the selected select gate line SGDsel, the unselected select gate lines SGDusel, and the select gate line SGS from the voltage generation circuit 43 via the row decoder 130. As a result, the select transistors ST1 and ST2 included in the selected block BLK are turned on. In addition, a read pass voltage VPASS_READ, for example, is applied to the selected word line WLsel and the unselected word lines from the voltage generation circuit 43 via the row decoder 130. The read pass voltage VPASS_READ is a voltage that can turn on the memory cell transistors MT regardless of the threshold voltage of the memory cell transistors MT, but does not change the threshold voltage. As a result, current is conducted in all NAND strings NS included in the selected block BLK, regardless of whether they are selected string units SU or unselected string units SU.

[0095] Next, a read voltage Vr such as VrA is applied to the word line WL (selected word line WLsel) connected to the memory cell transistor MT that is the target of the read operation from the voltage generation circuit 43 via the row decoder 130. A read pass voltage VPASS_READ is applied to the other word lines (unselected word lines WLusel).

[0096] Furthermore, while the voltages applied to the selected select gate line SGDsel and the select gate line SGS are maintained, a voltage VSS, for example, is applied to the unselected select gate line SGDusel from the voltage generation circuit 43 via the row decoder 130. As a result, the select transistor ST1 included in the selected string unit SU remains on, but the select transistor ST1 included in the unselected string units SU is turned off. Note that the select transistor ST2 included in the selected block BLK is turned on regardless of whether it is a selected string unit SU or an unselected string unit SU.

[0097] As a result, the NAND string NS included in the unselected string unit SU does not form a current path because at least the selection transistor ST1 is turned off. On the other hand, the NAND string NS included in the selected string unit SU forms or does not form a current path depending on the relationship between the read voltage Vr applied to the selected word line WLsel and the threshold voltage of the memory cell transistor MT.

[0098] The sense amplifier 120 applies a voltage to the bit line BL connected to the selected NAND string NS. In this state, the sense amplifier 120 reads data based on the value of the current flowing through the bit line BL. Specifically, it determines whether the threshold voltage of the memory cell transistor MT that is the target of the read operation is higher than the read voltage applied to the memory cell transistor MT. Note that data reading may also be performed based on the change in the potential of the bit line BL over time, rather than based on the value of the current flowing through the bit line BL. In the latter case, the bit line BL is precharged to a predetermined potential.

[0099] The verify operation described above is performed in the same manner as the read operation. In the verify operation, a verify voltage such as VfyA is applied from the voltage generation circuit 43 via the row decoder 130 to the word line WL connected to the memory cell transistor MT to be verified.

[0100] Note that the operation of applying a voltage of 5V to the selected select gate line SGDsel and the unselected select gate lines SGDusel in the initial stage of the program operation described above may be omitted. Similarly, the operation of applying a voltage of 5V to the unselected select gate lines SGDusel and applying a read pass voltage VPASS_READ to the selected word line WLsel in the initial stage of the read operation (verify operation) described above may be omitted.

[0101] 1.9 Specific configuration for reading data from a semiconductor memory device Next, a specific configuration for reading data from the semiconductor memory device 2a will be described. Fig. 9 is a diagram schematically illustrating a configuration along a path from the memory cell array 110 to the input / output pad group 31 in the semiconductor memory device 2a, i.e., a path along which data is read from the memory cell array 110.

[0102] 9, the sense amplifier 120 includes the sense amplifier unit SAU shown in FIG. 5, a plurality of latch circuits XDL, and a multiplexer 121. Data read from the memory cell array 110 is transmitted from the sense amplifier unit SAU to the latch circuit XDL, where it is temporarily held, and then transferred to the first holding unit 510 via the multiplexer 121. The multiplexer 121 and the first holding unit 510 are connected by a first data bus 501 consisting of, for example, 128 wires. Note that the number of wires included in the first data bus 501 is not limited to 128. The number of wires included in the first data bus 501 is less than the number of wires connecting the plurality of latch circuits XDL and the multiplexer 121. The multiplexer 121 sequentially transfers each piece of data transmitted from the plurality of latch circuits XDL to the first holding unit 510 via the first data bus 501.

[0103] The first holding unit 510 holds multiple pieces of data read from the memory cell array 110 and is a storage device configured to perform a so-called "First In First Out (FIFO)" operation. The first holding unit 510 temporarily holds multiple pieces of data transferred from the multiplexer 121 and outputs the data to the input / output circuit 21 in the order of the data input first. The first holding unit 510 and the input / output circuit 21 are connected via a second data bus 502 consisting of, for example, 16 signal lines. Note that the number of lines included in the second data bus 502 is not limited to 16. The data input from the first holding unit 510 to the input / output circuit 21 is temporarily held by the second holding unit 520 and then output to the outside from the input / output pad group 31 as a signal DQ<7:0>.

[0104] The input / output circuit 21 has a second holding unit 520, a write pointer generation circuit 541, a read pointer generation circuit 542, a multiplexer 531, and a driver 532. Circuits combining the second holding unit 520, the write pointer generation circuit 541, the read pointer generation circuit 542, the multiplexer 531, and the driver 532 are individually provided corresponding to each of the eight pads of the input / output pad group 31, i.e., the eight pads corresponding to the signals DQ<7:0>. In other words, the input / output circuit 21 is provided with eight each of the second holding units 520 and multiplexers 531. In FIG. 9, of these, only eight second holding units 520 and eight multiplexers 531 are provided. <0> Only those connected to the pads are shown, and the others are omitted from the illustration.

[0105] The second holding unit 520 receives data transmitted from the first holding unit 510 and holds multiple pieces of the data. The second holding unit 520 is divided into a section that holds even data and a section that holds odd data. The former section will be referred to below as the "second holding unit 521." The latter section will be referred to below as the "second holding unit 522."

[0106] The second holding unit 520 is a storage device configured to perform a so-called "first-in, first-out (FIFO)" operation, similar to the first holding unit 510. The second holding unit 520 temporarily accepts data input from the first holding unit 510, and then stores the data in the DQ in the order that it was input. <0> Such data output is alternately performed by the second holding unit 521 and the second holding unit 522 via the multiplexer 531 and the driver 532.

[0107] The write pointer generation circuit 541 is a circuit that generates a write pointer Wptr. The write pointer Wptr is a pointer that indicates the holding position (i.e., write position) when data transmitted from the first holding unit 510 is held in the second holding unit 520.

[0108] The read pointer generation circuit 542 is a circuit that generates a read pointer Rptr. The read pointer Rptr is a pointer that indicates the storage position (i.e., read position) of the data in the second storage unit 520 when the data is transmitted from the second storage unit 520 to the driver 532.

[0109] A pair of circuits consisting of a write pointer generation circuit 541 and a read pointer generation circuit 542 is provided for each of the second holding unit 521 and the second holding unit 522. In Fig. 9, only the write pointer generation circuit 541 and the read pointer generation circuit 542 provided for the second holding unit 522 are shown, and the write pointer generation circuit 541 and the read pointer generation circuit 542 provided for the second holding unit 521 are not shown.

[0110] The transmission of data from the first holding unit 510 to the second holding unit 520 and the transmission of data from the second holding unit 520 to the multiplexer 531 are controlled by the sequencer 41.

[0111] Specifically, the sequencer 41 controls the operations of the first holding unit 510 and the write pointer generation circuit 541 by transmitting a clock signal CLK1 to each of the first holding unit 510 and the write pointer generation circuit 541. The clock signal CLK1 is a signal that defines the timing at which the second holding unit 520 takes in data. The write pointer generation circuit 541 generates a write pointer Wptr based on the input clock signal CLK1. The write pointer Wptr is incremented by the write pointer generation circuit 541 when the clock signal CLK1 rises from the "L" level to the "H" level. By incrementing the write pointer Wptr, the holding position (i.e., write position) of the data taken in from the first holding unit 510 in the second holding unit 520 is sequentially switched.

[0112] Furthermore, the sequencer 41 controls the operations of the read pointer generation circuit 542 and the multiplexer 531 by transmitting a clock signal CLK2 to each of them. The sequencer 41 generates the clock signal CLK2 based on the read enable signal / RE input from the memory controller 1. The read pointer generation circuit 542 generates a read pointer Rptr based on the input clock signal CLK2. The read pointer Rptr is incremented by the read pointer generation circuit 542 when the clock signal CLK2 rises from the "L" level to the "H" level. By incrementing the read pointer Rptr, the holding position (i.e., read position) of the data in the second holding unit 520 when transmitting the data from the second holding unit 520 to the driver 532 is sequentially switched. This allows the second holding unit 520 to perform a "first-in, first-out" operation.

[0113] The multiplexer 531 alternately receives the even data input from the second holding unit 521 and the odd data input from the second holding unit 522 and outputs this to the driver 532 .

[0114] In order to operate at high speed, the first holding unit 510 and the input / output circuit 21 are configured using transistors with a lower threshold voltage than, for example, transistors used in the sense amplifier 120. In this embodiment, the first holding unit 510 and the input / output circuit 21 are an example of a data transfer circuit provided between the latch circuit XDL and the input / output pad group 31.

[0115] 10 is a block diagram showing a configuration for supplying current to the first holding unit 510 and the input / output circuit 21. Note that FIG. <0> Only those corresponding to the pads are shown, and the other ones are omitted from the illustration.

[0116] As shown in FIG. 10, the power supply voltage input terminals of the first holding unit 510 and the input / output circuit 21 are connected to a VCCQ pad 60 via a wiring 61. <0> Connected to VCCQ pad 60 <0> is included in the power supply input terminal group 33 shown in FIG. 2. VCCQ pad 60 <0> supplies the power supply voltage VCCQ to the first holding unit 510 and the input / output circuit 21 via the wiring 61.

[0117] The ground voltage input terminal of the first holding unit 510 is connected to a VSS pad 62 via a wiring 63a and a wiring 64. <0> The ground voltage input terminal of the input / output circuit 21 is connected to the VSS pad 62 via the wiring 63b and the wiring 64. <0> Connected to VSS pad 62 <0> is included in the power supply input terminal group 33 shown in FIG. 2. VSS pad 62 <0> applies the ground voltage VSS to the first holding unit 510 and the input / output circuit 21 via the wirings 63a, 63b and wiring 64.

[0118] Transistors 65a and 65b functioning as foot switches are provided on the wirings 63a and 63b, respectively. When the transistors 65a and 65b are turned on, current is supplied to the first holding unit 510 and the input / output circuit 21, enabling the first holding unit 510 and the input / output circuit 21 to operate. When the transistors 65a and 65b are turned off, the supply of current to the first holding unit 510 and the input / output circuit 21 is stopped. This makes it possible to reduce, for example, the standby current of the first holding unit 510 and the input / output circuit 21. The transistors 65a and 65b are controlled by a control signal FSW_enable transmitted from the sequencer 41. In this embodiment, the transistors 65a and 65b are an example of a cutoff unit and a switching element capable of cutting off the supply of current to the first holding unit 510 and the input / output circuit 21.

[0119] 1.10 Read operation of semiconductor memory device Next, we will explain specific signal exchanges that occur during a read operation between the semiconductor memory device 2a and the memory controller 1. Below, we will explain an example in which the target of the read operation is plane PL1, but the same applies to the case in which plane PL2 is used.

[0120] 11, during a read operation, first, at time t10, the memory controller 1 switches the chip enable signal / CE0 corresponding to the semiconductor memory device 2a from the "H" level to the "L" level, causing the semiconductor memory device 2a to transition to an enable state. This allows the semiconductor memory device 2a to receive signals from the memory controller 1. At this time, the sequencer 41 switches the transistors 65a and 65b shown in FIG. 10 from the off state to the on state, thereby supplying current to the first holding unit 510 and the input / output circuit 21, thereby driving the first holding unit 510 and the input / output circuit 21.

[0121] Next, the memory controller 1 sequentially inputs signals consisting of "00h", multiple "ADD"s, and "30h" as signals DQ<7:0> to the semiconductor memory device 2a. "00h" is a command for executing a data read operation from the memory cell array 110. "ADD" is a signal for specifying an address from which data is read. "30h" is a command for starting the read operation. In FIG. 10, t11 indicates the time when the memory controller 1 starts inputting signals DQ<7:0> to the semiconductor memory device 2a. Hereinafter, the signal consisting of "00h", multiple "ADD"s, and "30h" will also be referred to as the "read operation command set CSr."

[0122] After time t11, the memory controller 1 starts toggling the write enable signal / WE. As mentioned above, the write enable signal / WE is a signal for capturing a signal from the memory controller 1 to the semiconductor memory device 2a. The write enable signal / WE is alternately switched (toggled) between the "H" level and the "L" level. The write enable signal / WE, which is switched in this way, is used as an "capture signal" for capturing data.

[0123] When inputting "00h" and "30h" contained in the signal DQ<7:0>, the memory controller 1 switches the command latch enable signal CLE from "L" level to "H" level, thereby fetching "00h" and "30h" as commands into the semiconductor memory device 2a. When inputting multiple "ADD"s contained in the signal DQ<7:0>, the memory controller 1 switches the address latch enable signal ALE from "L" level to "H" level, thereby fetching the multiple "ADD"s into the semiconductor memory device 2a as address information from which data is to be read. The address information fetched by the semiconductor memory device 2a is stored in the register 42. The address information includes a block address and a row address.

[0124] In FIG. 10, t12 indicates the time when "30h" is input into the semiconductor memory device 2a. After time t12, internal operation begins in the semiconductor memory device 2a. Specifically, the sequencer 41 operates the row decoder 130 based on address information stored in the register 42, which is the address from which data is to be read. The row decoder 130 receives address information from the register 42, selects a block in the memory cell array 110 based on the block address included in the address information, and selects a word line WL based on the row address included in the address information. The row decoder 130 then switches the open / close states of the switches so that a voltage from the voltage generation circuit 43 is applied to the selected word line WL. This completes preparations for reading data from the memory cell array 110. Next, the sense amplifier 120 acquires data read from the memory cell transistors MT of the memory cell array 110 to the bit lines BL and transfers the acquired read data to the first holding unit 510 and the input / output circuit 21. This completes preparations for reading data from the semiconductor memory device 2a. 11, the time allocated for such internal operation of the semiconductor memory device 2a is indicated by tR. That is, at time t13, when a predetermined time tR has elapsed since time t12, the semiconductor memory device 2a is ready to read data. The predetermined time tR is, for example, 50 μsec to 100 μsec.

[0125] At time t14, a predetermined time after time t13, the memory controller 1 starts toggling the read enable signal / RE. As described above, the read enable signal / RE is a signal used by the memory controller 1 to read data from the semiconductor memory device 2a, and is input to the input / output pad group 31 of the semiconductor memory device 2a. After time t13, the read enable signal / RE is alternately switched (toggled) between the "H" level and the "L" level. The read enable signal / RE switched in this manner is used as a "read signal" for reading data.

[0126] The semiconductor memory device 2a outputs data as the signal DQ<7:0> and switches the data strobe signal DQS between the "H" level and the "L" level each time the read enable signal / RE switches (i.e., each time a read signal is input). In FIG. 11, each piece of data output as the signal DQ<7:0> is indicated as "D." The timing at which the first data is output and the data strobe signal DQS switches is indicated as time t15. In FIG. 11, the arrows indicate the correspondence between the switching of the read enable signal / RE input from the memory controller 1 and the switching of the data strobe signal DQS output from the semiconductor memory device 2a.

[0127] The output of read data from the semiconductor memory device 2a is performed by dividing one piece of data into even data consisting of even bits and odd data consisting of odd bits, and outputting them alternately. Each piece of data indicated by "D" in Fig. 11 is output as either even data or odd data.

[0128] 1, in a memory system 3 including multiple semiconductor memory devices 2a-2d, the memory controller 1 may instruct a specific semiconductor memory device 2a to perform a data read operation, and then, before acquiring data from the specific semiconductor memory device 2a, may instruct another semiconductor memory device 2b to perform various operations, such as a data read operation, via an interrupt. For example, when signals are exchanged between the memory controller 1 and the semiconductor memory device 2a as shown in FIG. 11, the instruction to the semiconductor memory device 2a to perform the data read operation is completed at time t12, but the memory controller 1 must wait from time t12 to time t13 until the internal operation of the semiconductor memory device 2a is completed. If the memory controller 1 instructs another semiconductor memory device 2b to perform a specific operation during this period, as shown in FIG. 12, the memory controller 1 switches the chip enable signal / CE0 from low to high at a specific time t20 after time t12. Furthermore, the memory controller 1 switches the chip enable signal / CE1 of another semiconductor memory device 2b from "H" level to "L" level to enable the semiconductor memory device 2b, thereby instructing the semiconductor memory device 2b to perform a predetermined operation.

[0129] 12, if a current continues to flow through the first holding unit 510 and the input / output circuit 21 after time t13 until the memory controller 1 starts reading data from the semiconductor memory device 2a, the standby current increases. In particular, since the first holding unit 510 and the input / output circuit 21 use transistors with low threshold voltages to speed up their operations, there is a concern that the standby current may easily increase.

[0130] Therefore, in this embodiment, after the internal operation of the semiconductor memory device 2a is completed at time t13, if the chip enable signal / CE0 is not at the “L” level at time t21, which is a predetermined time tS after time t13, i.e., if the semiconductor memory device 2a is not enabled, the sequencer 41 switches the transistors 65a and 65b shown in FIG. 10 to the off state using the control signal FSW_enable. As a result, the supply of current to the first holding unit 510 and the input / output circuit 21 is stopped at time t21, thereby reducing the standby current of the first holding unit 510 and the input / output circuit 21 after time t21. Note that the predetermined time tS is hereinafter referred to as the “standby time tS.” After time t21, the semiconductor memory device 2a enters a state of waiting for the memory controller 1 to read data.

[0131] On the other hand, when the supply of current to the first holding unit 510 and the input / output circuit 21 is stopped at time t21, the data transferred from the sense amplifier 120 to the first holding unit 510 and the input / output circuit 21 is erased. Therefore, when the memory controller 1 subsequently resumes reading data, the memory controller 1 needs to input a data out command to the semiconductor memory device 2a.

[0132] 12, when the memory controller 1 resumes reading data from the semiconductor memory device 2a at time t22 after time t21, the memory controller 1 first switches the chip enable signal / CE0 from "H" level to "L" level. This enables the semiconductor memory device 2a. At this time, the sequencer 41 switches the transistors 65a and 65b shown in FIG. 10 from an OFF state to an ON state using the control signal FSW_enable, thereby supplying current to the first holding unit 510 and the input / output circuit 21, thereby driving the first holding unit 510 and the input / output circuit 21.

[0133] Next, the memory controller 1 sequentially inputs signals consisting of "05h", multiple "ADD" signals, and "E0h" as signals DQ<7:0> to the semiconductor memory device 2a. "05h" is a command for causing the memory cell array 110 to execute a data-out operation. "ADD" is a signal for specifying an address from which data is read. "E0h" is a command for starting a read operation. In FIG. 12, t23 indicates the time when the memory controller 1 starts inputting signals DQ<7:0> to the semiconductor memory device 2a. Hereinafter, the signal consisting of "05h", multiple "ADD" signals, and "E0h" will also be referred to as the "data-out command set CSd."

[0134] After time t23, the memory controller 1 starts toggling the write enable signal / WE. Furthermore, when the memory controller 1 inputs the data-out command set CSd as the signal DQ<7:0>, it switches the command latch enable signal CLE and the address latch enable signal ALE between the "H" level and the "L" level as shown in FIG. 12 to load "05h" and "E0h" as commands into the semiconductor memory device 2a, and load a plurality of "ADD"s into the semiconductor memory device 2a as address information from which data is to be read. The address information loaded into the semiconductor memory device 2a is stored in the register 42.

[0135] In FIG. 12, t24 indicates the time when "E0h" is captured by the semiconductor memory device 2a. After time t25, which is a predetermined time tWHR2 after time t24, the memory controller 1 starts toggling the read enable signal / RE. The predetermined time tWHR2 is a time secured for data transfer from the sense amplifier 120 to the first holding unit 510 and the input / output circuit 21, thereby preparing to enable data reading from the semiconductor memory device 2a. After time t25, the memory controller 1 switches each of the read enable signal / RE and the data strobe signal DQS between the "H" level and the "L" level, as shown in FIG. 12. As a result, the semiconductor memory device 2a outputs data to the memory controller 1 as the signal DQ<7:0>.

[0136] As described above, in the semiconductor memory device 2a of this embodiment, when the supply of current to the first holding unit 510 and the input / output circuit 21 is temporarily stopped at time t21, it is necessary to input the data-out command set CSd to the semiconductor memory device 2a again as the signal DQ<7:0>. While this data-out command set CSd is being input from the memory controller 1 to the semiconductor memory device 2a, other operations such as data input / output operations cannot be performed on the other semiconductor memory devices 2b to 2d. This is a factor that deteriorates the bus utilization efficiency of the semiconductor memory device 2a.

[0137] 12, when the supply of current to the first holding unit 510 and the input / output circuit 21 has elapsed after the elapse of the standby time tS from the time t13, it is possible to continue to hold the read data in the first holding unit 510 and the input / output circuit 21. In this case, it is possible to read data from the semiconductor memory device 2a to the memory controller 1 without inputting a data-out command set CSd from the memory controller 1 to the semiconductor memory device 2a. However, if the supply of current to the first holding unit 510 and the input / output circuit 21 is not stopped, there is a concern that their standby currents may increase.

[0138] 12 is made variable as needed, thereby making it possible to change the timing at which the supply of current to the first holding unit 510 and the input / output circuit 21 is stopped after time t13. Next, the configuration of the semiconductor memory device 2a of this embodiment will be described.

[0139] In the semiconductor memory device 2a of this embodiment, a set value ta of the wait time tS is stored in a feature register 41a shown in Fig. 2. The memory controller 1 can store the set value ta of the wait time tS in the feature register 41a by inputting a signal DQ<7:0> including a set feature command to the semiconductor memory device 2a.

[0140] Specifically, the memory controller 1 executes a Set Feature operation when storing the setting value ta of the wait time tS in the feature register 41a. That is, the memory controller 1 inputs a signal DQ<7:0> including “CMD,” “C_ADD,” and “F_ADD” as shown in FIG. 13 to the semiconductor memory device 2a. “CMD” is a command for instructing the semiconductor memory device 2a to perform a Set Feature operation. The Set Feature operation is an operation for storing operational parameters specified as feature data in the feature register 41a. “C_ADD” is an address (feature address) that specifies the operational parameters to be set by the Set Feature operation. In other words, “C_ADD” is an address (feature address) that specifies the location in the feature register 41a where the operational parameters specified as feature data should be stored. “F_ADD” is the address of the feature register 41a where feature data D0 to D3 should be stored. The feature data D0 to D3 are the setting value ta of the wait time tS. The feature data D0 to D3 may be data input by the user operating the host 4. That is, in the memory system 3 of this embodiment, the user can set the waiting time tS to any value by operating the host 4.

[0141] When inputting the signal DQ<7:0> including "CMD", "C_ADD", and "F_ADD" to the semiconductor memory device 2a, the memory controller 1 switches the write enable signal / WE, the command latch enable signal CLE, and the address latch enable signal ALE between "H" level and "L" level as shown in FIG. 13, thereby fetching "CMD" as a command into the semiconductor memory device 2a and fetching "C_ADD" and "F_ADD" as addresses into the semiconductor memory device 2a.

[0142] In FIG. 13, t30 indicates the time when "F_ADD" is captured by the semiconductor memory device 2a. After time t31, which is a predetermined time after time t30, the feature data D0-D3 are transferred from the memory controller 1 to the semiconductor memory device 2a using the data strobe signals DQS and / DQS. That is, after time t31, the memory controller 1 inputs the signal DQ<7:0> including the feature data D0-D3 to the semiconductor memory device 2a and switches the data strobe signal DQS between the "H" level and the "L" level. As a result, the feature data D0-D3 are sequentially captured by the semiconductor memory device 2a in synchronization with the rising edges of the data strobe signals DQS and / DQS and stored in the feature register 41a. As a result, the set value ta for the wait time tS is stored in the feature register 41a.

[0143] The set value ta can be any time, such as a time longer than the predetermined time tR, a time longer than the period required for one page of data to be output, or the minimum time required for inputting a command to another semiconductor memory device. The following describes an example in which the set value ta is longer than the initial value tb shown in Figure 12, i.e., a case in which the relationship "ta>tb" holds between the initial value tb and the set value ta.

[0144] When instructing the semiconductor memory device 2a to perform a read operation, the memory controller 1 can change the waiting time tS from the initial value tb to a set value ta by inputting a signal DQ<7:0> including a prefix command.

[0145] For example, as shown in FIG. 14, when the memory controller 1 inputs the command set CSr for a read operation as the signal DQ<7:0>, it adds “xxh” before “00h.” “xxh” is a prefix command for instructing that the set value ta stored in the feature register 41a be used as the wait time tS. As shown in FIG. 14, when the signal DQ<7:0> including “xxh” is input to the semiconductor memory device 2a, the sequencer 41 of the semiconductor memory device 2a uses the set value ta stored in the feature register 41a as the wait time tS based on the prefix command xxh. As a result, as shown in FIG. 14, the wait time tS is changed from the initial value tb to the set value ta. Therefore, the sequencer 41 of the semiconductor memory device 2a continues to operate the first holding unit 510 and the input / output circuit 21 without switching the transistors 65a and 65b shown in FIG. 10 to the off state until the set value ta has elapsed from time t13. 14, when the memory controller 1 switches the chip enable signal / CE0 from "H" level to "L" level to resume reading data from the semiconductor memory device 2a at time t40, which is before the set value ta has elapsed since time t13, the memory controller 1 can immediately read data from the semiconductor memory device 2a as the signals DQ<7:0> after time t40. Specifically, after time t41, which is a predetermined time after time t40, the memory controller 1 can read data as the signals DQ<7:0> by switching the read enable signal / RE and the data strobe signal DQS between "H" level and "L" level. As is clear from comparison with the operation shown in FIG. 12, the operation of the semiconductor memory device 2a shown in FIG. 14 does not require input of the data-out command set CSd to the semiconductor memory device 2a, thereby improving the bus usage efficiency of the semiconductor memory device 2a.

[0146] Note that, if the memory controller 1 does not use the setting value ta stored in the feature register 41a as the wait time tS, as shown in FIG. 12, it does not input the prefix command xxh when inputting the command set CSr for the read operation as the signal DQ<7:0> to the semiconductor memory device 2a. As a result, if the command set CSr for the read operation does not include the prefix command xxh, the sequencer 41 of the semiconductor memory device 2a sets the wait time tS to the initial value tb. In this case, as shown in FIG. 12, if the chip enable signal / CE0 remains at the “H” level at time t21, which is the time tb after time t13, the sequencer 41 switches the transistors 65a and 65b shown in FIG. 10 to the off state using the control signal FSW_enable to stop the supply of current to the first holding unit 510 and the input / output circuit 21. Therefore, the standby current of the first holding unit 510 and the input / output circuit 21 is reduced after time t21.

[0147] Furthermore, the set value ta of the standby time tS can be set individually for each of the semiconductor memory devices 2a to 2d, which makes it possible to set an optimal set value ta of the standby time tS according to process variations and the like for each of the semiconductor memory devices 2a to 2d.

[0148] 1.11 Example of semiconductor memory device operation Next, an example of the operation of the semiconductor memory device 2a of this embodiment will be described. Note that the operations of the other semiconductor memory devices 2b to 2d are basically the same.

[0149] As shown in Figure 15, in the semiconductor memory device 2a of this embodiment, when the memory controller 1 requests a set feature operation from the semiconductor memory device 2a as shown in Figure 13 (step S10), the set value ta of the waiting time tS is set in the semiconductor memory device 2a by the set feature (step S20).

[0150] 15, the memory controller 1 transmits a command to the semiconductor memory device 2a to execute a data read operation (step S11). When the read command is received by the semiconductor memory device 2a (step S21), the semiconductor memory device 2a determines whether the prefix command xxh is attached to the read command (step S22). If the prefix command xxh is attached to the read command (step S22: YES), the semiconductor memory device 2a turns off the transistors 65a and 65b when the set value ta has elapsed after the internal operation for reading data from the memory cell array 110 is completed (step S23).

[0151] On the other hand, in the semiconductor memory device 2a, if the read command does not include the prefix command xxh (step S22: NO), the transistors 65a and 65b are turned off when the initial value tb has elapsed after the internal operation for reading data from the memory cell array 110 is completed (step S24).

[0152] 1.12 Actions and Effects of the Semiconductor Memory Device of the Present Embodiment As described above, the semiconductor memory device 2a includes the memory cell array 110, the latch circuit XDL (data holding unit), the input / output pad group 31 (pad unit), the first holding unit 510 (data transfer circuit), the input / output circuit 21 (data transfer circuit), and the sequencer 41 (control unit). The latch circuit XDL temporarily holds data read from the memory cell array 110. The input / output pad group 31 transmits and receives signals to and from the memory controller 1. The first holding unit 510 and the input / output circuit 21 are provided between the latch circuit XDL and the input / output pad group 31 and transfer the data held in the latch circuit XDL to the input / output pad group 31. The sequencer 41 controls the first holding unit 510 and the input / output circuit 21. The first holding unit 510 and the input / output circuit 21 are provided with transistors 65a and 65b (cutoff units) that can cut off the supply of current to them. When a standby time tS (predetermined time) has elapsed since data was transferred from the memory cell array 110 to the first holding unit 510 and the input / output circuit 21 via the latch circuit XDL without data transfer to the memory controller 1 being started, the sequencer 41 cuts off the supply of current to the first holding unit 510 and the input / output circuit 21 by the transistors 65a and 65b. The standby time tS is variable.

[0153] This configuration allows the standby time tS to be changed depending on the operating state of the semiconductor memory device 2a. Therefore, for example, in a situation where it is expected that a certain period of time will be required between when the memory controller 1 instructs the semiconductor memory device 2a to execute a read operation and when the data is actually output, the standby time tS can be set long. In this case, as shown in FIG. 14, even if the read operation of the semiconductor memory device 2a is started at time t10, then temporarily suspended at time t20, and then resumed at a subsequent time t40, it is possible to read data from the semiconductor memory device 2a without inputting a data-out command set CSd to the semiconductor memory device 2a. This improves the bus utilization efficiency of the semiconductor memory device 2a.

[0154] The transistors 65a and 65b are provided on the first holding unit 510 and the wiring 63a and 63b that apply the ground voltage to the input / output circuit 21.

[0155] According to this configuration, the supply of current to the first holding unit 510 and the input / output circuit 21 can be easily cut off by turning off the transistors 65a and 65b.

[0156] The semiconductor memory device 2a further includes a feature register 41a in which a set value ta of the standby time tS is stored. The sequencer 41 reads the set value ta of the standby time tS from the feature register 41a.

[0157] According to this configuration, it is possible to easily change the waiting time tS from the initial value tb to the set value ta.

[0158] In the semiconductor memory device 2a, the set value ta of the standby time tS stored in the feature register 41a can be updated based on a signal transmitted from the memory controller 1.

[0159] According to this configuration, the set value ta of the waiting time tS can be set to any value, thereby improving convenience.

[0160] Furthermore, the sequencer 41 changes the waiting time tS from the initial value tb to the set value ta based on the prefix command xxh sent from the memory controller 1.

[0161] With this configuration, the memory controller 1 can easily instruct the semiconductor memory device 2a to switch the wait time tS between the initial value tb and the set value ta. Therefore, for example, in a situation where it is expected that data output will be executed immediately after the memory controller 1 instructs the semiconductor memory device 2a to execute a read operation, the wait time tS can be left at the initial value tb. This prevents, for example, an increase in power consumption due to an unintended delay in the execution of data output caused by another factor.

[0162] The set value ta of the waiting time tS can be set by the user.

[0163] According to this configuration, the user can arbitrarily set the set value ta of the waiting time tS, thereby improving convenience.

[0164] 1.13 Modification of the memory system of the embodiment Next, a modification of the memory system 3 of the embodiment will be described.

[0165] As shown in FIG. 16, the semiconductor memory device 2a of this modification further includes a monitor circuit 23. The monitor circuit 23 monitors the operating state of the semiconductor memory device 2a and acquires monitor information therefrom. The monitor information includes, for example, information on signals transmitted between the memory controller 1 and the semiconductor memory device 2a, information on the current consumption of the semiconductor memory device 2a, and information on the temperature of the semiconductor memory device 2a. The monitor circuit 23 outputs the acquired monitor information to the sequencer 41. In this modification, the monitor circuit 23 is an example of a monitoring unit.

[0166] The sequencer 41 calculates a set value ta for the standby time tS based on the monitor information output from the monitor circuit 23. For example, based on the monitor information, the sequencer 41 calculates, as a recommended value tc, a standby time tS at which the memory controller 1 can read data without transmitting a data-out command set CSd. Furthermore, based on the monitor information, the sequencer 41 calculates, as a recommended value tc, a standby time tS at which the current consumption and temperature of the semiconductor memory device 2a can be optimized.

[0167] Furthermore, the sequencer 41 outputs a recommended value tc of the wait time tS to the memory controller 1 based on a request from the memory controller 1. In this case, if the memory controller 1 transmits the recommended value tc of the wait time tS to the host 4 based on a request from the host 4, the host 4 can output the recommended value tc of the wait time tS to the user.

[0168] According to this configuration, the user can set the setting value ta by referring to the recommended value tc of the standby time tS output from the host 4, thereby improving convenience.

[0169] The sequencer 41 may store the calculated recommended value tc of the wait time tS as a set value ta in the feature register 41a. With this configuration, the set value ta of the wait time tS can be automatically set in the semiconductor memory device 2a, eliminating the need for the memory controller 1 to input the set value ta of the wait time tS to the semiconductor memory device 2a, for example.

[0170] 2. Other Embodiments The present disclosure is not limited to the above specific examples.

[0171] For example, multiple setting values ​​ta for the wait time tS may be stored in the feature register 41a of one semiconductor memory device 2a. In this case, the memory controller 1 can change the wait time tS depending on the operating status of the semiconductor memory device 2a by specifying, using the prefix command xxh, which of the multiple setting values ​​ta to use as the wait time tS. In this way, the wait time tS may be selected from multiple setting values ​​ta.

[0172] The set value ta of the waiting time tS may be stored in advance in a predetermined register of the sequencer 41. In this case, the sequencer 41 sets the waiting time tS to either the set value ta or the initial value tb stored in the predetermined register, for example, depending on the operating status of the semiconductor memory device 2a.

[0173] The standby time tS can also be set to an infinite time. As a result, in the semiconductor memory device 2a, even if the data read by the memory controller 1 is interrupted during the internal operation of the memory cell array 110, for example, it is possible to realize an operation in which the supply of current to the first holding unit 510 and the input / output circuit 21 is not cut off, in other words, the semiconductor memory device 2a does not transition to a standby state.

[0174] 14, the sequencer 41 may determine whether a predetermined time has elapsed or not, and when the predetermined time has elapsed, may cut off the supply of current to, for example, the sense amplifier unit SAU, thereby making it possible to further reduce the standby current of the semiconductor memory device 2a.

[0175] In the semiconductor memory device 2a of the embodiment, the wait time tS can be switched between the initial value tb and the set value ta by using the prefix command xxh as shown in FIG. 15 . However, the method for switching the wait time tS is not limited to this. For example, the semiconductor memory device 2a may be able to switch the wait time tS between the initial value tb and the set value ta by using a set feature. For example, when the wait time tS is set to the initial value tb, as shown in FIG. 17 , the memory controller 1 sends a read command to the semiconductor memory device 2a (step S30), and when the read command is received by the semiconductor memory device 2a (step S40), the semiconductor memory device 2a turns off the transistors 65a and 65b when the initial value tb has elapsed after the internal operation for reading data from the memory cell array 110 is completed (step S41). Thereafter, when the memory controller 1 requests the semiconductor memory device 2a to perform a set feature operation as shown in FIG. 13 (step S31), the semiconductor memory device 2a switches the wait time tS to the set value ta by using the set feature (step S42). Thereafter, when the memory controller 1 transmits a read command to the semiconductor memory device 2a (step S32) and the read command is received by the semiconductor memory device 2a (step S43), the transistors 65a and 65b are turned off when the set value ta has elapsed after the internal operation for reading data from the memory cell array 110 is completed in the semiconductor memory device 2a (step S44). Note that, if it is desired to return the waiting time tS to the initial value tb thereafter, the memory controller 1 can switch the waiting time from the set value ta to the initial value tb by the set feature. Note that the operations of the other semiconductor memory devices 2b to 2d are basically similar.

[0176] In the semiconductor device 2a of the embodiment, the timing for turning off the transistors 65a and 65b may be changed as appropriate. For example, in the semiconductor device 2a of the embodiment, after a read operation command set CSr is input from the memory controller 1, an internal operation for reading data may be performed, and then data may be output to the memory controller 1 based on a further input of a data-out command set CSd from the memory controller 1. In such a case, the semiconductor device 2a may turn off the transistors 65a and 65b when a wait time tS has elapsed without data transfer to the memory controller 1 starting from the time the data-out command set CSd is input, i.e., from the time a signal consisting of "05h," multiple "ADD"s, and "E0h"s is input. Applying the configuration of the above embodiment to such a semiconductor memory device 2a makes it possible to change the wait time tS.

[0177] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments and their modifications are within the scope and spirit of the invention, and are included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0178] XDL: latch circuit (data holding unit), 1: memory controller, 2a to 2d: semiconductor memory device, 3: memory system, 4: host, 21: input / output circuit (data transfer circuit), 23: monitor circuit (monitoring unit), 31: input / output pad group (pad unit), 41: sequencer (control unit), 41a: feature register, 65a, 65b: transistor (cut-off unit, switching element), 110: memory cell array, 510: first holding unit (data transfer circuit, memory device).

Claims

1. a memory cell array; a data holding unit that temporarily holds data read from the memory cell array; a pad unit for transmitting and receiving signals to and from a memory controller; a data transfer circuit provided between the data holding unit and the pad unit, the data transfer circuit transferring data held in the data holding unit to the pad unit; a control unit that controls the data transfer circuit, the data transfer circuit is provided with a cutoff unit capable of cutting off the supply of current to the data transfer circuit; the control unit, when a predetermined time has elapsed since the data was transferred from the memory cell array to the data transfer circuit via the data holding unit without the transfer of data to the memory controller being started, causes the cutoff unit to cut off the supply of current to the data transfer circuit; The predetermined time period is variable. Semiconductor memory device.

2. The cutoff unit is a switching element provided on a wiring that applies a ground voltage to the data transfer circuit.

2. The semiconductor memory device according to claim 1.

3. further comprising a register in which a set value of the predetermined time is stored, The control unit reads the set value of the predetermined time from the register.

2. The semiconductor memory device according to claim 1.

4. The set value of the predetermined time stored in the register is updated based on a signal sent from the memory controller.

4. The semiconductor memory device according to claim 3.

5. The predetermined time period can be set by the user.

2. The semiconductor memory device according to claim 1.

6. The predetermined time can be selected from a plurality of preset values.

2. The semiconductor memory device according to claim 1.

7. The control unit changes the predetermined time based on a predetermined command transmitted from the memory controller.

2. The semiconductor memory device according to claim 1.

8. The data transfer circuit includes an input / output circuit.

2. The semiconductor memory device according to claim 1.

9. The data transfer circuit includes a storage device that operates first-in, first-out.

2. The semiconductor memory device according to claim 1.

10. a monitoring unit that monitors the operation state of the data transfer circuit; The control unit calculates a recommended value for the predetermined time based on an operating state of the data transfer circuit.

2. The semiconductor memory device according to claim 1.

11. The control unit outputs a recommended value of the predetermined time to the memory controller.

9. The semiconductor memory device according to claim 8.

12. a semiconductor memory device according to claim 11; a memory controller that controls the semiconductor memory device based on a request from a host; The memory controller outputs a recommended value of the predetermined time to the host. Memory system.

13. a memory cell array; a data holding unit that temporarily holds data read from the memory cell array; a pad unit for transmitting and receiving signals to and from a memory controller; a data transfer circuit provided between the data holding unit and the pad unit, the data transfer circuit transferring data held in the data holding unit to the pad unit; a control unit that controls the data transfer circuit, the data transfer circuit is provided with a cutoff unit capable of cutting off the supply of current to the data transfer circuit; the control unit, after data is transferred from the memory cell array to the data transfer circuit via the data holding unit, when a predetermined time has elapsed since a data out command set was transmitted from the memory controller without data transfer to the memory controller being started, cuts off the supply of current to the data transfer circuit by the cutoff unit; The predetermined time period is variable. Semiconductor memory device.

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