Semiconductor device and method for manufacturing semiconductor device

Abstract

To provide a semiconductor device which has a small arrangement pitch of an electrode, and can obtain metal connection having high reliability, even in the case of an arrangement pitch of 5 μm or less.SOLUTION: In a semiconductor device 1, a semiconductor device 10 has a first main surface 14 where first electrodes 16 are arranged at an arrangement pitch 201 of 5 μm or less, a connection part 50 has columnar metal electrodes 54 which connect a first electrode 16 of the semiconductor device 10 and a second electrode 36 of a wiring device 30, and are arranged at a pitch of 5 μm or less corresponding to the arrangement pitch 201, and a resin part 52 arranged around the columnar metal electrodes 54, wherein an area equivalent diameter of a cross section perpendicular to an axial direction 101 of the columnar metal electrodes 54 is smaller than the arrangement pitch 201, and the length in the axial direction 101 of the columnar metal electrode 54 from a part contacting the first main surface 14 to a part contacting the second main surface 34 is a length equal to or more a double the arrangement pitch 201.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Conventional microbump connection technology involves using a heat-resistant photosensitive resin to fill the space around the metal electrodes, opening vias in the resin using photolithography, and then forming metal electrodes in the vias. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-204818 Summary of the Invention [Problem to be solved by the invention]

[0004] With the heat-resistant photosensitive resin used in conventional technology, the aspect ratio of the via cannot be increased beyond about 1, so when the via diameter becomes smaller, the via height, and therefore the height of the metal electrode, also becomes smaller. When the via diameter becomes smaller and the height of the metal electrode becomes similar to the via diameter, the amount of solder material used to connect the metal electrodes becomes smaller, making it difficult to obtain a highly reliable metal connection.

[0005] Therefore, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can obtain highly reliable metal connections even when the electrode arrangement pitch is small, ie, 5 μm or less. [Means for solving the problem]

[0006] The semiconductor device of the present invention is a flip-chip bonded semiconductor device comprising a semiconductor device, a wiring device, and a connection portion connecting the semiconductor device and the wiring device, wherein the semiconductor device has a first main surface on which first electrodes are arranged at an arrangement pitch of 5 μm or less, and the wiring device has a second main surface on which second electrodes are arranged at a pitch of 5 μm or less corresponding to the arrangement pitch, and the connection portion comprises pillar-shaped metal electrodes connecting the first electrodes of the semiconductor device and the second electrodes of the wiring device, the pillar-shaped metal electrodes being arranged at a pitch of 5 μm or less corresponding to the arrangement pitch, and a resin portion arranged around the pillar-shaped metal electrodes, wherein the area-equivalent diameter of a cross section perpendicular to the axial direction of the pillar-shaped metal electrodes is smaller than the arrangement pitch, and the axial length of the pillar-shaped metal electrodes from the portion contacting the first main surface to the portion contacting the second main surface is at least twice the arrangement pitch.

[0007] A method for manufacturing a semiconductor device of the present invention includes the steps of: preparing a semiconductor device having a main surface on which electrodes are arranged at an arrangement pitch of 5 μm or less; forming an organic insulating film on one main surface of the semiconductor device; curing the organic insulating film; forming holes in the organic insulating film on the electrodes by dry etching at a pitch corresponding to the arrangement pitch of the electrodes; filling the holes with metal to form columnar metal electrodes; and aligning the semiconductor device with another wiring device and connecting them by flip-chip bonding. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a semiconductor device and a method for manufacturing the same that can obtain highly reliable metal connections even when the electrode arrangement pitch is small, ie, 5 μm or less. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view of a semiconductor device having another configuration. [Figure 3A] FIG. 3A is a cross-sectional view of a semiconductor device. [Figure 3B] FIG. 3B is a diagram showing a state in which a resin film has been formed on the semiconductor device. [Figure 3C] FIG. 3C is a diagram showing a state in which a resist film is formed on the resin film. [Figure 3D] FIG. 3D is a diagram showing the state after the resist film has been lithographically processed. [Figure 3E] FIG. 3E is a diagram showing the state after the resist film and the resin film have been dry-etched. [Figure 3F] FIG. 3F is a diagram showing the state after the resist film has been removed. [Figure 3G] FIG. 3G is a diagram showing a state in which a seed layer has been formed on the surface of the resin film, the first main surface, and the inner surface of the third recess. [Figure 3H] FIG. 3H is a diagram showing a state in which an electrode layer is formed in the third recess and the like. [Figure 3I] FIG. 3I is a diagram showing the state in which the surface of the resin film is flattened. [Figure 3J] FIG. 3J is a diagram showing a state in which the semiconductor device is bonded to the wiring device. DETAILED DESCRIPTION OF THE INVENTION

[0010] (Semiconductor Devices) An embodiment of the present invention will be described with reference to the drawings. Fig. 1 is a cross-sectional view of a semiconductor device 1 according to an embodiment of the present invention. As shown in Fig. 1, the semiconductor device 1 includes a semiconductor device 10, a connection portion 50, and a wiring device 30. The semiconductor device 10 is electrically connected to the wiring device 30 via the connection portion 50.

[0011] (Semiconductor devices and interconnect devices) A semiconductor device 10 is a semiconductor component in which semiconductor elements are formed on, for example, a silicon wafer. An example of a semiconductor device 10 is a semiconductor chip. The semiconductor device 10 includes a first substrate 12 and a first electrode 16. The first substrate 12 is a portion of the semiconductor device 10, such as a silicon wafer, that serves as a substrate on which semiconductor elements and the like are formed. An electrode formed on one surface of the semiconductor device 10 is called a first electrode 16. The surface of the semiconductor device 10 on which the first electrode 16 is formed is called a first main surface 14.

[0012] (wiring devices) The wiring device 30 is a component in which a wiring layer is formed on, for example, a silicon wafer. An example of the wiring device 30 is an interposer. A semiconductor element may be formed on the wiring device 30. Examples of the wiring device 30 include a semiconductor device including an active element such as a semiconductor element, a substrate containing only wiring and no active element, such as a silicon interposer, and an RDL interposer in which a wiring layer is formed on a carrier made of glass or the like and then peeled off from the carrier, leaving only the wiring layer. The wiring device 30 includes a second substrate 32 and a second electrode 36. The second substrate 32 is a portion of the wiring device 30, such as a silicon wafer, that serves as a substrate on which a wiring layer and the like are formed. The electrode formed on one surface of the wiring device 30 is called the second electrode 36. The surface of the wiring device 30 on which the second electrode 36 is formed is called the second main surface 34.

[0013] (Connection) The connection portion 50 is a portion that connects the semiconductor device 10 and the wiring device 30. The connection portion 50 includes a columnar metal electrode 54 and a resin portion 52. The columnar metal electrode 54 is a portion that electrically connects the first electrode 16 and the second electrode 36. The resin portion 52 is a portion made of resin that is arranged around the columnar metal electrode 54 in the connection portion 50. The resin portion 52 is made of insulating resin. The material of the resin film 80 can be, for example, polyimide, polyamideimide, benzocyclobutene (BCB), polybenzoxazole (PBO), etc.

[0014] The columnar metal electrode 54 can be formed of copper, solder, or the like. In the example shown in FIG. 1 , the columnar metal electrode 54 has a first electrode portion 61, a second electrode portion 62, and a third electrode portion 63. These are arranged in the following order from the first main surface 14: the first electrode portion 61, the third electrode portion 63, and the second electrode portion 62. The first electrode portion 61 is in contact with the first main surface 14. The second electrode portion 62 is in contact with the second main surface 34. The first electrode portion 61, the second electrode portion 62, and the third electrode portion 63 can be formed of different materials. For example, the first electrode portion 61 and the second electrode portion 62 can be formed of copper, and the third electrode portion 63 can be formed of solder. As will be explained later, when the semiconductor device 10 and the wiring device 30 are joined by hybrid bonding, the provision of the third electrode portion 63 formed of solder makes it possible to easily connect the first electrode 16 and the second electrode 36. Since interdiffusion of copper and solder components can occur when the solder melts, a barrier layer such as nickel that suppresses this may be formed between the first electrode portion 61 and the third electrode portion 63 and between the second electrode portion 62 and the third electrode portion 63.

[0015] (axial and principal plane directions) The direction indicated by the arrow 101 in FIG. 1 is called the axial direction 101 of the columnar metal electrode 54. The axial direction 101 is also the connection direction between the semiconductor device 10 and the wiring device 30. The direction indicated by the arrow 102 in FIG. 1 is a direction perpendicular to the axial direction 101. The direction of the arrow 102 is called the principal surface direction 102. The principal surface direction 102 is parallel to the first principal surface 14 and the second principal surface 34.

[0016] (electrode pitch) The length 201 shown in Fig. 1 is the pitch of the first electrodes 16 in the principal surface direction 102. The length 202 shown in Fig. 1 is the pitch of the second electrodes 36 in the principal surface direction 102. Both the length 201 and the length 202 are 5 µm or less. In other words, the pitch of the first electrodes 16 and the second electrodes 36 in the principal surface direction 102 is 5 µm or less.

[0017] 1 is the pitch of the columnar metal electrodes 54 in the principal surface direction 102. The length 203 is 5 μm or less. In other words, the pitch of the columnar metal electrodes 54 in the principal surface direction 102 is 5 μm or less.

[0018] The pitches of the first electrodes 16, the second electrodes 36, and the columnar metal electrodes 54 in the principal surface direction 102 correspond to one another. Corresponding means being substantially the same.

[0019] (Pitch) The length 201 shown in FIG.

[0020] (Equivalent diameter of the columnar metal electrode) The area-equivalent diameter is the diameter of the cross section perpendicular to the axial direction 101 of the columnar metal electrode 54. The area-equivalent diameter (diameter of a circle with an area equivalent to that of the cross section of the columnar metal electrode 54) is the diameter of a perfect circle with an area equal to that of the cross section of the columnar metal electrode 54. The area-equivalent diameter is smaller than the arrangement pitch 201.

[0021] The equivalent area diameter of the pillar-shaped metal electrodes 54 is preferably less than 5 μm. The equivalent area diameter is more preferably 3 μm or less. The equivalent area diameter may be 2.5 μm or less.

[0022] The area-equivalent diameter is preferably equal to or less than two-thirds of the arrangement pitch 201. The area-equivalent diameter may be equal to or less than half of the arrangement pitch 201.

[0023] The cross-sectional area of ​​the columnar metal electrode 54 in a cross section perpendicular to the axial direction 101 is preferably 30 μm 2 or less. The cross-sectional area of ​​the columnar metal electrode 54 in a cross section perpendicular to the axial direction 101 is more preferably 20 μm 2 or less. The cross-sectional area of ​​the columnar metal electrode 54 in a cross section perpendicular to the axial direction 101 may be 5 μm 2 or less.

[0024] As described above, in the semiconductor device 1 of this embodiment, the area-equivalent diameter of the columnar metal electrodes 54 is small. Therefore, even if the arrangement pitch 201 is small, the first electrode 16 and the second electrode 36 can be connected without causing a short circuit between adjacent columnar metal electrodes 54.

[0025] There are no particular limitations on the cross-sectional shape of the pillar-shaped metal electrode 54 in a cross section perpendicular to the axial direction 101. The cross-sectional shape may be, for example, circular or rectangular.

[0026] (axial length of columnar metal electrode) The length 211 in FIG. 1 indicates the length of the columnar metal electrode 54 in the axial direction 101. The length 211 is referred to as the axial length 211. The axial length 211 is approximately equal to the distance in the axial direction 101 between the first main surface 14 and the second main surface 34. The axial length 211 is at least twice the arrangement pitch 201.

[0027] The axial length 211 of the pillar-shaped metal electrode 54 is preferably 10 μm or more. The axial length 211 is more preferably 15 μm or more. The axial length 211 of the pillar-shaped metal electrode 54 may be 8 μm or more.

[0028] The axial length 211 is preferably three times or more the arrangement pitch 201 .

[0029] Moreover, the axial length 211 is preferably at least twice the area-equivalent diameter of the pillar-shaped metal electrode 54. The axial length 211 is more preferably at least three times the area-equivalent diameter.

[0030] As described above, in the semiconductor device 1 of this embodiment, when viewed in a cross section parallel to the axial direction 101 and the principal surface direction 102, the length of the columnar metal electrodes 54 in the axial direction 101 is considerably longer than the length of the columnar metal electrodes 54 in the principal surface direction 102, as described above. In other words, when viewed in a cross section parallel to the axial direction 101 and the principal surface direction 102, the columnar metal electrodes 54 have an elongated shape in the axial direction 101. Therefore, even when the arrangement pitch is small, the volume of the columnar metal electrodes 54 can be secured without causing short circuits between adjacent columnar metal electrodes 54. Therefore, even when the arrangement pitch is small, highly reliable metal connections can be obtained.

[0031] (Minimum length of resin part) The length 205 in FIG. 1 indicates the length in the principal surface direction 102 of the resin portion 52 arranged between adjacent columnar metal electrodes 54. Here, when the length 205 of the resin portion 52 in the principal surface direction 102 varies depending on the position in the axial direction 101, the shortest length 205 is referred to as the resin portion shortest length 205. The area-equivalent diameter of the columnar metal electrode 54 is preferably smaller than the resin portion shortest length 205. This enables high-density connection while ensuring insulation between adjacent columnar metal electrodes 54.

[0032] (Linearity of columnar metal electrodes) The linearity of the columnar metal electrode 54 will now be described. The linearity of the columnar metal electrode 54 refers to how closely a line representing the side surface 56 of the columnar metal electrode 54 resembles a straight line in a cross section parallel to the axial direction 101 and the principal surface direction 102. The linearity of the columnar metal electrode 54 can also be referred to as the flatness of the side surface 56. The linearity of the columnar metal electrode 54 will now be described from the perspective of the outer diameter 207 of the columnar metal electrode 54.

[0033] (Outer diameter) The length 207 shown in FIG. 1 is the length of the columnar metal electrode 54 in the principal surface direction 102 in a cross section parallel to the axial direction 101 and the principal surface direction 102. When the columnar metal electrode 54 has a rectangular cross section, the length 207 corresponds to the dimension of a side. When the columnar metal electrode 54 has a circular cross section, the length 207 corresponds to the outer diameter dimension. Hereinafter, the length 207 will be referred to as the outer diameter dimension 207.

[0034] In the semiconductor device 1 of this embodiment, the outer diameter 207 of the columnar metal electrode 54 at the portion where it contacts the first main surface 14 is substantially the same as the outer diameter 207 of the portion where it contacts the second main surface 34. The outer diameter 207 of the columnar metal electrode 54 at the portion where it contacts the first main surface 14 is referred to as a first outer diameter 2071. The outer diameter 207 of the columnar metal electrode 54 at the portion where it contacts the second main surface 34 is referred to as a second outer diameter 2072. The first outer diameter 2071 and the second outer diameter 2072 are substantially the same. Substantially the same means that the second outer diameter dimension 2072 is 95% or more and 105% or less of the outer diameter dimension 207 of the first outer diameter dimension 2071, and the first outer diameter dimension 2071 is 95% or more and 105% or less of the outer diameter dimension 207 of the second outer diameter dimension 2072.

[0035] It is preferable that the outer diameter 207 is substantially the same from the portion where the columnar metal electrode 54 contacts the first main surface 14 to the portion where the columnar metal electrode 54 contacts the second main surface 34. Here, the outer diameter 207 at the center position between the first main surface 14 and the second main surface 34 is defined as a reference outer diameter 2073. "The outer diameter 207 being substantially the same from the portion where the columnar metal electrode 54 contacts the first main surface 14 to the portion where the columnar metal electrode 54 contacts the second main surface 34" means that the outer diameter 207 at any position between the portion where the columnar metal electrode 54 contacts the first main surface 14 and the portion where the columnar metal electrode 54 contacts the second main surface 34 is 95% to 105% of the reference outer diameter 2073.

[0036] As described above, in the semiconductor device 1 of this embodiment, the outer diameter 207 of the columnar metal electrode 54 does not vary significantly from the portion where the columnar metal electrode 54 contacts the first main surface 14 to the portion where the columnar metal electrode 54 contacts the second main surface 34. This indicates that the columnar metal electrodes 54 have high linearity. In the semiconductor device 1 of this embodiment, the high linearity of the columnar metal electrodes 54 allows the spacing between adjacent columnar metal electrodes 54 in the main surface direction 102 to be narrowed. As a result, high-density wiring can be achieved. Furthermore, even when the arrangement pitch is small, the volume of the columnar metal electrodes 54 can be secured without causing short circuits between adjacent columnar metal electrodes 54. Therefore, highly reliable metal connections can be obtained even when the arrangement pitch is small. (arithmetic mean roughness of the side surface of the metal electrode pillar) The arithmetic mean roughness of the side surface 56 of the columnar metal electrode 54 will be described. The side surface 56 of the columnar metal electrode 54 can also be considered the boundary surface between the columnar metal electrode 54 and the resin portion 52. In a cross section along the axial direction 101 of the columnar metal electrode 54, the arithmetic mean roughness Ra of the side surface 56 of the columnar metal electrode 54 is 0.03 μm or less. When the arithmetic mean roughness Ra of the side surface 56 is 0.03 μm or less, voids are unlikely to form between the resin portion 52 and the side surface 56 of the columnar metal electrode 54, and therefore the durability of the semiconductor device 1 can be improved.

[0037] (Rectangularity of the vertical cross section of the columnar metal electrode) The rectangularity of the columnar metal electrode 54 in a cross section (longitudinal cross section) taken along the axial direction 101 of the columnar metal electrode 54 shown in FIG. 1 will be described. Here, rectangularity refers to (area inside the outline / area of ​​the circumscribed rectangle of the outline). To explain the rectangularity of the columnar metal electrode 54 of the present disclosure in more detail, the rectangularity is calculated by dividing the area formed by the outline of the columnar metal electrode 54 in the longitudinal cross section of the columnar metal electrode 54 by the area of ​​a minimum rectangle circumscribing the outline of the columnar metal electrode 54 so as to minimize the area of ​​the minimum rectangle. For example, the rectangularity is calculated based on a cross section (longitudinal cross section) taken along the axial direction 101 of the columnar metal electrode 54, the cross section passing through the center (center of gravity) of the cross section (transverse cross section) perpendicular to the axial direction 101 of the columnar metal electrode 54. The rectangularity of the columnar metal electrode 54 of this embodiment in the longitudinal cross section of the columnar metal electrode 54 is 0.95 or more. By setting the rectangularity of the vertical cross section of the columnar metal electrode 54 to 0.95 or more, it is possible to ensure the volume of the columnar metal electrode 54 without causing short circuits between adjacent columnar metal electrodes 54, even when the outer diameter 207 is small and the arrangement pitch is small. Therefore, a highly reliable metal connection can be obtained even when the arrangement pitch is small. However, it is difficult to increase the rectangularity of the vertical cross section of the columnar metal electrode arranged in the recess formed by photolithography, and the rectangularity is less than 0.9.

[0038] (Another configuration of the semiconductor device) Another configuration of the semiconductor device 1 will be described with reference to Fig. 2. The semiconductor device 1 shown in Fig. 1 had a three-layer structure of semiconductor devices 10, connection sections 50, and wiring devices 30. In contrast, the semiconductor device 11 shown in Fig. 2 has a five-layer structure including two layers each of wiring devices 30 and connection sections 50. The following description will focus on the differences between the semiconductor device 11 and the semiconductor device 1 shown in Fig. 1.

[0039] The semiconductor device 11 shown in FIG. 2 has a structure in which the semiconductor device 10, a first connection portion 501, a first wiring device 301, a second connection portion 502, and a second wiring device 302 are stacked in this order from the semiconductor device 10 in the axial direction 101. The first connection portion 501 and the second connection portion 502 have a configuration similar to that of the connection portion 50 shown in FIG. 1. In contrast, the first wiring device 301 and the second wiring device 302 have a configuration different from that of the wiring device 30 shown in FIG. 1. Unlike the wiring device 30, the first wiring device 301 and the second wiring device 302 have through electrodes formed therein. The through electrode formed in the first wiring device 301 is referred to as a first through electrode 71. The through electrode formed in the second wiring device 302 is referred to as a second through electrode 72. The formation of the through electrodes enables the first wiring device 301 and the second wiring device 302 of the semiconductor device 11 to function as a three-dimensional stacked device or an interposer.

[0040] The layer configuration will be described starting from the semiconductor device 10. The first main surface 14 of the semiconductor device 10 is in contact with the third main surface 511 of the first connection portion 501. At the interface between the first main surface 14 and the third main surface 511, the first electrode 16 of the semiconductor device 10 is electrically connected to the columnar metal electrode 54 of the first connection portion 501.

[0041] The fourth main surface 512 of the first connection portion 501 is in contact with the fifth main surface 311 of the first wiring device 301. At the interface between the fourth main surface 512 and the fifth main surface 311, the columnar metal electrode 54 of the first connection portion 501 is electrically connected to the first through electrode 71 of the first wiring device 301.

[0042] The sixth main surface 312 of the first wiring device 301 is in contact with the seventh main surface 521 of the second connection portion 502. At the interface between the sixth main surface 312 and the seventh main surface 521, the first through electrode 71 of the first wiring device 301 is electrically connected to the columnar metal electrode 54 of the second connection portion 502.

[0043] An eighth main surface 522 of the second connection portion 502 is in contact with a ninth main surface 321 of the second wiring device 302. At the interface between the eighth main surface 522 and the ninth main surface 321, the columnar metal electrode 54 of the second connection portion 502 is electrically connected to the second through electrode 72 of the second wiring device 302.

[0044] Connection terminals 60 such as solder balls are provided on the tenth main surface 322 of the second wiring device 302 at positions that are in electrical contact with the second through electrodes 72. The semiconductor device 1 is connected to, for example, an interposer or a printed wiring board via the connection terminals 60.

[0045] 2, by forming a through electrode in the wiring device, it is possible to include multiple layers of wiring devices in the semiconductor device 11. This allows for more complex wiring layout.

[0046] (Manufacturing method) The manufacturing method of the semiconductor device 1 will be described with reference to Figures 3A to 3J. Figures 3A to 3J are diagrams for explaining the manufacturing method of the semiconductor device 1, and are diagrams showing a cross section of the first substrate 12, etc. The manufacturing process progresses in order from Figure 3A to Figure 3J. Figures 3A to 3J are only diagrams for explaining the outline of the manufacturing process. Therefore, in Figures 3A to 3J, electrodes, wiring, and the like that do not have a significant impact on the manufacturing process are omitted from the illustration. Furthermore, descriptions of these elements will be omitted.

[0047] (Semiconductor device preparation process) 3A is a diagram showing a cross section of a semiconductor device 10. In the semiconductor device preparation process, semiconductor elements, wiring, electrodes, etc. are formed on a first substrate 12 of the semiconductor device 10. The semiconductor elements, wiring, electrodes, etc. are not shown in FIG. 3A. The first substrate 12 can be, for example, a silicon substrate.

[0048] (Resin film formation process) 3B is a diagram showing a state in which a resin film 80 has been formed on the semiconductor device 10. In the resin film formation step, the resin film 80 is formed on the first main surface 14 of the first substrate 12. The resin film 80 is formed by, for example, applying an insulating resin to the first main surface 14. The resin film 80 can be made of, for example, polyimide, polyamideimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or the like.

[0049] An example of a method for forming the resin film 80 will be specifically described. When a liquid resin is used as the material for the resin film 80, the liquid resin is applied to the first substrate 12, such as a semiconductor wafer, semiconductor chip, or silicon substrate, by a method such as spin coating, slit coating, or spray coating, and then dried and solidified by heating or light irradiation. When a film-like resin is used, the film-like resin is attached to the first substrate 12 and solidified by heating or light irradiation. When a solid resin is used, the solid resin is heated and melted to form a film on the first substrate 12.

[0050] (Resist film formation process) 3C is a diagram showing a state in which a resist film 84 has been formed on the resin film 80. The surface of the resin film 80 is called a resin film surface 82. In the resist film forming step, a resist film 84 is formed on the resin film surface 82. The resist film 84 can be formed by a coating method, a printing method, or the like. The material of the resist film 84 is not particularly limited as long as it is a photosensitive resist material.

[0051] (lithography processing) FIG. 3D is a diagram showing the state after the resist film 84 has been lithographically processed. In the lithographic processing step, the resist film 84 is processed by lithography to have predetermined intervals, predetermined sizes, predetermined shapes, etc. The resist film 84 is removed in a predetermined pattern, and recesses, i.e., holes, are formed in the resist film 84. The recesses are also called vias. The recesses formed in the resist film 84 shown in FIG. 3D are called first recesses 90. Inside the first recesses 90, the resin film surface 82 of the resin film 80 is exposed.

[0052] (Dry etching process) FIG. 3E is a diagram showing the state after the resist film 84 and resin film 80 have been dry-etched. In the dry etching process, the resin film 80 is dry-etched through the first recess 90 formed in the lithography process. This dry etching forms a recess penetrating the resist film 84 and the resin film 80. The recess penetrating the resist film 84 and the resin film 80 shown in FIG. 3E is called a second recess 92. The first main surface 14 of the semiconductor device 10 is exposed inside the second recess 92. Dry etching is performed in a vacuum chamber by introducing a gas mixed with oxygen to generate plasma. The plasma generator can be a parallel plate type, an ICP type, a microwave type, or a combination thereof.

[0053] In the dry etching process, in addition to the resin film 80, a portion of the resist film 84 is also etched. The length in the axial direction 101 of the resist film 84 before dry etching shown in FIG. 3D is defined as length 111. The length in the axial direction 101 of the resist film 84 after dry etching shown in FIG. 3E is defined as length 112. As shown in FIGS. 3D and 3E, length 112 is shorter than length 111. In the example shown in FIGS. 3D and 3E, length 112 is approximately half of length 111.

[0054] (Cross-sectional shape of the third recess) The second recess 92 is formed by dry etching. Therefore, the cross-sectional shape of the second recess 92 in a plane parallel to the axial direction 101 and the principal surface direction 102 is closer to a rectangle than the first recess 90 shown in FIG. 3D . Although a recess processed by photolithography may be depicted as a rectangle in a cross section along the axial direction of the recess, the actual rectangularity is low, less than 0.9 or less. Specifically, as shown in FIG. 3D , for example, the edges of both the via top and the via bottom of a recess processed by photolithography are rounded, resulting in a low rectangularity in a cross section along the axial direction of the recess. On the other hand, dry etching can form a recess with a very high rectangularity in a cross section along the axial direction of the recess. Specifically, as shown in FIG. 3F , the recess processed by dry etching has very sharp via tops and bottoms, resulting in a very high rectangularity in a cross section along the axial direction of the recess. As a result, the rectangularity of the cross section of the pillar-shaped metal electrode 54 formed in the process described below along the axial direction 101 of the pillar-shaped metal electrode 54 can be made 0.95 or more.

[0055] (resist removal process) FIG. 3F is a diagram showing the state after the resist film 84 has been removed. In the resist removal process, the resist film 84 remaining after dry etching is removed. By removing the resist film 84, only the patterned resin film 80 remains on the semiconductor device 10. The recess formed in the resin film 80 is called a third recess 94. The third recess 94 is a part of the second recess 92 shown in FIG. 3E on the first main surface 14 side. The resist can be removed using a chemical solution, oxygen plasma, or the like.

[0056] The flow of forming the third recess 94 described above can be summarized as follows. A resin film 80 is provided as the film in which the third recess 94, i.e., the via, is formed. A via is formed through the resin film 80 by dry etching. Specifically, a photosensitive resist film 84 is formed on the resin film 80, and only the photosensitive resist film 84 is removed from the resin film 80 at the location where the via is to be opened by photolithography. The via is then opened using a plasma etching device. Etching gases that can be used include O2, Ar, N2, SF6, NF3, and CF4.

[0057] The method for forming the third recess is not limited to the above-described method. Another method involves forming a metal film, such as copper, on a resin film by sputtering or other methods, forming a photosensitive resist film on top of that, and then using photolithography to remove only the photosensitive resist from the area of ​​the resin film where vias are to be drilled. The metal film from the area where the photosensitive resist was removed is then removed by wet etching using an acid or alkali solution or the aforementioned dry etching. The resin film is then dry-etched, and the photosensitive resist and metal film on the surface of the resin film are subsequently removed. This allows the formation of a via similar to the third recess. These can be removed by chemical dissolution or physical grinding or polishing.

[0058] (Cross-sectional shape of the third recess) The third recess 94 is a part of the second recess 92 formed by dry etching. Therefore, the cross-sectional shape of the third recess 94 in a plane parallel to the axial direction 101 and the principal surface direction 102 is closer to a rectangle than the first recess 90 shown in FIG. 3D .

[0059] (Aspect ratio of the third recess) In FIG. 3F, the length of the third recess 94 in the axial direction 101 is indicated by length 121. The length of the third recess 94 in the principal surface direction 102 is indicated by length 122. The aspect ratio of the third recess 94, i.e., length 121 / length 122, can be greater than 1. More preferably, length 121 / length 122 is 4 or greater. The third recess 94 is formed by dry etching. Therefore, the length 121 / length 122, i.e., the aspect ratio of the third recess 94 in a cross section parallel to the axial direction 101 and the principal surface direction 102, can be increased. Furthermore, the rectangularity of the cross section parallel to the axial direction 101 and the principal surface direction 102 of the third recess 94 can be increased.

[0060] 3F indicates the pitch 251 of the third recesses 94 in the principal surface direction 102. In the semiconductor device 1 of this embodiment, the third recesses 94 have a large aspect ratio and a high degree of rectangularity as described above, so the pitch 251 can be made small. Furthermore, even when the arrangement pitch is small, the volume of the plated electrode layer 132 that becomes the columnar metal electrodes 54 can be ensured.

[0061] (Seed sputtering process) 3G is a diagram showing a state in which a seed layer 130 has been formed on the resin film surface 82 and the inner surface of the third recess 94. The seed layer 130 is formed by seed sputtering.

[0062] In the seed sputtering step, a seed layer 130 is formed by sputtering on the resin film surface 82, the inner surface of the third recess 94, and the first main surface 14 exposed by the third recess 94. The formed seed layer 130 serves as an electrode in the next step, the electrolytic plating step. The conductive material used for the seed layer 130 is not particularly limited.

[0063] (Electrolytic plating process) FIG. 3H is a diagram showing a state in which an electrode layer 132 has been formed in the third recess 94 and the like. In the electrolytic plating process, electrolytic plating is performed using the seed layer 130 formed in the seed sputtering process as an electrode. This electrolytic plating forms a plating electrode layer 132 inside the third recess 94 and on the resin film surface 82. The material of the plating electrode layer 132 is not particularly limited. For example, the material of the plating electrode layer 132 may be copper or a solder material. It is preferable that the material of the plating electrode layer 132 contains at least a solder material. Note that the method of filling the third recess 94 with a conductive material is not limited to plating. For example, the third recess 94 can also be filled with a conductive material by printing a conductive paste or the like.

[0064] As described above, the columnar metal electrodes 54 shown in FIG. 1 and elsewhere are formed so as to fill the third recesses 94, i.e., the vias, formed in the resin film 80. The method for forming these columnar metal electrodes 54 is not particularly limited as long as it fills the vias. Examples include a method of forming them using a metal paste, a method of forming them using electroless plating, and a method of forming them using electrolytic plating. In this embodiment, electrolytic plating is used as an example. When electrolytic plating is used, a seed layer made of metal is formed on the surface of the resin film 80 where the vias are formed and inside the vias. Then, electrolytic plating is performed by passing current through this seed layer until the vias are filled. The method and material for forming the seed layer are not particularly limited, but examples include a method of forming a Ti layer and a copper layer in this order using a sputtering method.

[0065] (CMP planarization process) FIG. 3I is a diagram showing a planarized state of the resin film surface 82, which is the surface of the resin film 80. The surface of the resin film 80 is planarized in a CMP (Chemical Mechanical Polishing) planarization process. In the planarization process, not only CMP but also a fly cutter can be used. The metal layer formed by electrolytic plating, i.e., the plating electrode layer 132, is also formed on the surface of the resin film 80, so this is removed by CMP processing (CMP planarization process). During polishing, the polishing thickness and other factors are adjusted to achieve the shape of the columnar metal electrodes 54 described above. This polishing enables hybrid bonding of the component shown in FIG. 3I with another component having a similarly planarized resin film surface 82. Furthermore, when hybrid bonding two components, it is preferable that the resin films 80 of both components be made of the same material. In this planarization step, polishing is performed so that the axial length 261 of the plated electrode layer 132 that will become the columnar metal electrodes 54, from the portion that contacts the first main surface 14 as one main surface of the semiconductor device to the resin film surface 82 as the polishing end surface, is equal to or greater than the arrangement pitch 201. Alternatively, polishing is performed so that the length 261 is equal to or greater than the diameter equivalent to the cross section area of ​​the plated electrode layer 132 that will become the columnar metal electrodes 54.

[0066] (Joining process) Fig. 3J is a diagram showing a state in which the semiconductor device 10 is bonded to the wiring device 30. In the bonding process, the semiconductor device 10 is aligned with another component having a resin film 80 and a plating electrode layer 132 similar to those of the semiconductor device 10 shown in Fig. 3I, and then flip-chip bonded. Fig. 3J shows a state in which the semiconductor device 10 and the wiring device 30 are bonded.

[0067] The resin film 80 of the semiconductor device 10 and the resin film 80 of the wiring device 30 are bonded to each other at their resin film surfaces 82. Furthermore, the plated electrode layer 132 of the semiconductor device 10 and the plated electrode layer 132 of the wiring device 30 are bonded to each other.

[0068] The resin film 80 of the semiconductor device 10 is bonded to the resin film 80 of the wiring device 30, and the plated electrode layer 132 of the semiconductor device 10 is bonded to the plated electrode layer 132 of the wiring device 30, thereby forming the connection portion 50. In detail, the resin film 80 of the semiconductor device 10 is bonded to the resin film 80 of the wiring device 30 to form the resin portion 52 of the connection portion 50. The resin film 80 of the semiconductor device 10 and the resin film 80 of the wiring device 30 are preferably bonded by hybrid bonding. The plated electrode layer 132 of the semiconductor device 10 is bonded to the plated electrode layer 132 of the wiring device 30 to form the columnar metal electrode 54.

[0069] The above-mentioned bonding will be explained in detail. In order to bond semiconductor wafers together, semiconductor chips together, or a semiconductor chip and a semiconductor wafer without voids, the surface of the resin film 80 needs to be highly smooth. If the arithmetic mean roughness Ra of the resin film surface measured with an atomic force microscope is 1 nm or less, it becomes easier to suppress the generation of voids during bonding. Furthermore, if Ra is 0.5 nm or less, it becomes easier to suppress the generation of voids even when bonding at low pressure.

[0070] When bonding semiconductor wafers together, a wafer bonding device can be used to align the opposing columnar metal electrodes with high precision.When bonding semiconductor chips together or a semiconductor chip and a semiconductor wafer, a flip-chip bonder can be used to align the opposing columns with high precision.

[0071] The above-described manufacturing method can be modified in various ways. For example, in the above description, one plated electrode layer 132 is formed in the third recess 94. Multiple electrode layers 132 can also be formed in the third recess 94. For example, two types of electrode layers can be formed in order from the first main surface 14 to the axial direction 101. In this case, one layer in contact with the main surface corresponds to the first electrode portion 61 or the second electrode portion 62 described above with reference to FIG. 1 . The other layer corresponds to the third electrode portion 63. This allows the formation of the columnar metal electrode 54 having the first electrode portion 61, the second electrode portion 62, and the third electrode portion 63 shown in FIG. 1 . In this case, the third electrode portion 63 is formed by joining one electrode layer to the other electrode layer.

[0072] When forming multiple electrode layers 132 in the third recess 94, one layer in contact with the main surface can be made of copper, and the remaining layer can be made of solder. This allows the formation of the columnar metal electrodes 54, i.e., the connection between the electrodes, to be performed using a solder connection process such as reflow.

[0073] Specifically, to form a solder layer on the tip of the columnar metal in the third recess 94, the copper layer located below the solder layer is formed first by electrolytic plating, so that the thickness of the copper layer in the via (third recess 94) is kept below the depth of the via layer, and then the solder layer is formed by electrolytic plating. The required copper layer thickness can be obtained by setting (copper layer thickness) = (via depth) - (desired solder layer thickness). A solder layer thickness of 3 μm or more is preferable because it achieves a sufficiently strong solder connection.

[0074] In addition, when performing the above-mentioned bonding, the objects to be bonded are aligned, then pressure is applied below the melting temperature of the solder, and then heating is performed above the melting temperature of the solder. The pair of columnar metal electrode layers to be bonded may have a solder layer formed on only one tip, or may have a solder layer formed on both tips. When heating below the melting point of the solder, it is preferable to perform the heating at a temperature above the glass transition temperature of the resin film, as this makes it less likely that voids will occur and also makes it easier for the resin around the columnar metal electrode layers to deform in the film thickness direction, i.e., in the column height direction, making it easier to bond the columnar metal electrode layers together.

[0075] One aspect of the semiconductor device 1 described above can be summarized as follows. Specifically, one important means for improving the performance of semiconductor systems is to use a semiconductor package structure that can increase the bandwidth of signal transmission between semiconductor chips, such as between logic semiconductor chips or between logic semiconductor chips and memory semiconductor chips. Increasing the bandwidth of signal transmission can be achieved by increasing the transfer rate per signal line or by increasing the number of signal lines. Shortening the length of the signal lines to reduce signal transmission loss is an effective way to increase the transfer rate per signal line. A three-dimensional stacking structure for semiconductor chips is effective for this purpose. Thinning the signal lines and reducing the pitch between them is an effective way to increase the number of signal lines. Microbump technology is an effective way to three-dimensionally stack semiconductor chips, thin the signal wiring, and reduce the pitch between signal lines. This technology electrically connects three-dimensionally stacked semiconductor chips using columnar electrodes made of metal with small cross-sectional areas and short lengths. The columnar metal electrodes can be made of copper, solder, or copper with solder formed on the tip. Because copper-to-copper bonding requires high temperatures of 350°C or higher, it is effective to use solder materials for the columnar metal electrodes. Using temperatures above 350°C can damage semiconductor performance, exceed the heat resistance limit of the materials used, or cause problems such as significant warping of the semiconductor package.

[0076] When using solder material for electrodes, the solder material must first be melted. This creates a problem: when the pitch between the bump electrodes is narrow, the solder material can short-circuit adjacent columnar metal electrodes. To prevent this, an effective method is to fill the spaces between the columnar metal electrodes with an insulating resin material before bonding the semiconductor chips. In this method, it is important that the insulating resin material be solidified before bonding to prevent it from flowing during bonding. Furthermore, because the bonding process must bond not only the columnar metal electrodes but also the insulating resin, the surface of the insulating resin must be smoothed beforehand.

[0077] By reducing the cross-sectional area of ​​the columnar metal electrodes and arranging them at a smaller pitch and at a higher density, it is possible to increase the number of signal lines connecting between semiconductor chips, thereby increasing the bandwidth.

[0078] The shoreline of the UCIe-1.0 chiplet interface standard is 388.8 μm, and with a 55 μm columnar metal electrode pitch, a technology already in practical use, 57 rows of electrodes are required from the edge of five chips to the interior. In contrast, if the array pitch is set to 5 μm or less, only five rows or less are required, shortening the wiring length for chip-to-chip connections by more than 4 mm. This allows for significant reductions in power consumption and a significant increase in the transfer rate per electrode. Keeping the electrode cross-sectional area to 30 μm or less reduces connection problems caused by misalignment during semiconductor chip bonding. Keeping the electrode cross-sectional area to 20 μm or less ensures sufficient spacing between the columnar metal electrodes, ensuring reliable insulation between them.

[0079] If the length of the columnar metal electrodes of the bonded semiconductor chip is 10 μm or more, the thickness of the insulating resin layer can be increased, thereby increasing the ability to absorb particles that become trapped when the semiconductor chip or semiconductor wafer is bonded.If the length of the columnar metal electrodes of the semiconductor chip is 8 μm or more, the brittle deterioration of the columnar metal electrodes due to interdiffusion between the solder material and copper is more likely to be suppressed.

[0080] When the resin contains at least one of polyimide, polybenzoxazole, and benzocyclobutene, degassing, deterioration, peeling, etc. due to heat applied during metal electrode bonding are less likely to occur. Furthermore, since semiconductor wafers or semiconductor chips can be bonded at low pressure, it is preferable that the glass transition point of the resin material be equal to or lower than the melting point of the solder material.

[0081] As the solder material, metal Sn, Sn--Ag, Sn--Bi, Sn--Cu, Sn--Ag--Cu alloys, etc. can be preferably used.

[0082] The method for manufacturing the semiconductor device of the present disclosure is not particularly limited, for example, a method for manufacturing a semiconductor device in which two or more semiconductor chips are stacked and the semiconductor chips are electrically connected to each other via columnar metal electrodes containing a solder material, the gaps between the semiconductor chips other than the columnar metal electrodes are filled with resin, the length of the columnar metal electrodes / the diameter of the columnar metal electrodes is 4 or more, the close-packed arrangement pitch of the columnar metal electrodes is 5 μm or less, the cross-sectional area is 30 μm or less, and the length is 10 μm or more.However, the method can be realized by forming a resin film on the surface of a semiconductor wafer or semiconductor chip, then processing the resin film by a dry etching method to open vias that reach the surface of the semiconductor wafer, subsequently filling the vias with a metal material to form metal electrodes, and then flattening the surface of the resin film, and then bonding the metal electrodes and resin film of similarly prepared semiconductor wafers or semiconductor chips so that the metal electrodes face each other.

[0083] (1) The semiconductor device is a flip-chip bonded semiconductor device, a semiconductor device, a wiring device, and a connection portion that connects the semiconductor device and the wiring device; the semiconductor device has a first main surface on which first electrodes are arranged at an arrangement pitch of 5 μm or less; the wiring device has a second main surface on which second electrodes are arranged at a pitch of 5 μm or less corresponding to the arrangement pitch; the connection portion includes: pillar-shaped metal electrodes that connect the first electrodes of the semiconductor device and the second electrodes of the wiring device, the pillar-shaped metal electrodes being arranged at a pitch of 5 μm or less that corresponds to the arrangement pitch; and a resin portion that is arranged around the pillar-shaped metal electrodes; the cross-sectional area equivalent diameter of the pillar-shaped metal electrodes perpendicular to the axial direction is smaller than the arrangement pitch; The length of the columnar metal electrodes in the axial direction from the portion in contact with the first principal surface to the portion in contact with the second principal surface is at least twice the arrangement pitch.

[0084] (2) A method for manufacturing a semiconductor device, preparing a semiconductor device having one main surface on which electrodes are arranged at an arrangement pitch of 5 μm or less; forming an organic insulating film on one main surface of the semiconductor device; curing the organic insulating film; forming holes at a pitch corresponding to an arrangement pitch of the electrodes by dry etching the organic insulating film on the electrodes; filling the holes with metal to form columnar metal electrodes; and aligning and connecting the semiconductor device to other wiring devices by flip-chip bonding.

[0085] (3) In the above-mentioned method for manufacturing a semiconductor device, a diameter equivalent to an area of ​​a cross section perpendicular to the axial direction of the holes formed in the step of forming the holes is smaller than the arrangement pitch; The diameter equivalent to the area of ​​a cross section perpendicular to the axial direction of the metal pillar electrodes formed in the step of forming the metal pillar electrodes is smaller than the arrangement pitch.

[0086] (4) In the above-mentioned method for manufacturing a semiconductor device, The method includes a step of planarizing the organic insulating film and the columnar metal electrodes formed on the one main surface between the step of filling with metal and the step of flip-chip connection.

[0087] (5) In the above-mentioned method for manufacturing a semiconductor device, In the planarization step, the metal electrodes are polished so that the length in the axial direction of the metal electrodes from the portion in contact with one main surface of the semiconductor device to the polishing end surface is equal to or greater than the arrangement pitch.

[0088] (6) In the above-mentioned method for manufacturing a semiconductor device, In the planarization step, the columnar metal electrode is polished so that the length in the axial direction of the columnar metal electrode from the portion in contact with one main surface of the semiconductor device to the polishing end surface is equal to or greater than the diameter equivalent to the cross-sectional area of ​​the columnar metal electrode. [Explanation of symbols]

[0089] 1. Semiconductor device 10 Semiconductor Devices 11 Semiconductor devices 12 First substrate 14 First principal surface 16 First electrode 30 Wiring Devices 32 Second board 34 Second main surface 36 Second electrode 50 Connection 52 Resin part 54 Columnar metal electrode 56 Side 60 Connection terminal 61 first electrode part 62 Second electrode part 63 Third electrode part 71 First through electrode 72 Second through electrode 80 Resin Film 82 Resin film surface 84 Resist film 90 First recess 92 Second recess 94 Third Recess 101 Axial 102 Main surface direction 130 seed layer 132 Electrode layer 201 placement pitch 205 Resin part minimum length 207 Outer diameter 211 Axial length 251 pitches 301 First Wiring Device 302 Second Wiring Device 311 Fifth Plane 312 Sixth Plane 321 Ninth Plane 322 10th main face 501 First connection part 502 Second connection 511 Third Principal Surface 512 Fourth Principal Surface 521 Seventh Plane 522 Eighth Plane 2071 First outer diameter 2072 Second outer diameter 2073 Standard outer diameter

Claims

1. A flip-chip bonded semiconductor device, a semiconductor device, a wiring device, and a connection portion that connects the semiconductor device and the wiring device; the semiconductor device has a first main surface on which first electrodes are arranged at an arrangement pitch of 5 μm or less; the wiring device has a second main surface on which second electrodes are arranged at a pitch of 5 μm or less corresponding to the arrangement pitch; the connection portion includes: pillar-shaped metal electrodes that connect the first electrodes of the semiconductor device and the second electrodes of the wiring device, the pillar-shaped metal electrodes being arranged at a pitch of 5 μm or less that corresponds to the arrangement pitch; and a resin portion that is arranged around the pillar-shaped metal electrodes; the cross-sectional area equivalent diameter of the pillar-shaped metal electrodes perpendicular to the axial direction is smaller than the arrangement pitch; a length in the axial direction of the columnar metal electrodes from a portion in contact with the first principal surface to a portion in contact with the second principal surface is at least twice the arrangement pitch;

2. preparing a semiconductor device having one main surface on which electrodes are arranged at an arrangement pitch of 5 μm or less; forming an organic insulating film on one main surface of the semiconductor device; curing the organic insulating film; forming holes at a pitch corresponding to an arrangement pitch of the electrodes by dry etching the organic insulating film on the electrodes; filling the holes with metal to form columnar metal electrodes; and a step of aligning the semiconductor device with another wiring device and connecting the semiconductor device with another wiring device by flip-chip bonding.

3. a diameter equivalent to an area of ​​a cross section perpendicular to the axial direction of the holes formed in the step of forming the holes is smaller than the arrangement pitch; 3. The method for manufacturing a semiconductor device according to claim 2, wherein a diameter equivalent to an area of ​​a cross section perpendicular to the axial direction of the metal pillar electrodes formed in the step of forming the metal pillar electrodes is smaller than the arrangement pitch.

4. 4. The method for manufacturing a semiconductor device according to claim 2, further comprising, between the step of filling with metal and the step of flip-chip connecting, a planarization step of planarizing the organic insulating film and the columnar metal electrodes formed on the one main surface.

5. 5. The method for manufacturing a semiconductor device according to claim 4, wherein in the planarization step, polishing is performed so that a length in the axial direction of the columnar metal electrodes from a portion in contact with one main surface of the semiconductor device to a polishing end surface is equal to or greater than the arrangement pitch.

6. 5. The method for manufacturing a semiconductor device according to claim 4, wherein in the planarization step, polishing is performed so that a length in an axial direction of the pillar-shaped metal electrode from a portion in contact with one main surface of the semiconductor device to a polishing end surface is equal to or greater than a diameter equivalent to an area of ​​a cross section of the pillar-shaped metal electrode.

Images