Semiconductor device and method for manufacturing semiconductor device

Abstract

To provide a semiconductor device capable of suitably achieving both on-current and threshold voltage.SOLUTION: A semiconductor device comprises an oxide semiconductor layer, a first electrode, a second electrode, and a conductive layer. The oxide semiconductor layer includes a first end and a second end, and is provided so as to extend in a first direction from the first end toward the second end. The first electrode comes in contact with the first end of the oxide semiconductor layer. The second electrode comes in contact with the second end of the oxide semiconductor layer. The conductive layer is provided so as to surround a predetermined portion of the oxide semiconductor layer via an insulating film between the first end and the second end of the oxide semiconductor layer.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present embodiment relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Some semiconductor devices use an oxide semiconductor layer for the channel. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2024-621 Summary of the Invention [Problem to be solved by the invention]

[0004] According to the present disclosure, a semiconductor device that can achieve a favorable balance between on-current and threshold voltage, and a method for manufacturing the semiconductor device, are provided. [Means for solving the problem]

[0005] The semiconductor device of the embodiment includes an oxide semiconductor layer, a first electrode, a second electrode, and a conductive layer. The oxide semiconductor layer has a first end and a second end and is provided to extend in a first direction from the first end toward the second end. The first electrode is in contact with the first end of the oxide semiconductor layer. The second electrode is in contact with the second end of the oxide semiconductor layer. The conductive layer is provided between the first end and the second end of the oxide semiconductor layer so as to surround a predetermined portion of the oxide semiconductor layer with an insulating film interposed therebetween.

[0006] In a method for manufacturing a semiconductor device according to an embodiment, a first conductive layer, a first insulating layer, a conductive layer, and a second insulating layer are stacked in a first direction, a hole is formed that penetrates the second insulating layer, the conductive layer, and the first insulating layer and reaches the first conductive layer, an oxide semiconductor is deposited inside the hole by an ALD method, and when the oxide semiconductor layer is formed inside the hole, a cavity is formed inside a predetermined portion of the oxide semiconductor layer that is surrounded by the conductive layer, and oxygen is supplied to the oxide semiconductor layer. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 2 is a circuit diagram showing the circuit configuration of a memory cell array according to the embodiment. [Figure 2] 1 is a cross-sectional view showing a cross-sectional structure of a semiconductor memory device according to an embodiment; [Figure 3] 1 is a cross-sectional view showing a cross-sectional structure of a semiconductor device according to an embodiment; [Figure 4] 5A to 5C are cross-sectional views showing a part of a manufacturing process of the semiconductor device according to the embodiment. [Figure 5] 5A to 5C are cross-sectional views showing a part of a manufacturing process of the semiconductor device according to the embodiment. [Figure 6] 5A to 5C are cross-sectional views showing a part of a manufacturing process of the semiconductor device according to the embodiment. [Figure 7] 5A to 5C are cross-sectional views showing a part of a manufacturing process of the semiconductor device according to the embodiment. [Figure 8] 5A to 5C are cross-sectional views showing a part of a manufacturing process of the semiconductor device according to the embodiment. [Figure 9] 5A to 5C are cross-sectional views showing a part of a manufacturing process of the semiconductor device according to the embodiment. [Figure 10] 5A to 5C are cross-sectional views showing a part of a manufacturing process of the semiconductor device according to the embodiment. [Figure 11] FIG. 10 is a cross-sectional view showing a cross-sectional structure of a semiconductor device of a comparative example. [Figure 12] FIG. 10 is a cross-sectional view showing a cross-sectional structure of a first modified example of the semiconductor device of the embodiment. [Figure 13] FIG. 10 is a cross-sectional view showing a cross-sectional structure of a second modified example of the semiconductor device of the embodiment. [Figure 14] FIG. 10 is a cross-sectional view showing a cross-sectional structure of a third modified example of the semiconductor device of the embodiment. [Figure 15]FIG. 10 is a cross-sectional view showing a cross-sectional structure of a fourth modified example of the semiconductor device of the embodiment. [Figure 16] FIG. 10 is a cross-sectional view showing a cross-sectional structure of a fifth modified example of the semiconductor device according to the embodiment. [Figure 17] FIG. 10 is a cross-sectional view showing a cross-sectional structure of a sixth modified example of the semiconductor device according to the embodiment. [Figure 18] FIG. 10 is a cross-sectional view showing a cross-sectional structure of a sixth modified example of the semiconductor device according to the embodiment. [Figure 19] FIG. 13 is a cross-sectional view showing a cross-sectional structure of a seventh modified example of the semiconductor device according to the embodiment. [Figure 20] FIG. 13 is a cross-sectional view showing a cross-sectional structure of a seventh modified example of the semiconductor device according to the embodiment. [Figure 21] FIG. 13 is a cross-sectional view showing a cross-sectional structure of an eighth modified example of the semiconductor device according to the embodiment. [Figure 22] FIG. 13 is a cross-sectional view showing a cross-sectional structure of an eighth modified example of the semiconductor device according to the embodiment. [Figure 23] FIG. 13 is a cross-sectional view showing a cross-sectional structure of an eighth modified example of the semiconductor device according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described with reference to the drawings. To facilitate understanding of the description, the same components in the drawings will be denoted by the same reference numerals as much as possible, and redundant description will be omitted.

[0009] 1. Embodiment A semiconductor device and a manufacturing method thereof according to an embodiment will be described. Each drawing may show an X-axis, a Y-axis, and a Z-axis. The X-axis, the Y-axis, and the Z-axis form a right-handed, three-dimensional Cartesian coordinate system. Hereinafter, the direction of the X-axis arrow may be referred to as the +X direction, and the direction opposite to the arrow may be referred to as the -X direction. The same applies to the other axes. The +Z direction and the -Z direction may also be referred to as "upward" and "downward," respectively. In this embodiment, the +Z direction is an example of a first direction, and the -Z direction is an example of a second direction. Furthermore, planes perpendicular to the X-axis, Y-axis, or Z-axis may also be referred to as the YZ plane, ZX plane, or XY plane. Furthermore, the direction of the Z-axis may also be referred to as the "vertical direction." The terms "upward," "downward," and "vertical direction" merely indicate relative positional relationships within the drawings, and do not define orientations relative to the vertical direction.

[0010] Furthermore, unless otherwise specifically explained, the dimensions of components shown in each drawing may be shown differently from the actual dimensions in order to make the explanation easier to understand. In this specification, "connection" includes not only physical connection but also electrical connection, and unless otherwise specified, includes not only direct connection but also indirect connection.

[0011] In this specification, "formed above" does not only mean forming in contact with the upper part, but also includes forming above via another object unless otherwise specified. The same applies to "formed below" and the like.

[0012] 1.1 Overview of semiconductor device configuration Fig. 1 is a circuit diagram showing the circuit configuration of a semiconductor memory device 101 according to an embodiment. The semiconductor memory device 101 shown in Fig. 1 is an OS-RAM (Oxide Semiconductor-Random Access Memory) and includes a memory cell array. As shown in Fig. 1, the memory cell array includes a plurality of memory cells MC, a plurality of word lines WL, and a plurality of bit lines BL.

[0013] FIG. 1 shows a word line WL as an example of a plurality of word lines WL. n , word line WLn+1 , and the word line WL n+2 In FIG. 1, the bit line BL is shown as an example of the bit line BL. m , bit line BL m+1 , and the bit line BL m+2 1, where m is a positive integer. Note that the number of memory cells MC is not limited to the number shown in FIG.

[0014] A plurality of memory cells MC are arranged in a matrix to form a memory cell array. Each memory cell MC includes a memory transistor MTR and a memory capacitor MCP. The memory transistor MTR is a field effect transistor (FET).

[0015] A series of memory cells MC arranged along the row direction are connected to a word line WL corresponding to the row to which they belong. For example, a memory cell MC belonging to the nth row is connected to a word line WL n A series of memory cells MC arranged in the column direction are connected to the bit line BL corresponding to the column to which they belong. For example, a memory cell MC belonging to the (m+2)th column is connected to the bit line BL m+2 is connected to.

[0016] More specifically, the gate of the memory transistor MTR included in the memory cell MC is connected to the word line WL corresponding to the row to which the memory cell MC belongs, and one of the source or drain of the memory transistor MTR is connected to the bit line BL corresponding to the column to which the memory cell MC belongs.

[0017] One electrode of a memory capacitor MCP included in a memory cell MC is connected to the other of the source or drain of a memory transistor MTR included in the memory cell MC, and the other electrode of the memory cell MC is connected to a power supply line (not shown) that supplies a specific potential.

[0018] The memory cell MC is configured to be able to hold data by storing charge in the memory capacitor MCP due to a current flowing through the corresponding bit line BL when the memory transistor MTR is switched based on the potential of the corresponding word line WL.

[0019] 2 is a cross-sectional view showing a cross-sectional structure parallel to the ZX plane of the semiconductor memory device 101. As shown in FIG. 2, the semiconductor memory device 101 includes a semiconductor substrate 10, a circuit 11, a capacitor 20, a semiconductor device 30, a conductor 33, and insulating layers 34, 35, 45, and 63.

[0020] The capacitor 20 includes a conductor 21 , an insulating film 22 , a conductor 23 , a capacitor electrode 24 , and a capacitor electrode 25 .

[0021] The semiconductor device 30 includes a field-effect transistor 40, an upper electrode 50, and a lower electrode 32. The lower electrode 32 is provided below the field-effect transistor 40. The upper electrode 50 is provided above the field-effect transistor 40. In the semiconductor device 30, the lower electrode 32 functions as either a source electrode or a drain electrode of the field-effect transistor 40, and the upper electrode 50 functions as the other of the source electrode and the drain electrode. In this embodiment, the lower electrode 32 is an example of a first electrode, and the upper electrode 50 is an example of a second electrode.

[0022] The field-effect transistor 40 includes an oxide semiconductor layer 70 , a conductive layer 42 , and a gate insulating film 43 .

[0023] The oxide semiconductor layer 70 is formed in the insulating layer 45. The oxide semiconductor layer 70 has a lower end 74 and an upper end 75. In this embodiment, the lower end 74 is an example of a first end, and the upper end 75 is an example of a second end. The oxide semiconductor layer 70 is a columnar body extending in the +Z direction from the lower end 74 to the upper end 75. The oxide semiconductor layer 70 forms a channel of the field-effect transistor 40. The oxide semiconductor layer 70 has an amorphous structure. The oxide semiconductor layer 70 is a semiconductor in which oxygen vacancies serve as donors and contains indium (In), zinc (Zn), and gallium (Ga) as metal elements. More specifically, the oxide semiconductor layer 70 is an oxide of indium, gallium, and zinc, i.e., IGZO (InGaZnO). Note that the oxide semiconductor layer 70 may be made of other types of oxide semiconductors.

[0024] The conductive layer 42 functions as a gate electrode of the field-effect transistor 40. The conductive layer 42 is provided between a lower end 74 and an upper end 75 of the oxide semiconductor layer 70 so as to surround the oxide semiconductor layer 70 with the gate insulating film 43 interposed therebetween. The conductive layer 42 contains, for example, tungsten (W).

[0025] The gate insulating film 43 includes, for example, a silicon nitride film (Si3N4) containing silicon and nitrogen.

[0026] The upper electrode 50 is formed in the +Z direction with respect to the oxide semiconductor layer 70. The upper electrode 50 is in contact with an upper end 75 of the oxide semiconductor layer 70. The upper electrode 50 includes a metal oxide layer 51, a barrier metal layer 52, and a metal film 53.

[0027] The metal film 53 contains tungsten. The metal oxide layer 51 is formed between the metal film 53 and the upper end 75 of the oxide semiconductor layer 70. The metal oxide layer 51 contains a metal oxide containing metal elements such as indium and tin. In this embodiment, the metal oxide layer 51 is formed of indium-tin-oxide (ITO).

[0028] The barrier metal layer 52 contains titanium and nitrogen. The barrier metal layer 52 is formed between the metal oxide layer 51 and the metal film 53. In this embodiment, the barrier metal layer 52 is made of, for example, titanium nitride (TiN).

[0029] The lower electrode 32 is in contact with a lower end 74 of the oxide semiconductor layer 70. The lower electrode 32 is formed of an ITO layer containing a metal oxide such as indium tin oxide (ITO). The lower electrode 32 is not limited to ITO, and may be composed of at least one element selected from the group consisting of indium, tin, zinc, cadmium, gold, silver, platinum, lead, copper, nickel, tungsten, and iron. In this embodiment, the lower electrode 32 is an example of a first conductive layer.

[0030] The circuit 11 includes peripheral circuits such as a decoder, a sense amplifier connected to the bit line BL, and a register configured from an SRAM. The decoder is used to select a predetermined memory cell MC from among the plurality of memory cells MC in the semiconductor memory device 101. The circuit 11 may include a CMOS circuit having field effect transistors, such as a P-channel field effect transistor (Pch-FET) and an N-channel field effect transistor (Nch-FET), formed by a CMOS process.

[0031] The field-effect transistors of the circuit 11 can be formed using a semiconductor substrate 10 such as a single-crystal silicon substrate. The Pch-FET and Nch-FET are field-effect transistors having a channel region, a source region, and a drain region in the semiconductor substrate 10. More specifically, the Pch-FET and Nch-FET are so-called lateral field-effect transistors having a channel for flowing carriers in the X-axis direction or the Y-axis direction substantially parallel to the surface of the semiconductor substrate 10 in a region close to the surface of the semiconductor substrate 10. The semiconductor substrate 10 may have a P-type or N-type conductivity. For convenience, FIG. 2 illustrates an example of a field-effect transistor of the circuit 11.

[0032] The capacitor 20 is a memory capacitor MCP included in the memory cell MC shown in Fig. 1. Although four capacitors 20 are shown in Fig. 2, the number of capacitors 20 is not limited to four.

[0033] In this embodiment, a capacitor 20 is provided above a semiconductor substrate 10. A capacitor electrode 24 of the capacitor 20 is connected to the conductor 21 and the lower electrode 32. A capacitor electrode 25 faces the capacitor electrode 24. An insulating film 22 is provided between the capacitor electrode 24 and the capacitor electrode 25.

[0034] The capacitor 20 is a three-dimensional capacitor such as a pillar-type capacitor. Note that other capacitors having a configuration capable of storing electric charge may also be used as the capacitor of this embodiment.

[0035] The conductor 21 is formed to abut against the lower end face of the lower electrode 32 and extend downward from that end. The capacitor electrode 24 is formed to cover the lower electrode 32 and the conductor 21. The insulating film 22 is formed to cover the capacitor electrode 24. The capacitor electrode 25 is provided to surround a lower portion of the insulating film 22. The lower end of the capacitor electrode 25 abuts against the upper end face of the conductor 23.

[0036] The conductor 21 may contain a material such as amorphous silicon. The insulating film 22 may contain a material such as hafnium oxide. The conductor 23 and the capacitor electrodes 24 and 25 may contain a material such as tungsten and titanium nitride.

[0037] The conductor 33 includes wiring that electrically connects the circuit 11 and the semiconductor device 30. The conductor 33 has a via line formed to extend in the Z-axis direction, as shown in Fig. 2, for example. This via line connects the word line WL and the circuit 11 provided on the semiconductor substrate 10. The conductor 33 includes, for example, copper.

[0038] The insulating layer 34 is provided between the plurality of capacitors 20. The insulating layer 34 is, for example, a silicon oxide film containing silicon and oxygen.

[0039] The insulating layer 35 is provided above the insulating layer 34. The insulating layer 35 is, for example, a silicon nitride film containing silicon and nitrogen.

[0040] The semiconductor device 30 is provided above the capacitor 20. A field effect transistor 40 in the semiconductor device 30 corresponds to the memory transistor MTR of the memory cell MC shown in FIG.

[0041] 2 , in the semiconductor device 30, the field-effect transistor 40 is provided above the lower electrode 32. More specifically, the oxide semiconductor layer 70 of the field-effect transistor 40 is located above the lower electrode 32, i.e., in a direction away from the semiconductor substrate 10. The upper electrode 50 is located above the oxide semiconductor layer 70, i.e., in a direction away from the semiconductor substrate 10.

[0042] With the above-described structure, the field effect transistor 40 is configured as a so-called vertical transistor, which has a channel extending in the direction of the Z axis (vertical direction) that is approximately perpendicular to the surface of the semiconductor substrate 10.

[0043] 1.2 Structure of semiconductor device Next, the structure of the semiconductor device 30 of this embodiment will be described.

[0044] As shown in FIG. 3 , the oxide semiconductor layer 70 is tapered from its upper end 75 to its lower end 74, i.e., toward the −Z direction. The gate insulating film 43 is provided so as to surround the oxide semiconductor layer 70, and is therefore tapered like the oxide semiconductor layer 70. The conductive layer 42 is provided so as to surround a predetermined portion 71 located approximately in the center of the oxide semiconductor layer 70, via the gate insulating film 43. Hereinafter, the predetermined portion 71 of the oxide semiconductor layer 70 will be referred to as the “middle portion 71.” Furthermore, a portion of the oxide semiconductor layer 70 located in the −Z direction with respect to the middle portion 71 will be referred to as the “lower portion 72.” Furthermore, a portion of the oxide semiconductor layer 70 located in the +Z direction with respect to the middle portion 71 will be referred to as the “upper portion 73.”

[0045] A cavity 76 is formed inside the oxide semiconductor layer 70. Therefore, the oxide semiconductor layer 70 has a hollow structure. The cavity 76 is formed to extend in the Z-axis direction from approximately the center of the upper portion 73 of the oxide semiconductor layer 70, through the middle portion 71, to approximately the center of the lower portion 72. Like the oxide semiconductor layer 70 and the gate insulating film 43, the cavity 76 is also formed in a tapered shape that narrows toward the −Z direction.

[0046] A protrusion 510 is formed in the metal oxide layer 51 so as to extend in the −Z direction from an upper end 75 of the oxide semiconductor layer 70 into the oxide semiconductor layer 70. The lower end of the protrusion 510 reaches a cavity 76 inside the oxide semiconductor layer 70.

[0047] 1.3 Semiconductor device manufacturing method Next, a method for manufacturing the semiconductor device 30 of this embodiment will be described.

[0048] When manufacturing the semiconductor device 30, a molded product 30a as shown in FIG. 4 is first manufactured. In this molded product 30a, an insulating layer 45b, a conductive layer 42, and an insulating layer 45a are formed in this order above the insulating layer 35. In this embodiment, the insulating layer 45b is an example of a first insulating layer, and the insulating layer 45a is an example of a second insulating layer. The insulating layer 45b, the conductive layer 42, and the insulating layer 45a extend substantially parallel to the XY plane. The insulating layer 45a and the insulating layer 45b form the insulating layer 45 shown in FIG. 3. A transistor hole TH is formed in the molded product 30a so as to penetrate the insulating layer 45a, the conductive layer 42, and the insulating layer 45b. The transistor hole TH is formed so as to extend substantially parallel to the Z axis. The upper surface of the lower electrode 32 is exposed at the bottom of the transistor hole TH.

[0049] 5, an insulating film 43 is formed on the upper surface of this molded article 30a, and then part of the insulating film 43 is removed by reactive ion etching. As a result, as shown in FIG. 6, the upper part of the molded article 30a is etched back to expose the insulating layer 45a, and the lower electrode 32 is exposed at the bottom of the transistor hole TH.

[0050] Next, as shown in Fig. 7, an oxide semiconductor layer 70 is formed on the upper surface of the molded article 30a by atomic layer deposition (ALD), and then the upper side of the molded article 30a is subjected to chemical mechanical polishing. As a result, the molded article 30a shown in Fig. 8 is formed. In the molded article 30a shown in Fig. 8, a slot 76a is formed so as to extend in the Z-axis direction through the center of the oxide semiconductor layer 70. The slot 76a is open at an upper end 75 of the oxide semiconductor layer 70.

[0051] 9, a metal oxide layer 51, a barrier metal layer 52, and a metal film 53 are sequentially formed on the upper surface of the molded article 30a. At this time, the openings of the elongated holes 76a formed in the oxide semiconductor layer 70 are blocked by the metal oxide layer 51, thereby forming cavities 76 in the oxide semiconductor layer 70. Next, a mask is formed by performing film formation, resist application, exposure, development, peeling, etc. on the surface of the molded article 30a by a lithography method, and then etching is performed to form the upper electrode 50 as shown in FIG.

[0052] 10 , in order to activate the oxide semiconductor layer 70, oxygen annealing is performed, for example, by heating, to supply oxygen to the oxide semiconductor layer 70. As a result, oxygen is supplied to the oxide semiconductor layer 70 from the sidewall of the metal oxide layer 51 through the metal oxide layer 51. At this time, oxygen is supplied to the lower portion 72 of the oxide semiconductor layer 70 through cavities 76 formed inside the oxide semiconductor layer 70, making it easier to supply oxygen to the entire oxide semiconductor layer 70.

[0053] Thereafter, a step of forming an insulating layer 63 on the molded article 30a shown in FIG. 10 and other steps are carried out, thereby manufacturing the semiconductor device 30 shown in FIG.

[0054] 1.4 Functions and Effects of the Semiconductor Device of the Embodiment Fig. 11 is a cross-sectional view showing the cross-sectional structure of a semiconductor device 130 of a comparative example. This semiconductor device 130 has a structure similar to that of the semiconductor device 30 shown in Fig. 3, except that the cavity 76 is not provided. In the semiconductor device 130 shown in Fig. 10, the same components as those in the semiconductor device 30 shown in Fig. 3 are denoted by the same reference numerals.

[0055] 11 , if the oxide semiconductor layer 70, which functions as a channel, is thinned in a direction perpendicular to the Z-axis direction, the threshold voltage Vth of the semiconductor device 130 can be shifted to the positive side. However, thinning the oxide semiconductor layer 70 in a direction perpendicular to the Z-axis direction reduces the contact area between the oxide semiconductor layer 70 and the lower electrode 32 and the contact area between the oxide semiconductor layer 70 and the upper electrode 50. As a result, the on-current of the semiconductor device 130 may decrease.

[0056] In this regard, the semiconductor device 30 of this embodiment includes an oxide semiconductor layer 70, a lower electrode 32, an upper electrode 50, and a conductive layer 42. The oxide semiconductor layer 70 has a lower end 74 and an upper end 75, and is provided to extend in the +Z direction from the lower end 74 to the upper end 75. The lower electrode 32 is in contact with the lower end 74 of the oxide semiconductor layer 70. The upper electrode 50 is in contact with the upper end 75 of the oxide semiconductor layer 70. The conductive layer 42 is provided to surround a middle portion 71 of the oxide semiconductor layer 70 with a gate insulating film 43 interposed therebetween. A cavity 76 is provided inside the middle portion 71 of the oxide semiconductor layer 70.

[0057] If the cavity 76 is formed inside the intermediate portion 71 of the oxide semiconductor layer 70 as in this configuration, it is possible to thin only the intermediate portion 71 in the vicinity of the conductive layer 42 that functions as the gate electrode of the field-effect transistor 40. This makes it possible to shift the threshold voltage Vth of the semiconductor device 30 to the positive side. It is also possible to improve the S value of the semiconductor device 30.

[0058] Furthermore, by forming a cavity 76 in the middle portion 71 of the oxide semiconductor layer 70 near the conductive layer 42, it is possible to maintain the contact area between the lower portion 72 of the oxide semiconductor layer 70 and the lower electrode 32, and the contact area between the upper portion 73 of the oxide semiconductor layer 70 and the upper electrode 50, and therefore it is also possible to maintain the on-current of the field-effect transistor 40.

[0059] 3 , even if a cavity 76 is formed in the intermediate portion 71 of the oxide semiconductor layer 70, it is possible to maintain a predetermined length H as the width from the interface BF with the gate insulating film 43 to the inner wall surface of the cavity 76 in the oxide semiconductor layer 70. Experiments conducted by the inventors have confirmed that by setting the length H to 4 nm or more, a region with a high carrier concentration can be secured in the oxide semiconductor layer 70 when the field-effect transistor 40 is in the on-state. In the semiconductor device 30 of this embodiment, by setting the width H to 4 nm or more, a region with a high carrier concentration is secured in the oxide semiconductor layer 70. This configuration also makes it possible to maintain the on-current of the field-effect transistor 40.

[0060] 1.5 First Modification of the Semiconductor Device of the Embodiment Next, a first modification of the semiconductor device 30 of the embodiment will be described.

[0061] 12, in the semiconductor device 30 of this modification, an insulating layer 80 is embedded inside the oxide semiconductor layer 70 instead of the cavity 76. The insulating layer 80 is made of either silicon oxide or alumina.

[0062] The semiconductor device 30 is manufactured, for example, as follows. First, after the molded product 30a shown in Fig. 8 is manufactured, an insulating layer 80 is formed on the upper surface of the molded product 30a. This fills the elongated holes 76a with the insulating layer 80. After that, a portion of the insulating layer 80 is selectively removed by etching using silicon nitride (SiN) or phosphoric acid, and then steps similar to those shown in Figs. 9 and 10 are carried out.

[0063] 1.6 Second Modification of the Semiconductor Device of the Embodiment Next, a second modification of the semiconductor device 30 of the embodiment will be described.

[0064] 13 , in the semiconductor device 30 of this modification, the oxide semiconductor layer 70 and the gate insulating film 43 are formed in an inverse tapered shape so as to become narrower in the +Z direction. The cavity 76 is also formed in an inverse tapered shape so as to become narrower in the +Z direction. The semiconductor device 30 of this modification also differs from the semiconductor device 30 of the above embodiment in that the metal oxide layer 51 does not have a protrusion 510 formed therein. The upper portion 73 of the oxide semiconductor layer 70 is in contact with the bottom surface 511 of the metal oxide layer 51. Therefore, the upper portion of the cavity 76 is not in contact with the metal oxide layer 51.

[0065] The semiconductor device 30 is manufactured, for example, as follows. First, the transistor hole TH shown in FIG. 4 is formed in an inverse tapered shape, and then steps similar to those shown in FIGS. 5 to 10 are performed. When the transistor hole TH is formed in an inverse tapered shape, steps similar to those shown in FIGS. 5 and 6 are performed to form a gate insulating film 43 in the transistor hole TH, and the gate insulating film 43 is also formed in an inverse tapered shape. Furthermore, steps similar to those shown in FIGS. 7 and 8 are performed to form an oxide semiconductor layer 70 by atomic layer deposition, and the elongated hole 76a shown in FIG. 8 is also formed in an inverse tapered shape. As a result, it is possible to easily form the inverse tapered cavity 76.

[0066] 1.7 Third Modification of the Semiconductor Device of the Embodiment Next, a third modification of the semiconductor device 30 of the embodiment will be described.

[0067] 14 , the semiconductor device 30 of this modification differs from the semiconductor device 30 of the above embodiment in that the metal oxide layer 51 does not have a protrusion 510. The upper portion 73 of the oxide semiconductor layer 70 is in contact with the bottom surface 511 of the metal oxide layer 51. Therefore, the upper portion of the cavity 76 is not in contact with the metal oxide layer 51. Furthermore, in the semiconductor device 30 of this modification, a recess 320 is formed in the lower electrode 32, and the lower portion 72 of the oxide semiconductor layer 70 is formed to extend into the recess 320. The lower portion of the cavity 76 is formed to extend inside the lower portion 72 of the oxide semiconductor layer 70 and is located inside the recess 320. Therefore, the cavity 76 is formed to extend from the middle portion 71 of the oxide semiconductor layer 70 to the inside of the recess 320.

[0068] 1.8 Fourth Modification of Semiconductor Device of the Embodiment Next, a fourth modification of the semiconductor device 30 of the embodiment will be described.

[0069] 15, the semiconductor device 30 of this modification differs from the semiconductor device 30 of the above embodiment shown in FIG. 3 in that no protrusion 510 is formed on the metal oxide layer 51. An upper portion 73 of the oxide semiconductor layer 70 is in contact with a bottom surface 511 of the metal oxide layer 51. Therefore, the upper portion of the cavity 76 is not in contact with the metal oxide layer 51.

[0070] 1.9 Fifth Modification of Semiconductor Device of the Embodiment Next, a fifth modification of the semiconductor device 30 of the embodiment will be described.

[0071] 16, the semiconductor device 30 of this modification differs from the semiconductor device 30 of the above embodiment shown in Fig. 3 in that no protrusion 510 is formed on the metal oxide layer 51. The upper part of the cavity 76 is in contact with the bottom surface 511 of the metal oxide layer 51.

[0072] 1.10 Sixth Modification of Semiconductor Device of the Embodiment Next, a sixth modification of the semiconductor device 30 of the embodiment will be described.

[0073] 17 , the semiconductor device 30 of this modification differs from the semiconductor device 30 of the above embodiment in that no protrusion 510 is formed in the metal oxide layer 51. The upper part of the cavity 76 is in contact with the bottom surface 511 of the metal oxide layer 51. Furthermore, in the semiconductor device 30 of this modification, a recess 320 is formed in the lower electrode 32, and the lower portion 72 of the oxide semiconductor layer 70 is formed to extend into the recess 320. The cavity 76 is formed to extend from the middle portion 71 of the oxide semiconductor layer 70 into the recess 320.

[0074] In the semiconductor device 30 of this modification, for example, as shown in FIG. 18, a protrusion 510 may be formed on the metal oxide layer 51, and the upper portion of the cavity 76 may be in contact with this protrusion 510.

[0075] 1.11 Seventh Modification of Semiconductor Device of the Embodiment Next, a seventh modification of the semiconductor device 30 of the embodiment will be described.

[0076] 19, in the semiconductor device 30 of this modification, a protrusion 321 is formed on the lower electrode 32. The protrusion 321 is formed so as to protrude into the lower portion of the gate insulating film 43.

[0077] In addition, in the semiconductor device 30 of this modified example, by adopting a structure similar to the structure shown in Figure 15, the upper part of the cavity 76 does not need to be in contact with the metal oxide layer 51, as shown in, for example, Figure 20.

[0078] 1.12 Eighth Modification of Semiconductor Device of the Embodiment Next, an eighth modification of the semiconductor device 30 of the embodiment will be described.

[0079] 21 , the semiconductor device 30 of this modification differs from the semiconductor device 30 shown in FIG. 12 in that a cavity 77 is formed between the protruding portion 510 of the metal oxide layer 51 and the insulating layer 80. As shown in FIG. 21 , in the semiconductor device 30 of this modification, the insulating layer 80 is provided inside the intermediate portion 71 of the oxide semiconductor layer 70. Furthermore, inside the oxide semiconductor layer 70, a cavity 77 is further formed adjacent to the insulating layer 80 in the +Z direction. In this way, both the insulating layer 80 and the cavity 77 may be formed inside the oxide semiconductor layer 70.

[0080] 22, the protrusion 510 may be removed from the metal oxide layer 51, thereby allowing the upper portion 73 of the oxide semiconductor layer 70 to contact the bottom surface 511 of the metal oxide layer 51. In addition, with respect to the semiconductor device 30 shown in FIG. 22, the cavity 77 may be removed as shown in FIG.

[0081] 2. Other Embodiments The present disclosure is not limited to the above specific examples.

[0082] For example, as a method for supplying oxygen to the oxide semiconductor layer 70 in the manufacturing process of the semiconductor device 30, oxygen may be supplied to the oxide semiconductor layer 70 by performing the step shown in FIG. 7, i.e., the step of forming the oxide semiconductor layer 70, in an oxygen atmosphere.

[0083] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments and their modifications are within the scope and spirit of the invention, and are included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0084] TH: transistor hole, 30: semiconductor device, 32: lower electrode (first electrode, first conductive layer), 42: conductive layer, 43: gate insulating film, 45a: insulating layer (second insulating layer), 45b: insulating layer (first insulating layer), 50: upper electrode (second electrode), 70: oxide semiconductor layer, 71: intermediate portion (predetermined portion), 74: lower end (first end), 75: upper end (second end), 76, 77: cavity, 80: insulating layer (third insulating layer), 510: protrusion.

Claims

1. an oxide semiconductor layer having a first end and a second end and extending in a first direction from the first end toward the second end; a first electrode in contact with the first end of the oxide semiconductor layer; a second electrode in contact with the second end of the oxide semiconductor layer; a conductive layer provided between the first end and the second end of the oxide semiconductor layer so as to surround a predetermined portion of the oxide semiconductor layer via an insulating film, At least one of a cavity and an insulating layer is provided inside the predetermined portion of the oxide semiconductor layer. Semiconductor device.

2. The oxide semiconductor layer is in contact with the first electrode, and at least one of the cavity and the insulating layer is not in contact with the first electrode. The semiconductor device according to claim 1 .

3. a recess in which the first end of the oxide semiconductor layer is embedded is formed in the first electrode; At least one of the cavity and the insulating layer is formed to extend from the predetermined portion of the oxide semiconductor layer to the inside of the recess. The semiconductor device according to claim 1 .

4. The oxide semiconductor layer is in contact with the second electrode, and at least one of the cavity and the insulating layer is not in contact with the second electrode. The semiconductor device according to claim 1 .

5. a protrusion is formed on the second electrode so as to extend from the second end of the oxide semiconductor layer into the oxide semiconductor layer in a second direction opposite to the first direction; The tip of the protrusion is in contact with at least one of the cavity and the insulating layer. The semiconductor device according to claim 1 .

6. the oxide semiconductor layer is formed in a tapered shape so as to become thinner in a second direction opposite to the first direction, At least one of the cavity and the insulating layer is tapered in the second direction. The semiconductor device according to claim 1 .

7. the oxide semiconductor layer is formed in a tapered shape so as to become thinner in the first direction, At least one of the cavity and the insulating layer is tapered in the first direction. The semiconductor device according to claim 1 .

8. the insulating layer is provided inside the predetermined portion of the oxide semiconductor layer, The cavity is further formed inside the oxide semiconductor layer adjacent to the insulating layer in the first direction. The semiconductor device according to claim 1 .

9. The insulating layer is formed of either silicon oxide or alumina. The semiconductor device according to claim 1 .

10. stacking a first conductive layer, a first insulating layer, a conductive layer, and a second insulating layer in a first direction; forming a hole that penetrates the second insulating layer, the conductive layer, and the first insulating layer and reaches the first conductive layer; forming an oxide semiconductor layer inside the hole by an ALD method; When forming the oxide semiconductor layer inside the hole, a cavity is formed inside a predetermined portion of the oxide semiconductor layer that is surrounded by the conductive layer; supplying oxygen to the oxide semiconductor layer; A method for manufacturing a semiconductor device.

11. Depositing a third insulating layer in the cavity. The method for manufacturing a semiconductor device according to claim 10.

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