Signal output circuit

Abstract

To suppress power supply voltage dependency on level change time of an output signal to a lower level.SOLUTION: A signal output circuit (10) comprises an output transistor (M0) provided between an output terminal (OUT) and a ground, and a drive circuit (100) for controlling the output transistor via turn-on / off by feeding a turn-on current based on a power supply voltage (VDD) to a gate of the output transistor, or by drawing a turn-off current from the gate of the output transistor. The drive circuit comprises an adjustment transistor (M1) constituted from MOSFET of an N-channel type and a depletion type, a current limit resistance (R1) provided between the adjustment transistor and the output transistor, and a voltage-generating circuit (110A) for generating a gate voltage of the adjustment transistor. The turn-on current is fed to the output transistor through the adjustment transistor and the current limit resistance.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present disclosure relates to a signal output circuit. [Background technology]

[0002] Open-drain signal output circuits are used in various electric circuits (see, for example, Patent Document 1 below). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-132482

[0004] [overview] When an open-drain signal output circuit changes the level of an output signal between high and low levels, standards and other requirements may be imposed on the time it takes for the level to change. However, the power supply voltage for the signal output circuit may fluctuate. It is therefore necessary to minimize the dependency of the time it takes for the level of the output signal to change.

[0005] A signal output circuit according to one aspect of the present disclosure comprises an output transistor constituted by an N-channel MOSFET having a drain connected to an output terminal and a source connected to ground, and a drive circuit configured to control the output transistor to be on or off by supplying an on-current based on a power supply voltage to the gate of the output transistor or by drawing an off-current from the gate of the output transistor, and is an open-drain signal output circuit configured to generate an output signal at the output terminal according to the state of the output transistor, wherein the drive circuit has an adjustment transistor constituted by an N-channel depletion-type MOSFET, a current limiting resistor provided between the adjustment transistor and the gate of the output transistor, and a voltage generation circuit configured to generate a gate voltage of the adjustment transistor, and supplies the on-current to the gate of the output transistor via the adjustment transistor and the current limiting resistor. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram illustrating a signal output circuit and its peripheral circuits according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is an external perspective view of the semiconductor device according to the embodiment of the present disclosure. [Figure 3] FIG. 3 is a waveform diagram of an input signal, a gate voltage, and an output signal according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a diagram showing a signal output circuit and its peripheral circuits according to a reference example. [Figure 5] FIG. 5 is a waveform diagram according to a reference example. [Figure 6] FIG. 6 is a diagram showing a signal output circuit and its peripheral circuits according to a first example of an embodiment of the present disclosure. [Figure 7] FIG. 7 is a diagram showing the relationship between the power supply voltage and the voltage applied to the current limiting resistor according to a first example of the embodiment of the present disclosure. [Figure 8] FIG. 8 is a waveform diagram of some signals and voltages according to a first example of the embodiment of the present disclosure. [Figure 9] FIG. 9 is a diagram showing a signal output circuit and its peripheral circuits according to a second example of the embodiment of the present disclosure. [Figure 10] FIG. 10 is a diagram showing a modified arrangement of a group of transistors connected in series to each other according to a second example of the embodiment of the present disclosure. [Figure 11] FIG. 11 is a diagram showing a modified circuit configuration for generating the gate voltage of an adjustment transistor according to a fourth example of the embodiment of the present disclosure. [Figure 12] FIG. 12 is an explanatory diagram relating to a modification of the arrangement position of an adjustment transistor according to a fifth example belonging to the embodiment of the present disclosure. [Figure 13] FIG. 13 is a schematic configuration diagram of a system that performs communication by I2C according to a sixth example belonging to an embodiment of the present disclosure.

[0007] [Detailed explanation] Hereinafter, examples of embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the drawings, the same parts are designated by the same reference numerals, and duplicate descriptions of the same parts will be omitted as a general rule. In this specification, for the sake of simplicity, symbols or signs referring to information, signals, physical quantities, functional units, circuits, elements, or components may be used, and the names of the information, signals, physical quantities, functional units, circuits, elements, or components corresponding to the symbols or signs may be omitted or abbreviated.

[0008] First, some terms used in describing the embodiments of the present disclosure will be explained. Ground refers to a reference conductor having a reference potential of 0 V (zero volts), or refers to the 0 V potential itself. The reference conductor may be formed using a conductor such as metal. The 0 V potential is sometimes referred to as ground potential. In the embodiments of the present disclosure, a voltage indicated without a specific reference represents a potential seen from ground. Level refers to the level of potential, and for any signal or voltage of interest, a high level has a higher potential than a low level.

[0009] For any transistor configured as a FET (field effect transistor) exemplified by a MOSFET, the on-state refers to a state where conduction exists between the drain and source of the transistor, and the off-state refers to a state where non-conduction (cut-off state) exists between the drain and source of the transistor. The same applies to transistors not classified as FETs. Unless otherwise specified, a MOSFET is understood to be an enhancement-mode MOSFET. MOSFET is an abbreviation of "metal-oxide-semiconductor field-effect transistor". Also, unless otherwise specified, in any MOSFET, the back gate may be considered to be short-circuited to the source. Hereinafter, for any transistor, the on-state and off-state may also be simply expressed as on and off, respectively.

[0010] For any signal having a high-level or low-level signal level, the period during which the level of the signal is high is referred to as the high-level period, and the period during which the level of the signal is low is referred to as the low-level period. The same applies to any voltage having a high-level or low-level voltage level.

[0011] Unless otherwise specified, the connection between a plurality of parts forming a circuit, such as any circuit element, wiring, node, etc., may be understood to refer to an electrical connection.

[0012] When any two voltages to be compared are voltage va and vb, "va>vb" represents that voltage va is higher than voltage vb, "va<vb" represents that voltage va is lower than voltage vb, and "va=vb" represents that the value of voltage va is the same as the value of voltage vb. The same applies to other expressions including physical quantities other than voltage.

[0013] FIG. 1 shows a signal output circuit 10 and its peripheral circuits according to an embodiment of the present disclosure. The signal output circuit 10 includes an output transistor M0, a drive circuit 100, a capacitor C0, and a resistor R0. A control circuit 20 is connected to the drive circuit 100. The control circuit 20 may be considered to be included in the components of the signal output circuit 10. The control circuit 20 supplies an input signal Sin to the drive circuit 100. An output terminal OUT is connected to the signal output circuit 10. The output terminal OUT may be considered to be included in the components of the signal output circuit 10. A signal at the output terminal OUT is referred to as an output signal Sout. The signal output circuit 10 generates an output signal Sout at the output terminal OUT that corresponds to the input signal Sin (in other words, the signal output circuit 10 outputs an output signal Sout from the output terminal OUT that corresponds to the input signal Sin). The signal output circuit 10 is an open-drain signal output circuit that generates an output signal Sout at the output terminal OUT that corresponds to the state of the output transistor M0.

[0014] 2 is a perspective view of the appearance of a semiconductor device 1 according to an embodiment of the present disclosure. The semiconductor device 1 is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) that houses the semiconductor chip, and a plurality of external terminals that are exposed to the outside of the semiconductor device 1 from the housing. The semiconductor device 1 is formed by sealing the semiconductor chip in a housing (package) made of resin. Three of the plurality of external terminals provided on the semiconductor device 1 are a power supply terminal VDD IN 1 shows the power supply terminal VDD and the ground terminal GND, and the above-mentioned output terminal OUT. Other external terminals are also provided in the semiconductor device 1. A signal output circuit 10 and a control circuit 20 are provided in the semiconductor integrated circuit of the semiconductor device 1. The power supply terminal VDD shown in FIG. IN The relative positions of the ground terminal GND and the output terminal OUT, the number of external terminals of the semiconductor device 1, and the type of housing of the semiconductor device 1 are merely examples and can be designed arbitrarily.

[0015] A voltage source (not shown) provided outside the semiconductor device 1 is connected to the power supply terminal VDD INA power supply voltage VDD is supplied to the semiconductor device 1. The power supply voltage VDD is a positive DC voltage. Each circuit in the semiconductor device 1 is driven based on the power supply voltage VDD. The ground terminal GND is connected to the ground. A signal line SL is provided outside the semiconductor device 1. The output terminal OUT is connected to the signal line SL. The signal line SL is a wiring for propagating the output signal Sout.

[0016] A pull-up resistor R PU The signal line SL is connected to a pull-up resistor R PU That is, the pull-up resistor R PU The first terminal of the resistor R is connected to the power supply terminal 52. PU The second end of the power supply voltage VDD2 is connected to the signal line SL. The power supply voltage application end 52 is the application end of the power supply voltage VDD2 (i.e., the terminal to which the power supply voltage VDD2 is applied). The power supply voltage VDD2 may be the same as the power supply voltage VDD, or may be a positive DC voltage different from the power supply voltage VDD. In the following, unless otherwise required, the power supply voltage VDD2 is considered to be the same as the power supply voltage VDD.

[0017] The output transistor M0 is composed of an N-channel MOSFET. The drain of the output transistor M0 is connected to the output terminal OUT, and the source of the output transistor M0 is connected to ground. The voltage at the gate of the output transistor M0 is referred to as the gate voltage V0. The drive circuit 100 is connected to a power supply application terminal 51 and ground, and is also connected to the gate of the output transistor M0. The power supply application terminal 51 is an application terminal for the power supply voltage VDD (i.e., a terminal to which the power supply voltage VDD is applied).

[0018] The drive circuit 100 controls the gate voltage V0 of the output transistor M0 in response to an input signal Sin, thereby turning the output transistor M0 on or off. The input signal Sin is a binary signal having either a high level or a low level. The control circuit 20 operates based on a power supply voltage VDD with respect to ground. The control circuit 20 sets the high level of the input signal Sin to the level of the power supply voltage VDD, and sets the low level of the input signal Sin to the ground level.

[0019] It is also possible to control the output transistor M0 to be off when the input signal Sin is at a low level, and to control the output transistor M0 to be on when the input signal Sin is at a high level, but here it is assumed that the output transistor M0 is controlled to be on when the input signal Sin is at a low level, and to be off when the input signal Sin is at a high level.

[0020] When the input signal Sin is at a low level, the drive circuit 100 supplies an on-current (corresponding to the current Ion in FIG. 1) based on the power supply voltage VDD to the gate of the output transistor M0, thereby raising the gate voltage V0 and controlling the output transistor M0 to be on. However, the gate voltage V0 never rises above the power supply voltage VDD. When the input signal Sin is at a high level, the drive circuit 100 draws an off-current (corresponding to the current Ioff in FIG. 1) from the gate of the output transistor M0 to lower the gate voltage V0, thereby controlling the output transistor M0 to be off. However, the gate voltage V0 never drops below 0V. Note that although the on-current (Ion) and the off-current (Ioff) are shown together in FIG. 1, they never occur simultaneously.

[0021] When the output transistor M0 is on, a pull-up resistor R PU and current flows through the channel of the output transistor M0, so except for transient states, the pull-up resistor R PU When the output transistor M0 is off, the output signal Sout has a low level due to the voltage drop of the pull-up resistor R PUSince no current flows through the output signal Sout, the output signal Sout has a high level except in transient states. The output signal Sout has a potential greater than 0V and less than the power supply voltage VDD2. In the output signal Sout, the high level has a higher potential than the low level. In the output signal Sout, the low level is equal to the ground potential or has a level sufficiently close to the ground potential (for example, a voltage value less than 0.1 times the power supply voltage VDD2). In the output signal Sout, the high level is equal to the level of the power supply voltage VDD2 or has a level sufficiently close to the power supply voltage VDD2 (for example, a voltage value more than 0.9 times the power supply voltage VDD2).

[0022] Between the gate of the output transistor M0 and the output terminal OUT, a fall time t F A series circuit of a capacitor C0 and a resistor R0 is provided as a circuit for optimizing the output voltage Vout (see FIG. 3). More specifically, a first terminal of the capacitor C0 is connected to the gate of the output transistor M0, a second terminal of the capacitor C0 is connected to a first terminal of the resistor R0, and a second terminal of the resistor R0 is connected to the output terminal OUT.

[0023] The semiconductor device 1 and other circuit devices (not shown) are connected via a communication bus, and bidirectional communication is possible via the communication bus. The signal line SL is one of the signal lines in the communication bus. The communication bus is, for example, 2 The communication bus may be an Inter-Integrated Circuit (C) or Serial Peripheral Interface (SPI) communication bus. The standard of the communication bus defines the requirement regarding the time it takes for the output signal Sout to fall from a high level to a low level.

[0024] This will be explained in more detail with reference to Fig. 3. Fig. 3 shows the waveforms of the input signal Sin, the gate voltage V0, and the output signal Sout. At a certain time T A1 The input signal Sin is maintained at a high level before time T A1Before time T, the gate voltage V0 is maintained at 0V (zero volts), and the level of the output signal Sout is maintained at the level of the power supply voltage VDD2. A1 At time T A1 The gate voltage V0 starts to rise from 0V, and at time T A1 A time later than T A2 At this point, the gate voltage V0 reaches the voltage Vth, which is the gate threshold voltage of the output transistor M0.

[0025] Therefore, at time T A2 At time T A2 After that, the level of the output signal Sout gradually decreases toward the ground level, and at time T A3 At this point, the level of the output signal Sout drops to the ground level (0V).

[0026] Time T A2 and T A3 The on-current during this period is used to charge the gate capacitance of the output transistor M0 and the capacitor C0. A2 and T A3 During the period between the time T A2 and T A3 The period between the time T A3 Thereafter, the gate voltage V0 rises above the voltage Vth due to the on-current, and when the gate voltage V0 rises to a voltage that is higher than the voltage Vth and that depends on the configuration of the drive circuit 100, the rise of the gate voltage V0 stops.

[0027] In the process of decreasing the level of the output signal Sout, the output signal Sout reaches the voltage V H From the point when the output signal Sout has a voltage V L The time until the point where the fall time t F Voltage V H is the k of the power supply voltage VDD2 H times, and the voltage V L is the k of the power supply voltage VDD2 L At least “1>k H >k L >0” is established. Therefore, the voltage V H is the voltage V L For example, (k H ,k L )=(0.7,0.3). However, “k H = 1" and "k L =0”.

[0028] In the communication bus standard, the fall time t F On the other hand, the semiconductor device 1 does not have a regulator for the drive circuit 100, and an externally supplied power supply voltage VDD is supplied to the drive circuit 100. The power supply voltage VDD fluctuates in various ways. Here, the power supply voltage VDD is a voltage V MIN and voltage V MAX It is assumed that the specifications of the semiconductor device 1 are determined so that normal operation of the semiconductor device 1 is guaranteed if the following conditions are met: <V MIN <V MAX " is satisfied. For example, the voltage V MIN is 1.6V, and the voltage V MAX is 5.5 V. Ingenuity is required to meet the standards for the communication bus while resisting fluctuations in the power supply voltage VDD.

[0029] <<Reference example>> FIG. 4 shows a signal output circuit 910 according to a reference example, along with its peripheral circuits. The signal output circuit 910 is a circuit different from the signal output circuit 10 provided in the semiconductor device 1 and is intended for comparison with the signal output circuit 10. The signal output circuit 910 includes a transistor 911, which is a P-channel MOSFET, a transistor 912, which is an N-channel MOSFET, and a current-limiting resistor 913. In the signal output circuit 910, a power supply voltage VDD is supplied to the source of the transistor 911, the drain of the transistor 911 is connected to a first end of the current-limiting resistor 913, and the second end of the current-limiting resistor 913 is connected to the gate of the output transistor M0. The voltage at the first end of the current-limiting resistor 913 is referred to as voltage Va. In the signal output circuit 910, the drain of the transistor 912 is connected to the gate of the output transistor M0, and the source of the transistor 912 is connected to ground. In the signal output circuit 910, an input signal Sin is supplied to the gates of the transistors 911 and 912. In the signal output circuit 910, during the high level period of the input signal Sin, the transistor 911 is turned off and the transistor 912 is turned on, thereby controlling the output transistor M0 to be off, and during the low level period of the input signal Sin, the transistor 911 is turned on and the transistor 912 is turned off, thereby controlling the output transistor M0 to be on.

[0030] 5 shows a timing chart according to the reference example. In FIG. 5, solid line waveforms 921, 922, 923, and 924 respectively relate to the reference example and are used when "VDD=V MAX The waveforms of the input signal Sin, the voltage Va, the gate voltage V0, and the output signal Sout are shown when "VDD=V MIN 5 shows the waveforms of the input signal Sin, voltage Va, gate voltage V0, and output signal Sout when "VDD=VDD2". For convenience of illustration, in FIG. 5, waveforms 921 and 931 are shown slightly shifted from each other, and waveforms 922 and 932 are shown slightly shifted from each other. The same is true for waveforms 923 and 933, and also for waveforms 924 and 934. As mentioned above, it is assumed here that "VDD=VDD2".

[0031] In the reference example, "VDD=V MAX " when the fall time t F is the fall time t FMAX0 And, VDD=V MIN " when the fall time t F is the fall time t FMIN0 In the reference example, regardless of the level of the power supply voltage VDD, a voltage Va that substantially coincides with the power supply voltage VDD is applied to one end of the current limiting resistor 913 during the low level period of the input signal Sin. MAX "When VDD=V MIN " is considerably larger than the on-state current when "VDD=V MAX " when the fall time t F (i.e. t FMAX0 ) is "VDD=V MIN " when the fall time t F (i.e. t FMIN0 ) is considerably smaller than

[0032] As a result, in the reference example, “VDD=V MAX " when the fall time t F and “VDD=V MIN " when the fall time t F It is difficult to keep both within the specified time range. MIN " when the fall time t F When the value of the current limiting resistor 913 is set to a relatively small value so that is below the upper limit of the specified time range, MAX ", the on-current becomes too large, and "VDD=V MAX " when the fall time t F It is difficult to make the value of V equal to or greater than the lower limit of the specified time range. MAX " when the fall time t F When the value of the current limiting resistor 913 is set relatively large so that is equal to or greater than the lower limit of the specified time range, MIN "When "VDD=VMIN " when the fall time t F It is difficult to keep the time below the upper limit of the specified time range.

[0033] In this example, the fall time t F If a regulator is provided to generate a constant voltage from the power supply voltage VDD and the constant voltage is supplied to the source of the transistor 911, the fall time t F However, this method cannot be used in a semiconductor device 1 that does not have a regulator.

[0034] The present disclosure includes the following first to seventh examples. F This section describes a technology or application technology for suppressing the power supply voltage dependency of the present invention. The matters described above in this embodiment are applied to the following embodiments unless otherwise specified and unless contradicted (excluding matters related to the Reference Example). In the embodiments, if there are matters that contradict the matters described above, the description in each embodiment may take precedence. Furthermore, unless contradicted, matters described in any of the following embodiments can be applied to any of the other embodiments (i.e., any two or more of the multiple embodiments can be combined).

[0035] <<First Example>> A first embodiment will now be described. FIG. 6 shows a signal output circuit 10 according to the first embodiment and its peripheral circuits. The drive circuit 100 according to the first embodiment includes an adjustment transistor M1, a current limiting resistor R1, a transistor MH functioning as a high-side switch, a transistor ML functioning as a low-side switch, and a voltage generation circuit 110A. The voltage generation circuit 110A includes a resistor R2 and transistors M11, M12, and M13. Like the output transistor M0, the transistors MH, ML, and M11 to M13 are each an enhancement-type MOSFET, while the adjustment transistor M1 is a depletion-type MOSFET. The MOSFETs serving as the adjustment transistor M1 and the transistors ML and M11 to M13 are N-channel MOSFETs, and the MOSFET serving as the transistor MH is a P-channel MOSFET.

[0036] The source of the transistor MH is connected to the power supply application terminal 51 and receives the power supply voltage VDD. The drain of the transistor MH is connected to the drain of the adjustment transistor M1. The source of the adjustment transistor M1 is connected to the gate of the output transistor M0 via a current-limiting resistor R1. The gate of the output transistor M0 is connected to ground through the channel of the transistor ML. Specifically, the first terminal of the current-limiting resistor R1 is connected to the source of the adjustment transistor M1, and the second terminal of the current-limiting resistor R1 is connected to the gate of the output transistor M0. The drain of the transistor ML is connected to the gate of the output transistor M0, and the source of the transistor ML is connected to ground. An input signal Sin from the control circuit 20 is supplied to the gates of the transistors MH and ML. The voltage at the first terminal of the current-limiting resistor R1 is referred to as voltage V1. In the configuration of FIG. 6, voltage V1 is the voltage at the source of the adjustment transistor M1.

[0037] A first end of the resistor R2 is connected to the power supply application terminal 51 and receives the power supply voltage VDD. A second end of the resistor R2 is connected to a node 53 (a specific node). The node 53 is connected to the gate of the adjustment transistor M1. Therefore, the voltage at the node 53 is the gate voltage of the adjustment transistor M1. The voltage generating circuit 110A generates the gate voltage of the adjustment transistor M1 at the node 53 based on the power supply voltage VDD.

[0038] The voltage generating circuit 110A has one or more voltage generating elements between the node 53 and ground (and therefore between the gate of the adjustment transistor M1 and ground). In the first embodiment, each of the transistors M11 to M13 is a voltage generating element. The transistors M11 to M13 have the same structure and therefore the same electrical characteristics. In the configuration of FIG. 6, three voltage generating elements are provided in the voltage generating circuit 110A. In the first embodiment, each voltage generating element is a diode-connected MOSFET and therefore has its drain and gate shorted to each other. When two or more voltage generating elements are provided in the voltage generating circuit 110A, the two or more voltage generating elements are connected in series to each other.

[0039] 6, the drain and gate of transistor M11 are connected to node 53 (and therefore to the gate of adjustment transistor M1), the source of transistor M11 is connected to the drain and gate of transistor M12, and the source of transistor M12 is connected to the drain and gate of transistor M13. The source of transistor M13 is connected to ground. The sum of the gate threshold voltages of transistors M11, M12, and M13 is represented by a voltage 3Vf.

[0040] The operation of the signal output circuit 10 (particularly the drive circuit 100) in FIG. 6 will now be described. If "VDD≧3Vf", a drain current is supplied to each of the transistors M11 to M13 from the power supply application terminal 51 via the resistor R2, and the gate voltage of the adjustment transistor M1 is generated based on the gate-source voltage (gate potential as viewed from the source potential) of each of the transistors M11 to M13 when the drain current is supplied to the transistors M11 to M13. Here, "V MAX >3Vf>V MIN " is true. Therefore, "V MAX ≧VDD≧3Vf”, the gate voltage of the adjustment transistor M1 is substantially equal to the voltage 3Vf. MAX ≥ VDD ≥ 3Vf" is satisfied, the gate voltage of the adjustment transistor M1 also increases slightly as the power supply voltage VDD increases. MAX It is considered that the gate voltage of the adjustment transistor M1 always coincides with the voltage 3Vf when "VDD≧3Vf" is satisfied.

[0041] On the other hand, if "VDD<3Vf", the drain current of each of the transistors M11 to M13 is cut off, and therefore no current flows through the resistor R2, so that the power supply voltage VDD is applied directly to the node 53. In other words, when "VDD<3Vf", the voltage generating circuit 110A applies the power supply voltage VDD itself to the gate of the adjustment transistor M1. As a variant, "VDD≧3Vf" may always be true.

[0042] As described above, the drive circuit 100 controls the gate voltage V0 of the output transistor M0 in response to the input signal Sin, thereby controlling the output transistor M0 to be on or off. In this case, the drive circuit 100 switches the transistor MH from off to on and the transistor ML from on to off to transition the output transistor M0 from off to on, and switches the transistor MH from on to off and the transistor ML from off to on to transition the output transistor M0 from on to off. During a low-level period of the input signal Sin, the transistor MH is on and the transistor ML is off, and during a high-level period of the input signal Sin, the transistor MH is off and the transistor ML is on. The absolute value of the gate threshold voltage of the adjustment transistor M1 is represented by |Vth_M1|. The absolute value |Vth_M1| may be equal to the gate threshold voltages of the transistors M11 to M13.

[0043] Figure 7 shows the relationship between the power supply voltage VDD and the voltage V1. When "VDD ≥ 3Vf + |Vth_M1|" is established, if the input signal Sin is at a low level, the voltage V1 will be higher than the gate voltage of the adjustment transistor M1 by the absolute value |Vth_M1|, regardless of fluctuations in the power supply voltage VDD. In other words, it will match the voltage (3Vf + |Vth_M1|) (here, the drain-source voltages of the transistors MH and M1 are ignored as they are minute). MAX >3Vf+|Vth_M1|" is satisfied. When "VDD<3Vf+|Vth_M1|" is satisfied, if the input signal Sin is at a low level, the voltage V1 will match the power supply voltage VDD regardless of fluctuations in the power supply voltage VDD (here, the drain-source voltages of the transistors MH and M1 are ignored as they are tiny).

[0044] Specifically, consider a case where the voltage 3Vf is 2.1 V and the absolute value |Vth_M1| is 0.7 V. In this case, if the power supply voltage VDD is 2.8 V or higher, the voltage V1 will be 2.8 V during the low-level period of the input signal Sin regardless of fluctuations in the power supply voltage VDD; if the power supply voltage VDD is 2.1 V, the voltage V1 will be 2.1 V during the low-level period of the input signal Sin; and if the power supply voltage VDD is 1.6 V, the voltage V1 will be 1.6 V during the low-level period of the input signal Sin.

[0045] Thus, the voltage V1 during the low-level period of the input signal Sin is equal to the lower of the voltage (3Vf+|Vth_M1|) and the power supply voltage VDD. In other words, the adjustment transistor M1 limits and adjusts the voltage V1 supplied to the current limiting resistor R1 to be equal to or lower than the voltage (3Vf+|Vth_M1|), regardless of the value of the power supply voltage VDD.

[0046] During a low-level period of the input signal Sin, an on-state current based on the power supply voltage VDD is supplied from the power supply application terminal 51 to the gate of the output transistor M0 via the transistor MH, the adjustment transistor M1, and the current-limiting resistor R1. The on-state current is supplied to the gate of the output transistor M0 via the current-limiting resistor R1, causing the gate voltage V0 to rise. However, during the mirror period after the gate voltage V0 reaches the gate threshold voltage (Vth) of the output transistor M0, the output signal Sout decreases from the level of the power supply voltage VDD2 toward ground level while the increase in the gate voltage V0 is temporarily stopped (see FIG. 3). When the output signal Sout decreases to ground level, the on-state current increases the gate voltage V0 toward voltage V1. When the gate voltage V0 reaches voltage V1, the supply of the on-state current to the gate of the output transistor M0 is terminated.

[0047] During the high-level period of the input signal Sin, the drive circuit 100 draws an off-current from the gate of the output transistor M0 through the drain and source of the transistor ML to ground. As a result, the gate capacitance of the output transistor M0 and the capacitor C0 are discharged in the direction in which the gate voltage V0 of the output transistor M0 decreases, and when the gate voltage V0 falls below the gate threshold voltage (Vth) of the output transistor M0, the output transistor M0 switches from on to off. When the output transistor M0 switches from on to off, the pull-up resistor R PU The output signal Sout rises from the ground level to the power supply voltage VDD2 level at a rate that depends on the value of the capacitance added to the signal line SL and the value of the capacitance added to the signal line SL.

[0048] 8 shows a timing chart according to the first embodiment. In FIG. 8, solid waveforms 621, 622, 623, and 624 respectively represent the timings according to the first embodiment when "VDD=V MAX The dashed waveforms 631, 632, 633, and 634 show the waveforms of the input signal Sin, voltage V1, gate voltage V0, and output signal Sout when "VDD=V MIN 8 shows the waveforms of the input signal Sin, voltage V1, gate voltage V0, and output signal Sout when "VDD=VDD2". For convenience of illustration, in FIG. 8, waveforms 621 and 631 are shown slightly shifted from each other, and waveforms 622 and 632 are shown slightly shifted from each other. The same is true for waveforms 623 and 633, and also for waveforms 624 and 634. As mentioned above, it is assumed here that "VDD=VDD2".

[0049] a certain time T B1 The input signal Sin is maintained at a high level before time T B1 Before this, the voltages V1 and V0 are maintained at 0V (zero volts), and the level of the output signal Sout is set to the level of the power supply voltage VDD2 (here, the voltage V MAX or V MIN ) is maintained at time T B1At time T B1 The gate voltage V0 starts from 0V and rises to the gate threshold voltage (Vth) of the output transistor M0. Since the rate at which the gate voltage V0 rises depends on the voltage V1 (because it depends on the magnitude of the on-current), MAX " and "VDD=V MIN " is different from when "VDD=V MAX ", the voltage V1 during the low level period of the input signal Sin is the voltage (3Vf+|Vth_M1|). MIN ", the voltage V1 during the low level period of the input signal Sin is the power supply voltage VDD (=V MIN <3Vf+|Vth_M1|).

[0050] Time T B1 After that, when the gate voltage V0 reaches the gate threshold voltage (Vth) of the output transistor M0, current begins to flow between the drain and source of the output transistor M0, and as a result, the level of the output signal Sout begins to decrease from the level of the power supply voltage VDD2 toward ground. The period during which the level of the output signal Sout decreases from the level of the power supply voltage VDD2 toward ground corresponds to the mirror period, during which the gate voltage V0 is substantially maintained unchanged at the gate threshold voltage (Vth) of the output transistor M0. After the level of the output signal Sout decreases to ground, the on-current causes the gate voltage V0 to increase from the gate threshold voltage of the output transistor M0 toward voltage V1, and when the gate voltage V0 reaches voltage V1, the increase in the gate voltage V0 stops.

[0051] In the first embodiment, “VDD=V MAX " when the fall time t F is the fall time t FMAX1 And, VDD=V MIN" when the fall time t F is the fall time t FMIN1 In the first embodiment, "VDD=V MAX "Even if voltage V1 is voltage V MAX Since the voltage is limited to a lower voltage (3Vf + |Vth_M1|) than MAX " when the fall time t F is "V1=V MAX In other words, in comparison with the reference example (see FIGS. 4 and 5), in the first embodiment, MAX " when the fall time t F and “VDD=V MIN " when the fall time t F As a result, the difference between VDD and V MAX " when the fall time t F and “VDD=V MIN " when the fall time t F In this way, in the first embodiment, the fall time t F The power supply voltage dependency of the F (This can keep fluctuations in the

[0052] <<Second Example>> A second embodiment will now be described. FIG. 9 shows a signal output circuit 10 and its peripheral circuitry according to the second embodiment. The drive circuit 100 according to the second embodiment includes an adjustment transistor M1, a current-limiting resistor R1, a transistor MH functioning as a high-side switch, a transistor ML functioning as a low-side switch, and a voltage generator circuit 110B. The drive circuit 100 of the second embodiment is formed by replacing the voltage generator circuit 110A in FIG. 6 with the voltage generator circuit 110B, based on the drive circuit 100 of the first embodiment. Apart from this replacement, the circuit configuration and operation of the second embodiment are the same as those of the first embodiment. The voltage generator circuit 110B has a configuration in which a switching transistor M2 is added to the voltage generator circuit 110A in FIG. 6. The switching transistor M2 is an enhancement-type N-channel MOSFET and functions as a mode switch.

[0053] The voltage generating circuit 110B according to the second embodiment has a series circuit of one or more voltage generating elements and a switching transistor M2 (mode switching switch) between the node 53 and ground (and therefore between the gate of the adjustment transistor M1 and ground). In the configuration of FIG. 9, transistors M11 to M13 are provided in the voltage generating circuit 110B as three voltage generating elements. As in the first embodiment, each voltage generating element is a diode-connected MOSFET, and therefore has its drain and gate shorted to each other. When two or more voltage generating elements are provided in the voltage generating circuit 110B, the two or more voltage generating elements are connected in series to each other.

[0054] 9, the switching transistor M2 is inserted between the source of the transistor M13 and ground. That is, in the configuration of Fig. 9, the drain and gate of the transistor M11 are connected to the node 53 (and therefore to the gate of the adjustment transistor M1), the source of the transistor M11 is connected to the drain and gate of the transistor M12, the source of the transistor M12 is connected to the drain and gate of the transistor M13, the source of the transistor M13 is connected to the drain of the switching transistor M2, and the source of the switching transistor M2 is connected to ground.

[0055] A switching signal Ssw is supplied from the control circuit 20 to the gate of the switching transistor M2. Like the input signal Sin, the switching signal Ssw is a binary signal having either a high level or a low level. When the switching signal Ssw has a high level, the switching transistor M2 is on, and when the switching signal Ssw has a low level, the switching transistor M2 is off. The voltage of the node 53 can vary depending on whether the switching transistor M2 is on or off.

[0056] The control circuit 20 sets the operation mode of the voltage generation circuit 110B to a first mode or a second mode. The control circuit 20 sets the operation mode of the voltage generation circuit 110B to the first mode by supplying a high-level switching signal Ssw to the gate of the switching transistor M2, and sets the operation mode of the voltage generation circuit 110B to the second mode by supplying a low-level switching signal Ssw to the gate of the switching transistor M2. The operation mode of the voltage generation circuit 110B may also be interpreted as the operation mode of the drive circuit 100 or the signal output circuit 10.

[0057] In the first mode, the switching transistor M2 is turned on, and therefore the voltage at the node 53 is as shown in the first embodiment. Therefore, the operation of the signal output circuit 10 and the behavior of the output signal Sout in the first mode are the same as those shown in the first embodiment.

[0058] In contrast, in the second mode, the switching transistor M2 is turned off, so the voltage at the node 53 always coincides with the power supply voltage VDD, and the voltage V1 when the input signal Sin is at a low level always coincides with the power supply voltage VDD (here, the drain-source voltages of the transistors MH and M1 are ignored as being minute). Therefore, the operation of the signal output circuit 10 and the behavior of the output signal Sout in the second mode are the same as those in the reference example.

[0059] In the first mode, as described in the first embodiment, the fall time t F However, when the power supply voltage VDD is higher than 3Vf, current continues to flow through resistor R2 and transistors M11, M12, M13, and M2. Depending on the specifications of the system in which the semiconductor device 1 is installed, communication requirements may be met even in the second mode. Operating the signal output circuit 10 in the second mode can reduce the power consumed by the current supplied to resistor R2, etc., which is advantageous for power saving. By providing the switching transistor M2 as in the second embodiment, it is possible to operate the signal output circuit 10 in the first mode only when necessary.

[0060] For example, the control circuit 20 sets the operation mode of the voltage generator circuit 110B to the first or second mode based on mode setting data stored in its own memory (in other words, determines the level of the switching signal Ssw). In this case, when the mode setting data has a value of "0," the control circuit 20 sets the operation mode of the voltage generator circuit 110B to the first mode, and when the mode setting data has a value of "1," the control circuit 20 sets the operation mode of the voltage generator circuit 110B to the second mode. The memory that stores the mode setting data may be a volatile memory classified as a register or the like, or may be a nonvolatile memory. The value of the mode setting data may be determined based on a command signal from a higher-level circuit connected externally to the semiconductor device 1. Alternatively, the value of the mode setting data may be permanently set and stored in the nonvolatile memory during the manufacturing or shipping stage of the semiconductor device 1.

[0061] Alternatively, for example, a mode setting terminal may be included in the external terminals of the semiconductor device 1. In this case, the control circuit 20 sets the operation mode of the voltage generating circuit 110B to the first or second mode depending on the level of the voltage applied to the mode setting terminal (in other words, it determines the level of the switching signal Ssw).

[0062] The insertion position of the switching transistor M2 is arbitrary as long as the series circuit of the transistors M11 to M13 and M2 is inserted between the gate 53 and ground. Therefore, for example, as shown in Fig. 10, the switching transistor M2 may be inserted between the transistors M12 and M13, in which case the drain and gate of the transistor M11 are connected to the node 53, the source of the transistor M11 is connected to the drain and gate of the transistor M12, the source of the transistor M12 is connected to the drain of the switching transistor M2, the source of the switching transistor M2 is connected to the drain and gate of the transistor M13, and the source of the transistor M13 is connected to ground.

[0063] <<Third Example>> A third embodiment will now be described. In the first and second embodiments, it was assumed that the number of series-connected voltage generating elements provided in the voltage generating circuit 110 (110A or 110B) was three, but the number of series-connected voltage generating elements provided in the voltage generating circuit 110 (110A or 110B) may be two, or may be four or more.

[0064] Furthermore, the voltage generation circuit 110 (110A or 110B) may have only one voltage generation element. When the voltage generation circuit 110A of FIG. 6 is modified to have only one voltage generation element, the transistors M12 and M13 are deleted from the voltage generation circuit 110A, and the source of the transistor M11 is directly connected to ground. When the voltage generation circuit 110B of FIG. 9 is modified to have only one voltage generation element, the transistors M12 and M13 are deleted from the voltage generation circuit 110B, and the source of the transistor M11 is connected to the drain of the switching transistor M2, and the source of the switching transistor M2 is connected to ground (in this case, as described in the second embodiment, the positions of the transistor M11 and the switching transistor M2 may be reversed).

[0065] <<Fourth Example>> A fourth embodiment will now be described. The voltage generating element described above may be a diode formed by a semiconductor PN junction instead of a diode-connected MOSFET. For example, if the voltage generating element in the second embodiment is formed by a diode, diodes D11 to D13 are provided in the voltage generating circuit 110B of FIG. 9 instead of the transistors M11 to M13, as shown in FIG. 11. In this case, a series circuit of diodes D11 to D13 and a switching transistor M2 is provided between node 53 and ground. Specifically, in the configuration of FIG. 11, the anode of diode D11 is connected to node 53, the cathode of diode D11 is connected to the anode of diode D12, the cathode of diode D12 is connected to the anode of diode D13, the cathode of diode D13 is connected to the drain of switching transistor M2, and the source of switching transistor M2 is connected to ground. In the configuration of FIG. 11, the above-mentioned voltage 3Vf corresponds to the sum of the forward voltages of diodes D11 to D13.

[0066] As long as the series circuit of the diodes D11 to D13 and the switching transistor M2 is inserted between the gate 53 and ground, the insertion position of the switching transistor M2 can be changed as desired. The transistors M11 to M13 in the first embodiment (see FIG. 6) can also be replaced with diodes. The number of series-connected diodes serving as voltage generating elements can be any number as long as it is one or more.

[0067] The voltage generation circuit 110 according to the present disclosure has one or more voltage generation elements, and can generate a gate voltage of the adjustment transistor M1 based on a voltage generated by the one or more voltage generation elements when a current based on a power supply voltage VDD is supplied to the one or more voltage generation elements. Here, the current based on the power supply voltage VDD is the drain current of the MOSFET if each voltage generation element is a diode-connected MOSFET, or the forward current of the diode if each voltage generation element is a diode. The voltage generated by the one or more voltage generation elements when a current based on the power supply voltage VDD is supplied to the one or more voltage generation elements is the gate-source voltage of the MOSFET if each voltage generation element is a diode-connected MOSFET, or the forward voltage of the diode if each voltage generation element is a diode.

[0068] <<Fifth Example>> A fifth embodiment will now be described. In any of the embodiments described above or below, the positions of the transistor MH and the adjustment transistor M1 may be reversed. That is, as shown in FIG. 12, the drain of the adjustment transistor M1 may be connected to the power supply application terminal 51, the source of the adjustment transistor M1 may be connected to the source of the transistor MH, and the drain of the transistor MH may be connected to the first terminal of the current-limiting resistor R1. The second terminal of the current-limiting resistor R1 is connected to the gate of the output transistor M0 and the drain of the transistor ML, as described above.

[0069] <<Sixth Example>> A sixth embodiment will be described. 213 shows the overall system configuration when the semiconductor device 1 functions as a master device for communication by C. When the semiconductor device 1 functions as a master device, the semiconductor device 1 is provided with two signal output circuits 10, namely, signal output circuits 10[1] and 10[2], and with two terminals OUT corresponding to the signal output circuits 10[1] and 10[2], namely, terminals OUT[1] and OUT[2]. The signal line SL connected to the terminal OUT[1] is referred to as the signal line SL[1], and the signal line SL connected to the terminal OUT[2] is referred to as the signal line SL[2]. The signal Sout on the signal line SL[1] is referred to as the signal Sout[1], and the signal Sout on the signal line SL[2] is referred to as the signal Sout[2]. The signal line SL[1] is connected to a pull-up resistor R PU [1] is connected to the application terminal of the power supply voltage VDD2, and the signal line SL[2] is connected to the pull-up resistor R PU [2] is connected to the power supply voltage VDD2 application terminal.

[0070] 13 includes a semiconductor device 1 and a plurality of slave devices 2. Each slave device 2 is connected to signal lines SL[1] and SL[2], and communication between the semiconductor device 1 and I is performed via the signal lines SL[1] and SL[2]. 2 C. Signal lines SL[1] and SL[2] are I 2 Form a communication bus in C.

[0071] Signal Sout[1] is I 2 The signal Sout[2] is a clock signal for communication between I and C, and is always output from the signal output circuit 10[1] (therefore, the terminal OUT[1] is an output terminal). 2 C communication. The data signal is output from the semiconductor device 1 as the master device, or from one of the slave devices 2. When the semiconductor device 1 transmits a data signal, the data signal is output from the signal output circuit 10[2]. When a data signal is transmitted from one of the slave devices 2, the data signal is received by a receiving circuit (not shown) provided in the semiconductor device 1 and connected to the terminal OUT[2] (therefore, the terminal OUT[2] functions as an input / output terminal).

[0072] The semiconductor device 1 may function as a slave device. In this case, the signal output circuit 10 in the semiconductor device 1 transmits (outputs) a data signal to the master device when the semiconductor device 1 is on the transmitting side.

[0073] The communication performed in the system including the semiconductor device 1 is I 2 Although communication according to C has been exemplified, communication performed in the system may be communication according to other standards (for example, communication according to SPI).

[0074] <<Seventh Example>> A seventh embodiment will now be described.

[0075] The semiconductor device 1 includes a functional circuit in addition to the signal output circuit 10. The functional circuit may be, for example, an AD conversion circuit that converts an analog signal input to the semiconductor device 1 into a digital signal, in which case the semiconductor device 1 functions as an AD conversion device. The functional circuit is not limited to an AD conversion circuit and may be any circuit; therefore, the semiconductor device 1 may be a DA conversion device, a power supply control device (DC / DC converter), a PMIC (Power Management IC), a motor driver, an LED driver, or the like.

[0076] With respect to any signal or voltage, the relationship between the high level and the low level thereof may be reversed without prejudice to the above-mentioned gist.

[0077] The channel types of the FETs (field effect transistors) shown in the above embodiments are merely examples, and the channel type of any FET may be changed between P-channel and N-channel types without departing from the spirit of the above.

[0078] Any of the transistors described above may be any type of transistor, provided that no disadvantages arise. For example, any of the transistors described above as MOSFETs may be replaced with junction field effect transistors (FETs), insulated gate bipolar transistors (IGBTs), or bipolar transistors, provided that no disadvantages arise. Any of the transistors has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor that is not an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.

[0079] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0080] <<Additional Notes>> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0081] A signal output circuit (10) according to one aspect of the present disclosure comprises an output transistor (M0) configured as an N-channel MOSFET having a drain connected to an output terminal (OUT) and a source connected to ground, and a drive circuit (100) configured to control the output transistor to be on or off by supplying an on-current (Ion) based on a power supply voltage (VDD) to the gate of the output transistor or by drawing an off-current (Ioff) from the gate of the output transistor, and is an open-drain signal output circuit configured to generate an output signal (Sout) at the output terminal according to the state of the output transistor, and the drive circuit has an adjustment transistor (M1) configured as an N-channel depletion-type MOSFET, a current-limiting resistor (R1) provided between the adjustment transistor and the gate of the output transistor, and a voltage generation circuit (110A, 110B) configured to generate a gate voltage of the adjustment transistor, and is configured (first configuration) to supply the on-current to the gate of the output transistor through the adjustment transistor and the current-limiting resistor.

[0082] This allows the voltage applied to the current limiting resistor to be limited (adjusted) to a voltage that depends on the gate voltage and gate threshold voltage of the adjustment transistor, even when the power supply voltage is relatively high. As a result, the on-current is limited to a current that corresponds to the limited voltage, so that the power supply voltage dependency of the level change time of the output signal when the output transistor switches from off to on can be kept low.

[0083] In the signal output circuit according to the first configuration, the drive circuit may further include a high-side switch (MH) connected in series with the adjustment transistor between the application terminal (51) of the power supply voltage and the current limiting resistor, and a low-side switch (ML) provided between the current limiting resistor and ground, and the drive circuit may be configured to transition the output transistor from off to on by switching the high-side switch from off to on and the low-side switch from on to off, and to transition the output transistor from on to off by switching the high-side switch from on to off and the low-side switch from off to on (second configuration).

[0084] In the signal output circuit according to the first or second configuration, the voltage generating circuit (110A, 110B) may have one or more voltage generating elements (M11, M12, M13, D11, D12, D13) and may be configured (third configuration) to be capable of generating a gate voltage of the adjustment transistor based on a voltage generated by the one or more voltage generating elements when a current based on the power supply voltage is supplied to the one or more voltage generating elements.

[0085] In the signal output circuit according to the third configuration, the voltage generating circuit (110A, 110B) may have, in addition to the one or more voltage generating elements provided between a specific node (53) and ground, a resistor (R2) provided between the application terminal of the power supply voltage and the specific node, and may be configured to generate a gate voltage of the adjustment transistor at the specific node (fourth configuration).

[0086] In the signal output circuit according to the fourth configuration, the voltage generating circuit (110B) may have a series circuit of the one or more voltage generating elements and a mode switching switch (M2), the series circuit being provided between the specific node and ground, the voltage generating circuit operating in either a first mode or a second mode based on a given switching signal (Ssw), and the mode switching switch being on in the first mode and off in the second mode (fifth configuration).

[0087] In the signal output circuit according to any of the third to fifth configurations, each voltage generating element may be a MOSFET (M11, M12, M13) or a diode (D11, D12, D13) having a drain and gate shorted to each other (sixth configuration).

[0088] The signal output circuit according to any one of the first to sixth configurations may be configured (seventh configuration) to output the output signal to a signal line (SL) of a communication bus connected to the output terminal.

[0089] The signal output circuit according to any one of the first to seventh configurations may have a configuration (eighth configuration) in which a series circuit of a capacitor (C0) and a resistor (R0) is provided between the gate of the output transistor and the output terminal. [Explanation of symbols]

[0090] 1. Semiconductor device 10 Signal output circuit 20 Control circuit 51, 52 Power supply end 100 Drive circuit M0 output transistor C0 capacitor R0 resistance R PU pull-up resistor OUT output terminal Sin input signal Sout output signal SL signal line VDD, VDD2 power supply voltage V0 Gate voltage Ion On current Ioff Off current VDD IN power terminal GND Ground terminal 110A, 110B voltage generation circuit M1 Adjustment transistor MH, ML, M11, M12, M13 transistors R1 Current limiting resistor R2 resistance 53 nodes M2 switching transistor Ssw switching signal D11, D12, D13 diodes 2 Slave devices 10[1], 10[2] Signal output circuit OUT[1], OUT[2] terminals Sout[1], Sout[2] signal SL[1], SL[2] signal line R PL [1], R PL [2] Pull-up resistor 910 Signal output circuit 911, 912 Transistors 913 Current limiting resistor

Claims

1. An open-drain signal output circuit comprising: an output transistor configured as an N-channel MOSFET having a drain connected to an output terminal and a source connected to ground; and a drive circuit configured to control the output transistor to be on or off by supplying an on-current based on a power supply voltage to the gate of the output transistor or by drawing an off-current from the gate of the output transistor, wherein the open-drain signal output circuit is configured to generate an output signal at the output terminal according to the state of the output transistor, The drive circuit has an adjustment transistor configured by an N-channel depletion type MOSFET, a current limiting resistor provided between the adjustment transistor and the gate of the output transistor, and a voltage generation circuit configured to generate a gate voltage of the adjustment transistor, and supplies the on-current to the gate of the output transistor through the adjustment transistor and the current limiting resistor. , signal output circuit.

2. the drive circuit further includes a high-side switch connected in series with the adjustment transistor between an application terminal of the power supply voltage and the current limiting resistor, and a low-side switch provided between the current limiting resistor and ground; The drive circuit switches the high-side switch from off to on and the low-side switch from on to off to transition the output transistor from off to on, and switches the high-side switch from on to off and the low-side switch from off to on to transition the output transistor from on to off.

2. The signal output circuit according to claim 1.

3. The voltage generating circuit has one or more voltage generating elements, and is configured to be able to generate a gate voltage of the adjustment transistor based on a voltage generated by the one or more voltage generating elements when a current based on the power supply voltage is supplied to the one or more voltage generating elements.

3. The signal output circuit according to claim 1 or 2.

4. The voltage generating circuit has, in addition to the one or more voltage generating elements provided between the specific node and ground, a resistor provided between the application terminal of the power supply voltage and the specific node, and generates a gate voltage of the adjustment transistor at the specific node.

4. The signal output circuit according to claim 3.

5. the voltage generating circuit includes a series circuit of the one or more voltage generating elements and a mode switching switch; the series circuit is provided between the specific node and ground, the voltage generating circuit operates in either a first mode or a second mode based on a given switching signal; The mode changeover switch is on in the first mode and off in the second mode.

5. The signal output circuit according to claim 4.

6. Each voltage generating element is a MOSFET or a diode with its drain and gate shorted together.

4. The signal output circuit according to claim 3.

7. The output signal is output to a signal line of a communication bus connected to the output terminal.

3. The signal output circuit according to claim 1 or 2.

8. A series circuit of a capacitor and a resistor is provided between the gate of the output transistor and the output terminal.

3. The signal output circuit according to claim 1 or 2.

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