Semiconductor storage device

Abstract

To provide a semiconductor storage device that improves interface performance.SOLUTION: A semiconductor storage device includes: a memory cell; a bit line electrically connected to the memory cell; a sense amplifier circuit electrically connected to the bit line; a first data wiring electrically connected to the sense amplifier circuit; a data latch circuit electrically connected to the first data wiring; and second and third data wirings that are electrically connected to the data latch circuit and can transfer data signals that are reversed from each other. The data latch circuit includes a first node that stores data and a second node that stores data reversed from the data. The second data wiring is electrically connected to the first node. The first and third data wirings are electrically connected to the second node.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present embodiment relates to a semiconductor memory device. [Background technology]

[0002] 2. Description of the Related Art A semiconductor memory device is known that includes memory cells, bit lines electrically connected to the memory cells, and sense amplifier circuits electrically connected to the bit lines. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-176309 Summary of the Invention [Problem to be solved by the invention]

[0004] To improve the interface performance of a semiconductor memory device. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes memory cells, bit lines electrically connected to the memory cells, sense amplifier circuits electrically connected to the bit lines, first data wiring electrically connected to the sense amplifier circuit, a data latch circuit electrically connected to the first data wiring, and second and third data wiring electrically connected to the data latch circuit and capable of transferring mutually inverted data signals. The data latch circuit includes a first node that holds data and a second node that holds inverted data of the data. The second data wiring is electrically connected to the first node. The first data wiring and the third data wiring are electrically connected to the second node. [Brief explanation of the drawings]

[0006] [Figure 1]1 is a schematic block diagram showing the configuration of a memory system 10 according to a first embodiment. [Figure 2] FIG. 2 is a schematic block diagram showing the configuration of a portion of a memory die MD. [Figure 3] FIG. 2 is a schematic circuit diagram showing the configuration of a portion of a memory die MD. [Figure 4] 1 is a schematic perspective view showing the configuration of a portion of a memory die MD. [Figure 5] FIG. 2 is a schematic block diagram showing the configuration of a sense amplifier module SAM. [Figure 6] FIG. 2 is a schematic block diagram showing the configuration of a cache memory CM. [Figure 7] FIG. 2 is a schematic circuit diagram showing the configuration of a latch circuit XDL10. [Figure 8] 10 is a timing chart for explaining the operation of the latch circuit XDL10 at the time of data input. [Figure 9] 10 is a timing chart for explaining the operation of the latch circuit XDL10 at the time of data input. [Figure 10] 10 is a timing chart for explaining the operation of the latch circuit XDL10 when data is output. [Figure 11] 10 is a timing chart for explaining the operation of the latch circuit XDL10 when data is output. [Figure 12] FIG. 10 is a schematic circuit diagram showing the configuration of a latch circuit according to a comparative example. [Figure 13] 10 is a timing chart for explaining the operation of a latch circuit according to a comparative example. [Figure 14] 10 is a timing chart for explaining the operation of a latch circuit according to a comparative example. [Figure 15] FIG. 10 is a schematic circuit diagram showing the configuration of a latch circuit XDL20 according to a second embodiment. [Figure 16] FIG. 10 is a schematic circuit diagram showing the connection relationship of a multiplexer MUX according to a third embodiment. [Figure 17]FIG. 2 is a schematic circuit diagram showing the configuration of a multiplexer MUX. [Figure 18] 10 is a timing chart for explaining the operation of the multiplexer MUX when data is output. [Figure 19] FIG. 10 is a schematic circuit diagram showing the configuration of a multiplexer MUX2 according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiment is merely an example and is not intended to limit the present invention.

[0008] Furthermore, in this specification, the term "semiconductor memory device" may refer to a memory die, or may refer to a memory system including a controller die, such as a memory chip, a memory card, or an SSD. Furthermore, it may refer to a configuration including a host computer, such as a smartphone, a tablet terminal, or a personal computer.

[0009] Furthermore, in this specification, when a first component is said to be "electrically connected" to a second component, the first component may be directly connected to the second component, or the first component may be connected to the second component via wiring, a semiconductor member, a transistor, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in the OFF state.

[0010] Furthermore, in this specification, when it is said that a first configuration is "connected between" a second configuration and a third configuration, it may mean that the first configuration, the second configuration, and the third configuration are connected in series, and that the first configuration is provided in the current path of the second configuration and the third configuration.

[0011] Furthermore, in this specification, when it is said that a circuit or the like "conducts" two wirings or the like, it may mean, for example, that the circuit or the like includes a transistor or the like, that the transistor or the like is provided in the current path between the two wirings, and that the transistor or the like is in the ON state.

[0012] [First embodiment] [Memory System 10] FIG. 1 is a schematic block diagram showing the configuration of a memory system 10 according to the first embodiment.

[0013] The memory system 10 performs operations such as reading, writing, and erasing user data in response to signals transmitted from a host computer 20. The memory system 10 is, for example, a memory chip, a memory card, an SSD, or other system capable of storing user data. The memory system 10 includes multiple memory dies MD and a controller die CD. The memory die MD stores user data. The controller die CD is connected to the multiple memory dies MD and the host computer 20. The controller die CD includes, for example, a processor, RAM, etc. The controller die CD performs processes such as conversion between logical and physical addresses, bit error detection / correction, garbage collection (compaction), and wear leveling. The functions of each part of the controller die CD can be realized by dedicated hardware, a processor executing a program, or a combination of these.

[0014] [Memory die MD configuration] Fig. 2 is a schematic block diagram showing the configuration of a memory die MD according to the first embodiment, Fig. 3 is a schematic circuit diagram showing the configuration of a portion of the memory die MD, and Fig. 4 is a schematic perspective view showing the configuration of a portion of the memory die MD.

[0015] FIG. 2 illustrates a plurality of control terminals, etc. These control terminals may be represented as control terminals corresponding to high-active signals (positive logic signals). Furthermore, the control terminals may be represented as control terminals corresponding to low-active signals (negative logic signals). Furthermore, the control terminals may be represented as control terminals corresponding to both high-active signals and low-active signals. In FIG. 2, the reference numerals of control terminals corresponding to low-active signals include an overline. In this specification, the reference numerals of control terminals corresponding to low-active signals include a slash (" / "). Note that the illustration in FIG. 2 is an example, and specific aspects can be adjusted as appropriate. For example, it is possible to make some or all of the high-active signals low-active signals, or some or all of the low-active signals high-active signals.

[0016] 2, the memory die MD includes memory cell arrays MCA0 and MCA1 that store user data, and a peripheral circuit PC connected to the memory cell arrays MCA0 and MCA1. In the following description, the memory cell arrays MCA0 and MCA1 may be referred to as the memory cell array MCA.

[0017] [Configuration of memory cell array MCA] As shown in FIG. 3, the memory cell array MCA includes a plurality of memory blocks BLK. Each of the memory blocks BLK includes a plurality of string units SU. Each of the string units SU includes a plurality of memory strings MS. One end of each of the memory strings MS is connected to a peripheral circuit PC via a bit line BL. The other end of each of the memory strings MS is connected to the peripheral circuit PC via a common source line SL.

[0018] The memory string MS includes a drain-side select transistor STD, a plurality of memory cells MC (memory transistors), and a source-side select transistor STS. The drain-side select transistor STD, the plurality of memory cells MC, and the source-side select transistor STS are connected in series between a bit line BL and a source line SL. Hereinafter, the drain-side select transistor STD and the source-side select transistor STS may be simply referred to as select transistors (STD, STS).

[0019] The memory cells MC are field-effect transistors. Each memory cell MC includes a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cells MC varies depending on the amount of charge in the charge storage film. Each memory cell MC stores one or more bits of data. A word line WL is connected to the gate electrodes of the memory cells MC corresponding to one memory string MS. Each of these word lines WL is commonly connected to all memory strings MS in one memory block BLK.

[0020] The select transistors (STD, STS) are field-effect transistors. The select transistors (STD, STS) include a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate electrodes of the select transistors (STD, STS) are connected to select gate lines (SGD, SGS), respectively. One drain-side select gate line SGD is commonly connected to all memory strings MS in one string unit SU. One source-side select gate line SGS is commonly connected to all memory strings MS in one memory block BLK.

[0021] The memory cell array MCA is provided above a semiconductor substrate 100, as shown in Fig. 4, for example. In the example of Fig. 4, a plurality of transistors Tr constituting a peripheral circuit PC are provided between the semiconductor substrate 100 and the memory cell array MCA. The transistor Tr includes a plurality of electrodes gc. The plurality of electrodes gc are connected to the wiring layer D0, etc., via contacts CS.

[0022] The memory cell array MCA includes a plurality of memory blocks BLK arranged in the Y direction. An inter-block insulating layer ST made of silicon oxide (SiO 2 ) or the like is provided between two memory blocks BLK adjacent to each other in the Y direction.

[0023] As shown in FIG. 4, the memory block BLK includes a plurality of conductive layers 110 arranged in the Z direction, a plurality of semiconductor pillars 120 extending in the Z direction, and a plurality of gate insulating films 130 respectively provided between the plurality of conductive layers 110 and the plurality of semiconductor pillars 120.

[0024] The conductive layer 110 is a substantially plate-shaped conductive layer extending in the X direction. The conductive layer 110 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive layer 110 may also include polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 such as silicon oxide (SiO2) is provided between the multiple conductive layers 110 arranged in the Z direction.

[0025] Furthermore, one or more conductive layers 110 located in the lowest layer among the plurality of conductive layers 110 function as source-side select gate lines SGS (FIG. 3) and gate electrodes of the plurality of source-side select transistors STS connected thereto. These plurality of conductive layers 110 are electrically independent for each memory block BLK.

[0026] Furthermore, the plurality of conductive layers 110 positioned above the word lines WL function as gate electrodes of the word lines WL (FIG. 3) and the plurality of memory cells MC (FIG. 3) connected thereto. These conductive layers 110 are electrically independent for each memory block BLK.

[0027] Furthermore, one or more conductive layers 110 located above the drain-side select gate line SGD function as gate electrodes of the drain-side select transistors STD (FIG. 3) connected to the drain-side select gate line SGD. Each of these conductive layers 110 is electrically independent for each string unit SU.

[0028] A conductive layer 112 is provided below the conductive layer 110. The conductive layer 112 may include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 made of silicon oxide (SiO2) or the like is provided between the conductive layer 112 and the conductive layer 110. The conductive layer 112 may include a semiconductor layer 113 and a conductive layer 114 connected to the lower surface of the semiconductor layer 113. The semiconductor layer 113 may include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). The conductive layer 114 may include, for example, a metal such as tungsten (W), a conductive layer such as tungsten silicide, or another conductive layer.

[0029] The conductive layer 112 functions as a source line SL (FIG. 3). The source line SL is provided in common to all memory blocks BLK included in the memory cell array MCA, for example.

[0030] The semiconductor pillars 120 are arranged in a predetermined pattern in the X and Y directions, as shown in FIG. 4, for example. The semiconductor pillars 120 function as channel regions of multiple memory cells MC and select transistors (STD, STS) included in one memory string MS (FIG. 3). The semiconductor pillars 120 are, for example, semiconductor layers made of polycrystalline silicon (Si). As shown in FIG. 4, for example, the semiconductor pillars 120 have a substantially cylindrical shape, and an insulating layer 125 made of silicon oxide or the like is provided in their central portions. The outer peripheries of the semiconductor pillars 120 are surrounded by the conductive layers 110 and face the conductive layers 110.

[0031] An impurity region 121 containing N-type impurities such as phosphorus (P) is provided at the upper end of the semiconductor pillar 120. The impurity region 121 is connected to the bit line BL via a contact Ch and a contact Cb.

[0032] The gate insulating film 130 has a substantially cylindrical shape that covers the outer circumferential surface of the semiconductor pillar 120. The gate insulating film 130 includes, for example, a tunnel insulating film, a charge storage film, and a block insulating film stacked between the semiconductor pillar 120 and the conductive layer 110. The tunnel insulating film and the block insulating film are, for example, insulating films made of silicon oxide (SiO2) or the like. The charge storage film is, for example, silicon nitride (Si3N4) or the like, and is a film that can store electric charges. The tunnel insulating film, the charge storage film, and the block insulating film are, for example, substantially cylindrical, and extend in the Z direction along the outer circumferential surface of the semiconductor pillar 120 excluding the contact portion between the semiconductor pillar 120 and the conductive layer 112.

[0033] The gate insulating film 130 may include a floating gate made of, for example, polycrystalline silicon containing N-type or P-type impurities.

[0034] A plurality of contacts CC are provided at the ends of the plurality of conductive layers 110 in the X direction. The plurality of conductive layers 110 are connected to the peripheral circuit PC (FIG. 2) via these contacts CC. As shown in FIG. 4, these contacts CC extend in the Z direction and are connected to the conductive layers 110 at their lower ends. The contacts CC may include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0035] [Peripheral circuit PC configuration] As shown in FIG. 2, the peripheral circuit PC includes row decoders RD0 and RD1 connected to memory cell arrays MCA0 and MCA1, respectively, sense amplifier modules SAM0 and SAM1, and cache memories CM0 and CM1 (data registers). The peripheral circuit PC also includes a voltage generator VG and a sequencer SQC. The peripheral circuit PC also includes an input / output control circuit I / O, a logic circuit CTR, an address register ADR, a command register CMR, and a status register STR. In the following description, the row decoders RD0 and RD1 may be referred to as the row decoder RD, the sense amplifier modules SAM0 and SAM1 as the sense amplifier module SAM, and the cache memories CM0 and CM1 as the cache memory CM.

[0036] [Configuration of row decoder RD] The row decoder RD includes an address decoder that decodes the address data Add, and a block selection circuit and a voltage selection circuit that transfer an operating voltage to the memory cell array MCA in response to an output signal from the address decoder.

[0037] The address decoder sequentially refers to the row addresses RA of the address register ADR in accordance with a control signal from the sequencer SQC, decodes the row addresses RA, and turns on a predetermined block selection transistor and a voltage selection transistor corresponding to the row address RA, while turning off other block selection transistors and voltage selection transistors.

[0038] [Configuration of the sense amplifier module SAM] 5 is a schematic block diagram showing the configuration of the sense amplifier module SAM. The sense amplifier module SAM includes a plurality of sense amplifier units SAU, as shown in FIG. 5, for example. The plurality of sense amplifier units SAU correspond to a plurality of bit lines BL, respectively. Each of the sense amplifier units SAU includes a sense amplifier SA, a wiring LBUS, and latch circuits SDL, DL0 to DLn (n is a natural number). Each of the plurality of wirings LBUS is connected to one wiring DBUS via a switch transistor DSW.

[0039] The sense amplifier SA includes, for example, sense circuits corresponding to the plurality of bit lines BL, respectively. The sense circuits detect the voltage or current of the bit lines BL and output data indicating the detection results. The latch circuits SDL, DL0 to DLn (n is a natural number) hold the data output from the sense circuits, user data Dat input from the cache memory CM, etc.

[0040] The switch transistor DSW is, for example, an NMOS transistor. The switch transistor DSW is connected between the wiring LBUS and the wiring DBUS. The gate electrode of the switch transistor DSW is connected to the sequencer SQC via the signal line DBS (FIG. 5).

[0041] 5, the above-mentioned signal lines STB, HLL, XXL, BLX, BLC, and BLS are each commonly connected to all the sense amplifier units SAU included in the sense amplifier module SAM. DD The voltage supply line and voltage V SRCThe voltage supply lines to which these signals are supplied are each connected in common to all the sense amplifier units SAU included in the sense amplifier module SAM. Also, the signal lines STI and STL of the latch circuit SDL are each connected in common to all the sense amplifier units SAU included in the sense amplifier module SAM. Similarly, the signal lines TI0 to TIn and TL0 to TLn corresponding to the signal lines STI and STL in the latch circuits DL0 to DLn are each connected in common to all the sense amplifier units SAU included in the sense amplifier module SAM. Meanwhile, a plurality of the above-mentioned signal lines DBS are provided corresponding to all the sense amplifier units SAU included in the sense amplifier module SAM.

[0042] [Cache memory CM configuration] 6 is a schematic block diagram showing the configuration of the cache memory CM. The cache memory CM includes, for example, a plurality of latch circuit rows XDL_COL, as shown in FIG.

[0043] The latch circuit column XDL_COL includes a plurality of latch circuits XDL. The plurality of latch circuits XDL included in one latch circuit column XDL_COL are connected to one wiring DBUS.

[0044] Each latch circuit XDL is connected to a pair of wires XBUS and XBUSn. Although not shown in Fig. 6, a multiplexer is connected between the wires XBUS and XBUSn and the bus wire IOBUS (Fig. 2).

[0045] The plurality of latch circuits XDL included in the cache memory CM are provided, for example, corresponding to the respective bit lines BL. The plurality of latch circuits XDL may be provided in the same number as the bit lines BL, for example.

[0046] The user data Dat contained in the latch circuit XDL is sequentially transferred to the sense amplifier module SAM (FIG. 5) via the wiring DBUS during a write operation, which will be described later. Also, the user data Dat contained in the latch circuit in the sense amplifier module SAM is sequentially transferred to the latch circuit XDL (FIG. 6) during a read operation, which will be described later.

[0047] Furthermore, the user data Dat contained in the latch circuit XDL is transferred sequentially to the input / output control circuit I / O (FIG. 2) via the wirings XBUS and XBUSn at the time of data out (to be described later). Furthermore, at the time of data in (to be described later), the user data Dat is transferred from the input / output control circuit I / O to the latch circuit XDL (FIG. 6) via the wirings XBUS and XBUSn.

[0048] The specific configuration of the latch circuit XDL will be described later.

[0049] A column decoder (not shown) is connected to the cache memory CM. The column decoder decodes a column address CA held in an address register ADR (FIG. 2) and selects a latch circuit XDL corresponding to the column address CA.

[0050] [Configuration of voltage generation circuit VG] The voltage generating circuit VG (FIG. 2) includes, for example, a step-down circuit such as a regulator and a step-up circuit such as a charge pump circuit. These step-down circuit and step-up circuit are connected to a power supply terminal V CC and power terminal V PP , and a ground terminal V to which the ground voltage is supplied. SS It is connected to the power supply terminal V CC , power supply terminal V PP , and ground terminal V SS Each of these is realized by, for example, a pad electrode.

[0051] The voltage generation circuit VG generates a plurality of operating voltages to be applied to the bit lines BL, source lines SL, word lines WL, and select gate lines (SGD, SGS) during read, write, and erase operations on the memory cell array MCA in accordance with control signals from the sequencer SQC, and outputs these voltages simultaneously to a plurality of voltage supply lines. The operating voltages output from the voltage supply lines are adjusted appropriately in accordance with the control signals from the sequencer SQC.

[0052] [Configuration of the SQC sequencer] The sequencer SQC outputs internal control signals to the row decoders RD0 and RD1, the sense amplifier modules SAM0 and SAM1, and the voltage generation circuit VG in accordance with the command data Cmd stored in the command register CMR. The sequencer SQC also outputs status data Stt, which indicates the internal operating state of the memory die MD, to the status register STR as appropriate.

[0053] [Address register ADR configuration] 2, the address register ADR is connected to the input / output control circuit I / O and holds address data Add input from the input / output control circuit I / O. The address register ADR includes, for example, a plurality of 8-bit register strings. When an internal operation such as a read operation, a write operation, or an erase operation is executed, the register string holds a plurality of address data Add including address data Add corresponding to the operation currently being executed and address data Add corresponding to the operation to be executed next.

[0054] The address data Add includes, for example, a column address CA and a row address RA. The row address RA includes, for example, a block address that identifies a memory block BLK (FIG. 3), a page address that identifies a string unit SU and a word line WL, a plane address that identifies a memory cell array MCA (plane), and a chip address that identifies a memory die MD.

[0055] [Configuration of command register CMR] The command register CMR is connected to the input / output control circuit I / O and holds command data Cmd input from the input / output control circuit I / O. The command register CMR has, for example, at least one set of an 8-bit register string. When the command data Cmd is held in the command register CMR, a control signal is input to the sequencer SQC.

[0056] [Status register STR configuration] The status register STR is connected to the input / output control circuit I / O and holds status data Stt to be output to the input / output control circuit I / O. The status register STR includes, for example, a plurality of 8-bit register strings.

[0057] [Configuration of input / output control circuit I / O] The input / output control circuit I / O (FIG. 2) includes data signal input / output terminals DQ0 to DQ7, data strobe signal input / output terminals DQS and / DQS, a shift register, and a buffer circuit. Each circuit in the input / output control circuit I / O is connected to a power supply terminal V CCQ and ground terminal V SS It is connected to the power supply terminal V CCQ is realized by, for example, a pad electrode.

[0058] Each of the data signal input / output terminals DQ0 to DQ7 and the data strobe signal input / output terminals DQS, / DQS is realized by, for example, a pad electrode. Data input via the data signal input / output terminals DQ0 to DQ7 is input from a buffer circuit to the cache memory CM, address register ADR, and command register CMR in response to an internal control signal from the logic circuit CTR. Data output via the data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM and status register STR to the buffer circuit in response to an internal control signal from the logic circuit CTR. The functions of the data strobe signal input / output terminals DQS, / DQS will be described later.

[0059] [Configuration of logic circuit CTR] The logic circuit CTR (Fig. 2) includes a plurality of external control terminals / CE, CLE, ALE, / WE, / RE, RE, and / WP, and a logic circuit connected to these plurality of external control terminals / CE, CLE, ALE, / WE, / RE, RE, and / WP. The logic circuit CTR receives external control signals from the controller die CD via the external control terminals / CE, CLE, ALE, / WE, / RE, RE, and / WP, and outputs internal control signals to the input / output control circuit I / O in response to these signals.

[0060] [Memory die MD operation] Next, the operation of the memory die MD will be described.

[0061] The memory die MD is configured to be able to perform a read operation. The read operation is an operation in which the sense amplifier module SAM (Fig. 2) reads user data Dat from the memory cell array MCA, holds the read user data Dat in a latch circuit in the sense amplifier module SAM, and transfers this user data Dat to a latch circuit XDL (Fig. 6) in the cache memory CM. In the read operation, the user data Dat read from the memory cell array MCA is transferred to the latch circuit XDL via the bit line BL, the sense amplifier module SAM, and the wiring DBUS.

[0062] The memory die MD is also configured to be able to execute data out. Data out is an operation of outputting user data Dat contained in the latch circuit XDL (FIG. 6) in the cache memory CM to the controller die CD (FIG. 1). In data out, the user data Dat contained in the latch circuit XDL is output to the controller die CD via the wiring XBUS, XBUSn, the bus wiring IOBUS, and the input / output control circuit I / O.

[0063] The memory die MD is also configured to be able to perform a write operation. The write operation is an operation in which user data Dat input from the controller die CD is held in a latch circuit in the sense amplifier module SAM and this user data Dat is written to memory cells MC in the memory cell array MCA. In the write operation, a program operation for storing electrons in the charge storage film of the memory cell MC and a verify operation for determining whether the threshold voltage of the memory cell MC has increased to a target value are performed once or multiple times.

[0064] The memory die MD is also configured to be able to execute data-in. Data-in is an operation of inputting user data Dat input from the controller die CD to the latch circuit XDL (FIG. 6). In data-in, the user data Dat is input to the latch circuit XDL via the input / output control circuit I / O, the bus wiring IOBUS, and the wiring XBUS, XBUSn, etc.

[0065] The memory die MD is also configured to be able to perform an erase operation. The erase operation is an operation for erasing data written in memory cells MC in the memory cell array MCA. In the erase operation, an erase voltage supply operation for extracting electrons from the charge storage film of the memory cells MC and a verify operation for determining whether the threshold voltage of the memory cells MC has decreased to a target value are performed once or multiple times.

[0066] [Latch circuit XDL10] Next, a latch circuit XDL10 will be described as an example of the configuration of the latch circuit XDL. Fig. 7 is a schematic circuit diagram showing the configuration of the latch circuit XDL10.

[0067] The latch circuit XDL10 is connected to lines XBUS and XBUSn as input / output wiring on the input / output control circuit I / O side, and to line DBUS as input / output wiring on the sense amplifier module SAM side. The lines XBUS and XBUSn are signal lines that transmit complementary signals. For example, the lines XBUS and XBUSn transmit signals that are inverted to each other.

[0068] The latch circuit XDL10 (FIG. 7) includes transistors TN11 to TN15, transistors TP11 to TP13, a node LAT, and a node INV. The transistors TN11 to TN15 are N-channel MOS transistors. The transistors TP11 to TP13 are P-channel MOS transistors.

[0069] The transistors TP11 and TN11 are connected in series to a current path between a power supply voltage node VDD and a ground voltage node VSS via a node LAT. The gate electrodes of the transistors TP11 and TN11 are connected to a node INV. The transistors TP11 and TN11 function as an inverter circuit.

[0070] The power supply voltage node VDD is connected to the power supply voltage, e.g., voltage V D The ground voltage node VSS is supplied with a voltage V D A smaller voltage, e.g., voltage V S is supplied.

[0071] The transistors TP12 and TN12 are connected in series to a current path between a power supply voltage node VDD and a ground voltage node VSS via a node INV. The gate electrodes of the transistors TP12 and TN12 are connected to a node LAT. The transistors TP12 and TN12 function as an inverter circuit.

[0072] Hereinafter, the portion including the transistors TP11, TN11, TP12, and TN12 may be referred to as the circuit CR1. In the circuit CR1, two inverter circuits are cross-connected.

[0073] The transistor TN13 is connected between the line XBUS and the node LAT. The transistor TN14 is connected between the line XBUSn and the node INV. The gate electrodes of the transistors TN13 and TN14 are connected to the signal supply line XTL. The transistors TN13 and TN14 function as a switch circuit that turns ON / OFF in response to the signal on the signal supply line XTL.

[0074] The transistor TP13 is connected to the current path between the power supply voltage node VDD and the transistor TP12. The gate electrode of the transistor TP13 is connected to the signal supply line XLI. The transistor TP13 functions as a switch circuit that turns ON / OFF in response to the signal on the signal supply line XLI.

[0075] The transistor TN15 is connected between the node INV and the wiring DBUS. The gate electrode of the transistor TN15 is connected to the signal supply line XTI. The transistor TN15 functions as a switch circuit that turns ON / OFF in response to the signal on the signal supply line XTI.

[0076] [Operation of latch circuit XDL10 during data input] 8 and 9 are timing charts for explaining the operation of the latch circuit XDL10 during data input. During data input, signals input via the lines XBUS and XBUSn are transferred to the nodes LAT and INV of the latch circuit XDL10 and held at the nodes LAT and INV. Mutually inverted signals are held at the nodes LAT and INV.

[0077] In the following description, a high-level signal "H" has a magnitude that turns off a P-channel MOS transistor and turns on an N-channel MOS transistor. "H" is a power supply voltage, for example, a voltage V D The low-level signal "L" has a magnitude that turns on a P-channel MOS transistor and turns off an N-channel MOS transistor. "L" is, for example, a voltage V S It is about the same size.

[0078] FIG. 8 is a timing chart when "L" is input from the line XBUS and "H" is input from the line XBUSn.

[0079] During data in, the signal supply line XTI is maintained at "L" and the transistor TN15 is turned off to disconnect the node INV from the wiring DBUS. Also, the signal supply line XLI is maintained at "L" and the transistor TP13 is turned on.

[0080] At timing t101, the nodes INV and LAT are either in the "H" or "L" state, or in the "L" or "H" state. Also, "L" is supplied from the signal supply line XTL, and the transistors TN13 and TN14 are in the OFF state.

[0081] At timing t102, a data-in operation is executed. In the data-in operation, the signal supply line XTL rises from "L" to "H" and transistors TN13 and TN14 are turned on. As a result, the signal voltage "L" from the line XBUS is transferred to the node LAT, and the signal voltage "H" from the line XBUSn is transferred to the node INV, causing the node LAT to go to "L" and the node INV to go to "H."

[0082] As a result of the above, the user data Dat is transferred from the input / output control circuit I / O to the latch circuit XDL10.

[0083] FIG. 9 is a timing chart when "H" is input from the line XBUS and "L" is input from the line XBUSn.

[0084] The state of each wiring at timing t111 is basically the same as the state of each wiring at timing t101, except for the wirings XBUS and XBUSn.

[0085] At timing t112, the same data-in operation as at timing t102 is executed. As a result, the signal voltage “H” from the line XBUS is transferred to the node LAT, and the signal voltage “L” from the line XBUSn is transferred to the node INV, so that the node LAT becomes “H” and the node INV becomes “L”.

[0086] As a result of the above, the user data Dat is transferred from the input / output control circuit I / O to the latch circuit XDL10.

[0087] [Operation of latch circuit XDL10 when data is output] 10 and 11 are timing charts for explaining the operation of the latch circuit XDL10 during data output. During data output, signals held at nodes LAT and INV of the latch circuit XDL10 are output to the input / output control circuit I / O via wirings XBUS and XBUSn.

[0088] FIG. 10 is a timing chart for when data is output from a state in which the node LAT is "L" and the node INV is "H."

[0089] During data output, the signal supply line XTI is maintained at "L" and the transistor TN15 is turned off to disconnect the node INV from the wiring DBUS. Also, the signal supply line XLI is maintained at "L" and the transistor TP13 is turned on.

[0090] At timing t121, the signal supply line XTL is "L" and transistors TN13 and TN14 are in the OFF state. Since node LAT is "L" and node INV is "H", transistors TP12 and TN11 are ON and transistors TP11 and TN12 are in the OFF state. Also, at timing t121, precharging is performed and the wiring XBUS and XBUSn are set to the "H" state.

[0091] At timing t122, a data-out operation is performed. In the data-out operation, the signal supply line XTL rises from "L" to "H" and the transistors TN13 and TN14 are turned ON. As a result, the line XBUS is discharged via the two transistors TN13 and TN11 that are ON, and changes from "H" to "L". The line XBUSn remains "H" because no discharge occurs after precharging.

[0092] As a result of the above, the user data Dat is transferred from the latch circuit XDL10 via the lines XBUS and XBUSn.

[0093] FIG. 11 is a timing chart for when data is output from a state in which the node LAT is "H" and the node INV is "L."

[0094] The state of each wiring at timing t131 is basically the same as the state of each wiring at timing t121, except for the nodes LAT and INV. However, because the node LAT is “H” and the node INV is “L,” the transistors TP11 and TN12 are ON, and the transistors TP12 and TN11 are OFF.

[0095] At timing t132, the same data-out operation as at timing t122 ​​is executed. As a result, the line XBUSn is discharged via the two transistors TN14 and TN12 that are ON, and changes from "H" to "L." The line XBUS maintains "H" because no discharge occurs after precharging.

[0096] As a result of the above, the user data Dat is transferred from the latch circuit XDL10 to the input / output control circuit I / O.

[0097] [Comparative Example] Next, a latch circuit according to a comparative example will be described with reference to Fig. 12 to Fig. 14. Fig. 12 is a schematic circuit diagram showing the configuration of a latch circuit according to a comparative example.

[0098] The latch circuit XDLX0 according to the comparative example is connected only to the wiring XBUS_X (FIG. 12) as the input / output wiring on the input / output control circuit I / O side, instead of the wiring XBUS and XBUSn (FIG. 7). Furthermore, the latch circuit XDLX0 does not have the transistors TN13 and TN14 (FIG. 7), but has transistors TPX1 and TNX1 between the wiring XBUS_X and the node LAT_X. The wiring XBUS_X is connected to the node LAT_X via the transistors TPX1 and TNX1, and is not connected to the node INV_X.

[0099] In addition, the latch circuit XDLX0 is provided with a transistor TPX2 between the power supply voltage node VDD and the transistor TP11, and a transistor TNX2 between the transistor TN11 and the ground voltage node VSS. The transistors TNX1 and TNX2 are N-channel MOS transistors. The transistors TPX1 and TPX2 are P-channel MOS transistors.

[0100] Furthermore, signal supply lines XNL and XLL are connected to the latch circuit XDLX0 (FIG. 12). The gate electrodes of transistors TNX2 and TPX1 are connected to the signal supply line XNL. The gate electrode of transistor TNX1 is connected to the signal supply line XTL. The gate electrode of transistor TPX2 is connected to the signal supply line XLL.

[0101] [Operation of latch circuit XDLX0 during data input] 13 is a timing chart for explaining the operation of the latch circuit according to the comparative example when data is in. When data is in, a signal input via the wiring XBUS_X is transferred to and held at the node LAT_X of the latch circuit XDLX0, and an inverted signal of the node LAT_X is held at the node INV_X.

[0102] FIG. 13 is a timing chart when "L" is input from the wiring XBUS_X.

[0103] During data-in, the signal supply line XTI is maintained at "L" and the transistor TN15 is turned OFF, disconnecting the node INV_X from the wiring DBUS. Also, the signal supply line XLI is maintained at "L" and the transistor TP13 is turned ON. Also, the signal supply line XLL is maintained at "H" and the transistor TPX2 is turned OFF.

[0104] At timing tx01, the nodes INV_X and LAT_X are in the "L" and "H" states, so the transistors TP11 and TN12 are ON and the transistors TP12 and TN11 are OFF. The signal supply lines XNL and XTL are "H" and "L", so the transistor TNX2 is ON and the transistors TPX1 and TNX1 are OFF.

[0105] At timing tx02, the signal supply lines XNL and XTL are set to "L" and "H", turning transistors TPX1 and TNX1 ON and transistor TNX2 OFF. As a result, the signal voltage "L" from the wiring XBUS_X is transferred to node LAT_X, causing node LAT_X to go to "L". Here, "L" from LAT_X is input to the input of the inverter circuit made up of transistors TP12 and TN12, and because transistors TP12 and TP13 are ON, node INV_X goes to the same potential as power supply voltage node VDD and goes to "H".

[0106] [Operation of latch circuit XDLX0 when data is output] 14 is a timing chart for explaining the operation of the latch circuit according to the comparative example at the time of data output. At the time of data output, the signal held at the node LAT_X of the latch circuit XDLX0 is output to the input / output control circuit I / O via the line XBUS_X.

[0107] FIG. 14 is a timing chart showing a case where data is output from a state in which the node LAT_X is "L" and the node INV_X is "H."

[0108] During data out, the signal supply line XTI is maintained at "L", transistor TN15 is turned OFF, and node INV_X is disconnected from wiring DBUS. Furthermore, the signal supply lines XLI and XLL are maintained at "L", and transistors TP13 and TPX2 are turned ON. Furthermore, the signal supply line XNL is maintained at "H", transistor TPX1 is turned OFF, and transistor TNX2 is turned ON.

[0109] At timing tx11, the signal supply line XTL is "L" and transistor TNX1 is in the OFF state. Since node LAT_X is "L" and node INV_X is "H", transistors TP12 and TN11 are ON and transistors TP11 and TN12 are in the OFF state. Also, at timing tx11, precharging is performed and the wiring XBUS_X is set to the "H" state.

[0110] At timing tx12, the signal supply line XTL rises from "L" to "H" and the transistor TNX1 is turned ON. As a result, the wiring XBUS_X is discharged via the three transistors TNX1, TN11, and TNX2 that are ON, and changes from "H" to "L".

[0111] In the latch circuit XDLX0 according to the comparative example, the discharge path when the voltage level of the precharged line XBUS_X falls from "H" to "L" at timing tx12 includes three transistors (transistors TNX1, TN11, and TNX2). Because the discharge path of the line XBUS_X includes a relatively large number of transistors and has high resistance, the discharge time can be long. Therefore, it can be difficult to speed up the latch operation.

[0112] [effect] In the latch circuit XDL10 (FIG. 7) according to the first embodiment, when transistors TN13 and TN14 are turned on during data input, voltages related to the data are transferred directly from the wirings XBUS and XBUSn to the nodes LAT and INV. As a result, in this embodiment, the transistors TPX2 and TNX2 that function as switches, which were necessary during data input in the comparative example, are no longer necessary.

[0113] Furthermore, in the latch circuit XDL10, when data is output, both lines XBUS and XBUSn are first precharged to "H." At timing t122 ​​(FIG. 10), the discharge path when the voltage level of the precharged line XBUS changes from "H" to "L" includes two transistors (transistors TN13 and TN11). Because the discharge path includes a relatively small number of transistors and has low resistance, the discharge time of the line XBUS can be made relatively short. This allows for faster latch operations.

[0114] To speed up the discharge of the above-mentioned wiring XBUS, it is conceivable to reduce the resistance by increasing the size (e.g., channel width) of the transistor in the current path. However, since a large number of latch circuits XDL10 are arranged corresponding to the bit lines BL, increasing the transistor area of ​​each latch circuit XDL10 leads to a significant increase in the area occupied by the transistors in the chip, which is not desirable.

[0115] In this embodiment, the operation speed of the latch circuit XDL10 related to data output can be increased without increasing the number or size of the transistors included in the latch circuit XDL10, thereby improving the interface performance of the semiconductor memory device.

[0116] [Second embodiment] Fig. 15 is a circuit diagram showing the configuration of a latch circuit XDL20 according to the second embodiment. In Fig. 15, the same components as those in Fig. 7 are given the same reference numerals, and the description thereof will be omitted.

[0117] The semiconductor memory device according to the second embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment. However, while in the latch circuit XDL10 according to the first embodiment (FIG. 7), a wiring DBUS is connected between the sense amplifier module SAM and the latch circuit XDL10, in the latch circuit XDL20 according to the second embodiment (FIG. 15), a wiring DBUSn is connected between the sense amplifier module SAM and the latch circuit XDL20 in addition to the wiring DBUS. Furthermore, unlike the latch circuit XDL10, the latch circuit XDL20 does not include a transistor TP13.

[0118] The wires DBUS and DBUSn are signal lines that transmit complementary signals. The wires DBUS and DBUSn transmit signals that are inverted to each other.

[0119] In the latch circuit XDL20, the line DBUSn is connected to a node LAT, and a transistor TN21 is provided between the line DBUSn and the node LAT. The transistor TN21 is an N-channel MOS transistor.

[0120] In a read operation of the semiconductor memory device according to the second embodiment, data is transferred from the sense amplifier module SAM to the latch circuit XDL20 via the wiring DBUS and DBUSn. In such a case, data can be input directly to the nodes LAT and INV from the wiring DBUS and DBUSn, making the transistor TP13 included in the latch circuit XDL10 (FIG. 7) unnecessary. In such a configuration without the transistor TP13 (FIG. 7), the charging time required to change the potential held at the node INV from "L" to "H" is shortened, and the operation of the latch circuit XDL20 can be sped up.

[0121] [Third embodiment] In the first and second embodiments, the configurations of the latch circuit XDL10 (FIG. 7) and the latch circuit XDL20 (FIG. 15) have been described. In the third embodiment, the configuration of a multiplexer that can be used in combination with the latch circuits XDL10 and XDL20 will be described.

[0122] Fig. 16 is a circuit diagram showing the connection relationship of a multiplexer MUX according to the third embodiment. Fig. 17 is a schematic circuit diagram showing the configuration of the multiplexer MUX. In Fig. 16, the same components as those in Fig. 6 are designated by the same reference numerals, and their description will be omitted.

[0123] The semiconductor memory device according to the third embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment. However, in the semiconductor memory device according to the third embodiment, a multiplexer MUX (FIG. 16) according to the third embodiment is connected between the wiring XBUS, XBUSn and the bus wiring IOBUS.

[0124] The multiplexer MUX (FIG. 17) includes a bus wiring IOBUS and circuits CR30 and CR31 connected between wirings XBUS and XBUSn.

[0125] The circuit CR30 includes transistors TN31 to TN35, transistors TP31 to TP35, a node ND1, a node ND2, and a node XBUS_OUTn.When data is output, the circuit CR30 of the multiplexer MUX is operated.

[0126] The circuit CR31 includes transistors TN36 to TN39, transistors TP36 to TP40, and a node ND3. When data is input, the circuit CR31 of the multiplexer MUX is operated.

[0127] The transistors TN31 to TN39 are N-channel MOS transistors, and the transistors TP31 to TP40 are P-channel MOS transistors.

[0128] The transistors TP31 and TN31 are connected in series to a current path between a power supply voltage node VDD and a ground voltage node VSS via a node ND1. The gate electrodes of the transistors TP31 and TN31 are connected to a node ND2. The transistors TP31 and TN31 function as an inverter circuit.

[0129] The transistors TP32 and TN32 are connected in series to a current path between a power supply voltage node VDD and a ground voltage node VSS via a node ND2. The gate electrodes of the transistors TP32 and TN32 are connected to a node ND1. The transistors TP32 and TN32 function as an inverter circuit.

[0130] In the portion including the transistors TP31 and TN31 and the transistors TP32 and TN32, two inverter circuits are cross-connected.

[0131] The transistor TP33 is connected between the power supply voltage node VDD and the transistor TP31. The gate electrode of the transistor TP33 is connected to the line XBUSn. The transistor TP33 functions as a switch circuit that is turned on / off in response to a signal on the line XBUSn.

[0132] The transistor TP34 is connected between the power supply voltage node VDD and the transistor TP32. The gate electrode of the transistor TP34 is connected to the line XBUS. The transistor TP34 functions as a switch circuit that turns ON / OFF in response to a signal on the line XBUS.

[0133] The transistor TN33 is connected in parallel to the transistor TN31 between the node ND1 and the ground voltage node VSS. The transistor TN34 is connected in parallel to the transistor TN32 between the node ND2 and the ground voltage node VSS. The transistor TP35 is connected between the power supply voltage node VDD and the transistors TP33 and TP34. The gate electrodes of the transistors TN33, TN34, and TP35 are connected to the signal supply line DOUTn. The transistors TP33, TN34, and TN35 function as a switch circuit that is turned ON / OFF in response to the signal on the signal supply line DOUTn.

[0134] The transistor TN35 is connected between the bus line IOBUS and the ground voltage node VSS. The gate electrode of the transistor TN35 is connected to the node ND2. The transistor TN35 functions as a switch circuit that discharges the voltage of the bus line IOBUS to reduce or maintain the voltage, depending on the state of the node ND2.

[0135] The transistors TP36 and TN36 are connected in series to a current path between the power supply voltage node VDD and the ground voltage node VSS via a node ND3. The gate electrodes of the transistors TP36 and TN36 are connected to the bus wiring IOBUS. The transistors TP36 and TN36 function as an inverter circuit.

[0136] The transistors TP37 and TN37 are connected in parallel to the current path between the node ND3 and the wiring XBUSn. The transistors TP38 and TN38 are connected in parallel to the current path between the IOBUS and the wiring XBUS. The gate electrodes of the transistors TP37 and TP38 are connected to the signal supply line DINn. The gate electrodes of the transistors TN37 and TN38 are connected to the signal supply line DIN. The transistors TP37, TN37, TP38, and TN38 function as switch circuits that are turned ON / OFF in response to the signals on the signal supply lines DINn and DIN.

[0137] The transistors TP39 and TN39 are connected in series to a current path between the power supply voltage node VDD and the ground voltage node VSS. The node between the transistors TP39 and TN39 is connected to the line XBUS. The gate electrode of the transistor TP39 is connected to the signal supply line PRECHGn. The gate electrode of the transistor TN39 is connected to the signal supply line XDLRST. The transistor TP39 functions as a switch circuit for precharging the line XBUS to the "H" level. The transistor TN39 functions as a switch circuit for resetting the line XBUS to the "L" level.

[0138] The transistor TP40 is connected to a current path between the power supply voltage node VDD and the line XBUSn. The gate electrode of the transistor TP40 is connected to the signal supply line XDLRST_PRECHGn. The transistor TP40 functions as a switch circuit for precharging or resetting the line XBUSn.

[0139] [Multiplexer MUX operation when data is output] FIG. 18 is a timing chart for explaining the operation of the multiplexer MUX when data is output.

[0140] When data is output, the signals held at nodes LAT and INV of latch circuit XDL10 (FIG. 7), latch circuit XDL20 (FIG. 12), etc. are input to circuit CR30 in MUX via wiring XBUS and XBUSn, and are output to input / output control circuit I / O via bus wiring IOBUS.

[0141] 18 is a timing chart showing the case where data is output when the line XBUS is "L" and the line XBUSn is "H." Since the line XBUS is "L" and the line XBUSn is "H," the transistor TP34 is ON and the transistor TP33 is OFF.

[0142] When data is output, the signal supply lines XDLRST and DIN are maintained at "L", the signal supply lines XDLRST_PRECHGn and DINn are maintained at "H", the transistors TN37 to TN39 and the transistors TP37, TP38, and TP40 in the circuit CM31 are turned OFF, and the circuit CM31 is prevented from operating.

[0143] At timing t301, the signal supply line PRECHGn is set to "H." This turns transistor TN39 OFF. Also, "H" is supplied to the signal supply line DOUTn, turning transistor TP35 OFF and transistors TN33 and TN34 ON. This causes nodes ND1, ND2, and XBUS_OUTn to go to "L," the same potential as the ground voltage node VSS, the bus wiring IOBUS is not discharged and is "H," and the transistors TP31 and TP32 are ON.

[0144] At timing t302, the signal supply line PRECHGn falls from "H" to "L", and then rises to "H" after a certain period of time has passed. This turns on the transistor TP39 for a certain period of time, and the line XBUS is charged from "L" to "H". When the line XBUS becomes "H", the transistor TP34 turns off.

[0145] At timing t303, data is transferred from the node LAT of the latch circuit XDL10 (FIG. 7), the latch circuit XDL20 (FIG. 12), etc. to the line XBUS, and the line XBUS is set to "L," thereby turning on the transistor TP34.

[0146] At timing t304, the signal supply line DOUTn falls from "H" to "L," turning on transistor TP35 and turning off transistors TN33 and TN34. Because transistors TP35, TP34, and TP32 are on, nodes ND2 and XBUS_OUTn go to "H," the same potential as the power supply voltage node. Also, transistor TP31 turns off, and node ND1 is discharged via transistor TN31, going from "H" to "L." This turns off transistor TN32. Also, transistor TN35 turns on, and the bus wiring IOBUS goes to "L."

[0147] [Operation of the multiplexer MUX when data is input] When data is input, the signal supply lines DIN and DINn are set to "H" and "L", and the transistors TN37, TN38, TP37, and TP38 are turned on. As a result, data transferred from the bus wiring IOBUS is transferred to the wiring XBUS. In addition, the data transferred from the bus wiring IOBUS is inverted via an inverter circuit formed by transistors TN36 and TP36, and the inverted data is output from the wiring XBUSn.

[0148] [Fourth embodiment] Fig. 19 is a schematic circuit diagram showing the configuration of a multiplexer MUX2 according to the fourth embodiment. In Fig. 19, the same components as those in the multiplexer MUX in Fig. 17 are given the same reference numerals, and their description will be omitted.

[0149] The multiplexer MUX2 (FIG. 19) according to the fourth embodiment is basically configured in the same manner as the multiplexer MUX (FIG. 17) according to the third embodiment. However, the multiplexer MUX2 is provided with a circuit CR40 instead of the circuit CR30 of the multiplexer MUX.

[0150] The circuit CR40 includes transistors TN41 to TN43, transistors TP41 and TP42, and a node ND4. When data is output, the circuit CR40 of the multiplexer MUX2 is operated.

[0151] The transistors TN41 to TN43 are N-channel MOS transistors, and the transistors TP41 and TP42 are P-channel MOS transistors.

[0152] The transistors TP41 and TP42 are connected in series to a current path between a power supply voltage node VDD and a node ND4. The transistors TN41 and TN42 are connected in parallel to a current path between the node ND4 and a ground voltage node VSS. The gate electrodes of the transistors TP41 and TN41 are connected to the wiring XBUS. The gate electrodes of the transistors TP42 and TN42 are connected to a signal supply line DOUTn. The transistors TN41 and TN42 and the transistors TP41 and TP42 function as a NOR circuit having two input terminals connected to the wiring XBUS and the signal supply line DOUTn, and an output terminal connected to the node ND4.

[0153] The transistor TN43 is connected between the bus line IOBUS and the ground voltage node VSS. The gate electrode of the transistor TN43 is connected to a node ND4. The transistor TN43 functions as a switch circuit that discharges the voltage of the bus line IOBUS to reduce or maintain the voltage, depending on the state of the node ND4.

[0154] The operation of the multiplexer MUX2 during data input is similar to that of the multiplexer MUX (FIG. 17).

[0155] The operation of the multiplexer MUX2 when outputting data is, for example, to precharge the bus wiring IOBUS in advance to "H".

[0156] When "L" is input to the line XBUS and the signal supply line DOUTn, the transistors TN41 and TN42 are turned OFF and the transistors TP41 and TP42 are turned ON. As a result, the node ND4 becomes "H" which is the same potential as the power supply voltage node VDD, the transistor TN43 is turned ON, and the bus line IOBUS is discharged to "L".

[0157] When "H" is input to at least one of the wiring XBUS and the signal supply line DOUTn, at least one of the transistors TN41 and TN42 is turned ON and at least one of the transistors TP42 and TN42 is turned OFF. As a result, the node ND4 becomes "L" which is the same potential as the ground voltage node VSS, the transistor TN43 is not turned ON, and the bus wiring IOBUS remains "H".

[0158] [others] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0159] MC...memory cell, BL...bit line, SA...sense amplifier, SAU...sense amplifier unit, SAM...sense amplifier module, DBUS...wiring, XDL10...latch circuit, XBUS...wiring, XBUSn...wiring, LAT...node, INV...node.

Claims

1. A memory cell; a bit line electrically connected to the memory cell; a sense amplifier circuit electrically connected to the bit line; a first data line electrically connected to the sense amplifier circuit; a data latch circuit electrically connected to the first data wiring; a second data wiring and a third data wiring electrically connected to the data latch circuit and capable of transferring mutually inverted data signals; Equipped with the data latch circuit includes a first node that holds data and a second node that holds inverted data of the data; the second data wiring is electrically connected to the first node; The second node is electrically connected to the first data wiring and the third data wiring. Semiconductor memory device.

2. The data latch circuit a first voltage node; and a second voltage node capable of supplying a voltage lower than that of the first voltage node; a first P-channel MOS transistor and a first N-channel MOS transistor connected in series to a first current path between the first voltage node and the second voltage node via the first node; a second P-channel MOS transistor and a second N-channel MOS transistor connected in series via the second node in a second current path different from the first current path between the first voltage node and the second voltage node; Equipped with the gate electrodes of the first P-channel MOS transistor and the first N-channel MOS transistor are connected to the second node; The gate electrodes of the second P-channel MOS transistor and the second N-channel MOS transistor are connected to the first node.

2. The semiconductor memory device according to claim 1.

3. a fourth data line electrically connected to the sense amplifier circuit and the data latch circuit and capable of transferring a data signal that is an inversion of the data transferred by the first data line; The fourth data wiring is electrically connected to the first node.

2. The semiconductor memory device according to claim 1.

4. a first MOS transistor connected between the second data line and the first node; a second MOS transistor connected between the third data line and the second node; Equipped with 2. The semiconductor memory device according to claim 1.

5. a multiplexer electrically connected to the second data wiring and the third data wiring; a fifth data line electrically connected to the multiplexer; Equipped with The multiplexer a first switch circuit electrically connected between the fifth data wiring and the second data wiring; a first inverter circuit having an input terminal electrically connected to the fifth data wiring; a second switch circuit electrically connected between the output terminal of the first inverter circuit and the third data wiring; Contains 2. The semiconductor memory device according to claim 1.

6. The multiplexer a third voltage node; and a fourth voltage node capable of supplying a voltage lower than that of the third voltage node; a third MOS transistor and a second inverter circuit connected in series in a third current path between the third voltage node and the fourth voltage node; a fourth MOS transistor and a third inverter circuit connected in series to a fourth current path different from the third current path between the third voltage node and the fourth voltage node; a fifth MOS transistor having a gate electrode electrically connected to the output terminal of the second inverter circuit and the input terminal of the third inverter circuit; Equipped with the second data line is connected to a gate electrode of the third MOS transistor; the gate electrode of the fourth MOS transistor is connected to the third data line; an input terminal of the second inverter circuit is electrically connected to an output terminal of the third inverter circuit; The fifth MOS transistor is electrically connected between the fifth data line and the fourth voltage node.

6. The semiconductor memory device according to claim 5.

7. The multiplexer a fifth voltage node; and a sixth MOS transistor having a gate electrode electrically connected to the third data line; Equipped with The sixth MOS transistor is electrically connected between the fifth data line and the fifth voltage node.

6. The semiconductor memory device according to claim 5.

8. The memory cell a semiconductor layer extending in a first direction; a conductive layer facing the semiconductor layer in a second direction intersecting the first direction; a charge storage layer provided between the semiconductor layer and the conductive layer; an insulating layer provided between the semiconductor layer and the charge storage layer; 2. The semiconductor memory device according to claim 1, comprising:

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