Semiconductor module and semiconductor device

Abstract

To provide a semiconductor module in which a module terminal can be disposed at a proper position of a mount substrate.SOLUTION: A semiconductor module 1 includes a module substrate 4, a semiconductor element 2, and a plurality of module terminals T and is mounted on a mount substrate 3. The module terminals T include a plurality of external connection terminals 11 disposed on an outer peripheral side of different sides of a rectangular arrangement region 7 of the module terminals T, a plurality of relay terminals 12 disposed on an inner peripheral side with respect to the external connection terminals 11, and a common relay terminal 12 electrically connected to an object terminal 6 through a wire on the module substrate 4. As one of the relay terminals 12 is selectively connected to the common relay terminal 12 on the mount substrate, one of the external connection terminals 11 is selectively connected to the object terminal 6.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor module and a semiconductor device. [Background technology]

[0002] For example, Japanese Patent Laid-Open Publication No. 9-232505 (Patent Document 1) discloses a technology relating to a semiconductor module. In the following description of the background art, the reference numerals in parentheses refer to those in Patent Document 1.

[0003] The semiconductor module (multi-chip module 1) of Patent Document 1 includes a module substrate (island 2), multiple semiconductor elements (chips 3) mounted on the module substrate, and multiple module terminals for connecting to external circuits. The semiconductor elements and these module terminals are electrically connected within the semiconductor module. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 9-232505 Summary of the Invention [Problem to be solved by the invention]

[0005] Generally, module terminals are assigned signals that need to be transmitted between semiconductor elements mounted on the semiconductor module and external circuit elements (electronic components including connectors, etc.). Such semiconductor modules can be mounted on various substrates depending on their intended use. Therefore, depending on the layout of the circuit elements on the substrate, the signal wiring distance to the corresponding module terminals may become long, which may result in degradation of signal quality (signal waveform). In other words, when mounting a semiconductor module on a substrate, the module terminals may not be positioned appropriately on the substrate. In particular, with signal frequencies becoming increasingly higher in recent years, it is important to position the module terminals appropriately on the substrate and keep the wiring distance of the signal wiring short.

[0006] Therefore, a semiconductor module is desired that allows the module terminals to be arranged at appropriate positions on the mounting substrate. [Means for solving the problem]

[0007] A semiconductor module according to the present disclosure is a semiconductor module mounted on a mounting substrate, the semiconductor module comprising: a module substrate; at least one semiconductor element mounted on a first surface of the module substrate; and a plurality of module terminals arranged in a rectangular grid pattern on a second surface of the module substrate, the module terminals being terminals connected to target terminals of the semiconductor elements, the module terminals including: a plurality of external connection terminals arranged on the outer periphery of different sides of a rectangular arrangement area of ​​the plurality of module terminals; a plurality of relay terminals electrically connected to corresponding external connection terminals via wiring on the module substrate and arranged on the inner periphery of the external connection terminals; and at least one common relay terminal electrically connected to the target terminal via wiring on the module substrate; and on the mounting substrate, one of the plurality of relay terminals is selectively connected to the common relay terminal, thereby selectively connecting one of the plurality of external connection terminals to the target terminal.

[0008] This configuration allows one of multiple relay terminals to be selectively connected to a common relay terminal on a substrate. Therefore, when a semiconductor module is mounted on a substrate, the wiring distance between the external connection terminal connected to a circuit on the substrate and the target terminal of the semiconductor element can be kept short. This relatively simple configuration makes it easy to avoid degradation of signal quality (signal waveform) due to long wiring distances. Furthermore, this configuration minimizes variations in signal quality due to the length of the wiring distance, depending on the type of substrate on which the semiconductor module is mounted. Thus, this configuration allows the module terminals to be positioned appropriately on the substrate.

[0009] Further features and advantages of the semiconductor module and the semiconductor device will become apparent from the following description of exemplary, non-limiting embodiments, which are given with reference to the drawings. [Brief explanation of the drawings]

[0010] [Figure 1] Schematic exploded perspective view of a semiconductor device [Figure 2] Semiconductor module component layout diagram [Figure 3] FIG. 1 is a plan view schematically showing a connection between a semiconductor module and a main board; [Figure 4] 1 is a cross-sectional view schematically illustrating a connection between a semiconductor module and a main board; [Figure 5] FIG. 10 is a plan view schematically illustrating the connection between the second external connection terminal and the third external connection terminal; [Figure 6] FIG. 10 is a plan view schematically illustrating the arrangement of module terminals in a configuration for transmitting differential signals. [Figure 7] FIG. 10 is a plan view schematically showing an example of a connection between a target terminal pair and a common relay terminal pair; [Figure 8] FIG. 10 is a plan view schematically showing another example of the connection between the target terminal pairs and the common relay terminal pairs; DETAILED DESCRIPTION OF THE INVENTION

[0011] [First embodiment] A first embodiment in which a semiconductor module 1 is applied to a semiconductor device 10 will be described below with reference to the drawings. As shown in FIG. 1, the semiconductor module 1 is mounted on a mount substrate 3. In this embodiment, the semiconductor module 1 is mounted on a main substrate 5, which serves as the mount substrate 3. The semiconductor device 10 includes the semiconductor module 1 and the main substrate 5, which serves as the mount substrate 3. In this example, the semiconductor module 1 and at least one circuit element 50 are mounted on a first surface (main substrate first surface 5a) of the main substrate 5. The semiconductor module 1 and the circuit element 50 are electrically connected on the main substrate 5. The circuit element 50 includes a semiconductor element, a passive element, a connector, etc.

[0012] The semiconductor module 1 includes a module substrate 4, at least one semiconductor element 2 mounted on a first surface (module substrate first surface 4a) of the module substrate 4, and a plurality of module terminals T arranged in a rectangular grid pattern on a second surface (module substrate second surface 4b) of the module substrate 4. In this embodiment, the semiconductor module 1 includes a plurality of semiconductor elements 2. In this example, the semiconductor module 1 is configured as a multi-chip module including a system LSI 2a and a memory 2b operating in cooperation with the system LSI 2a as the plurality of semiconductor elements 2, and a module substrate 4 on which these elements are mounted. As shown in the component layout diagram of FIG. 2, the module substrate 4 is mounted with an SoC (System on a Chip) as the system LSI 2a and two SDRAMs (Synchronous Dynamic Random Access Memory) as the memory 2b. Examples of the SDRAM include, but are not limited to, Double Data Rate 4 (DDR4) SDRAM and Double Data Rate 5 (DDR5) SDRAM.

[0013] In this embodiment, the semiconductor element 2 has an element terminal B (FIG. 6). In this example, each of the multiple semiconductor elements 2 (system LSI 2a, memory 2b) has an element terminal B. The element terminal B is a hemispherical connection terminal that protrudes from the surface of the semiconductor element 2 facing the module substrate first surface 4a toward the module substrate first surface 4a. The element terminal B is electrically connected to a different semiconductor element 2 on the module substrate 4, or electrically connected to a module terminal T via the module substrate 4 (specifically, a through hole, a land, or the like). If the surface of the module substrate 4 facing the main substrate first surface 5a (the opposing surface) is referred to as the module substrate second surface 4b, the module substrate first surface 4a is the surface opposite the module substrate second surface 4b, i.e., the surface on the side where the main substrate 5 is not arranged.

[0014] Each of the multiple module terminals T is provided on the module substrate second surface 4b and is a hemispherical connection terminal that protrudes from the module substrate second surface 4b toward the main substrate first surface 5a. Each module terminal T is connected to the main substrate first surface 5a. The module terminals T include signal terminals that transmit signals and power terminals that transmit power. The signal terminals include input terminals, output terminals, and bidirectional terminals (input / output terminals). In this example, the multiple module terminals T are arranged in a rectangular ring shape along the periphery (here, the rectangular periphery) of the module substrate 4. Therefore, the area (arrangement area 7) in which the multiple module terminals T are arranged has a rectangular shape as a whole. In this example, the multiple module terminals T are arranged over the entire surface of the arrangement area 7, but this is not limited to this.

[0015] The system LSI 2a is configured with multiple functional blocks (arithmetic units such as a CPU, audio DSP, video capture, USB host, memory interface, etc.), and the semiconductor module 1 as a multi-chip module similarly has multiple functional blocks. Each functional block is connected to a specific circuit or device, or an interface circuit (receiver, driver) or connector of the device via the target terminal 6 or module terminal T. The above-mentioned circuit element 50 corresponds to these specific circuits, devices, interface circuits, connectors, etc., and FIG. 1 illustrates an integrated circuit as an example.

[0016] As shown in Figures 3 and 5, the module terminal T includes a plurality of external connection terminals 11, a plurality of relay terminals 12, and at least one common relay terminal 13. The plurality of relay terminals 12 are provided to correspond to the plurality of external connection terminals 11. Here, the number of external connection terminals 11 and the number of relay terminals 12 are the same. Figures 3 to 5 illustrate an example in which the module terminal T includes one common relay terminal 13. The common relay terminal 13 is electrically connected to one of the plurality of relay terminals 12. The common relay terminal 13 is connected to a target terminal 6, among the element terminals B of the semiconductor element 2, to which the above-mentioned external connection terminal 11 is connected.

[0017] The external connection terminals 11 are terminals connected to the target terminals 6 of the semiconductor element 2 and are arranged on the outer periphery of different sides of the rectangular array area 7 of the module terminals T. In this embodiment, the external connection terminals 11 are arranged on the outermost periphery of different sides of the array area 7. However, as long as it is possible to pass wiring between the outermost module terminals T on the mounted substrate 3 and to a module terminal T arranged more inward than the second outermost periphery, the external connection terminals 11 may be arranged inside the outermost periphery. When the semiconductor module 1 is mounted on the main substrate 5, the external connection terminals 11 are connected to the circuit element 50 mounted on the first surface 5a of the main substrate. Furthermore, the external connection terminals 11 are connected to the target terminals 6 via the relay terminals 12 and the common relay terminal 13. This electrically connects the circuit element 50 and the semiconductor element 2. In this example, the external connection terminals 11 are arranged along the outermost periphery of three of the four sides of the rectangular array area 7. In this example, the periphery (four sides) of the arrangement region 7 is formed so as to follow the periphery (four sides) of the module substrate second surface 4b.

[0018] As shown in FIGS. 3 and 5, in this embodiment, the module terminal T includes a first external connection terminal 11a, a second external connection terminal 11b, and a third external connection terminal 11c as the external connection terminals 11. The first external connection terminal 11a, the second external connection terminal 11b, and the third external connection terminal 11c are arranged on different outer peripheries of the rectangular array area 7. In this example, the first external connection terminal 11a, the second external connection terminal 11b, and the third external connection terminal 11c are three of the module terminals T arranged on the outermost periphery. These three external connection terminals 11 are arranged separately on adjacent sides (three of the four sides of the array area 7). The three external connection terminals 11 are arranged in the center of each side (line segment). In the illustrated example, the system LSI 2a is arranged along the side on which these three external connection terminals 11 are not arranged.

[0019] As shown in FIGS. 3 to 5 , the common relay terminal 13 is electrically connected to the target terminals 6 via wiring on the module substrate 4. In this embodiment, the common relay terminal 13 is arranged more inward than the external connection terminals 11 in the arrangement region 7 (toward the center of the rectangular arrangement region 7). Furthermore, the common relay terminal 13 is arranged more inward than the multiple relay terminals 12. In the illustrated example, one module terminal T arranged in the center of the arrangement region 7 is used as the common relay terminal 13. The common relay terminal 13 is surrounded by the multiple relay terminals 12 and is located approximately equidistant from each of the relay terminals 12. Note that the common relay terminal 13 is arranged at a position offset from the target terminals 6 (toward the center of the arrangement region 7) when viewed from a direction perpendicular to the module substrate first surface 4a, but is not limited to this and may be arranged at positions overlapping each other.

[0020] The relay terminals 12 are electrically connected to the corresponding external connection terminals 11 via wiring (module wiring 14) on the module substrate 4 and are arranged on the inner periphery of the external connection terminals. In this embodiment, the relay terminals 12 are arranged more inward than the external connection terminals 11 and more outward than the common relay terminals 13 (toward the periphery of the arrangement area 7). As described above, the relay terminals 12 are arranged to surround the common relay terminal 13. The relay terminals 12 are electrically connected to the corresponding external connection terminals 11 via module wiring 14 provided on the module substrate second surface 4b (FIG. 4). That is, the module substrate second surface 4b has a plurality of module wirings 14 formed thereon. The module wirings 14 do not have to be formed on the module substrate second surface 4b. For example, the module wirings 14 may be arranged on an inner layer of the module substrate 4 and connected to the external connection terminals 11 and the relay terminals 12 via through holes and lands.

[0021] 3 and 5, in this embodiment, the module terminal T includes, as relay terminals 12, a first relay terminal 12a connected to the first external connection terminal 11a, a second relay terminal 12b connected to the second external connection terminal 11b, and a third relay terminal 12c connected to the third external connection terminal 11c. In this example, when viewed from a direction perpendicular to the module substrate first surface 4a, the first relay terminal 12a, the second relay terminal 12b, and the third relay terminal 12c, together with the target terminals 6, are arranged to surround the common relay terminal 13. In addition, multiple (here, three) module wirings 14 connecting each relay terminal 12 to the corresponding external connection terminal 11 are arranged to minimize the wiring distance. In this example, these three relay terminals 12 are arranged more inward than the three corresponding external connection terminals 11. In addition, these three relay terminals 12 are arranged in the central region of the arrangement region 7.

[0022] 3 and 4, on the mounted substrate 3 (here, the main substrate 5), one of the plurality of relay terminals 12 is selectively connected to the common relay terminal 13, thereby selectively connecting one of the plurality of external connection terminals 11 to the target terminal 6. In this embodiment, the first relay terminal 12a is connected to the common relay terminal 13 on the main substrate 5, thereby connecting the first external connection terminal 11a to the target terminal 6. The second relay terminal 12b is connected to the common relay terminal 13 on the main substrate 5, thereby connecting the second external connection terminal 11b to the target terminal 6. The third relay terminal 12c is connected to the common relay terminal 13 on the main substrate 5, thereby connecting the third external connection terminal 11c to the target terminal 6.

[0023] 3 and 5, the main substrate 5 includes a selection wiring 8 that connects the common relay terminal 13 to one of the plurality of relay terminals 12, and a signal wiring 9 that is connected to the external connection terminal 11 that is connected to the selected relay terminal 12. The selection wiring 8 and the signal wiring 9 are provided on the main substrate 5 (here, on the main substrate first surface 5a). As shown in FIGS. 1, 3, and 5, the signal wiring 9 is routed from a circuit element 50 and electrically connects the circuit element 50 to the plurality of external connection terminals 11. In this example, with the semiconductor module 1 mounted on the main substrate 5, the signal wiring 9 routed from the circuit element 50 is connected to the external connection terminal 11 that is closest to the circuit element 50 out of the first external connection terminal 11a, the second external connection terminal 11b, and the third external connection terminal 11c.

[0024] In this embodiment, on the mounted substrate 3 (main substrate 5), the first relay terminal 12a is selectively connected to the common relay terminal 13, thereby enabling the first external connection terminal 11a to be selectively connected to the target terminal 6. As shown in FIGS. 3 to 5, in this example, of the multiple external connection terminals 11, the first external connection terminal 11a is disposed at a position closest to the circuit element 50. The signal wiring 9 is formed on the main substrate 5 (here, the main substrate first surface 5a) so as to minimize the wiring distance connecting the first external connection terminal 11a and the circuit element 50 (FIG. 1). Also, as shown in FIGS. 3 to 5, the selection wiring 8 connects the first relay terminal 12a and the common relay terminal 13. As a result, the first external connection terminal 11a is connected to the target terminal 6, and the circuit element 50 is electrically connected to the target terminal 6. In this example, the selection wiring 8 is formed on the main board 5 (here, on the main board first surface 5a) so that the wiring distance connecting the first relay terminal 12a and the common relay terminal 13 is the shortest.

[0025] In this embodiment, as shown in Fig. 1, the circuit element 50 is arranged at a position closest to the first external connection terminal 11a among the multiple external connection terminals 11. On the other hand, if the circuit element 50 is located relatively far from the first external connection terminal 11a, as indicated by the two-dot chain line in Fig. 1, the signal wiring 9 is routed from the position indicated by the two-dot chain line to the first external connection terminal 11a. This results in a longer wiring distance for the signal wiring 9 than when the circuit element 50 is located at the position indicated by the solid line in Fig. 1, which may result in degradation of signal quality (signal waveform). However, as shown in Figs. 3 to 5, by using a semiconductor module 1 in which multiple external connection terminals 11 are provided at different positions in the arrangement area 7, and which is also provided with multiple module wirings 14, multiple relay terminals 12, and a common relay terminal 13, the wiring distance for the signal wiring 9 can be kept short even when the semiconductor module 1 is mounted on a mount substrate 3 in which the positions of the circuit elements 50 are different.

[0026] In this embodiment, one of the three external connection terminals 11 is selectively connected to one target terminal 6 and one common relay terminal 13 via a corresponding relay terminal 12 and module wiring 14. Therefore, the other two unselected external connection terminals 11, the two corresponding relay terminals 12, and the two module wirings 14 connecting them form redundant circuits. However, in this embodiment, these redundant circuit terminals and wiring can be effectively utilized. As shown in FIG. 5, in this embodiment, the second external connection terminal 11b and the third external connection terminal 11c can be connected by connecting the second relay terminal 12b and the third relay terminal 12c. That is, in this example, the main board 5 can further include a bypass wiring 18. Then, in a state where the circuit element 50 is electrically connected to the target terminal 6 (here, a state where the signal wiring 9 is connected to the first external connection terminal 11a and the selection wiring 8 is connected to the first relay terminal 12a and the common relay terminal 13), the bypass wiring 18 is configured to be able to connect the second relay terminal 12b and the third relay terminal 12c. This electrically connects the second external connection terminal 11b and the third external connection terminal 11c. The bypass wiring 18 is laid on the first surface 5a of the main board.

[0027] As indicated by the two-dot chain line in FIG. 1 , the position of the circuit element 50 on the main substrate 5 can be changed as needed. For example, if the circuit element 50 is located closest to the second external connection terminal 11b, the signal wiring 9 extending from the circuit element 50 is connected to the second external connection terminal 11b. The selection wiring 8 is located so as to connect the second relay terminal 12b and the common relay terminal 13. Similarly, if the circuit element 50 is located closest to the third external connection terminal 11c, the signal wiring 9 is connected to the third external connection terminal 11c. The selection wiring 8 is located so as to connect the third relay terminal 12c and the common relay terminal 13. This allows the length of the signal wiring 9 to be kept short. Furthermore, the wiring distance from the external connection terminal 11 connected to the signal wiring 9 to the target terminal 6 can also be kept short. Here, it is preferable that the bypass wiring 18 is arranged to connect the first relay terminal 12a and the third relay terminal 12c when the signal wiring 9 is connected to the second external connection terminal 11b and the selection wiring 8 is connected to the second relay terminal 12b and the common relay terminal 13. Similarly, it is preferable that the bypass wiring 18 is arranged to connect the first relay terminal 12a and the second relay terminal 12b when the signal wiring 9 is connected to the third external connection terminal 11c and the selection wiring 8 is connected to the third relay terminal 12c and the common relay terminal 13. Note that the positions of the external connection terminals 11, relay terminals 12, and common relay terminal 13 can be changed as needed within the arrangement region 7. The arrangement of the multiple module terminals T can also be changed as needed.

[0028] Second Embodiment A second embodiment of the semiconductor module 1 will be described with reference to the drawings (FIGS. 6 and 7). The following description of the semiconductor module 1 of this embodiment will focus on the differences from the first embodiment. Points that are not specifically mentioned are the same as those of the first embodiment, and the same reference numerals will be used to omit detailed description.

[0029] As shown in FIG. 6 , target terminals 6 are target terminal pairs that transmit differential signals, multiple external connection terminals 11 are external connection terminal pairs corresponding to the target terminal pairs, multiple relay terminals 12 are relay terminal pairs corresponding to the external connection terminal pairs, and common relay terminal 13 is a common terminal pair corresponding to the target terminal pairs. In this embodiment, information is transmitted between semiconductor element 2 and circuit element 50 using differential signals. For example, an in-vehicle camera capable of outputting image signals at a resolution of 4 million pixels or higher and 30 frames per second or higher may be connected to a video capture device using differential signals. Furthermore, a display interface that outputs video signals at a resolution of full high-definition (1920 pixels × 1080 pixels) or higher is often connected to a display using the HDMI (registered trademark) (High-Definition Multimedia Interface) standard, which transmits information using differential signals. Furthermore, information is also transmitted between a USB host and various USB-compatible devices using differential signals.

[0030] In this example, a semiconductor element 2 (system LSI 2a) is provided with a plurality of target terminals 6 (target terminal pairs). A plurality of first external connection terminals 11a, second external connection terminals 11b, and third external connection terminals 11c are arranged as external connection terminal pairs. A plurality of first relay terminals 12a, second relay terminals 12b, and third relay terminals 12c are arranged as relay terminal pairs. A plurality of common relay terminals 13 are arranged to correspond to the plurality of target terminals 6 and the plurality of relay terminals 12. Hereinafter, a group of the plurality of first relay terminals 12a will be referred to as a first relay terminal group A1, a group of the plurality of second relay terminals 12b will be referred to as a second relay terminal group A2, and a group of the plurality of third relay terminals 12c will be referred to as a third relay terminal group A3.

[0031] As described above, the target terminals 6 are configured to transmit differential signals. In this type of differential transmission, signals are transmitted differentially between two signals, so one target terminal 6 (target terminal pair) and its corresponding common relay terminal 13 (common relay terminal pair) are connected by two wires for transmitting a positive signal and a negative signal, respectively. Similarly, one relay terminal 12 (relay terminal pair) and its corresponding external connection terminal 11 (external connection terminal pair) are also connected by two wires (one set of module wires 14). Furthermore, although not shown, each signal wire 9 is also configured by two wires so as to correspond to the external connection terminal pair.

[0032] In this embodiment, the respective relay terminal pairs (relay terminals 12) are arranged side by side in a direction that is not parallel to any side of the rectangular array area 7. In this example, in each of the multiple relay terminals 12, the relay terminal pairs are arranged alternately and inclined with respect to each side of the array area 7 (so-called staggered arrangement). Furthermore, in each of the first relay terminal group A1, the second relay terminal group A2, and the third relay terminal group A3, the multiple relay terminals 12 (relay terminal pairs) are arranged so as to be inclined as a whole with respect to each side of the array area 7.

[0033] 7 and 8, the selection wiring 8 connecting the relay terminal 12 and the common relay terminal 13 is also configured with two wirings (a pair of selection wirings 8) to transmit a positive signal and a negative signal. Here, the relay terminal pairs of the relay terminal 12 are arranged in a staggered pattern as described above. This allows the wiring lengths to be shorter, for example, even when two wirings in the selection wiring 8 are swapped, compared to when the relay terminal pairs are arranged side by side along each side of the array region 7 (FIGS. 7 and 8).

[0034] In this example, as shown in FIG. 6 , when a plurality of first relay terminals 12a and a corresponding plurality of common relay terminals 13 are connected to each other by selection wiring 8 (not shown), the second relay terminal 12b and the third relay terminal 12c are not connected to the common relay terminal 13. In this way, an area where a plurality of relay terminals 12 that are not connected to the plurality of common relay terminals 13 are arranged can be defined as a surplus area E, and a plurality of bypass wirings 18 can be arranged on the main board 5 corresponding to the surplus area E. In the illustrated example, a plurality of first relay terminals 12a are connected to a plurality of common relay terminals 13, and a second relay terminal group A2 and a third relay terminal group A3 are arranged in the surplus area E. In such a case, a plurality of second relay terminals 12b and a plurality of third relay terminals 12c are connected to each other by bypass wirings 18, thereby forming a plurality of bypass paths. Therefore, the surplus area E can be effectively utilized.

[0035] Summary of the embodiment The semiconductor module 1 and the semiconductor device 10 described above will now be briefly summarized.

[0036] The semiconductor module (1) according to the present disclosure is a semiconductor module (1) that is mounted on a substrate (3) and includes a module substrate (4), at least one semiconductor element (2) mounted on a first surface of the module substrate (4), and a plurality of module terminals (T) arranged in a rectangular lattice pattern on a second surface of the module substrate (4). The module terminals (T) are terminals that are connected to target terminals (6) of the semiconductor element (2), and include a plurality of external connection terminals (11) that are arranged on the outer periphery of different sides of a rectangular arrangement area (7) of the plurality of module terminals (T); The module includes a plurality of relay terminals (12) electrically connected to the corresponding external connection terminals (11) via wiring on the module substrate (4) and arranged on the inner periphery of the external connection terminals (11), and at least one common relay terminal (12) electrically connected to the target terminal (6) via wiring on the module substrate (4), and one of the plurality of relay terminals (12) is selectively connected to the common relay terminal (12) on the mounted substrate (3), thereby selectively connecting one of the plurality of external connection terminals (11) to the target terminal (6).

[0037] This configuration allows one of the multiple relay terminals (12) to be selectively connected to the common relay terminal (13) on the substrate (3). Therefore, when the semiconductor module (1) is mounted on the substrate (3), the wiring distance between the external connection terminal (11) connected to the circuit on the substrate (3) and the target terminal (6) of the semiconductor element (2) can be kept short. This relatively simple configuration makes it easy to avoid degradation of signal quality (signal waveform) due to long wiring distances. Furthermore, this configuration minimizes variations in signal quality due to the length of the wiring distance, depending on the type of substrate (3) on which the semiconductor module (1) is mounted. Thus, this configuration allows the module terminal (T) to be positioned appropriately on the substrate (3).

[0038] It is preferable that the target terminals (6) are target terminal pairs that transmit differential signals, the plurality of external connection terminals (11) are external connection terminal pairs that correspond to the target terminal pairs, the plurality of relay terminals (12) are relay terminal pairs that correspond to the external connection terminal pairs, the common relay terminals (13) are common relay terminal (13) pairs that correspond to the target terminal pairs, and each of the relay terminal pairs is arranged side by side in a direction that is not parallel to any side of the rectangular array area (7).

[0039] In recent years, the use of differential signals has increased with the increase in processing speed. This configuration allows the same semiconductor module (1) to be mounted on various substrates (3) and allows appropriate transmission of differential signals. Furthermore, this configuration also allows multiple relay terminal pairs to be arranged in a direction that is not parallel to any of the sides of the rectangular array area (7) of the external connection terminals (11). By arranging these relay terminal pairs in a staggered pattern, it is easier to secure a larger area for arranging wiring for connection to other module terminals (T) than when the relay terminal pairs are arranged parallel to any of the sides of the array area (7).

[0040] The external connection terminals (11) include a first external connection terminal (11a), a second external connection terminal (11b), and a third external connection terminal (11c), and the first external connection terminal (11a), the second external connection terminal (11b), and the third external connection terminal (11c) are arranged on the outer periphery of different sides of the rectangular array area (7), and the relay terminals (12) include a first relay terminal (12a) connected to the first external connection terminal (11a), a second relay terminal (12b) connected to the second external connection terminal (11b), and a third relay terminal (11c) connected to the first external connection terminal (11a). and a third relay terminal (12c) connected to the third external connection terminal (11c), and it is preferable that, on the mounted substrate (3), the first relay terminal (12a) is selectively connected to the common relay terminal (13), thereby making the first external connection terminal (11a) selectively connectable to the target terminal (6), and that the second external connection terminal (11b) and the third external connection terminal (11c) are connectable by connecting the second relay terminal (12b) and the third relay terminal (12c).

[0041] Because the semiconductor module (1) is configured so that one of the multiple external connection terminals (11) is selectively connected to the target terminal (6), areas on the mounted substrate (3) that could be used for other wiring, such as areas where the unselected module terminals (T) contact the mounted substrate (3), become dead space, potentially reducing the wiring area. According to this configuration, by connecting the second relay terminal (12b) and the third relay terminal (12c) that are not connected to the common relay terminal (13), it is possible to electrically connect the second external connection terminal (11b) and the third external connection terminal (11c), thereby forming a so-called bypass path on the mounted substrate (3). Thus, according to this configuration, it is possible to effectively utilize the remaining terminals that are not connected to the semiconductor element (2) and secure the wiring area on the mounted substrate (3).

[0042] Furthermore, it is preferable that the semiconductor device (10) includes the semiconductor module (1) and a main board (5) as the mounted substrate (3), and the main board (5) includes a selection wiring (8) that connects the common relay terminal (13) to one of the plurality of relay terminals (12), and a signal wiring (9) that is connected to the external connection terminal (11) that is connected to the selected relay terminal (12).

[0043] According to this configuration, in the semiconductor device (10), the length of the signal wiring (9) can be kept short and the semiconductor module (1) can be appropriately mounted on the main board (5).

[0044] The semiconductor module and semiconductor device according to the present disclosure may have at least one of the above-described effects. [Explanation of symbols]

[0045] 1: Semiconductor module 2: Semiconductor element 3: Mounted substrate 4: Module substrate 5: Main substrate 6: Target terminal 7: Array area 8: Selection wiring 9: Signal wiring 10: Semiconductor device 11: External connection terminal 11a: First external connection terminal 11b: Second external connection terminal 11c: Third external connection terminal 12: Relay terminal 12a: First relay terminal 12b: Second relay terminal 12c: Third relay terminal 13: Common relay terminal T: Module terminal

Claims

1. A semiconductor module comprising: a module substrate; at least one semiconductor element mounted on a first surface of the module substrate; and a plurality of module terminals arranged in a rectangular lattice pattern on a second surface of the module substrate, the semiconductor module being mounted on a substrate to be mounted; The module terminal is a plurality of external connection terminals which are connected to target terminals of the semiconductor element and are arranged on outer peripheries of different sides of a rectangular array area of ​​the plurality of module terminals; a plurality of relay terminals electrically connected to the corresponding external connection terminals via wiring on the module substrate and disposed on the inner periphery side of the external connection terminals; at least one common relay terminal electrically connected to the target terminal via wiring on the module substrate; On the mounted substrate, one of the plurality of relay terminals is selectively connected to the common relay terminal, thereby selectively connecting one of the plurality of external connection terminals to the target terminal.

2. the target terminals are a target terminal pair that transmit differential signals, the plurality of external connection terminals are external connection terminal pairs each corresponding to the target terminal pair, the plurality of relay terminals are relay terminal pairs each corresponding to the external connection terminal pair, the common relay terminal is a common relay terminal pair corresponding to the target terminal pair, The semiconductor module according to claim 1 , wherein the relay terminal pairs are arranged side by side in a direction that is not parallel to any side of the rectangular array region.

3. The external connection terminals include a first external connection terminal, a second external connection terminal, and a third external connection terminal; the first external connection terminal, the second external connection terminal, and the third external connection terminal are arranged on outer circumferential sides of different sides of the rectangular array area, the relay terminals include a first relay terminal connected to the first external connection terminal, a second relay terminal connected to the second external connection terminal, and a third relay terminal connected to the third external connection terminal; 3. The semiconductor module according to claim 1, wherein, on the mounted substrate, the first relay terminal is selectively connected to the common relay terminal, thereby enabling the first external connection terminal to be selectively connected to the target terminal, and the second relay terminal is connected to the third relay terminal, thereby enabling the second external connection terminal to be connected to the third external connection terminal.

4. A semiconductor device comprising the semiconductor module according to claim 1 or 2 and a main substrate as the mounted substrate, The semiconductor device, wherein the main substrate is provided with a selection wiring that connects the common relay terminal to one of the plurality of relay terminals, and a signal wiring that is connected to the external connection terminal that is connected to the selected relay terminal.

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