Semiconductor device and method for manufacturing the same

Abstract

To reduce the on-resistance of a semiconductor device.SOLUTION: A semiconductor device includes a semiconductor chip 8 having a first main surface 10 and a second main surface 11, a first semiconductor region 46A of a first conductivity type formed on the first main surface 10 side of the semiconductor chip 8, a second semiconductor region 46B of a second conductivity type formed on the second main surface 11 side of the first semiconductor region 46A, a trench structure 17 including a trench 48 penetrating from the first main surface 10 through the first semiconductor region 46A, and a third semiconductor region 46C of the first conductivity type formed on the second main surface 11 side of the second semiconductor region 46B and located on the second main surface 11 side of the trench structure 17 across the second semiconductor region 46B.SELECTED DRAWING: Figure 14

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor chip having a first main surface, an n-type drift layer formed on a surface portion of the first main surface, a trench gate structure formed on the first main surface so as to be in contact with the drift layer, a p-type channel region formed in the drift layer so as to cover the sidewall of the trench gate structure, and a first source / drain region and a second source / drain region formed at an interval in the drift layer in a region along the sidewall of the trench gate structure so as to face each other across the channel region. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2021 / 065740

[0004] [overview] There is a demand for a semiconductor device that can reduce the on-resistance. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a circuit diagram of a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a schematic perspective view of the semiconductor device according to the first embodiment of the present disclosure. [Figure 3] FIG. 3 is a plan view of the semiconductor device of FIG. [Figure 4] FIG. 4 is a plan view showing the internal structure of the semiconductor device of FIG. [Figure 5] FIG. 5 is a plan view showing the internal structure of the semiconductor device of FIG. [Figure 6] FIG. 6 is a plan view showing the internal structure of the semiconductor device of FIG. [Figure 7] FIG. 7 is a plan view showing the internal structure of the semiconductor device of FIG. [Figure 8] FIG. 8 is an enlarged view of the part surrounded by the two-dot chain line VIII in FIG. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. [Figure 10] FIG. 10 is a cross-sectional view taken along line XX in FIG. [Figure 11] FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. [Figure 12] FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. [Figure 13A] FIG. 13A is a diagram showing a part of the manufacturing process of the semiconductor device according to the first embodiment of the present disclosure. [Figure 13B] FIG. 13B shows the next step in FIG. 13A. [Figure 13C] FIG. 13C shows the next step in FIG. 13B. [Figure 13D] FIG. 13D shows the next step in FIG. 13C. [Figure 13E] FIG. 13E shows the next step in FIG. 13D. [Figure 13F] FIG. 13F shows the next step in FIG. 13E. [Figure 13G] FIG. 13G shows the next step in FIG. 13F. [Figure 13H] FIG. 13H shows the next step in FIG. 13G. [Figure 13I] FIG. 13I shows the next step of FIG. 13H. [Figure 13J] FIG. 13J shows the next step of FIG. 13I. [Figure 14] FIG. 14 is a cross-sectional view showing a current path in the semiconductor device according to the first embodiment of the present disclosure. [Figure 15] FIG. 15 is a plan view showing a current path of the semiconductor device according to the first embodiment of the present disclosure. [Figure 16]FIG. 16 is a cross-sectional view showing a first modification of the semiconductor device according to the first embodiment of the present disclosure. [Figure 17] FIG. 17 is a cross-sectional view showing a second modification of the semiconductor device according to the first embodiment of the present disclosure. [Figure 18] FIG. 18 is a cross-sectional view showing a third modification of the semiconductor device according to the first embodiment of the present disclosure. [Figure 19] FIG. 19 is a schematic plan view showing the internal structure of the semiconductor device according to the second embodiment of the present disclosure. [Figure 20] FIG. 20 is an enlarged view of the portion surrounded by the two-dot chain line XX in FIG. [Figure 21] FIG. 21 is an enlarged view of the portion surrounded by the two-dot chain line XX in FIG. [Figure 22] FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. [Figure 23] FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. [Figure 24] FIG. 24 is a cross-sectional view taken along line XXIV-XXIV in FIG. [Figure 25] FIG. 25 is a cross-sectional view showing a current path in the semiconductor device according to the second embodiment of the present disclosure. [Figure 26] FIG. 26 is a plan view showing a current path of the semiconductor device according to the second embodiment of the present disclosure. [Figure 27] FIG. 27 is a plan view showing a modified example of the semiconductor device according to the second embodiment of the present disclosure.

[0006] [Detailed explanation] [First embodiment] (Structure of semiconductor device 1A) FIG. 1 is a circuit diagram of a semiconductor device 1A according to a first embodiment of the present disclosure.

[0007] The semiconductor device 1A includes a common source-drain type MISFET (Metal Insulator Semiconductor Field Effect Transistor) 2. The MISFET 2 includes a base B, a gate G, a first source-drain SD1, and a second source-drain SD2. The first source-drain SD1 and the second source-drain SD2 serve as both a source and a drain. For example, depending on the connection topology of the semiconductor device 1A, the first source-drain SD1 may be the source and the second source-drain SD2 may be the drain. Alternatively, the first source-drain SD1 may be the drain and the second source-drain SD2 may be the source.

[0008] A reference voltage (for example, ground voltage) is applied to the base B. A gate voltage VG, which is referenced to the base B, is applied to the gate G. The gate G controls the conduction and blocking of a current I flowing between the first source-drain SD1 and the second source-drain SD2. A first source-drain voltage VSD1 (first voltage) is applied to the first source-drain SD1. A second source-drain voltage VSD2 (second voltage), which is different from the first source-drain voltage VSD1, is applied to the second source-drain SD2.

[0009] The semiconductor device 1A further includes a diode pair 3 connected to the first source-drain SD1 and the second source-drain SD2. The diode pair 3 regulates (blocks) the current I flowing between the first source-drain SD1 and the second source-drain SD2 when the MISFET 2 is in an off state.

[0010] Specifically, the diode pair 3 includes a first body diode D1 and a second body diode D2 that are reverse-bias connected. The first body diode D1 and the second body diode D2 each include an anode and a cathode.

[0011] The anode of the first body diode D1 is connected to the base B. The cathode of the first body diode D1 is connected to the first source-drain SD1. The anode of the second body diode D2 is connected to the base B. The cathode of the second body diode D2 is connected to the second source-drain SD2.

[0012] The semiconductor device 1A is a four-terminal device including four external terminals 4, 5, 6, and 7. Specifically, the external terminals 4 to 7 include a base terminal 4, a gate terminal 5, a first source-drain terminal 6, and a second source-drain terminal 7. The base terminal 4 is connected to the base B. The gate terminal 5 is connected to the gate G. The first source-drain terminal 6 is connected to the first source-drain SD1. The second source-drain terminal 7 is connected to the second source-drain SD2.

[0013] The MISFET2 is a bidirectional device that can conduct current I in both directions between the first source-drain terminal 6 and the second source-drain terminal 7. That is, when the first source-drain terminal 6 is connected to the high voltage side (input side), the second source-drain terminal 7 is connected to the low voltage side (output side). On the other hand, when the first source-drain terminal 6 is connected to the low voltage side (output side), the second source-drain terminal 7 is connected to the high voltage side (input side).

[0014] When a gate voltage VG (Vth ≤ VG) equal to or higher than the gate threshold voltage Vth is applied to the gate terminal 5, a current I flows between the first source-drain terminal 6 and the second source-drain terminal 7. When a gate voltage VG (VG < Vth) lower than the gate threshold voltage Vth is applied to the gate terminal 5, no current I flows between the first source-drain terminal 6 and the second source-drain terminal 7. In this way, the on / off of the MISFET2 is controlled.

[0015] The semiconductor device 1A can realize the function of a circuit in which the drains of two non-common source-drain MISFETs are connected to each other using a single MISFET 2. Therefore, the semiconductor device 1A can achieve low on-resistance by shortening the current path. The specific structure of the semiconductor device 1A will be described below.

[0016] Fig. 2 is a schematic perspective view of a semiconductor device 1A according to a first embodiment of the present disclosure. Fig. 3 is a plan view of the semiconductor device 1A of Fig. 2. Below, an example will be described in which the semiconductor device 1A is formed of a chip-size package having the same size as the chip.

[0017] 2 and 3, the semiconductor device 1A has a laminated structure including a semiconductor chip 8 and an insulating layer 9. As shown in FIG. The semiconductor chip 8 is formed in a rectangular parallelepiped shape. The semiconductor chip 8 includes a first main surface 10 on one side, a second main surface 11 on the other side, and side surfaces 12A, 12B, 12C, and 12D connecting the first main surface 10 and the second main surface 11. The side surfaces 12A to 12D specifically include the first side surface 12A, the second side surface 12B, the third side surface 12C, and the fourth side surface 12D.

[0018] The insulating layer 9 is formed on the first main surface 10. The insulating layer 9 includes an insulating main surface 13 and insulating side surfaces 14A, 14B, 14C, and 14D. The insulating side surfaces 14A to 14D specifically include a first insulating side surface 14A, a second insulating side surface 14B, a third insulating side surface 14C, and a fourth insulating side surface 14D. The insulating side surfaces 14A to 14D extend from the periphery of the insulating main surface 13 toward the semiconductor chip 8 and are continuous with the side surfaces 12A to 12D. Specifically, the insulating side surfaces 14A to 14D are formed flush with the side surfaces 12A to 12D.

[0019] The external terminals 4 to 7 are formed on the insulating main surface 13. In this embodiment, the external terminals 4 to 7 are arranged in a matrix of 5 rows and 5 columns at intervals in the first direction X and the second direction Y.

[0020] The base terminal 4 is arranged in the third row and the first column. The gate terminal 5 is arranged in the third row and the fifth column. The gate terminal 5 faces the base terminal 4 in the first direction X. The plurality of first source-drain terminals 6 are arranged in the first to fifth columns of the first row and the first to fifth columns of the fourth row. The plurality of second source-drain terminals 7 are arranged in the first to fifth columns of the second row and the first to fifth columns of the fifth row.

[0021] The second source-drain terminals 7 arranged in the second row face the first source-drain terminals 6 arranged in the first row in a one-to-one correspondence in the second direction Y. The second source-drain terminals 7 arranged in the fifth row face the first source-drain terminals 6 arranged in the fourth row in a one-to-one correspondence in the second direction Y.

[0022] In this embodiment, spaces are provided in the second, third, and fourth columns of the third row. Any one of the base terminal 4, gate terminal 5, first source / drain terminal 6, and second source / drain terminal 7 may be arranged in each space. An electrically open terminal may be arranged in each space. The number and arrangement of the base terminals 4, gate terminals 5, first source / drain terminals 6, and second source / drain terminals 7 are arbitrary and are not limited to the number and arrangement shown in FIGS. 2 and 3.

[0023] Figures 4 to 7 are plan views showing the internal structure of the semiconductor device 1A of Figure 2. Figure 4 shows the planar structure of the semiconductor chip 8, and Figures 5 to 7 show the wiring pattern inside the insulating layer 9. 4 to 7, an active area 15 and a peripheral area 16 surrounding the active area 15 are defined on a first main surface 10 of the semiconductor chip 8. As shown in FIG.

[0024] The outer peripheral region 16 may coincide with the annular peripheral portion along the side surfaces 12A to 12D of the semiconductor chip 8. The outer peripheral region 16 may be an annular region extending from the side surfaces 12A to 12D of the semiconductor chip 8 to a position several μm inward. The active region 15 may be a central region of the semiconductor chip 8 surrounded by the outer peripheral region 16. The active region 15 may be, for example, a region in which most of the element structure of the MISFET 2 is formed.

[0025] 4, an element structure of a MISFET 2 is formed in the active region 15. In this embodiment, the element structure is a trench gate lateral type MISFET (Metal Insulator Semiconductor Field Effect Transistor) structure.

[0026] The MISFET 2 includes a first trench structure 17 and a trench connection structure 18 as trench structures formed on the first main surface 10. The first trench structure 17 may also be referred to as a "trench gate structure." The multiple first trench structures 17 are each formed in an inner portion of the first main surface 10 at intervals from the periphery of the first main surface 10. The multiple first trench structures 17 are arranged at intervals in the first direction X and each formed in a band shape extending in the second direction Y. The multiple first trench structures 17 are formed in a stripe shape extending in the second direction Y in a plan view. Each of the multiple first trench structures 17 has a first end on one side and a second end on the other side in the second direction Y.

[0027] The trench connection structure 18 is connected to the first trench structure 17. The multiple (two in this embodiment) trench connection structures 18 include a trench connection structure 18 on one side (the third side surface 12C side) that connects first ends of the multiple first trench structures 17, and a trench connection structure 18 on the other side (the fourth side surface 12D side) that connects second ends of the multiple first trench structures 17.

[0028] The trench connection structure 18 is formed in an inner portion of the first main surface 10 at a distance from the periphery of the first main surface 10. The trench connection structure 18 is formed in a strip shape extending in a direction (specifically, the first direction X) intersecting the direction in which the plurality of first trench structures 17 extend, and is connected to first ends and second ends of the plurality of first trench structures 17. As a result, a plurality of closed regions surrounded by pairs of first trench structures 17 and pairs of trench connection structures 18 are formed on the first main surface 10.

[0029] Each of the multiple closed regions 19-21 is sandwiched between first trench structures 17 in the first direction X, and is formed in a strip shape extending in the second direction Y. The multiple closed regions 19-21 are arranged in the first direction X, separated by the first trench structures 17, and are formed in a stripe shape as a whole. The multiple closed regions 19-21 may include a first source / drain region 19, a second source / drain region 20, and a drift region 21.

[0030] In this embodiment, a first source / drain region 19 and a second source / drain region 20 face each other across a drift region 21. A first trench structure 17 is formed between the first source / drain region 19 and the drift region 21, and between the drift region 21 and the second source / drain region 20, to separate them.

[0031] The plurality of first source / drain regions 19 and the plurality of second source / drain regions 20 are alternately arranged at intervals in the first direction X so that the drift region 21 is sandwiched between adjacent first source / drain regions 19 and second source / drain regions 20. In FIG. 4, from the left side of the page, a set of the first source / drain region 19, the drift region 21, the second source / drain region 20, and the drift region 21 is repeatedly arranged in the first direction X.

[0032] A first contact region 22 is formed in the first source / drain region 19. The first contact region 22 may also be referred to as a "first source / drain contact region." In this embodiment, a strip-shaped first contact region 22 extending in the second direction Y is formed in an inner region of each first source / drain region 19. The first contact region 22 has an annular outer periphery at a portion spaced inward from the first trench structure 17 and the trench connection structure 18.

[0033] A first lower contact 23 is formed in the first contact region 22. The first lower contact 23 may also be referred to as a "first source-drain contact." In this embodiment, a plurality of first lower contacts 23 are formed at intervals in the second direction Y. Each first lower contact 23 is formed in a rectangular shape in plan view that is long along the second direction Y. Only one first lower contact 23 may be formed in each first contact region 22.

[0034] A second contact region 24 is formed in the second source / drain region 20. The second contact region 24 may also be referred to as a "second source / drain contact region." In this embodiment, a strip-shaped second contact region 24 extending in the second direction Y is formed in an inner region of each second source / drain region 20. The second contact region 24 has an annular outer periphery at a portion spaced inward from the first trench structure 17 and the trench connection structure 18.

[0035] A second lower contact 25 is formed in the second contact region 24. The second lower contact 25 may also be referred to as a "second source-drain contact." In this embodiment, a plurality of second lower contacts 25 are formed at intervals in the second direction Y. Each second lower contact 25 is formed in a rectangular shape in plan view that is long along the second direction Y. Only one second lower contact 25 may be formed in each second contact region 24.

[0036] A first base contact 26 is formed in the drift region 21. In this embodiment, a plurality of first base contacts 26 are formed at intervals in the second direction Y. Each first base contact 26 is formed in a rectangular shape in plan view that is long along the second direction Y. Only one first base contact 26 may be formed in each drift region 21.

[0037] In this embodiment, first lower contact 23, second lower contact 25, and first base contact 26 are electrically isolated from one another and fixed to different potentials. The plurality of first lower contacts 23, the plurality of second lower contacts 25, and the plurality of first base contacts 26 are discretely arranged on first main surface 10. In this embodiment, the plurality of first lower contacts 23, the plurality of second lower contacts 25, and the plurality of first base contacts 26 are arranged with a regularity such that contacts of the same type (same potential) are aligned in first direction X.

[0038] 4, from the top of the page, a row of multiple first lower contacts 23 aligned in the first direction X, a row of multiple first base contacts 26 aligned in the first direction X, and a row of multiple second lower contacts 25 aligned in the first direction X are formed in this order. As a result, the multiple first lower contacts 23, the multiple second lower contacts 25, and the multiple first base contacts 26 do not face contacts of different types in the first direction X.

[0039] A first gate contact 27 is formed in the trench connection structure 18. In this embodiment, the plurality of first gate contacts 27 are arranged at intervals in the first direction X. The plurality of first gate contacts 27 may include a first gate contact 27 arranged at an intersection of the trench connection structure 18 and the first trench structure 17. The plurality of first gate contacts 27 may be arranged at a position facing at least one of the first source / drain region 19, the second source / drain region 20, and the drift region 21 in the second direction Y.

[0040] 5 to 7, a plurality of wiring layers are formed on the first main surface 10 of the semiconductor chip 8, and the above-mentioned plurality of external terminals are connected to the uppermost layer of the plurality of wiring layers. The plurality of wiring layers form a multilayer wiring structure, and include, for example, a first wiring layer 28 shown by a solid line in FIG. 5 and a second wiring layer 29 shown by a solid line in FIG. 6, in this order from the first main surface 10 upward. In this embodiment, the external terminals are connected to the second wiring layer 29, as shown in FIG. 7.

[0041] The first wiring layer 28 may be referred to as a "first metal." Referring to FIG. 5, the first wiring layer 28 includes a first gate wiring layer 30, a first lower wiring layer 31, a second lower wiring layer 32, and a first base wiring layer 33. The first gate wiring layer 30, the first lower wiring layer 31, the second lower wiring layer 32, and the first base wiring layer 33 are wiring layers that are physically independent from one another. The first lower wiring layer 31 may be referred to as a "first lower source / drain wiring layer." The second lower wiring layer 32 may be referred to as a "second lower source / drain wiring layer."

[0042] The first gate wiring layer 30 is formed along the outer periphery region 16 of the semiconductor chip 8. The first gate wiring layer 30 has a shape that surrounds the active region 15. For example, the first gate wiring layer 30 surrounds the active region 15 from three sides and has a shape that is open on one side (the first side surface 12A in FIG. 5) of the side surfaces 12A to 12D of the semiconductor chip 8. The first gate wiring layer 30 is formed by three straight line portions that extend along the outer periphery region 16. Of the three straight line portions, a pair of straight line portions that face each other in the second direction Y cover the plurality of first gate contacts 27 and are connected to the plurality of first gate contacts 27.

[0043] The first lower wiring layer 31 is formed to cover the first lower contacts 23 and is connected to the first lower contacts 23. In this embodiment, the first lower wiring layer 31 is formed in a strip shape extending in the first direction X so as to collectively cover the plurality of first lower contacts 23 that are linearly aligned in the first direction X.

[0044] The second lower wiring layer 32 is formed to cover the second lower contacts 25 and is connected to the second lower contacts 25. In this embodiment, the second lower wiring layer 32 is formed in a strip shape extending in the first direction X so as to collectively cover the plurality of second lower contacts 25 that are linearly aligned in the first direction X.

[0045] The plurality of first lower wiring layers 31 and the plurality of second lower wiring layers 32 are alternately arranged at intervals in the second direction Y. In this embodiment, two strip-shaped first lower wiring layers 31 and two strip-shaped second lower wiring layers 32 are formed in a stripe pattern at intervals from each other.

[0046] The first base wiring layer 33 is formed to cover the first base contacts 26 and is connected to the first base contacts 26. In this embodiment, the first base wiring layer 33 is formed in a strip shape extending in the first direction X so as to collectively cover the multiple first base contacts 26 that are linearly aligned in the first direction X. In this embodiment, the strip-shaped first base wiring layers 33 are arranged one by one in the region between the first lower wiring layer 31 and the second lower wiring layer 32. All of the first base wiring layers 33 are connected collectively on the open side (the side of the first side surface 12A) of the first gate wiring layer 30.

[0047] The second wiring layer 29 may be referred to as a "second metal." Referring to FIG. 6, the second wiring layer 29 includes a second gate wiring layer 34, a first upper wiring layer 35, a second upper wiring layer 36, and a second base wiring layer 37. The second gate wiring layer 34, the first upper wiring layer 35, the second upper wiring layer 36, and the second base wiring layer 37 are wiring layers that are physically independent from one another. The first upper wiring layer 35 may be referred to as a "first upper source-drain wiring layer." The second upper wiring layer 36 may be referred to as a "second upper source-drain wiring layer." In FIG. 6, the first wiring layer 28 is indicated by a dashed line to clarify the relationship between the second wiring layer 29 and the first wiring layer 28.

[0048] The second gate wiring layer 34 and the second base wiring layer 37 are each formed in a rectangular shape in a plan view. The second gate wiring layer 34 and the second base wiring layer 37 are formed in positions facing each other in the first direction X in the center of the semiconductor chip 8 in the second direction Y. In this embodiment, the second gate wiring layer 34 is arranged near the first side surface 12A of the side surfaces 12A to 12D of the semiconductor chip 8, and the second base wiring layer 37 is arranged near the opposite second side surface 12B. The second gate wiring layer 34 is connected to the first gate wiring layer 30 via a second gate contact 38. The second base wiring layer 37 is connected to the first base wiring layer 33 via a second base contact 39.

[0049] The first upper wiring layer 35 is formed in a strip shape extending along the first lower wiring layer 31, and covers the first lower wiring layer 31. The first upper wiring layer 35 is connected to the first lower wiring layer 31 via a first upper contact 40. A plurality of first upper contacts 40 may be formed and arranged at intervals in the first direction X.

[0050] The second upper wiring layer 36 is formed in a strip shape extending along the second lower wiring layer 32, and covers the second lower wiring layer 32. The second upper wiring layer 36 is connected to the second lower wiring layer 32 via second upper contacts 41. A plurality of second upper contacts 41 may be formed and arranged at intervals in the first direction X.

[0051] 7, the plurality of external terminals are arranged on corresponding second wiring layers 29. In FIG. 7, the second wiring layers 29 are shown by dashed lines to clarify the relationship between the plurality of external terminals and the second wiring layers 29.

[0052] The gate terminal 5 is provided on the second gate wiring layer 34 and connected to the second gate wiring layer 34 via a gate terminal contact 42. The base terminal 4 is provided on the second base wiring layer 37 and connected to the second base wiring layer 37 via a base terminal contact 43.

[0053] The multiple first source-drain terminals 6 are arranged at intervals in the longitudinal direction of the strip-shaped first upper wiring layer 35. Each of the first source-drain terminals 6 is connected to the first upper wiring layer 35 via a first terminal contact 44.

[0054] The second source-drain terminals 7 are arranged at intervals in the longitudinal direction of the strip-shaped second upper wiring layer 36. Each second source-drain terminal 7 is connected to the second upper wiring layer 36 via a second terminal contact 45.

[0055] Fig. 8 is an enlarged view of a portion surrounded by a two-dot chain line VIII in Fig. 4. Fig. 9 is a cross-sectional view taken along line IX-IX in Fig. 8. Fig. 10 is a cross-sectional view taken along line XX in Fig. 8. Fig. 11 is a cross-sectional view taken along line XI-XI in Fig. 8. Fig. 12 is a cross-sectional view taken along line XII-XII in Fig. 8.

[0056] 9 to 12, the semiconductor device 1A includes a semiconductor chip 8. The semiconductor chip 8 is, for example, a semiconductor chip 8 made of a single layer. The semiconductor chip 8 made of a single layer has a single structure of a semiconductor substrate without an epitaxial layer. In this embodiment, the semiconductor chip 8 includes a single crystal of Si (silicon) or a wide bandgap semiconductor without an epitaxial layer. A wide bandgap semiconductor is a semiconductor having a bandgap greater than the bandgap of Si. The semiconductor chip 8 may be a Si chip or a SiC (silicon carbide) chip.

[0057] The semiconductor device 1A includes a first semiconductor region 46A of n-type (first conductivity type) formed in a region on the first main surface 10 side in the semiconductor chip 8. The first semiconductor region 46A may be referred to as a "drift layer." The first semiconductor region 46A is formed in the semiconductor chip 8 at an interval from the second main surface 11 toward the first main surface 10. The first semiconductor region 46A is formed in a layer shape extending along the first main surface 10 in a surface layer portion of the first main surface 10, and is exposed from the entire first main surface 10 and parts of the first to fourth side surfaces 12A to 12D.

[0058] Of course, the first semiconductor region 46A may be formed in the inner part of the first main surface 10 at intervals from the first to fourth side surfaces 12A to 12D in a plan view. 14 cm -3 More than 1×10 18 cm -3 The first semiconductor region 46A may have an n-type impurity concentration of 0.05 to 0.05 μm. The n-type impurity concentration of the first semiconductor region 46A may be constant or may vary. In one example, the n-type impurity concentration of the first semiconductor region 46A decreases from the first main surface 10 side toward the second main surface 11 side. In this case, the n-type impurity concentration may be, for example, an average concentration.

[0059] The semiconductor device 1A includes a p-type (second conductivity type) second semiconductor region 46B formed in a region closer to the second main surface 11 than the first semiconductor region 46A in the semiconductor chip 8. The p-type impurity concentration of the second semiconductor region 46B will be described later.

[0060] The second semiconductor region 46B is formed in the semiconductor chip 8 at a distance from the second main surface 11 toward the first main surface 10. The second semiconductor region 46B is formed in a layer shape extending along the first main surface 10 (first semiconductor region 46A) in the semiconductor chip 8, and is exposed from a portion of the first to fourth side surfaces 12A to 12D. The second semiconductor region 46B is electrically connected to the first semiconductor region 46A in the semiconductor chip 8. Specifically, the second semiconductor region 46B forms a pn junction with the first semiconductor region 46A.

[0061] The semiconductor device 1A includes an n-type (first conductivity type) third semiconductor region 46C formed in a region closer to the second main surface 11 than the second semiconductor region 46B in the semiconductor chip 8. In other words, the third semiconductor region 46C is formed on the second main surface 11 side in the thickness direction of the semiconductor chip 8, sandwiching the second semiconductor region 46B therebetween. The third semiconductor region 46C has a capacitance of 1×10 14 cm -3 More than 1×10 18 cm -3The third semiconductor region 46C may have an n-type impurity concentration equal to or lower than the n-type impurity concentration of the first semiconductor region 46A. In one example, the n-type impurity concentration of the third semiconductor region 46C is lower than the n-type impurity concentration of the first semiconductor region 46A. In this case, the n-type impurity concentration may be, for example, an average concentration.

[0062] The third semiconductor region 46C is formed in a layer shape extending along the first main surface 10 (second semiconductor region 46B) and is exposed from parts of the first to fourth side surfaces 12A to 12D. The third semiconductor region 46C is electrically connected to the second semiconductor region 46B within the semiconductor chip 8.

[0063] Therefore, the semiconductor device 1A includes, in the thickness direction of the semiconductor chip 8, an n-type (first conductivity type) first semiconductor region 46A formed on the first main surface 10 side, a p-type (second conductivity type) second semiconductor region 46B formed on the second main surface 11 side of the first semiconductor region 46A, and an n-type (first conductivity type) third semiconductor region 46C formed on the second main surface 11 side of the second semiconductor region 46B. The second semiconductor region 46B electrically separates the first semiconductor region 46A and the third semiconductor region 46C. Details of the first semiconductor region 46A, the second semiconductor region 46B, and the third semiconductor region 46C will be described later.

[0064] The semiconductor device 1A includes a fourth semiconductor region 46D of p-type (second conductivity type) formed in a region closer to the second main surface 11 than the third semiconductor region 46C in the semiconductor chip 8. The fourth semiconductor region 46D may also be referred to as a "base layer." The fourth semiconductor region 46D has a density of 1×10 13 cm -3 More than 1×10 16 cm -3 The p-type impurity concentration may be as follows:

[0065] The plurality of first trench structures 17 penetrate the first semiconductor region 46A to reach the second semiconductor region 46B. In this embodiment, the plurality of first trench structures 17 each have a bottom wall located within the second semiconductor region 46B. The plurality of first trench structures 17 are configured to respectively control inversion and non-inversion of a channel (a channel 96 described below) in the second semiconductor region 46A.

[0066] The plurality of first trench structures 17 may be arranged at intervals (pitch) of 0.02 μm or more and 20 μm or less (preferably 0.2 μm or more and 5 μm or less). The plurality of first trench structures 17 are preferably arranged at approximately equal intervals in the first direction X. Each of the plurality of first trench structures 17 may have a width in the first direction X of 0.01 μm or more and 10 μm or less (preferably 0.1 μm or more and 0.5 μm or less). Each of the plurality of first trench structures 17 may have a depth of 0.2 μm or more and 30 μm or less (preferably 0.5 μm or more and 10 μm or less).

[0067] The following describes the internal structure of one first trench structure 17. The first trench structure 17 includes a first trench 48, a gate insulating film 49 (control insulating film), a gate electrode 50 (control electrode), and a buried insulator 51.

[0068] The first trench 48 may also be referred to as a "gate trench." The first trench 48 is formed in the first main surface 10 and defines the wall surfaces (side walls and bottom wall) of the first trench structure 17. The first trench 48 exposes the first semiconductor region 46A and the second semiconductor region 46B from the wall surfaces.

[0069] The first trench 48 may be formed in a tapered shape in which the opening width narrows from the first main surface 10 side toward the bottom wall side in a cross-sectional view. Of course, the first trench 48 may be formed perpendicular to the first main surface 10. The corners on the bottom wall side of the first trench 48 may be formed in a curved shape. Of course, the entire bottom wall of the first trench 48 may be formed in a curved shape toward the second main surface 11 side.

[0070] The gate insulating film 49 covers the sidewalls and bottom wall of the first trench 48 in a film-like manner. In this embodiment, the gate insulating film 49 covers the sidewalls and bottom wall of the first trench 48 on the bottom wall side, and defines a recess space on the bottom wall side of the first trench 48. The gate insulating film 49 may have a thickness of 5 nm to 1000 nm in the normal direction to the wall surface of the first trench 48. The gate insulating film 49 includes at least one of a silicon oxide film, a silicon nitride film, an aluminum oxide film, a zirconium oxide film, a hafnium oxide film, and a tantalum oxide film. The gate insulating film 49 is preferably made of a silicon oxide film. It is particularly preferable that the gate insulating film 49 be made of an oxide (thermal oxide film) of the semiconductor chip 8.

[0071] The gate electrode 50 is embedded in the first trench 48 with a gate insulating film 49 sandwiched therebetween. Specifically, the gate electrode 50 is embedded in a recess space defined by the gate insulating film 49 on the bottom wall side of the first trench 48, and faces the second semiconductor region 46B and the third semiconductor region 46C with the gate insulating film 49 sandwiched therebetween. The gate electrode 50 crosses the depth position of a boundary portion 60A between the first semiconductor region 46A and the second semiconductor region 46B in the depth direction of the first trench 48.

[0072] 8 and 12, the gate electrode 50 includes a plurality of lead-out portions 52 that are led from the bottom wall side of the first trench 48 to the opening side. The number of the lead-out portions 52 is arbitrary. In this embodiment, the plurality of lead-out portions 52 includes a pair of lead-out portions 52 that are spaced apart in the second direction Y. In this embodiment, the pair of lead-out portions 52 are formed at both ends of the first trench 48, respectively. The plurality of lead-out portions 52 each extend in the second direction Y in a plan view.

[0073] The multiple lead-out portions 52 define an opening-side recess from the wall surface of the first trench 48 on the opening side of the first trench 48. The opening-side recess is defined in a strip shape extending in the second direction Y in a plan view. The multiple lead-out portions 52 may protrude above the first main surface 10. The multiple lead-out portions 52 may be led out from the first trench 48 onto the first main surface 10 with part of the gate insulating film 49 sandwiched between them. Of course, the multiple lead-out portions 52 may be located on the bottom wall side of the first trench 48 with respect to the first main surface 10.

[0074] The gate electrode 50 may include at least one of a metal and a non-metal conductor. The gate electrode 50 may include at least one of tungsten, aluminum, copper, an aluminum alloy, a copper alloy, and conductive polysilicon. The gate electrode 50 preferably includes a non-metal conductor (conductive polysilicon). The conductive polysilicon may be p-type polysilicon or n-type polysilicon. The conductive polysilicon is preferably n-type polysilicon.

[0075] The buried insulator 51 is buried on the opening side of the first trench 48 so as to cover the gate electrode 50 within the first trench 48. Specifically, the buried insulator 51 is buried in a recess on the opening side defined by the gate electrode 50. The buried insulator 51 is provided as a field insulator that relieves the electric field with respect to the first trench 48. The buried insulator 51 is configured so that the area facing the first semiconductor region 46A exceeds the area of ​​the gate electrode 50 facing the second semiconductor region 46B.

[0076] The buried insulator 51 has a thickness greater than the thickness of the gate electrode 50 in the depth direction of the first trench 48. The buried insulator 51 includes at least one of a silicon oxide film, a silicon nitride film, an aluminum oxide film, a zirconium oxide film, a hafnium oxide film, and a tantalum oxide film. The buried insulator 51 is preferably made of a silicon oxide film. The buried insulator 51 is preferably made of the same material as the gate insulating film 49. In this case, the buried insulator 51 is preferably made of an insulating vapor-deposited film and has a density different from that of the gate insulating film 49.

[0077] 8 to 11, the semiconductor device 1A includes a plurality of mesas 53 to 55 defined on the first main surface 10 (first semiconductor region 46A) by a plurality of first trench structures 17. The plurality of mesas 53 to 55 are defined in strip shapes extending in the second direction Y in regions between pairs of adjacent first trench structures 17. The plurality of mesas 53 to 55 include a plurality of first mesas 53, a plurality of second mesas 54, and a plurality of drift mesas 55.

[0078] The first mesa 53 and the second mesa 54 are arranged at an interval in the first direction X so as to sandwich one drift mesa 55 therebetween. The first mesa 53 forms a first source / drain region 19 and may be referred to as a "first source / drain mesa." The second mesa 54 forms a second source / drain region 20 and may be referred to as a "second source / drain mesa." The drift mesa 55 forms a drift region 21.

[0079] 8 and 12, the trench connection structures 18 penetrate the first semiconductor region 46A to reach the second semiconductor region 46B. That is, the trench connection structures 18, together with the first trench structures 17, define the mesas 53 to 55 (the first mesas 53, the second mesas 54, and the drift mesas 55).

[0080] The trench connection structure 18 may have a width in the second direction Y of 0.01 μm or more and 10 μm or less (preferably 0.1 μm or more and 2 μm or less). The trench connection structure 18 may have a width approximately equal to the width of the first trench structure 17. The trench connection structures 18 may each have a depth of 0.2 μm or more and 30 μm or less (preferably 0.5 μm or more and 10 μm or less). The trench connection structure 18 may have a depth approximately equal to the depth of the first trench structure 17.

[0081] The trench connection structure 18 includes a connection trench 56, a connection insulating film 57, and a connection electrode 58. The connection trench 56 is formed in the first main surface 10 so as to communicate with the plurality of first trenches 48, and defines the wall surfaces (side walls and bottom wall) of the trench connection structure 18. The wall surfaces (side walls and bottom wall) of the trench connection structure 18 are continuous with the wall surfaces (side walls and bottom wall) of the plurality of first trenches 48. The connection trench 56 exposes the first semiconductor region 46A and the second semiconductor region 46B from the wall surfaces.

[0082] The connection trench 56 may be formed in a tapered shape in which the opening width narrows from the first main surface 10 side toward the bottom wall side in a cross-sectional view. Of course, the connection trench 56 may be formed perpendicular to the first main surface 10. The corners on the bottom wall side of the connection trench 56 may be formed in a curved shape. Of course, the entire bottom wall of the connection trench 56 may be formed in a curved shape toward the second main surface 11 side.

[0083] The connection insulating film 57 coats the sidewalls and bottom wall of the connection trench 56 in a film-like manner. In this embodiment, the connection insulating film 57 coats the sidewalls and bottom wall on the opening side and bottom wall side of the connection trench 56, and defines a recess space within the connection trench 56. The connection insulating film 57 is continuous with the plurality of gate insulating films 49 at the communicating portions with the plurality of first trenches 48.

[0084] The connection insulating film 57 may have a thickness of 5 nm or more and 1000 nm or less. The connection insulating film 57 preferably has a thickness approximately equal to that of the gate insulating film 49. The connection insulating film 57 includes at least one of a silicon oxide film, a silicon nitride film, an aluminum oxide film, a zirconium oxide film, a hafnium oxide film, and a tantalum oxide film. The connection insulating film 57 is preferably made of the same material as the gate insulating layer.

[0085] The connection electrode 58 is embedded in the connection trench 56 with the connection insulating film 57 interposed therebetween, and faces the first semiconductor region 46A and the second semiconductor region 46B. The connection electrode 58 is connected to the plurality of gate electrodes 50 at the communicating portions with the plurality of first trenches 48. Specifically, the connection electrode 58 is connected to the plurality of lead-out portions 52. As a result, the connection electrode 58 is fixed to the same potential as the gate electrodes 50.

[0086] The portion of the connection electrode 58 that is continuous with the drawn-out portion 52 may be included in the components of the connection electrode 58, or may be included in the components of the gate electrode 50. The connection electrode 58 has an upper end that is located on the first main surface 10 side with respect to the upper end of the gate electrode 50. The connection electrode 58 may protrude above the first main surface 10. The connection electrode 58 may be drawn out from the connection trench 56 onto the first main surface 10 with part of the connection insulating film 57 sandwiched therebetween. Of course, the connection electrode 58 may be located on the bottom wall side of the connection trench 56 with respect to the first main surface 10.

[0087] The connection electrode 58 may include at least one of a metal and a non-metal conductor. The connection electrode 58 may include at least one of tungsten, aluminum, copper, an aluminum alloy, a copper alloy, and conductive polysilicon. The connection electrode 58 is preferably made of the same material as the gate electrode 50.

[0088] In the multiple first mesas 53, the first source / drain regions 19 are formed by the first semiconductor regions 46A. The first contact regions 22 are formed in the surface layer portions of the first source / drain regions 19. The first contact regions 22 have a higher n-type impurity concentration than the first semiconductor regions 46A. The n-type impurity concentration of the first contact regions 22 is 1×10 18 cm -3 More than 1×10 21 cm -3 Below (in this form 1 × 10 19 cm -3 degree).

[0089] The first contact region 22 is preferably formed in the center of the corresponding first mesa portion 53 in a plan view. The first contact region 22 has a length in the second direction Y that is less than the length of the first trench structure 17, and is formed spaced apart inward from both end portions of the first trench structure 17. Both end portions of the first contact region 22 face the trench connection structure 18 in the second direction Y, with part of the first semiconductor region 46A sandwiched therebetween.

[0090] The first contact region 22 extends in the lateral direction (second direction Y) along the first main surface 10 in a cross-sectional view. Specifically, the first contact region 22 is formed at a depth position on the first main surface 10 side with respect to the upper end portion of the gate electrode 50. The first contact region 22 faces the buried insulator 51 in the lateral direction along the first main surface 10, with a part of the first semiconductor region 46A sandwiched between them. The first contact region 22 is spaced from the upper end portion of the gate electrode 50 toward the first main surface 10, and does not face the gate electrode 50 in the lateral direction along the first main surface 10. This reduces the electric field applied to the plurality of first trench structures 17.

[0091] The first contact region 22 may have a thickness of 10 nm to 150 nm (preferably 50 nm to 100 nm). The first contact region 22 is preferably formed at a distance of 0.1 μm to 2 μm (preferably 0.5 μm to 1.5 μm) from the upper end of the gate electrode 50 in the thickness direction (normal direction Z) of the semiconductor chip 8.

[0092] In the multiple second mesas 54, the second source / drain regions 20 are formed by the first semiconductor regions 46A. The second contact regions 24 are formed in the surface layer portions of the second source / drain regions 20. The second contact regions 24 have a higher n-type impurity concentration than the first semiconductor regions 46A. The n-type impurity concentration of the second contact regions 24 is 1×10 18 cm -3 More than 1×10 21 cm -3 Below (in this form 1 × 10 19 cm -3 degree).

[0093] The second contact region 24 is preferably formed in the center of the corresponding second mesa portion 54 in plan view. The second contact region 24 has a length in the second direction Y that is less than the length of the first trench structure 17, and is formed spaced apart inward from both end portions of the first trench structure 17. Both end portions of the second contact region 24 face the trench connection structure 18 in the second direction Y, with part of the first semiconductor region 46A sandwiched therebetween.

[0094] The second contact region 24 extends in the lateral direction (second direction Y) along the first main surface 10 in a cross-sectional view. Specifically, the second contact region 24 is formed at a depth position on the first main surface 10 side with respect to the upper end portion of the gate electrode 50. The second contact region 24 faces the buried insulator 51 in the lateral direction along the first main surface 10, with a part of the first semiconductor region 46A sandwiched between them. The second contact region 24 is spaced from the upper end portion of the gate electrode 50 toward the first main surface 10, and does not face the gate electrode 50 in the lateral direction along the first main surface 10. This reduces the electric field applied to the plurality of first trench structures 17.

[0095] The second contact region 24 may have a thickness of 10 nm to 150 nm (preferably 50 nm to 100 nm). The second contact region 24 is preferably formed at a distance of 0.1 μm to 2 μm (preferably 0.5 μm to 1.5 μm) from the upper end of the gate electrode 50 in the thickness direction (normal direction Z) of the semiconductor chip 8.

[0096] 8 and 11, p-type protrusions 59 are formed in the plurality of drift mesas 55, selectively protruding from the second semiconductor region 46B toward the first main surface 10 into the first semiconductor region 46A. Referring to FIG. 11, the protrusions 59 may extend upward in a parabolic shape from a boundary 60A between the first semiconductor region 46A and the second semiconductor region 46B and have an apex near the first main surface 10. In this embodiment, the protrusions 59 have an apex at a position away from the first main surface 10 toward the second main surface 11. Parts of the drift region 21 may be formed on both sides of the protrusions 59 in the first direction X. The portions of the drift region 21 are sandwiched between the protrusions 59 and the first trench structure 17.

[0097] Referring to FIG. 8, the protrusions 59 are selectively formed on the drift mesa 55 in the second direction Y. In this embodiment, a plurality of protrusions 59 are arranged at intervals along the second direction Y. Each protrusion 59 is formed across the first trench structure 17 on one side and the first trench structure 17 on the other side in the first direction X. As a result, the drift region 21 is divided by the protrusions 59 at a plurality of locations along the second direction Y. The p-type impurity concentration of the protrusions 59 is 1×10 16 cm -3 More than 1×10 22 cm -3 Below (in this form 1 × 10 19 cm -3 degree).

[0098] 8, the multiple protrusions 59 divide the drift region 21 in the second direction Y into multiple contact regions 61 and multiple current regions 62. Each contact region 61 is a region in which a protrusion 59 is formed in a plan view. Each current region 62 is a region in which no protrusion 59 is formed in a plan view, and is formed by the first semiconductor region 46A (drift region 21) from the boundary 60A to the first main surface 10.

[0099] In the second direction Y, the contact region 61 may be shorter than the current region 62. For example, the length of the contact region 61 in the second direction Y may be 0.1 μm or more and 100 μm or less, and the length of the current region 62 in the second direction Y may be 1 μm or more and 3000 μm or less.

[0100] First impurity regions 63 are further formed in the plurality of drift mesas 55. In FIG. 8, the first impurity regions 63 are omitted. The first impurity regions 63 are selectively formed in the contact region 61 out of the contact region 61 and the current region 62. The first impurity regions 63 are formed in the surface layer portion of the first main surface 10, in contact with the tops of the protrusions 59. The first impurity regions 63 have a higher n-type impurity concentration than the first semiconductor region 46A. The n-type impurity concentration of the first impurity regions 63 is 1×10 15 cm -3More than 1×10 20 cm -3 Below (in this form 1 × 10 18 cm -3 degree).

[0101] The semiconductor device 1A includes a main surface insulating film 64 that selectively covers the first main surface 10. The main surface insulating film 64 may be part of the insulating layer 9 described above. The main surface insulating film 64 covers the first trench structures 17 and the trench connection structures 18 on the first main surface 10. In this embodiment, the main surface insulating film 64 covers the entire first main surface 10 and is continuous with the first to fourth side surfaces 12A to 12D.

[0102] The main surface insulating film 64 may have a thickness of 0.1 μm or more and 2 μm or less. The thickness of the main surface insulating film 64 preferably exceeds the thickness of the gate insulating film 49. The main surface insulating film 64 includes at least one of a silicon oxide film, a silicon nitride film, an aluminum oxide film, a zirconium oxide film, a hafnium oxide film, and a tantalum oxide film. The main surface insulating film 64 is preferably made of a silicon oxide film.

[0103] In this embodiment, the main surface insulating film 64 is made of the same material as the buried insulator 51 and is formed integrally with the buried insulator 51. That is, the main surface insulating film 64 extends from above the first main surface 10 into the multiple first trenches 48 as part of the buried insulator 51. In other words, the main surface insulating film 64 is made of an insulating film in which the portions of the multiple buried insulators 51 that protrude from the multiple first trenches 48 are integrated into a film shape on the first main surface 10.

[0104] 8 and 9, the semiconductor device 1A includes a plurality of first electrodes 65 electrically connected to the first semiconductor region 46A in the plurality of first mesas 53. In this embodiment, the plurality of first electrodes 65 are provided as "first lower contacts 23." The plurality of first electrodes 65 penetrate the main surface insulating film 64 and are connected to the plurality of first mesas 53, respectively. Specifically, the plurality of first electrodes 65 are respectively arranged in a plurality of first connection openings 66 formed in the main surface insulating film 64.

[0105] Each of the multiple first electrodes 65 is made of metal. In this embodiment, each of the multiple first electrodes 65 has a layered structure including a first barrier film 67 and a first electrode body 68. The first barrier film 67 is formed in a film shape along the inner wall of the first connection opening 66. The first barrier film 67 may be made of a titanium-based metal film. The first barrier film 67 may have a single-layer structure or a layered structure including either or both of a titanium film and a titanium nitride film.

[0106] The first electrode body 68 is embedded in the first connection opening 66 with the first barrier film 67 sandwiched therebetween, and is electrically connected to the first mesa portion 53 (first contact region 22) with the first barrier film 67 sandwiched therebetween. The first electrode body 68 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, and a copper alloy. In this embodiment, the first electrode body 68 contains tungsten. Of course, the multiple first electrodes 65 may not have the first barrier film 67 and may be composed only of the first electrode body 68.

[0107] 8 and 10 , the semiconductor device 1A includes a plurality of second electrodes 69 electrically connected to the first semiconductor region 46A in the plurality of second mesas 54. In this embodiment, the plurality of second electrodes 69 are provided as "second lower contacts 25." The plurality of second electrodes 69 penetrate the main surface insulating film 64 and are connected to the plurality of second mesas 54, respectively. Specifically, the plurality of second electrodes 69 are respectively arranged in a plurality of second connection openings 70 formed in the main surface insulating film 64.

[0108] Each of the multiple second electrodes 69 is made of metal. In this embodiment, each of the multiple second electrodes 69 has a layered structure including a second barrier film 71 and a second electrode body 72. The second barrier film 71 is formed in a film shape along the inner wall of the second connection opening 70. The second barrier film 71 may be made of a titanium-based metal film. The second barrier film 71 may have a single-layer structure or a layered structure including either or both of a titanium film and a titanium nitride film.

[0109] The second electrode body 72 is embedded in the second connection opening 70 with the second barrier film 71 sandwiched therebetween, and is electrically connected to the second mesa portion 54 (second contact region 24) with the second barrier film 71 sandwiched therebetween. The second electrode body 72 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, and a copper alloy. In this embodiment, the second electrode body 72 contains tungsten. Of course, the multiple second electrodes 69 may not have the second barrier film 71 and may be composed only of the second electrode body 72.

[0110] 8 and 11, the semiconductor device 1A includes a plurality of second trench structures 73 formed in the first main surface 10 in the plurality of drift mesas 55. In this embodiment, the plurality of second trench structures 73 are formed in the corresponding drift mesa portions 55, penetrating the main surface insulating film 64. Specifically, the plurality of second trench structures 73 are formed in the drift mesa portions 55 via a plurality of base connection openings 74 formed in the main surface insulating film 64. Referring to FIG. 8 , the second trench structures 73 are selectively formed in the contact region 61, and are not formed in the current region 62.

[0111] 11 , the plurality of second trench structures 73 are formed to reach the protruding portion 59. In this embodiment, the plurality of second trench structures 73 are formed shallower than the plurality of first trench structures 17. Specifically, the plurality of second trench structures 73 penetrate the first impurity region 63 and reach the protruding portion 59. Each of the plurality of second trench structures 73 has a bottom wall located within the protruding portion 59.

[0112] The spacing between the first trench structure 17 and the second trench structure 73 may be 0.01 μm to 10 μm (preferably 0.1 μm to 0.5 μm). Each of the second trench structures 73 may have a width in the first direction X of 0.01 μm to 10 μm (preferably 0.1 μm to 0.5 μm). The width of each of the second trench structures 73 may be equal to or greater than the width of the first trench structure 17, or may be less than the width of the first trench structure 17. Each of the second trench structures 73 may have a depth of 0.1 μm to 10 μm (preferably 0.2 μm to 0.5 μm). With this depth, a silicide layer 79 (described below) can be formed over the entire second trench structure 73.

[0113] The second trench structure 73 includes a base trench 75 and a base electrode 76. In this embodiment, the base electrode 76 is provided as a "first base contact 26." The base trench 75 is formed in the first main surface 10, penetrating the main surface insulating film 64, and defines the wall surfaces (side walls and bottom wall) of the second trench structure 73. In this embodiment, the base trench 75 includes a base connection opening 74 formed in the main surface insulating film 64. Specifically, the base trench 75 penetrates the main surface insulating film 64 and the first impurity region 63 to reach the protruding portion 59. The base trench 75 exposes the first impurity region 63 and the protruding portion 59 from the wall surfaces.

[0114] The base trench 75 may be formed in a tapered shape in which the opening width narrows from the first main surface 10 side toward the bottom wall side in a cross-sectional view. Of course, the base trench 75 may be formed perpendicular to the first main surface 10. The corners on the bottom wall side of the base trench 75 may be formed in a curved shape. Of course, the entire bottom wall of the base trench 75 may be formed in a curved shape toward the second main surface 11 side.

[0115] The base electrode 76 is buried in the base trench 75 without an insulating film therebetween. The base electrode 76 is mechanically and electrically connected to the first impurity region 63 and the protruding portion 59 within the base trench 75, and is mechanically connected to the main surface insulating film 64. Within the base trench 75, the base electrode 76 has a portion located on the semiconductor chip 8 side with respect to the first main surface 10, and a portion located on the main surface insulating film 64 side with respect to the first main surface 10. In other words, the base electrode 76 has an upper end portion that protrudes above the first main surface 10. Furthermore, the upper end portion of the base electrode 76 protrudes above the upper end portion of the gate electrode 50 (the upper end portion of the drawn-out portion 52).

[0116] The base electrode 76 may include at least one of a metal and a non-metal conductor. The base electrode 76 is preferably formed of a conductive material different from that of the gate electrode 50. The base electrode 76 preferably includes a metal. In this embodiment, the base electrode 76 has a layered structure including a base barrier film 77 and a base electrode body 78.

[0117] The base barrier film 77 is formed in a film shape along the sidewalls and bottom wall of the base trench 75, and covers the first impurity region 63, the protrusion 59, and the main surface insulating film 64 within the base trench 75. The base barrier film 77 defines a recess space within the base trench 75. The base barrier film 77 may be made of a titanium-based metal film. The base barrier film 77 may have a single-layer structure or a multilayer structure including either or both of a titanium film and a titanium nitride film. The base barrier film 77 is preferably made of the same material as the first barrier film 67 and the second barrier film 71.

[0118] The base electrode body 78 is buried in the base trench 75 with a base barrier film 77 sandwiched therebetween, and covers the first impurity region 63, the protrusion 59, and the main surface insulating film 64 with the base barrier film 77 sandwiched therebetween. The base electrode body 78 is electrically connected to the first impurity region 63 and the protrusion 59 via the base barrier film 77. The base electrode body 78 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, and a copper alloy. The base electrode body 78 is preferably made of the same material as the first electrode body 68 and the second electrode body 72. In this embodiment, the base electrode body 78 contains tungsten. Of course, the base electrode 76 may be formed only by the base electrode body 78 without the base barrier film 77.

[0119] A silicide layer 79 is formed on the inner wall of the base trench 75. The silicide layer 79 is formed over the entire sidewall and bottom wall of the base trench 75 at the boundary between the semiconductor chip 8 and the base barrier film 77. The silicide layer 79 may cross the boundary between the first impurity region 63 and the protrusion 59 in the thickness direction of the semiconductor chip 8 from top to bottom.

[0120] If the silicide layer 79 is formed over the entire sidewall and bottom wall of the base trench 75, the surface condition of the inner wall of the base trench 75 can be improved and smoothed, thereby achieving good contact between the base electrode body 78 and the base trench 75. This reduces the contact resistance of the base electrode body 78. As a result, even if the second trench structure 73 is not formed in the current region 62 but is only formed in the contact region 61, it is possible to sufficiently obtain the effect of fixing the potential of the second semiconductor region 46B at a predetermined potential.

[0121] 8 and 12, the semiconductor device 1A includes a plurality of third electrodes 80 electrically connected to the plurality of first trench structures 17. The plurality of third electrodes 80 are provided as "first gate contacts 27." The plurality of third electrodes 80 penetrate the main surface insulating film 64 and are mechanically and electrically connected to either or both of the plurality of first trench structures 17 (lead-out portions 52) and the plurality of trench connection structures 18 (connection electrodes 58).

[0122] Specifically, the multiple third electrodes 80 are respectively disposed in multiple third connection openings 81 formed in the main surface insulating film 64. In this embodiment, the multiple third electrodes 80 are mechanically and electrically connected to the multiple trench connection structures 18. That is, the multiple third electrodes 80 are electrically connected to the multiple first trench structures 17 via the multiple trench connection structures 18.

[0123] 8, in this embodiment, the multiple third electrodes 80 are formed at intervals along the trench connection structures 18 in a plan view. The multiple third electrodes 80 may have any planar shape. The multiple third electrodes 80 may be formed in a circular or rectangular shape in a plan view. Of course, the multiple third electrodes 80 may each be formed in a strip shape extending along the corresponding trench connection structure 18 in a plan view.

[0124] Each of the multiple third electrodes 80 is made of metal. In this embodiment, each of the multiple third electrodes 80 has a layered structure including a third barrier film 82 and a third electrode body 83. The third barrier film 82 is formed in a film shape along the inner wall of the third connection opening 81. The third barrier film 82 may be made of a titanium-based metal film. The third barrier film 82 may have a single-layer structure or a layered structure including either or both of a titanium film and a titanium nitride film. The third barrier film 82 is preferably made of the same material as the first barrier film 67, the second barrier film 71, and the base barrier film 77.

[0125] The third electrode body 83 is embedded in the third connection opening 81 with the third barrier film 82 sandwiched therebetween, and is electrically connected to the lead portion 52 (connection electrode 58) with the third barrier film 82 sandwiched therebetween. The third electrode body 83 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, and a copper alloy. The third electrode body 83 is preferably made of the same material as the first electrode body 68. In this embodiment, the third electrode body 83 contains tungsten. Of course, the multiple third electrodes 80 may not have the third barrier film 82 and may be composed of only the third electrode body 83.

[0126] (Detailed Structures of the First Semiconductor Region 46A, the Second Semiconductor Region 46B, and the Third Semiconductor Region 46C) 9 to 12, the first semiconductor region 46A, the second semiconductor region 46B, and the third semiconductor region 46C will be described. The third semiconductor region 46C is located on the second main surface 11 side of the trench structure 17, sandwiching the second semiconductor region 46B. The second semiconductor region 46B covers the bottom wall and sidewall of the first trench structure 17 at the lower end of the first trench structure 17. The second semiconductor region 46B faces the gate electrode 50 at the bottom wall of the first trench structure 17, sandwiching a gate insulating film 49 therebetween.

[0127] The second semiconductor region 46B is formed in a shape whose thickness changes in the X direction. More specifically, the second semiconductor region 46B is thicker at a position overlapping the bottom wall of the first trench structure 17 (hereinafter sometimes referred to as the tip of the trench) and gradually becomes thinner as it moves away from the tip of the trench. In a cross-sectional view, the second semiconductor region 46B has a shape in which multiple circles are lined up in the X direction and adjacent circles partially overlap. The circles forming this shape are arranged so that their centers are located directly below the tip of the trench. In this case, the second semiconductor region 46B is thickest in the portion directly below the tip of the trench and thinnest in the portion where adjacent circles overlap (hereinafter sometimes referred to as the constricted portion). In this case, the boundary 60A between the first semiconductor region 46A and the second semiconductor region 46B and the boundary 60B between the second semiconductor region 46B and the third semiconductor region 46C have a shape in which multiple arcs aligned in the X direction are connected between adjacent first trench structures 17.

[0128] The average thickness of the first semiconductor region 46A may be 0.2 μm or more and 40 μm or less (preferably 0.5 μm or more and 10 μm or less). In the Z direction, the distance from the contact point between the boundary portion 60A and the sidewall of the first trench structure 17 to the first main surface 10 is defined as a first thickness of the first semiconductor region 46A. The first thickness of the first semiconductor region 46A may be 0.2 μm or more and 30 μm or less (preferably 0.5 μm or more and 10 μm or less).

[0129] The distance in the Z direction from a point located at the tip of the constricted portion of the second semiconductor region 46B at the boundary 60A to the first main surface 10 is defined as the second thickness of the first semiconductor region 46A. The second thickness of the first semiconductor region 46A may be 0.2 μm or more and 40 μm or less (preferably 0.5 μm or more and 10 μm or less). The second thickness of the first semiconductor region 46A is preferably thicker than the first thickness of the first semiconductor region 46A.

[0130] The thickness of the first semiconductor region 46A directly under at least one of the first contact region 22 and the second contact region 24 is defined as the third thickness of the first semiconductor region 46A. The third thickness of the first semiconductor region 46A may be 0.2 μm or more and 40 μm or less (preferably 0.5 μm or more and 10 μm or less). The third thickness of the first semiconductor region 46A is thicker than the first thickness of the first semiconductor region 46A.

[0131] The average thickness of the second semiconductor region 46B may be 0.01 μm or more and 10 μm or less (preferably 0.1 μm or more and 1 μm or less). The thickness of the portion of the second semiconductor region 46B located directly below the tip of the trench is defined as the first thickness of the second semiconductor region 46B. The first thickness of the second semiconductor region 46B may be 0.01 μm or more and 10 μm or less (preferably 0.1 μm or more and 1 μm or less).

[0132] The thickness of the constricted portion of the second semiconductor region 46B is defined as the second thickness of the second semiconductor region 46B. The second thickness of the second semiconductor region 46B may be 0.01 μm or more and 10 μm or less (preferably 0.01 μm or more and 1 μm or less). The second thickness of the second semiconductor region 46B is preferably thinner than the first thickness of the second semiconductor region 46B.

[0133] The thickness of the second semiconductor region 46B directly under at least one of the first contact region 22 and the second contact region 24 is defined as a third thickness of the second semiconductor region 46B. The third thickness of the second semiconductor region 46B may be 0.01 μm or more and 10 μm or less (preferably 0.01 μm or more and 1 μm or less).

[0134] The thickness of the portion of the third semiconductor region 46C located directly below the tip of the trench is defined as the first thickness of the third semiconductor region 46C. The first thickness of the third semiconductor region 46C may be 0.001 μm or more (preferably 0.01 μm or more).

[0135] The distance in the Z direction from the point located at the tip of the constricted portion of the second semiconductor region 46B at the boundary 60B to the fourth semiconductor region 46D is defined as the second thickness of the third semiconductor region 46C. The second thickness of the third semiconductor region 46C may be 0.001 μm or more (preferably 0.01 μm or more). The second thickness of the third semiconductor region 46C is preferably thicker than the first thickness of the third semiconductor region 46C.

[0136] The thickness of the third semiconductor region 46C directly below at least one of the first contact region 22 and the second contact region 24 is defined as the third thickness of the third semiconductor region 46C. The third thickness of the third semiconductor region 46C may be 0.001 μm or more (preferably 0.01 μm or more). The third thickness of the third semiconductor region 46C is preferably thicker than the first thickness of the third semiconductor region 46C.

[0137] The second semiconductor region 46B includes a high-concentration region 46B1 having a high concentration of p-type impurities and a low-concentration region 46B2 having a lower p-type impurity concentration than the high-concentration region 46B1. The high-concentration region 46B1 is a circular region whose center is located directly below the tip of the trench in a cross-sectional view. The high-concentration region 46B1 is formed at each tip of the trench. The low-concentration region 46B2 is a region that completely surrounds the high-concentration region 46B1 in a cross-sectional view.

[0138] In one example, the second semiconductor region 46B has high-concentration regions 46B1 adjacent to each other in the X direction formed to be spaced apart from each other, and low-concentration regions 46B2 formed between the adjacent high-concentration regions 46B1. Alternatively, the high-concentration regions 46B1 adjacent to each other in the X direction may be connected to each other. Alternatively, the second semiconductor region 46B may include a portion where the high-concentration regions 46B1 adjacent to each other in the X direction are connected to each other, and a portion where the high-concentration regions 46B1 adjacent to each other in the X direction are not connected to each other.

[0139] The p-type impurity concentration of the high concentration region 46B1 is 1×10 10 cm -3 Over 2×10 18 cm -3Below (in this form 1 × 10 15 cm -3 The p-type impurity concentration of the low concentration region 46B2 may be about 0.5×10 10 cm -3 More than 1×10 18 cm -3 Below (in this form 1 × 10 14 cm -3 The high concentration region 46B1 and the low concentration region 46B2 are formed, for example, by the p-type impurity concentration decreasing in a gradational manner with increasing distance from the center located directly below the tip of the trench.

[0140] 9, around the first trench structure 17, the first source / drain region 19, the second source / drain region 20, and the drift region 21 are arranged in the X direction (first direction) with the first trench structure 17 sandwiched between them. In one example, the X direction length (first direction length) of the drift region 21 (drift mesa portion 55) is shorter than the X direction length (first direction length) of the first source / drain region 19 (first mesa portion 53). The X direction length (first direction length) of the drift region 21 (drift mesa portion 55) is shorter than the X direction length (first direction length) of the second source / drain region 20 (second mesa portion 54).

[0141] In this case, the X-direction length of the drift region 21 (drift mesa portion 55) may be 0.01 μm or more and 3 μm or less (preferably 0.01 μm or more and 0.5 μm or less). The X-direction length of the first source / drain region 19 (first mesa portion 53) may be 0.1 μm or more and 3 μm or less (preferably 0.1 μm or more and 0.5 μm or less). The X-direction length of the second source / drain region 20 (second mesa portion 54) may be 0.1 μm or more and 3 μm or less (preferably 0.1 μm or more and 0.5 μm or less).

[0142] 9 to 12, semiconductor device 1A includes a first interlayer insulating film 85 stacked on main surface insulating film 64. First interlayer insulating film 85 may be a part of insulating layer 9 described above. First interlayer insulating film 85 may include at least one of silicon oxide and silicon nitride. First interlayer insulating film 85 covers the entire main surface insulating film 64 and is continuous with first to fourth side surfaces 12A to 12D. First interlayer insulating film 85 may have a flat surface extending along first main surface 10. The flat surface of first interlayer insulating film 85 may have grinding marks.

[0143] A first wiring layer 28 is formed on the first interlayer insulating film 85. The first wiring layer 28 may contain at least one of titanium, tungsten, aluminum, copper, an aluminum alloy, a copper alloy, and conductive polysilicon. The first wiring layer 28 may contain at least one of a Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.

[0144] As described above, the first wiring layer 28 includes a first gate wiring layer 30, a first lower wiring layer 31, a second lower wiring layer 32, and a first base wiring layer 33. The first gate wiring layer 30 is connected to the first gate contact 27 (FIG. 12), and the first lower wiring layer 31 is connected to the first lower contact 23 (FIG. 9). The second lower wiring layer 32 is connected to the second lower contact 25 (FIG. 10), and the first base wiring layer 33 is connected to the first base contact 26 (FIG. 11).

[0145] 9 to 12, semiconductor device 1A includes second interlayer insulating film 86 stacked on first interlayer insulating film 85 so as to cover first wiring layer 28. Second interlayer insulating film 86 may be a part of insulating layer 9 described above. Second interlayer insulating film 86 may include at least one of silicon oxide and silicon nitride. Second interlayer insulating film 86 covers the entire area of ​​first interlayer insulating film 85 and is continuous with first to fourth side surfaces 12A to 12D. Second interlayer insulating film 86 may have a flat surface extending along first main surface 10. The flat surface of second interlayer insulating film 86 may have grinding marks.

[0146] A second wiring layer 29 is formed on the second interlayer insulating film 86. The second wiring layer 29 may contain at least one of titanium, tungsten, aluminum, copper, an aluminum alloy, a copper alloy, and conductive polysilicon. The second wiring layer 29 may contain at least one of a Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.

[0147] As described above, the second wiring layer 29 includes the second gate wiring layer 34, the first upper wiring layer 35, the second upper wiring layer 36, and the second base wiring layer 37. The second gate wiring layer 34 is connected to the first gate wiring layer 30 via a second gate contact 38 that penetrates the second interlayer insulating film 86 (FIG. 6), and the first upper wiring layer 35 is connected to the first lower wiring layer 31 via a first upper contact 40 that penetrates the second interlayer insulating film 86 (FIG. 6). The second upper wiring layer 36 is connected to the second lower wiring layer 32 via a second upper contact 41 that penetrates the second interlayer insulating film 86 (FIG. 6), and the second base wiring layer 37 is connected to the first base wiring layer 33 via a second base contact 39 that penetrates the second interlayer insulating film 86 (FIG. 6).

[0148] 12, the semiconductor device 1A includes a top insulating film 87 formed on the second interlayer insulating film 86. The top insulating film 87 is omitted in FIGS. 9 to 11. The top insulating film 87 may be a part of the insulating layer 9 described above. The top insulating film 87 may also be referred to as a "passivation film." The top insulating film 87 may have a laminated structure including an inorganic insulating film (inorganic film) and an organic insulating film (organic film) laminated in this order from the second interlayer insulating film 86 side. Of course, the top insulating film 87 may have a single-layer structure made of an inorganic insulating film (inorganic film) or an organic insulating film (organic film). The inorganic insulating film is preferably made of an insulating material different from that of the second interlayer insulating film 86. The inorganic insulating film may be made of, for example, a silicon nitride film. The organic insulating film may be made of a photosensitive resin. The organic insulating film may include at least one of a polyimide film, a polyamide film, and a polybenzoxazole film.

[0149] A plurality of external terminals 4 to 7 are formed on the top insulating film 87 (see FIG. 7). As described above, the plurality of external terminals 4 to 7 include the base terminal 4, the gate terminal 5, the first source / drain terminal 6, and the second source / drain terminal 7. The base terminal 4 is connected to the second base wiring layer 37 via a base terminal contact 43 that penetrates the top insulating film 87 (FIG. 7), and the gate terminal 5 is connected to the second gate wiring layer 34 via a gate terminal contact 42 that penetrates the top insulating film 87 (FIG. 7). The first source / drain terminal 6 is connected to the first upper wiring layer 35 via a first terminal contact 44 that penetrates the top insulating film 87 (FIG. 7), and the second source / drain terminal 7 is connected to the second upper wiring layer 36 via a second terminal contact 45 that penetrates the top insulating film 87 (FIG. 7).

[0150] 9 to 12, the semiconductor device 1A includes a back surface protective film 88 that covers the second main surface 11 of the semiconductor chip 8. In this embodiment, the back surface protective film 88 covers the entire second main surface 11 and also covers the first to fourth side surfaces 12A to 12D (FIG. 12). The back surface protective film 88 may have a single-layer structure made of an inorganic insulating film (inorganic film) or an organic insulating film (organic film). The inorganic insulating film may be made of, for example, a silicon nitride film. The organic insulating film may be made of a photosensitive resin. The organic insulating film may include at least one of a polyimide film, a polyamide film, and a polybenzoxazole film.

[0151] 9 to 11, the semiconductor device 1A includes a first pn junction 89 and a second pn junction 90, each formed inside the semiconductor chip 8. The first pn junction 89 is formed at a boundary 60A between the first semiconductor region 46A and the second semiconductor region 46B on the first mesa 53 side. As a result, a first body diode D1 is formed in the first mesa 53, the first body diode D1 including the second semiconductor region 46B as an anode region and the first semiconductor region 46A as a cathode region.

[0152] The second pn junction 90 is formed at the boundary 60A between the first semiconductor region 46A and the second semiconductor region 46B on the second mesa 54 side. As a result, a second body diode D2 including the second semiconductor region 46B as an anode region and the first semiconductor region 46A as a cathode region is formed in the second mesa 54. The anode of the second body diode D2 (second pn junction 90) is electrically connected to the anode of the first body diode D1 (first pn junction 89) via the second semiconductor region 46B.

[0153] (Manufacturing process of semiconductor device 1A) Next, an example of a method for manufacturing the semiconductor device 1A will be described. Figures 13A to 13J are cross-sectional views showing an example of a method for manufacturing the semiconductor device 1A shown in Figure 1. Figures 13A to 13J are all cross-sectional views of a region corresponding to Figure 11.

[0154] Referring to FIG. 13A, a disk-shaped wafer 91 is prepared. The wafer 91 includes a first wafer main surface 92 on one side and a second wafer main surface 93 on the other side. The wafer 91 is made of a p-type semiconductor substrate formed entirely of a p-type (second conductivity type) semiconductor region 91A. Next, an n-type semiconductor region 91B is formed in a surface layer portion of the first wafer main surface 92. The semiconductor region 91B is formed by introducing n-type impurities into the surface layer portion of the first wafer main surface 92 by ion implantation. The n-type impurities may be introduced into the entire surface layer portion of the first wafer main surface 92 without using an ion implantation mask. The remaining portion of the semiconductor region 91A on the second wafer main surface 93 side where the semiconductor region 91B is not formed becomes the fourth semiconductor region 46D. At this time, the introduction of n-type impurities may be repeated multiple times. When n-type impurities are introduced multiple times, it is easy to form a semiconductor region 91B in which the n-type impurity concentration is relatively high on the first wafer main surface 92 side and the n-type impurity concentration is relatively low on the second wafer main surface 93 side.

[0155] The semiconductor region 91B may be formed by growing silicon from the semiconductor region 91A (semiconductor substrate) by epitaxial growth. In this case, the first wafer main surface 92 is formed by the crystal plane (crystal growth plane) of the semiconductor region 91B.

[0156] Referring to FIG. 13B, a plurality of first trenches 48 and a plurality of connection trenches 56 are formed on the first wafer main surface 92. In this step, unnecessary portions of the wafer 91 are selectively removed by etching using a hard mask (not shown). The etching may be wet etching and / or dry etching. The etching is preferably RIE (Reactive Ion Etching), which is an example of dry etching. As a result, a plurality of first trenches 48 and a plurality of connection trenches 56 are formed. Furthermore, a plurality of mesa portions 53 to 55 are defined on the first wafer main surface 92 by the plurality of first trenches 48 (a plurality of connection trenches 56). The hard mask is then removed.

[0157] 13C , a first base insulating film 94 that serves as a base for the plurality of gate insulating films 49 and the plurality of connection insulating films 57 is formed on the first wafer main surface 92. The first base insulating film 94 is formed on the first wafer main surface 92, including the inner walls of the plurality of first trenches 48 and the inner walls of the plurality of connection trenches 56. The first base insulating film 94 may be formed by an oxidation process and / or a CVD process (preferably a thermal oxidation process).

[0158] 13D, the second semiconductor region 46B is formed in the semiconductor region 91B. The second semiconductor region 46B divides the semiconductor region 91B into a region located closer to the first wafer main surface 92 than the second semiconductor region 46B and a region located closer to the second wafer main surface 93 than the second semiconductor region 46B. The region located closer to the first wafer main surface 92 than the second semiconductor region 46B becomes the first semiconductor region 46A. The region located closer to the second wafer main surface 93 than the second semiconductor region 46B becomes the third semiconductor region 46C.

[0159] In this step, first, an ion implantation mask (not shown) having a predetermined pattern is formed on the first wafer main surface 92. Next, p-type impurities are selectively introduced into the semiconductor region 91B from the tips of the plurality of first trenches 48 and the plurality of connection trenches 56 by ion implantation via the ion implantation mask. This forms the second semiconductor region 46B.

[0160] At this time, by repeatedly introducing p-type impurities multiple times, the second semiconductor region 46B including the high-concentration region 46B1 and the low-concentration region 46B22 can be formed. When introducing p-type impurities multiple times, the processing conditions for the p-type impurity introduction process may be the same for all times, or may be different for all times or for specific times. The number of times the p-type impurity is introduced is, for example, two times.

[0161] Furthermore, in parallel with the formation of the second semiconductor region 46B, p-type impurities are selectively introduced into the semiconductor region 91B (first semiconductor region 46A) from the first wafer main surface 92 by ion implantation via the ion implantation mask, thereby forming the protrusion 59. The ion implantation mask is then removed.

[0162] 13E, a plurality of first contact regions 22, a plurality of second contact regions 24, and a plurality of first impurity regions 63 are formed. In this step, first, an ion implantation mask (not shown) having a predetermined pattern is formed on the first wafer main surface 92. Next, n-type impurities are selectively introduced into the first semiconductor region 46A by ion implantation via the ion implantation mask. This forms a plurality of first contact regions 22, a plurality of second contact regions 24, and a plurality of first impurity regions 63. The ion implantation mask is then removed.

[0163] Referring to FIG. 13F, a first base electrode (not shown) that serves as a base for the multiple gate electrodes 50, the multiple lead portions 52, and the multiple connection electrodes 58 is formed on the first wafer main surface 92. The first base electrode is formed in the form of a film that fills the multiple first trenches 48 and the multiple connection trenches 56 and covers the first wafer main surface 92. In this embodiment, the first base electrode includes conductive polysilicon. The first base electrode may be formed by a CVD method. Next, unnecessary portions of the first base electrode are removed. This results in the multiple gate electrodes 50, the multiple lead portions 52, and the multiple connection electrodes 58.

[0164] 13G, a second base insulating film 95, which serves as a base for the buried insulator 51 and the main surface insulating film 64, is formed on the first wafer main surface 92. In this embodiment, the second base insulating film 95 is made of a silicon oxide film. The second base insulating film 95 may be formed by a CVD method. The CVD method for the second base insulating film 95 is preferably a HDP (high density plasma)-CVD method.

[0165] The second base insulating film 95 fills recess spaces defined by the plurality of lead portions 52 in the plurality of first trenches 48, and covers the first wafer main surface 92, the plurality of lead portions 52, and the connection electrodes 58. This forms the buried insulators 51 located in the first trenches 48 and the main surface insulating film 64 located on the first wafer main surface 92.

[0166] 13H, a plurality of first connection openings 66, a plurality of second connection openings 70, a plurality of third connection openings 81, and a plurality of base trenches 75 (base connection openings 74) are formed in the first wafer main surface 92. In this process, a resist mask (not shown) having a predetermined pattern is first formed on the main surface insulating film 64. Next, unnecessary portions of the main surface insulating film 64 are selectively removed by etching via the resist mask. The etching method may be wet etching and / or dry etching (preferably RIE). As a result, a plurality of first connection openings 66, a plurality of second connection openings 70, a plurality of third connection openings 81, and a plurality of base connection openings 74 are formed in the main surface insulating film 64.

[0167] Next, unnecessary portions of the wafer 91 are removed by etching through the resist mask. The etching may be wet etching and / or dry etching (preferably RIE). The unnecessary portions of the wafer 91 are removed until they penetrate the first impurity regions 63 and expose the protrusions 59. This forms a plurality of base trenches 75, each including a base connection opening 74, in the first wafer main surface 92. The resist mask is then removed.

[0168] Referring to FIG. 13I, a second base electrode (not shown) serving as a base for the plurality of first electrodes 65, the plurality of second electrodes 69, the plurality of base electrodes 76, and the plurality of third electrodes 80 is formed on the main surface insulating film 64. In this embodiment, the second base electrode has a base barrier film and an electrode body film stacked in this order from the wafer 91 side. Next, unnecessary portions of the second base electrode are selectively removed by etching. The etching may be wet etching and / or dry etching (preferably RIE). The second base electrode is removed until the main surface insulating film 64 is exposed. This forms the plurality of first electrodes 65, the plurality of second electrodes 69, the plurality of base electrodes 76, and the plurality of third electrodes 80. After these electrodes are formed, a silicide layer 79 is formed on the inner wall of the base trench 75 by annealing (for example, at a temperature of 500° C. or higher and 1100° C. or lower).

[0169] 13J, first interlayer insulating film 85, first wiring layer 28, second interlayer insulating film 86, second wiring layer 29, top insulating film 87, back surface protective film 88, and external terminals 4 to 7 are formed, and wafer 91 is selectively cut in the thickness direction. Through the steps including those described above, semiconductor device 1A is manufactured.

[0170] (Function of semiconductor device 1A) Fig. 14 is a cross-sectional view showing a current path 97 of the semiconductor device 1A according to the first embodiment of the present disclosure. Fig. 15 is a plan view showing a current path 97 of the semiconductor device 1A according to the first embodiment of the present disclosure. The current path 97 includes a first current path 97A and a second current path 97B.

[0171] The semiconductor device 1A has a trench-gate lateral MISFET structure. In this MISFET structure, a gate potential is applied to the first trench structure 17 (gate electrode 50), a drain potential is applied to the first mesa portion 53, and a source potential is applied to the second mesa portion 54. As a result, a channel 96 is formed in the second semiconductor region 46B in a region below the first trench structure 17, and a first lateral current path 97A is formed connecting the first electrode 65 (first mesa portion 53) and the second electrode 69 (second mesa portion 54).

[0172] As shown in FIG. 14, the first current path 97A is a path through which current flows in the order of the first mesa portion 53 (first semiconductor region 46A) → the second semiconductor region 46B (high concentration region 46B1) → the drift mesa portion 55 (first semiconductor region 46A) → the second semiconductor region 46B (high concentration region 46B1) → the second mesa portion 54 (first semiconductor region 46A).

[0173] When a current equal to or greater than a certain level flows through the first current path 97A, a second horizontal current path 97B is newly formed, connecting the first electrode 65 (first mesa portion 53) and the second electrode 69 (second mesa portion 54). The second current path 97B is a path through which a current flows in the following order: the first mesa portion 53 (first semiconductor region 46A) → the second semiconductor region 46B (low-concentration region 46B2) → the third semiconductor region 46C → the second semiconductor region 46B (low-concentration region 46B2) → the second mesa portion 54 (first semiconductor region 46A). By forming the second current path 97B as the current path 97 in addition to the first current path 97A, the current flowing through the current path 97 can be increased. As a result, the on-resistance can be reduced.

[0174] 8, in the semiconductor device 1A, the drift region 21 is divided into a contact region 61 and a current region 62 in the second direction Y. A base electrode 76 for fixing the potential (substrate potential) of the second semiconductor region 46B is selectively formed in the contact region 61, but not in the current region 62. This allows a current path 97 that connects the first electrode 65 and the second electrode 69 over the shortest distance to be formed in the current region 62. In other words, by separately arranging the contact region 61 for fixing the substrate potential and the current region 62 for the current path 97, a current can flow without detouring around the base electrode 76, thereby reducing the on-resistance.

[0175] 11, the contact region 61 has a protrusion 59 extending toward the first main surface 10. This allows the contact point with the second semiconductor region 46B to be raised toward the first main surface 10 beyond the boundary 60 between the first semiconductor region 46A and the second semiconductor region 46B. Therefore, it is not necessary to form a second trench structure 73 that reaches the boundary 60, and the substrate potential can be fixed by the relatively shallow second trench structure 73. Because the base trench 75 can be shallow, contact with the substrate potential can be ensured with a simple structure.

[0176] 11 , for example, if the second trench structure 73 has a depth reaching the second main surface 11 side beyond the boundary 60A, the silicide layer 79 may be formed only locally on the inner wall of the base trench 75. Specifically, the silicide layer 79 may be formed locally on the bottom wall and the upper end of the sidewall of the base trench 75, and not on other portions of the inner wall. In contrast, in the structure shown in FIG. 11 , the base trench 75 is shallow, so the silicide layer 79 can be formed over the entire second trench structure 73. This can improve the smoothness of the surface condition of the inner wall of the base trench 75, thereby achieving good contact between the base electrode body 78 and the base trench 75. This can reduce the contact resistance of the base electrode body 78.

[0177] Because the contact region 61 for fixing the substrate potential is formed in the active region 15, there is no need to form a peripheral structure for fixing the substrate potential in the peripheral region 16. This makes it possible to reduce the area of ​​the peripheral region 16 and increase the area of ​​the active region 15. As a result, the current characteristics of the semiconductor device 1A can be improved. For example, in the semiconductor device 1A, the occupancy rate of the active region 15 on the first main surface 10 may be 10% or more and 99.9% or less.

[0178] (Effects of semiconductor device 1A) (1-1) The semiconductor device includes a semiconductor chip 8 having a first main surface 10 and a second main surface 11, a first semiconductor region 46A of a first conductivity type formed on the first main surface 10 side of the semiconductor chip 8, a second semiconductor region 46B of a second conductivity type formed on the second main surface 11 side of the first semiconductor region 46A, a trench structure 17 including a trench 48 penetrating from the first main surface 10 through the first semiconductor region 46A, and a third semiconductor region 46C of the first conductivity type formed on the second main surface 11 side of the second semiconductor region 46B and located on the second main surface 11 side of the trench structure 17 across the second semiconductor region 46B.

[0179] According to this configuration, a first current path 97A and a second current path 97B are formed as a lateral current path 97 connecting the first electrode 65 (first mesa portion 53) and the second electrode 69 (second mesa portion 54). This allows the current flowing through the current path 97 to be increased, thereby reducing the on-resistance.

[0180] (1-2) The thickness of the second semiconductor region 46B directly below at least one of the first contact region 22 and the second contact region 24 is 10 μm or less. By reducing this thickness, the distance between the first semiconductor region 46A and the third semiconductor region 46C directly below the first contact region 22 or directly below the second contact region 24 is shortened. This reduces the value of the current flowing through the first current path 97A, which is necessary for current to flow through the second current path 97B. This shortens the time from when current begins to flow through the first current path 97A until it actually flows through the second current path 97B. As a result, the effect of reducing the on-resistance is improved.

[0181] (Modification of semiconductor device 1A) Next, modifications of the semiconductor device 1A will be described with reference to FIGS. FIG. 16 is a cross-sectional view showing a first modified example of the semiconductor device 1A according to the first embodiment of the present disclosure, and is a cross-sectional view corresponding to FIG.

[0182] 16 , the protrusion 59 may extend from the second semiconductor region 46B through the drift mesa 55 and reach the first main surface 10. As a result, the protrusion 59 may have a top 98 exposed from the first main surface 10 in the contact region 61. In this case, the base electrode 76 does not have to be formed as the second trench structure 73. The base electrode 76 may be embedded in the base connection opening 74 and have a bottom on the first main surface 10. As a result, the base electrode 76 is connected to the protrusion 59 on the first main surface 10. With this configuration, the step of forming the second trench structure 73 can be omitted, thereby simplifying the manufacturing process and reducing materials and costs.

[0183] FIG. 17 is a cross-sectional view showing a second modified example of the semiconductor device 1A according to the first embodiment of the present disclosure, and is a cross-sectional view corresponding to FIG. 17, the second trench structure 73 may be deeper than the first trench structure 17. Specifically, a base trench 75 deeper than the first trench 48 may cross the boundary portion 60 and reach the second semiconductor region 46B. This makes it possible to omit the step of forming the protrusion 59, thereby simplifying the manufacturing process and reducing materials and costs.

[0184] FIG. 18 is a cross-sectional view showing a third modified example of the semiconductor device 1A according to the first embodiment of the present disclosure, and is a cross-sectional view corresponding to FIG. 18, the back surface protective film 88 does not have to be formed on the second main surface 11 of the semiconductor chip 8. The second main surface 11 of the semiconductor chip 8 may be an exposed surface. This makes it possible to omit the step of forming the back surface protective film 88, thereby simplifying the manufacturing process and reducing materials and costs.

[0185] [Second embodiment] (Structure of semiconductor device 1B) 19 is a schematic plan view showing the internal structure of a semiconductor device 1B according to a second embodiment of the present disclosure. In the second embodiment, a description of the external structure of the semiconductor device 1B, such as the arrangement of the external terminals 4 to 7 shown in FIGS. 2 and 3, will be omitted, and the internal structure of the semiconductor device 1B will be mainly described.

[0186] The semiconductor device 1B includes a semiconductor chip 101. The semiconductor chip 101 is formed in a rectangular parallelepiped shape. The semiconductor chip 101 includes a first main surface 102 on one side, a second main surface 103 on the other side (see FIG. 22 and subsequent figures), and side surfaces 104A, 104B, 104C, and 104D connecting the first main surface 102 and the second main surface 103. The side surfaces 104A to 104D specifically include the first side surface 104A, the second side surface 104B, the third side surface 104C, and the fourth side surface 104D.

[0187] An active area 105 and a peripheral area 106 surrounding the active area 105 are defined on a first main surface 102 of the semiconductor chip 101 . The outer peripheral region 106 may coincide with an annular peripheral portion along the side surfaces 104A to 104D of the semiconductor chip 101. The outer peripheral region 106 may be an annular region extending from the side surfaces 104A to 104D of the semiconductor chip 101 to a position several micrometers inward. The active region 105 may be a central region of the semiconductor chip 101 surrounded by the outer peripheral region 106. The active region 105 may be, for example, a region in which most of the element structure of the MISFET 2 is formed.

[0188] The active region 105 has an element structure of a MISFET 2. In this embodiment, the element structure is a trench gate lateral type MISFET (Metal Insulator Semiconductor Field Effect Transistor) structure.

[0189] The MISFET 2 includes a first source / drain region 107, a second source / drain region 108, and a drift region 109 as an element structure formed in the active region 105. In this embodiment, a plurality of first source / drain regions 107 and a plurality of second source / drain regions 108 are alternately arranged at intervals in the first direction X. A drift region 109 is sandwiched between adjacent first source / drain regions 107 and second source / drain regions 108. As a result, the first source / drain regions 107 and the second source / drain regions 108 face each other with the drift region 109 sandwiched between them. In FIG. 19 , from the top of the page, sets of the first source / drain region 107, drift region 109, second source / drain region 108, and drift region 109 are repeatedly arranged in the first direction X.

[0190] In the first main surface 102, a repeating structure of a plurality of first source / drain regions 107, a plurality of second source / drain regions 108, and a plurality of drift regions 109 is divided into a plurality of sections and aggregated. The plurality of sections includes a plurality of cell regions 110. The plurality of cell regions 110 is partitioned by a plurality of wiring regions 111 extending in the first direction X. In this embodiment, two wiring regions 111 extend in the first direction X, dividing the first main surface 102 into three. A region of a constant width sandwiched between the two wiring regions 111 and a region outside each wiring region 111 in the second direction Y are the cell regions 110. As a result, a plurality of (three in FIG. 19 ) cell regions 110 are arranged at intervals in the second direction Y. The wiring region 111 extends in the first direction X between adjacent cell regions 110, and crosses the vicinity of each end of the plurality of first source / drain regions 107 and the plurality of second source / drain regions .

[0191] In each cell region 110, the first source / drain region 107 and the second source / drain region 108 are formed in strip shapes extending in the second direction Y. The first source / drain regions 107, the second source / drain regions 108, and the drift regions 109 are arranged with a regularity such that regions of the same type are aligned in the second direction Y.

[0192] 19, from the top of the page, rows of a plurality of first source / drain regions 107 aligned in the second direction Y and rows of a plurality of second source / drain regions 108 aligned in the second direction Y are alternately formed. Between these rows, rows of a plurality of drift regions 109 aligned in the second direction Y are formed. As a result, the plurality of first source / drain regions 107, the plurality of second source / drain regions 108, and the plurality of drift regions 109 do not face regions of different species in the second direction Y. In other words, in FIG. 19, the plurality of first source / drain regions 107, the plurality of second source / drain regions 108, and the plurality of drift regions 109 extending in strip shapes in the second direction Y may be divided into a plurality of portions by a plurality of wiring regions 111, and each portion may constitute one first source / drain region 107, one second source / drain region 108, and one drift region 109.

[0193] A plurality of wiring layers are formed on the first main surface 102 of the semiconductor chip 101, and the above-mentioned plurality of external terminals are connected to the uppermost layer of the plurality of wiring layers. The plurality of wiring layers form a multilayer wiring structure, and only the first wiring layer 112 is shown in FIG.

[0194] The first wiring layer 112 may be referred to as the "first metal." The first wiring layer 112 includes a first gate wiring layer 113 and a first base wiring layer 114. The first wiring layer 112 includes other wiring layers, which will be described later. The first gate wiring layer 113 and the first base wiring layer 114 are wiring layers that are physically independent of each other.

[0195] The first gate wiring layer 113 includes a gate peripheral portion 115 extending along the peripheral region 106, and gate branch portions 116 extending from the gate peripheral portion 115 toward the inside of the semiconductor chip 101, on the wiring region 111, and along the peripheral edge of the semiconductor chip 101. The gate peripheral portion 115 extends linearly along the third side surface 104C on one side of the plurality of cell regions 110 in the first direction X (in this embodiment, on the third side surface 104C side). Parts of the gate branch portions 116 are formed linearly, extending in pairs from midway along the longitudinal direction of the gate peripheral portion 115 toward each wiring region 111. The pair of gate branch portions 116 are parallel to each other. Other portions of the gate branch portions 116 extend linearly on the peripheral region 106 from each of both ends of the gate peripheral portion 115.

[0196] The first gate wiring layer 113 is connected to a first gate contact 117. In this embodiment, the plurality of first gate contacts 117 are covered by the gate branch portion 116. In each gate branch portion 116, the plurality of first gate contacts 117 are arranged at intervals in the first direction X.

[0197] The first base wiring layer 114 includes a base peripheral portion 118 extending along the peripheral region 106 and a base branch portion 119 extending from the base peripheral portion 118 toward the inside of the semiconductor chip 101 over the wiring region 111. The base peripheral portion 118 is formed in a closed ring shape that collectively surrounds the multiple cell regions 110 and the first gate wiring layer 113. In this embodiment, the base peripheral portion 118 is formed in a quadrangular ring shape in a plan view. The base branch portions 119 are formed in linear shapes that extend one by one from the middle of one longitudinal side of the base peripheral portion 118 toward each wiring region 111. In this embodiment, each base branch portion 119 is arranged between a pair of gate branch portions 116 arranged in the wiring region 111 and is sandwiched between the pair of gate branch portions 116.

[0198] The first base wiring layer 114 is connected to the first base contacts 120. In this embodiment, the plurality of first base contacts 120 are covered by the base branch portion 119. In each base branch portion 119, the plurality of first base contacts 120 are arranged at intervals in the first direction X.

[0199] Fig. 20 is an enlarged view of a portion surrounded by a two-dot chain line XX in Fig. 19. Fig. 21 is an enlarged view of a portion surrounded by a two-dot chain line XX in Fig. 19. Fig. 22 is a cross-sectional view taken along line XXII-XXII in Fig. 20. Fig. 23 is a cross-sectional view taken along line XXIII-XXIII in Fig. 20. Fig. 24 is a cross-sectional view taken along line XXIV-XXIV in Fig. 20.

[0200] 20 to 24, the semiconductor device 1B includes a semiconductor chip 101. The semiconductor chip 101 is, for example, a semiconductor chip 101 made of a single layer. The semiconductor chip 101 made of a single layer has a single structure of a semiconductor substrate without an epitaxial layer. In this embodiment, the semiconductor chip 101 includes a single crystal of Si (silicon) or a wide bandgap semiconductor without an epitaxial layer. A wide bandgap semiconductor is a semiconductor having a bandgap greater than the bandgap of Si. The semiconductor chip 101 may be a Si chip or a SiC (silicon carbide) chip.

[0201] The semiconductor device 1B includes a first semiconductor region 121A of n-type (first conductivity type) formed in a region on the first main surface 102 side in the semiconductor chip 101. The first semiconductor region 121A may be referred to as a "drift layer." The first semiconductor region 121A is formed in the semiconductor chip 101 at an interval from the second main surface 103 toward the first main surface 102. The first semiconductor region 121A is formed in a layer shape extending along the first main surface 102 in a surface layer portion of the first main surface 102, and is exposed from the entire first main surface 102 and parts of the first to fourth side surfaces 104A to 104D.

[0202] Of course, the first semiconductor region 121A may be formed in the inner part of the first main surface 102 at a distance from the first to fourth side surfaces 104A to 104D in a plan view. The configuration of the first semiconductor region 121A is similar to that of the first semiconductor region 46A of the semiconductor device 1A described above.

[0203] The semiconductor device 1B includes a p-type (second conductivity type) second semiconductor region 121B formed in a region closer to the second main surface 103 than the first semiconductor region 121A in the semiconductor chip 101. The configuration of the second semiconductor region 121B is similar to that of the second semiconductor region 46B of the semiconductor device 1A described above.

[0204] The semiconductor device 1B includes an n-type (first conductivity type) third semiconductor region 121C formed in a region closer to the second main surface 103 than the second semiconductor region 121B within the semiconductor chip 101. The configuration of the third semiconductor region 121C is similar to that of the third semiconductor region 46C of the semiconductor device 1A described above.

[0205] The semiconductor device 1B includes a fourth semiconductor region 121D of p-type (second conductivity type) formed in a region of the semiconductor chip 101 closer to the second main surface 103 than the third semiconductor region 121C. The fourth semiconductor region 121D may also be referred to as a "base layer." The configuration of the fourth semiconductor region 121D is similar to that of the fourth semiconductor region 46D of the semiconductor device 1A described above.

[0206] The MISFET 2 includes a first trench structure 123, a trench connection structure 124, and a trench breakdown withstanding structure 125 as trench structures formed on the first main surface 102. The multiple first trench structures 123 may also be referred to as "trench gate structures." The multiple first trench structures 123 are arranged at intervals in the first direction X and are each formed in a band shape extending in the second direction Y. The multiple first trench structures 123 are formed in a stripe shape extending in the second direction Y in a plan view. Each of the multiple first trench structures 123 has a first end on one side and a second end on the other side in the second direction Y.

[0207] The plurality of first trench structures 123 penetrate the first semiconductor region 121A to reach the second semiconductor region 121B. In this embodiment, the plurality of first trench structures 123 each have a bottom wall located within the second semiconductor region 121B. The plurality of first trench structures 123 are configured to respectively control inversion and non-inversion of a channel (channel 184 described below) in the second semiconductor region 121B.

[0208] The plurality of first trench structures 123 may be arranged at intervals (pitch) of 0.03 μm or more and 10 μm or less (preferably 0.1 μm or more and 0.3 μm or less). The plurality of first trench structures 123 are preferably arranged at approximately equal intervals in the first direction X. Each of the plurality of first trench structures 123 may have a width in the first direction X of 0.01 μm or more and 10 μm or less (preferably 0.1 μm or more and 0.5 μm or less). Each of the plurality of first trench structures 123 may have a depth of 0.2 μm or more and 30 μm or less (preferably 0.5 μm or more and 10 μm or less).

[0209] The following describes the internal structure of one first trench structure 123. The first trench structure 123 includes a first trench 126, a gate insulating film 127 (control insulating film), a gate electrode 128 (control electrode), and a buried insulator 129.

[0210] The first trench 126 may also be referred to as a "gate trench." The first trench 126 is formed in the first main surface 102 and defines the wall surfaces (side walls and bottom wall) of the first trench structure 123. The first trench 126 exposes the first semiconductor region 121A and the second semiconductor region 121B from the wall surfaces.

[0211] The first trench 126 may be formed in a tapered shape in which the opening width narrows from the first main surface 102 side toward the bottom wall side in a cross-sectional view. Of course, the first trench 126 may be formed perpendicular to the first main surface 102. The corners on the bottom wall side of the first trench 126 may be formed in a curved shape. Of course, the entire bottom wall of the first trench 126 may be formed in a curved shape toward the second main surface 103 side.

[0212] The gate insulating film 127 covers the sidewalls and bottom wall of the first trench 126 in a film-like manner. In this embodiment, the gate insulating film 127 covers the sidewalls and bottom wall of the first trench 126 on the bottom wall side, and defines a recess space on the bottom wall side of the first trench 126. The gate insulating film 127 may have a thickness of 5 nm to 1000 nm in the normal direction to the wall surface of the first trench 126. The gate insulating film 127 includes at least one of a silicon oxide film, a silicon nitride film, an aluminum oxide film, a zirconium oxide film, a hafnium oxide film, and a tantalum oxide film. The gate insulating film 127 is preferably made of a silicon oxide film. It is particularly preferable that the gate insulating film 127 be made of an oxide (thermal oxide film) of the semiconductor chip 101.

[0213] The gate electrode 128 is embedded in the first trench 126 with a gate insulating film 127 sandwiched therebetween. Specifically, the gate electrode 128 is embedded in a recess space defined by the gate insulating film 127 on the bottom wall side of the first trench 126, and faces the second semiconductor region 121B with the gate insulating film 127 sandwiched therebetween. The gate electrode 128 crosses the depth position of a boundary portion 144A between the first semiconductor region 121A and the second semiconductor region 121B in the depth direction of the first trench 126.

[0214] The gate electrode 128 includes a plurality of lead-out portions 130 that are led out from the bottom wall side of the first trench 126 to the opening side. The number of the lead-out portions 130 is arbitrary. In this embodiment, the plurality of lead-out portions 130 includes a pair of lead-out portions 130 that are spaced apart in the second direction Y. In this embodiment, the pair of lead-out portions 130 are formed at both ends of the first trench 126, respectively. The plurality of lead-out portions 130 each extend in the second direction Y in plan view.

[0215] The multiple lead-out portions 130 define an opening-side recess from the wall surface of the first trench 126 on the opening side of the first trench 126. The opening-side recess is defined in a strip shape extending in the second direction Y in a plan view. The multiple lead-out portions 130 may protrude above the first main surface 102. The multiple lead-out portions 130 may be led out from the first trench 126 onto the first main surface 102 with part of the gate insulating film 127 sandwiched therebetween. Of course, the multiple lead-out portions 130 may be located on the bottom wall side of the first trench 126 with respect to the first main surface 102.

[0216] The gate electrode 128 may include at least one of a metal and a non-metal conductor. The gate electrode 128 may include at least one of tungsten, aluminum, copper, an aluminum alloy, a copper alloy, and conductive polysilicon. The gate electrode 128 preferably includes a non-metal conductor (conductive polysilicon). The conductive polysilicon may be p-type polysilicon or n-type polysilicon. The conductive polysilicon is preferably n-type polysilicon.

[0217] The buried insulator 129 is buried on the opening side of the first trench 126 so as to cover the gate electrode 128 within the first trench 126. Specifically, the buried insulator 129 is buried in a recess on the opening side defined by the gate electrode 128. The buried insulator 129 is provided as a field insulator that relieves the electric field with respect to the first trench 126. The buried insulator 129 is configured so that the area facing the first semiconductor region 121A exceeds the area facing the gate electrode 128 with respect to the first semiconductor region 121A.

[0218] The buried insulator 129 has a thickness greater than the thickness of the gate electrode 128 in the depth direction of the first trench 126. The buried insulator 129 includes at least one of a silicon oxide film, a silicon nitride film, an aluminum oxide film, a zirconium oxide film, a hafnium oxide film, and a tantalum oxide film. The buried insulator 129 is preferably made of a silicon oxide film. The buried insulator 129 is preferably made of the same material as the gate insulating film 127. In this case, the buried insulator 129 is preferably made of an insulating vapor-deposited film and has a density different from that of the gate insulating film 127.

[0219] The semiconductor device 1B includes a plurality of mesas 131-133 defined on the first main surface 102 (first semiconductor region 121A) by a plurality of first trench structures 123. The plurality of mesas 131-133 are defined in strip shapes extending in the second direction Y in regions between pairs of adjacent first trench structures 123. The plurality of mesas 131-133 include a plurality of first mesas 131, a plurality of second mesas 132, and a plurality of drift mesas 133.

[0220] The first mesa portion 131 and the second mesa portion 132 are arranged at an interval in the first direction X so as to sandwich one drift mesa portion 133. The first mesa portion 131 forms the first source / drain region 107 and may be referred to as the "first source / drain mesa portion." The second mesa portion 132 forms the second source / drain region 108 and may be referred to as the "second source / drain mesa portion." The drift mesa portion 133 forms the drift region 109.

[0221] The trench connection structure 124 is connected to the first trench structure 123. The plurality of trench connection structures 124 includes a trench connection structure 124 on one side connecting first ends of the plurality of first trench structures 123, and a trench connection structure 124 on the other side connecting second ends of the plurality of first trench structures 123.

[0222] In this embodiment, the trench connection structure 124 connects the ends of a pair of first trench structures 123 adjacent to each other in the first direction X. Specifically, one trench connection structure 124 is connected to each of the first ends and second ends of the pair of first trench structures 123. As a result, a plurality of closed regions surrounded by the pair of first trench structures 123 and the pair of trench connection structures 124 are formed on the first main surface 10.

[0223] The pair of first trench structures 123 and the pair of trench connection structures 124 define the first source / drain region 107 and the second source / drain region 108. In other words, the semiconductor device 1B has, on the first main surface 102 side, the first source / drain region 107 and the second source / drain region 108 that are separated and independent from each other and are surrounded by a trench structure that is rectangular in plan view and is formed by the pair of first trench structures 123 and the pair of trench connection structures 124.

[0224] The plurality of trench connection structures 124 penetrate the first semiconductor region 121A to reach the second semiconductor region 121B. That is, the trench connection structures 124, together with the plurality of first trench structures 123, define a plurality of mesas 131 to 133 (a plurality of first mesas 131, a plurality of second mesas 132, and a plurality of drift mesas 133).

[0225] The trench connection structure 124 may have a width in the second direction Y of 0.01 μm or more and 10 μm or less (preferably 0.1 μm or more and 2 μm or less). The trench connection structure 124 may have a width approximately equal to the width of the first trench structure 123. The trench connection structures 124 may each have a depth of 0.2 μm or more and 30 μm or less (preferably 0.5 μm or more and 10 μm or less). The trench connection structure 124 may have a depth approximately equal to the depth of the first trench structure 123.

[0226] The trench connection structure 124 includes a connection trench 134, a connection insulating film 135, and a connection electrode 136. The connection trench 134 is formed in the first main surface 102 so as to communicate with the plurality of first trenches 126, and defines the wall surfaces (side walls and bottom wall) of the trench connection structure 124. The wall surfaces (side walls and bottom wall) of the trench connection structure 124 are integrally connected to the wall surfaces (side walls and bottom wall) of the plurality of first trenches 126. The connection trench 134 exposes the first semiconductor region 121A and the second semiconductor region 121B from the wall surfaces.

[0227] The connection trench 134 may be formed in a tapered shape in which the opening width narrows from the first main surface 102 side toward the bottom wall side in a cross-sectional view. Of course, the connection trench 134 may be formed perpendicular to the first main surface 102. The corners on the bottom wall side of the connection trench 134 may be formed in a curved shape. Of course, the entire bottom wall of the connection trench 134 may be formed in a curved shape toward the second main surface 103 side.

[0228] The connection insulating film 135 coats the sidewalls and bottom wall of the connection trench 134 in a film-like manner. In this embodiment, the connection insulating film 135 coats the sidewalls and bottom wall on the opening side and bottom wall side of the connection trench 134, and defines a recess space in the connection trench 134. The connection insulating film 135 is integrally connected to the plurality of gate insulating films 127 at the communicating portions with the plurality of first trenches 126.

[0229] The connection insulating film 135 may have a thickness of 5 nm or more and 1000 nm or less. The connection insulating film 135 preferably has a thickness approximately equal to that of the gate insulating film 127. The connection insulating film 135 includes at least one of a silicon oxide film, a silicon nitride film, an aluminum oxide film, a zirconium oxide film, a hafnium oxide film, and a tantalum oxide film. The connection insulating film 135 is preferably made of the same material as the gate insulating layer.

[0230] The connection electrode 136 is embedded in the connection trench 134 with the connection insulating film 135 interposed therebetween, and faces the first semiconductor region 121A and the second semiconductor region 121B. The connection electrode 136 is connected to the plurality of gate electrodes 128 at the communicating portions with the plurality of first trenches 126. Specifically, the connection electrode 136 is connected to the plurality of lead-out portions 130. As a result, the connection electrode 136 is fixed to the same potential as the gate electrodes 128.

[0231] The portion of the connection electrode 136 that is continuous with the drawn-out portion 130 may be included in the components of the connection electrode 136, or may be included in the components of the gate electrode 128. The connection electrode 136 has an upper end that is located on the first main surface 102 side with respect to the upper end of the gate electrode 128. The connection electrode 136 may protrude above the first main surface 102. The connection electrode 136 may be drawn out from the connection trench 134 onto the first main surface 102 with part of the connection insulating film 135 sandwiched therebetween. Of course, the connection electrode 136 may be located on the bottom wall side of the connection trench 134 with respect to the first main surface 102.

[0232] The connection electrode 136 may include at least one of a metal and a non-metal conductor. The connection electrode 136 may include at least one of tungsten, aluminum, copper, an aluminum alloy, a copper alloy, and conductive polysilicon. The connection electrode 136 is preferably made of the same material as the gate electrode 128.

[0233] 20, each of the trench breakdown withstanding structures 125 is formed across a pair of first trench structures 123 in the first direction X. Specifically, from one of the pair of first trench structures 123 to the other, the trench breakdown withstanding structures 125 crosses each of the first source / drain regions 107 and each of the second source / drain regions 108, dividing the first source / drain regions 107 and the second source / drain regions 108 at each end.

[0234] As a result, an isolation region 137, in which parts of the first source / drain region 107 and the second source / drain region 108 are separated, is formed between the trench connection structure 124 and the trench breakdown withstanding structure 125. The isolation region 137 is a region surrounded by the pair of first trench structures 123, the trench connection structure 124, and the trench breakdown withstanding structure 125. Due to the formation of the isolation region 137, the first source / drain region 107 and the second source / drain region 108 are separated from the trench connection structure 124 in the second direction Y by the isolation region 137.

[0235] The trench breakdown withstanding structure 125 covers the ends in the second direction Y of the first source / drain region 107 and the second source / drain region 108 that are remote from the trench connection structure 124 .

[0236] The plurality of trench breakdown withstanding structures 125 penetrate the first semiconductor region 121A to reach the second semiconductor region 121B. In this embodiment, the plurality of trench breakdown withstanding structures 125 each have a bottom wall located within the second semiconductor region 121B.

[0237] The trench breakdown withstanding structure 125 may have a width in the second direction Y of 0.01 μm or more and 10 μm or less (preferably 0.1 μm or more and 2 μm or less). The trench breakdown withstanding structure 125 may have a width approximately equal to the width of the first trench structure 123. The trench breakdown withstanding structures 125 may each have a depth of 0.2 μm or more and 30 μm or less (preferably 0.5 μm or more and 10 μm or less). The trench breakdown withstanding structure 125 may have a depth approximately equal to the depth of the first trench structure 123.

[0238] The trench voltage-resistant structure 125 includes a voltage-resistant trench 138 , a voltage-resistant insulating film 139 , a voltage-resistant electrode 140 and a voltage-resistant insulator 141 . The breakdown-resistant trench 138 is formed in the first main surface 102 and defines the wall surfaces (side walls and bottom wall) of the trench breakdown-resistant structure 125. The wall surfaces (side walls and bottom wall) of the trench breakdown-resistant structure 125 are integrally connected to the wall surfaces (side walls and bottom walls) of the multiple first trenches 126. The breakdown-resistant trench 138 exposes the first semiconductor region 121A and the second semiconductor region 121B from the wall surfaces.

[0239] The voltage-resistant trench 138 may be formed in a tapered shape in which the opening width narrows from the first main surface 102 side toward the bottom wall side in a cross-sectional view. Of course, the voltage-resistant trench 138 may be formed perpendicular to the first main surface 102. The corners on the bottom wall side of the voltage-resistant trench 138 may be formed in a curved shape. Of course, the entire bottom wall of the voltage-resistant trench 138 may be formed in a curved shape toward the second main surface 103 side.

[0240] The voltage-resistant insulating film 139 coats the sidewalls and bottom wall of the voltage-resistant trench 138 in a film-like manner. In this embodiment, the voltage-resistant insulating film 139 coats the sidewalls and bottom wall on the bottom wall side of the voltage-resistant trench 138 and defines a recess space on the bottom wall side of the voltage-resistant trench 138. The voltage-resistant insulating film 139 is integrally connected to the multiple gate insulating films 127. The voltage-resistant insulating film 139 may have a thickness of 5 nm or more and 1000 nm or less in the normal direction of the wall surface of the voltage-resistant trench 138. It is preferable that the voltage-resistant insulating film 139 have a thickness approximately equal to that of the gate insulating film 127.

[0241] The voltage-resistant insulating film 139 includes at least one of a silicon oxide film, a silicon nitride film, an aluminum oxide film, a zirconium oxide film, a hafnium oxide film, and a tantalum oxide film. The voltage-resistant insulating film 139 is preferably made of the same material as the gate insulating layer.

[0242] The voltage-withstanding electrode 140 is embedded in the voltage-withstanding trench 138 with a voltage-withstanding insulating film 139 sandwiched therebetween. Specifically, the voltage-withstanding electrode 140 is embedded in a recess space partitioned by the voltage-withstanding insulating film 139 on the bottom wall side of the voltage-withstanding trench 138, and faces the second semiconductor region 121B with the voltage-withstanding insulating film 139 sandwiched therebetween. The voltage-withstanding electrode 140 is integrally connected to the gate electrode 128. The voltage-withstanding electrode 140 traverses the depth position of the boundary between the first semiconductor region 121A and the second semiconductor region 121B in the depth direction of the voltage-withstanding trench 138.

[0243] The voltage-bearing electrode 140 may include at least one of a metal and a non-metal conductor. The voltage-bearing electrode 140 may include at least one of tungsten, aluminum, copper, an aluminum alloy, a copper alloy, and conductive polysilicon. The voltage-bearing electrode 140 preferably includes a non-metal conductor (conductive polysilicon). The conductive polysilicon may be p-type polysilicon or n-type polysilicon. The conductive polysilicon is preferably n-type polysilicon.

[0244] The voltage-withstanding insulator 141 is embedded in the voltage-withstanding trench 138 on the opening side of the voltage-withstanding trench 138 so as to cover the voltage-withstanding electrode 140. Specifically, the voltage-withstanding insulator 141 is embedded in an opening-side recess defined by the voltage-withstanding electrode 140. The voltage-withstanding insulator 141 is provided as a field insulator that reduces the electric field to the voltage-withstanding trench 138. The voltage-withstanding insulator 141 is configured so that the facing area of ​​the first semiconductor region 121A exceeds the facing area of ​​the voltage-withstanding electrode 140 to the second semiconductor region 121B.

[0245] The voltage-resistant insulator 141 has a thickness greater than that of the voltage-resistant electrode 140 in the depth direction of the voltage-resistant trench 138. The voltage-resistant insulator 141 includes at least one of a silicon oxide film, a silicon nitride film, an aluminum oxide film, a zirconium oxide film, a hafnium oxide film, and a tantalum oxide film. The voltage-resistant insulator 141 is preferably made of a silicon oxide film. The voltage-resistant insulator 141 is preferably made of the same material as the voltage-resistant insulating film 139. In this case, the voltage-resistant insulator 141 is preferably made of an insulating vapor-deposited film and has a density different from that of the voltage-resistant insulating film 139.

[0246] In the multiple first mesas 131, the first source / drain regions 107 are formed by the first semiconductor regions 121A. A first contact region 142 is formed in a surface layer portion of the first source / drain region 107. The first contact region 142 has a higher n-type impurity concentration than the first semiconductor region 121A. The n-type impurity concentration of the first contact region 142 is 1×10 18 cm -3 More than 1×10 21 cm -3 Below (in this form 1 × 10 19 cm -3 degree).

[0247] The first contact region 142 is preferably formed in the center of the corresponding first mesa portion 131 in a plan view. The first contact region 142 has a length in the second direction Y that is less than the length of the first trench structure 123, and is formed spaced apart inward from both ends of the first trench structure 123. Both ends of the first contact region 142 face the trench breakdown withstanding structure 125 in the second direction Y, sandwiching a part of the first semiconductor region 121A therebetween.

[0248] The first contact region 142 extends in the lateral direction (second direction Y) along the first main surface 102 in a cross-sectional view. Specifically, the first contact region 142 is formed at a depth position on the first main surface 102 side with respect to the upper end portion of the gate electrode 128. The first contact region 142 faces the buried insulator 129 with a part of the first semiconductor region 121A interposed therebetween in the lateral direction along the first main surface 102. The first contact region 142 is spaced apart from the upper end portion of the gate electrode 128 toward the first main surface 102, and does not face the gate electrode 128 in the lateral direction along the first main surface 102. This reduces the electric field applied to the plurality of first trench structures 123.

[0249] The first contact region 142 may have a thickness of 10 nm to 150 nm (preferably 50 nm to 100 nm). The first contact region 142 is preferably formed at a distance of 0.1 μm to 2 μm (preferably 0.5 μm to 1.5 μm) from the upper end of the gate electrode 128 in the thickness direction (normal direction Z) of the semiconductor chip 101.

[0250] In the multiple second mesas 132, the second source / drain regions 108 are formed by the first semiconductor regions 121A. Second contact regions 143 are formed in the surface layer portions of the second source / drain regions 108. The second contact regions 143 have a higher n-type impurity concentration than the first semiconductor regions 121A. The n-type impurity concentration of the second contact regions 143 is 1×10 18 cm -3 More than 1×10 21 cm -3 Below (in this form 1 × 10 19 cm -3 degree).

[0251] The second contact region 143 is preferably formed in the center of the corresponding second mesa portion 132 in plan view. The second contact region 143 has a length in the second direction Y that is less than the length of the first trench structure 123, and is formed spaced apart inward from both ends of the first trench structure 123. Both ends of the second contact region 143 face the trench breakdown withstanding structure 125 in the second direction Y, sandwiching a part of the first semiconductor region 121A therebetween.

[0252] The second contact region 143 extends in the lateral direction (second direction Y) along the first main surface 102 in a cross-sectional view. Specifically, the second contact region 143 is formed at a depth position on the first main surface 102 side with respect to the upper end portion of the gate electrode 128. The second contact region 143 faces the buried insulator 129 with a part of the first semiconductor region 121A interposed therebetween in the lateral direction along the first main surface 102. The second contact region 143 is spaced from the upper end portion of the gate electrode 128 toward the first main surface 102, and does not face the gate electrode 128 in the lateral direction along the first main surface 102. This reduces the electric field applied to the plurality of first trench structures 123.

[0253] The second contact region 143 may have a thickness of 10 nm to 150 nm (preferably 50 nm to 100 nm). The second contact region 143 is preferably formed at a distance of 0.1 μm to 2 μm (preferably 0.5 μm to 1.5 μm) from the upper end of the gate electrode 128 in the thickness direction (normal direction Z) of the semiconductor chip 101.

[0254] In the multiple drift mesas 133, the drift region 109 is formed by the first semiconductor region 121A. In this embodiment, the drift region 109 is formed by the first semiconductor region 121A over the entire area from a boundary 144A between the first semiconductor region 121A and the second semiconductor region 121B to the first main surface 102. The width of the drift region 109 in the first direction X is narrower than the width of the drift region 21 of the first embodiment. For example, the width of the drift region 21 is not less than 0.2 μm and not more than 10 μm, whereas the width of the drift region 109 is not less than 0.01 μm and not more than 0.3 μm.

[0255] The wiring region 111 is formed by the first semiconductor region 121A between adjacent cell regions 110. The wiring region 111 is integrally connected to the end of the drift region 109 in the second direction Y.

[0256] In the wiring region 111, a p-type protruding portion 145 is formed, which selectively protrudes from the second semiconductor region 121B toward the first main surface 102 and into the first semiconductor region 121A. With reference to FIG. 24 , the protruding portion 145 may extend upward in a parabolic shape from a boundary 144A between the first semiconductor region 121A and the second semiconductor region 121B and have an apex in the vicinity of the first main surface 102. In this embodiment, the protruding portion 145 has an apex at a position away from the first main surface 102 toward the second main surface 103. A part of the wiring region 111 (drift region 109) may be formed between the apex of the protruding portion 145 and the first main surface 102. With reference to FIG. 20 , the protruding portion 145 is formed in a strip shape extending in the first direction X. Since the protrusion 145 is formed in the wiring region 111 (in this embodiment, a region where a current path 185 (described later) is not formed), the protrusion 145 can be formed in a strip shape. This allows a contact for a substrate potential to be formed at any position in the wiring region 111. Of course, a plurality of protrusions 145 may be arranged at intervals in the first direction X.

[0257] The protruding portion 145 has a higher p-type impurity concentration than the second semiconductor region 121B (low-concentration region 121B2). The p-type impurity concentration of the protruding portion 145 is 1×1016 cm -3 More than 1×10 22 cm -3 Below (in this form 1 × 10 19 cm -3 degree).

[0258] A first impurity region 146 is further formed in the plurality of isolation regions 137 and the wiring region 111. The first impurity region 146 is omitted in FIG. 20. The first impurity region 146 is formed in the surface layer portion of the first main surface 102, contacting the top of the protruding portion 145. The first impurity region 146 has a higher n-type impurity concentration than the first semiconductor region 121A. The n-type impurity concentration of the first impurity region 146 is 1×10 15 cm -3 More than 1×10 20 cm -3 Below (in this form 1 × 10 18 cm -3 degree).

[0259] The semiconductor device 1B includes a main surface insulating film 147 that selectively covers the first main surface 102. The main surface insulating film 147 may be part of the insulating layer 9 described above. The main surface insulating film 147 covers the first trench structures 123, the trench connection structures 124, and the trench breakdown withstanding structures 125 on the first main surface 102. In this embodiment, the main surface insulating film 147 covers the entire first main surface 102 and is continuous with the first to fourth side surfaces 104A to 104D.

[0260] The main surface insulating film 147 may have a thickness of 0.1 μm or more and 2 μm or less. The thickness of the main surface insulating film 147 preferably exceeds the thickness of the gate insulating film 127. The main surface insulating film 147 includes at least one of a silicon oxide film, a silicon nitride film, an aluminum oxide film, a zirconium oxide film, a hafnium oxide film, and a tantalum oxide film. The main surface insulating film 147 is preferably made of a silicon oxide film.

[0261] In this embodiment, the main surface insulating film 147 is made of the same material as the buried insulators 129 and the voltage-resistant insulators 141, and is formed integrally with the buried insulators 129 and the voltage-resistant insulators 141. That is, the main surface insulating film 147 extends from above the first main surface 102 into the multiple first trenches 126 and the voltage-resistant trenches 138 as part of the buried insulators 129 and the voltage-resistant insulators 141. In other words, the main surface insulating film 147 is made of an insulating film in which the portions of the multiple buried insulators 129 that protrude from the multiple first trenches 126 and the portions of the multiple voltage-resistant insulators 141 that protrude from the multiple voltage-resistant trenches 138 are integrated into a film shape on the first main surface 102.

[0262] The semiconductor device 1B includes a plurality of first electrodes 148 electrically connected to the first semiconductor region 121A in the plurality of first mesas 131. In this embodiment, the plurality of first electrodes 148 are provided as "first lower contacts." The plurality of first electrodes 148 penetrate the main surface insulating film 147 and are connected to the plurality of first mesas 131, respectively. Specifically, the plurality of first electrodes 148 are respectively arranged in a plurality of first connection openings 149 formed in the main surface insulating film 147.

[0263] Each of the multiple first electrodes 148 is made of metal. In this embodiment, each of the multiple first electrodes 148 has a laminated structure including a first barrier film 150 and a first electrode body 151. The first barrier film 150 is formed in the form of a film along the inner wall of the first connection opening 149. The first barrier film 150 may be made of a titanium-based metal film. The first barrier film 150 may have a single-layer structure or a laminated structure including either or both of a titanium film and a titanium nitride film.

[0264] The first electrode body 151 is embedded in the first connection opening 149 with the first barrier film 150 sandwiched therebetween, and is electrically connected to the first mesa portion 131 (first contact region 142) with the first barrier film 150 sandwiched therebetween. The first electrode body 151 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, and a copper alloy. In this embodiment, the first electrode body 151 contains tungsten. Of course, the multiple first electrodes 148 may not have the first barrier film 150 and may be composed only of the first electrode body 151.

[0265] The semiconductor device 1B includes a plurality of second electrodes 152 electrically connected to the first semiconductor region 121A in the plurality of second mesas 132. In this embodiment, the plurality of second electrodes 152 are provided as "second lower contacts." The plurality of second electrodes 152 penetrate the main surface insulating film 147 and are connected to the plurality of second mesas 132, respectively. Specifically, the plurality of second electrodes 152 are respectively arranged in a plurality of second connection openings 153 formed in the main surface insulating film 147.

[0266] Each of the multiple second electrodes 152 is made of metal. In this embodiment, each of the multiple second electrodes 152 has a layered structure including a second barrier film 154 and a second electrode body 155. The second barrier film 154 is formed in the form of a film along the inner wall of the second connection opening 153. The second barrier film 154 may be made of a titanium-based metal film. The second barrier film 154 may have a single-layer structure or a layered structure including either or both of a titanium film and a titanium nitride film.

[0267] The second electrode body 155 is embedded in the second connection opening 153 with the second barrier film 154 sandwiched therebetween, and is electrically connected to the second mesa portion 132 (second contact region 143) with the second barrier film 154 sandwiched therebetween. The second electrode body 155 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, and a copper alloy. In this embodiment, the second electrode body 155 contains tungsten. Of course, the multiple second electrodes 152 may not have the second barrier film 154 and may be composed only of the second electrode body 155.

[0268] The semiconductor device 1B includes a plurality of second trench structures 156 formed in the first main surface 102 in the wiring region 111. In this embodiment, the multiple second trench structures 156 are arranged at intervals in the first direction X. For example, if the multiple protrusions 145 are formed at intervals in the first direction X, the multiple second trench structures 156 may be formed in a one-to-one correspondence with each protrusion 145. Each second trench structure 156 is arranged in a position facing each drift region 109 near the end of each drift region 109 in the second direction Y. In this embodiment, the second trench structures 156 are arranged adjacent to each other at both ends of the drift region 109 in the second direction Y.

[0269] The second trench structure 156 is formed to reach the protruding portion 145. In this embodiment, the second trench structure 156 is formed shallower than the first trench structure 123. Specifically, the second trench structure 156 penetrates the first impurity region 146 and reaches the protruding portion 145. The second trench structure 156 has a bottom wall located within the protruding portion 145.

[0270] The width of the second trench structure 156 may be equal to or greater than the width of the first trench structure 123, or may be less than the width of the first trench structure 123. The second trench structure 156 may have a depth of 0.1 μm to 10 μm (preferably 0.2 μm to 0.5 μm). This depth allows a silicide layer 162 (described below) to be formed over the entire second trench structure 156.

[0271] The second trench structure 156 includes a base trench 157 and a base electrode 158. The base electrode 158 is provided as a "first base contact 120" in this embodiment.

[0272] The base trench 157 is formed in the first main surface 102, penetrating the main surface insulating film 147, and defines the wall surfaces (side walls and bottom wall) of the second trench structure 156. In this embodiment, the base trench 157 includes a base connection opening 159 formed in the main surface insulating film 147. Specifically, the base trench 157 penetrates the main surface insulating film 147 and the first impurity region 146 to reach the protruding portion 145. The base trench 157 exposes the first impurity region 146 and the protruding portion 145 from the wall surfaces.

[0273] Base trench 157 may be formed in a tapered shape in which the opening width narrows from the first main surface 102 side toward the bottom wall side in a cross-sectional view. Of course, base trench 157 may be formed perpendicular to first main surface 102. The corners on the bottom wall side of base trench 157 may be formed in a curved shape. Of course, the entire bottom wall of base trench 157 may be formed in a curved shape toward second main surface 103.

[0274] The base electrode 158 is buried in the base trench 157 without an insulating film therebetween. The base electrode 158 is mechanically and electrically connected to the first impurity region 146 and the protruding portion 145 within the base trench 157, and is mechanically connected to the main surface insulating film 147. Within the base trench 157, the base electrode 158 has a portion located on the semiconductor chip 101 side with respect to the first main surface 102, and a portion located on the main surface insulating film 147 side with respect to the first main surface 102. In other words, the base electrode 158 has an upper end portion that protrudes above the first main surface 102. Furthermore, the upper end portion of the base electrode 158 protrudes above the upper end portion of the gate electrode 128 (the upper end portion of the drawn-out portion 130).

[0275] The base electrode 158 may include at least one of a metal and a non-metal conductor. The base electrode 158 is preferably formed of a conductive material different from that of the gate electrode 128. The base electrode 158 preferably includes a metal. In this embodiment, the base electrode 158 has a layered structure including a base barrier film 160 and a base electrode body 161.

[0276] The base barrier film 160 is formed in a film shape along the sidewalls and bottom wall of the base trench 157, and covers the first impurity region 146, the protruding portion 145, and the main surface insulating film 147 within the base trench 157. The base barrier film 160 defines a recess space within the base trench 157. The base barrier film 160 may be made of a titanium-based metal film. The base barrier film 160 may have a single-layer structure or a multilayer structure including either or both of a titanium film and a titanium nitride film. The base barrier film 160 is preferably made of the same material as the first barrier film 150 and the second barrier film 154.

[0277] The base electrode body 161 is embedded in the base trench 157 with the base barrier film 160 sandwiched therebetween, and covers the first impurity region 146, the protruding portion 145, and the main surface insulating film 147 with the base barrier film 160 sandwiched therebetween. The base electrode body 161 is electrically connected to the first impurity region 146 and the protruding portion 145 via the base barrier film 160. The base electrode body 161 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, and a copper alloy. The base electrode body 161 is preferably made of the same material as the first electrode body 151 and the second electrode body 155. In this embodiment, the base electrode body 161 contains tungsten. Of course, the base electrode 158 may be formed only by the base electrode body 161 without the base barrier film 160.

[0278] A silicide layer 162 is formed on the inner wall of the base trench 157. The silicide layer 162 is formed over the entire sidewall and bottom wall of the base trench 157 at the boundary between the semiconductor chip 101 and the base barrier film 160. The silicide layer 162 may cross the boundary between the first impurity region 146 and the protruding portion 145 in the thickness direction of the semiconductor chip 101 from top to bottom.

[0279] If the silicide layer 162 is formed over the entire sidewall and bottom wall of the base trench 157, the surface condition of the inner wall of the base trench 157 can be improved and smoothed, thereby achieving good contact between the base electrode body 161 and the base trench 157. This reduces the contact resistance of the base electrode body 161.

[0280] The semiconductor device 1B includes a plurality of third electrodes 163 electrically connected to the plurality of first trench structures 123. The plurality of third electrodes 163 are provided as "first gate contacts 117." The plurality of third electrodes 163 penetrate the main surface insulating film 147 and are mechanically and electrically connected to either or both of the plurality of first trench structures 123 (lead-out portions 130) and the plurality of trench connection structures 124 (connection electrodes 136).

[0281] Specifically, the multiple third electrodes 163 are respectively disposed in multiple third connection openings 164 formed in the main surface insulating film 147. In this embodiment, the multiple third electrodes 163 are mechanically and electrically connected to the multiple trench connection structures 124. That is, the multiple third electrodes 163 are electrically connected to the multiple first trench structures 123 via the multiple trench connection structures 124.

[0282] In this embodiment, the plurality of third electrodes 163 are formed to correspond to the respective trench connection structures 124 in plan view. The planar shape of the plurality of third electrodes 163 is arbitrary. The plurality of third electrodes 163 may be formed in a circular or rectangular shape in plan view.

[0283] Each of the multiple third electrodes 163 is made of metal. In this embodiment, each of the multiple third electrodes 163 has a layered structure including a third barrier film 165 and a third electrode body 166. The third barrier film 165 is formed in a film shape along the inner wall of the third connection opening 164. The third barrier film 165 may be made of a titanium-based metal film. The third barrier film 165 may have a single-layer structure or a layered structure including either or both of a titanium film and a titanium nitride film. The third barrier film 165 is preferably made of the same material as the first barrier film 150, the second barrier film 154, and the base barrier film 160.

[0284] The third electrode body 166 is embedded in the third connection opening 164 with the third barrier film 165 sandwiched therebetween, and is electrically connected to the lead portion 130 (connection electrode 136) with the third barrier film 165 sandwiched therebetween. The third electrode body 166 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, and a copper alloy. The third electrode body 166 is preferably made of the same material as the first electrode body 151. In this embodiment, the third electrode body 166 contains tungsten. Of course, the multiple third electrodes 163 may not have the third barrier film 165 and may be composed only of the third electrode body 166.

[0285] The semiconductor device 1B includes a first interlayer insulating film 168 stacked on the main surface insulating film 147. The first interlayer insulating film 168 may be part of the insulating layer 9 described above. The first interlayer insulating film 168 may contain at least one of silicon oxide and silicon nitride. The first interlayer insulating film 168 covers the entire main surface insulating film 147 and is continuous with the first to fourth side surfaces 104A to 104D. The first interlayer insulating film 168 may have a flat surface extending along the first main surface 102. The flat surface of the first interlayer insulating film 168 may have grinding marks.

[0286] A first wiring layer 112 is formed on the first interlayer insulating film 168. The first wiring layer 112 may contain at least one of titanium, tungsten, aluminum, copper, an aluminum alloy, a copper alloy, and conductive polysilicon. The first wiring layer 112 may contain at least one of a Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.

[0287] As described above, the first wiring layer 112 includes the first gate wiring layer 113 and the first base wiring layer 114. Referring to FIG. 21 , one of a pair of first gate wiring layers 113 (gate branch portions 116) extending in the first direction X through the wiring region 111 is connected to the connection electrode 136 of the cell region 110 on one side of the wiring region 111. The other of the pair of first gate wiring layers 113 (gate branch portions 116) is connected to the third electrode 163 (connection electrode 136) of the cell region 110 on the other side of the wiring region 111. In this embodiment, the first gate wiring layer 113 is arranged to cover the trench connection structure 124 but not to cover the trench breakdown withstanding structure 125 in a plan view.

[0288] The first base wiring layer 114 extends in the wiring region 111 in the first direction X and is connected to a plurality of base electrodes 158 (first base contacts 120). In this embodiment, as shown in FIG. 19 , the plurality of first base contacts 120 are arranged below the base outer periphery 118 and the base branch portion 119 and are connected to the base outer periphery 118 and the base branch portion 119.

[0289] The first wiring layer 112 further includes a first lower wiring layer 169 and a second lower wiring layer 170. Referring to Fig. 22, the first lower wiring layer 169 penetrates the first interlayer insulating film 168 and is connected to the first electrode 148, and the second lower wiring layer 170 penetrates the first interlayer insulating film 168 and is connected to the second electrode 152.

[0290] The semiconductor device 1B includes a second interlayer insulating film 171 stacked on the first interlayer insulating film 168 so as to cover the first wiring layer 112. The second interlayer insulating film 171 may be part of the insulating layer 9 described above. The second interlayer insulating film 171 may contain at least one of silicon oxide and silicon nitride. The second interlayer insulating film 171 covers the entire first interlayer insulating film 168 and is continuous with the first to fourth side surfaces 104A to 104D. The second interlayer insulating film 171 may have a flat surface extending along the first main surface 102. The flat surface of the second interlayer insulating film 171 may have grinding marks.

[0291] A second wiring layer 172 is formed on the second interlayer insulating film 171. The second wiring layer 172 may contain at least one of titanium, tungsten, aluminum, copper, an aluminum alloy, a copper alloy, and conductive polysilicon. The second wiring layer 172 may contain at least one of a Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.

[0292] The second wiring layer 172 includes a first upper wiring layer 173, a second upper wiring layer 174, a second gate wiring layer (not shown), and a second base wiring layer (not shown). The first upper wiring layer 173 is connected to the first lower wiring layer 169 through the second interlayer insulating film 171. The second upper wiring layer 174 is connected to the second lower wiring layer 170 through the second interlayer insulating film 171. The second gate wiring layer is connected to the first gate wiring layer 113 through the second interlayer insulating film 171. The second base wiring layer is connected to the first base wiring layer 114 through the second interlayer insulating film 171.

[0293] The semiconductor device 1B includes a top insulating film 175 formed on the second interlayer insulating film 171. The top insulating film 175 may be part of the insulating layer 9 described above. The top insulating film 175 may also be referred to as a "passivation film." The top insulating film 175 may have a layered structure including an inorganic insulating film (inorganic film) and an organic insulating film (organic film) stacked in this order from the second interlayer insulating film 171 side. Of course, the top insulating film 175 may have a single-layer structure made of an inorganic insulating film (inorganic film) or an organic insulating film (organic film). The inorganic insulating film is preferably made of an insulating material different from that of the second interlayer insulating film 171. The inorganic insulating film may be made of, for example, a silicon nitride film. The organic insulating film may be made of a photosensitive resin. The organic insulating film may include at least one of a polyimide film, a polyamide film, and a polybenzoxazole film.

[0294] On the uppermost insulating film 175, a plurality of external terminals 4 to 7 are formed, similarly to the first embodiment. The semiconductor device 1B includes a back surface protective film 176 that covers the second main surface 103 of the semiconductor chip 101. In this embodiment, the back surface protective film 176 covers the entire second main surface 103 and also covers the first to fourth side surfaces 104A to 104D. The back surface protective film 176 may have a single-layer structure made of an inorganic insulating film (inorganic film) or an organic insulating film (organic film). The inorganic insulating film may be made of, for example, a silicon nitride film. The organic insulating film may be made of a photosensitive resin. The organic insulating film may include at least one of a polyimide film, a polyamide film, and a polybenzoxazole film.

[0295] 22, the semiconductor device 1B includes a first pn junction 177 and a second pn junction 178 formed inside the semiconductor chip 101. The first pn junction 177 is formed at a boundary 144A between the first semiconductor region 121A and the second semiconductor region 121B on the first mesa portion 131 side. As a result, a first body diode D1 including the second semiconductor region 121B as an anode region and the first semiconductor region 121A as a cathode region is formed in the first mesa portion 131.

[0296] The second pn junction 178 is formed at the boundary 144A between the first semiconductor region 121A and the second semiconductor region 121B on the second mesa 132 side. As a result, a second body diode D2 including the second semiconductor region 121B as an anode region and the first semiconductor region 121A as a cathode region is formed in the second mesa 132. The anode of the second body diode D2 (second pn junction 178) is electrically connected to the anode of the first body diode D1 (first pn junction 177) via the second semiconductor region 121B.

[0297] (Function of semiconductor device 1B) Fig. 25 is a cross-sectional view showing a current path 185 of a semiconductor device 1B according to a second embodiment of the present disclosure. Fig. 26 is a plan view showing a current path 185 of a semiconductor device 1B according to a second embodiment of the present disclosure. The current path 185 includes a first current path 185A and a second current path 185B.

[0298] The semiconductor device 1B has a trench-gate lateral MISFET structure. In this MISFET structure, a gate potential is applied to the first trench structure 123 (gate electrode 128), a drain potential is applied to the first mesa portion 131, and a source potential is applied to the second mesa portion 132. As a result, a channel 184 is formed in the second semiconductor region 121B in a region below the first trench structure 123, and a first lateral current path 185A is formed connecting the first electrode 148 (first mesa portion 131) and the second electrode 152 (second mesa portion 132).

[0299] As shown in FIG. 25, the first current path 185A is a path through which current flows in the order of the first mesa portion 131 (first semiconductor region 121A) → the second semiconductor region 121B (high concentration region 121B1) → the drift mesa portion 133 (first semiconductor region 121A) → the second semiconductor region 121B (high concentration region 121B1) → the second mesa portion 132 (first semiconductor region 121A).

[0300] When a current equal to or greater than a certain level flows through the first current path 185A, a second horizontal current path 185B is newly formed, connecting the first electrode 148 (first mesa portion 131) and the second electrode 152 (second mesa portion 132). The second current path 185B is a path through which a current flows in the order of the first mesa portion 131 (first semiconductor region 121A) → the second semiconductor region 121B (low-concentration region 121B2) → the third semiconductor region 121C → the second semiconductor region 121B (low-concentration region 121B2) → the second mesa portion 132 (first semiconductor region 121A). By forming the second current path 185B as the current path 185 in addition to the first current path 185A, the current flowing through the current path 185 can be increased. As a result, the on-resistance can be reduced.

[0301] 26, in the semiconductor device 1B, the base electrode 158 for fixing the potential (substrate potential) of the second semiconductor region 121B is formed in a wiring region 111 that is separated in the second direction Y from the drift region 109 in which the current path 185 is formed, and is not formed in the drift region 109. This allows the current path 185 that connects the first electrode 148 and the second electrode 152 over the shortest distance to be formed throughout the entire drift region 109. In other words, by separately arranging the wiring region 111 for fixing the substrate potential and the drift region 109 for the current path 185, the on-resistance can be reduced.

[0302] Furthermore, because no space for the base electrode 158 is required in the drift region 109, the width of the drift region 109 in the first direction X can be narrowed. This reduces the resistance value of each drift region 109 and increases the number of cells arranged in one cell region 110. As a result, the on-resistance can be reduced.

[0303] 24, the protrusion 145 extends toward the first main surface 102. This allows the contact point with the second semiconductor region 121B to be raised toward the first main surface 102 beyond the boundary 144A between the first semiconductor region 121A and the second semiconductor region 121B. Therefore, there is no need to form a second trench structure 156 that reaches the boundary 144A, and the substrate potential can be fixed by the relatively shallow second trench structure 156. Because the base trench 157 can be shallow, contact with the substrate potential can be ensured with a simple structure.

[0304] 24 , for example, if second trench structure 156 has a depth reaching second main surface 103 beyond boundary 144A, silicide layer 162 may be formed only locally on the inner wall of base trench 157. Specifically, silicide layer 162 may be formed locally on the bottom wall and the upper end of the sidewall of base trench 157, but not on other parts of the inner wall. In contrast, in the structure shown in FIG. 24 , base trench 157 is shallow, so silicide layer 162 can be formed over the entire second trench structure 156. This can improve the smoothness of the surface condition of the inner wall of base trench 157, thereby achieving good contact between base electrode body 161 and base trench 157. This can reduce the contact resistance of base electrode body 161.

[0305] Because the wiring region 111 for fixing the substrate potential is formed in the active region 105, there is no need to form a peripheral structure for fixing the substrate potential in the peripheral region 106. This makes it possible to reduce the area of ​​the peripheral region 106 and increase the area of ​​the active region 105. As a result, the current characteristics of the semiconductor device 1B can be improved. For example, in the semiconductor device 1B, the occupancy rate of the active region 105 on the first main surface 102 may be 10% or more and 99.9% or less.

[0306] Furthermore, the ends of the first source / drain region 107 and the second source / drain region 108 in the second direction Y are separated by the trench breakdown structure 125. As a result, the trench breakdown structure 125 is interposed between the first source / drain region 107 and the second source / drain region 108 and the trench connection structure 124, and therefore the breakdown voltage in the lateral direction along the first main surface 102 of the semiconductor device 1B can be improved.

[0307] (Effects of semiconductor device 1B) The semiconductor device 1B also provides the same effects as those described above in (1-1) and (1-2).

[0308] (Modification of semiconductor device 1B) Next, a modification of the semiconductor device 1B will be described. 19, the plurality of first gate contacts 117 and the plurality of first base contacts 120 are arranged at intervals in the first direction X. In contrast to this, as shown in FIG. 27, a single first gate contact 117 and a single first base contact 120 may be formed so as to cross regions near the ends of the plurality of first source / drain regions 107 and the plurality of second source / drain regions 108.

[0309] The protruding portion 145 may extend from the second semiconductor region 121B through the first semiconductor region 121A and reach the first main surface 102. As a result, the protruding portion 145 may have a top portion exposed from the first main surface 102 in the wiring region 111. In this case, the base electrode 158 does not have to be formed as the second trench structure 156. The base electrode 158 may be embedded in the base connection opening 159 and have a bottom portion on the first main surface 102. As a result, the base electrode 158 is connected to the protruding portion 145 on the first main surface 102. With this configuration, the step of forming the second trench structure 156 can be omitted, thereby simplifying the manufacturing process and reducing materials and costs.

[0310] 17, the second trench structure 156 may be deeper than the first trench structure 123. Specifically, a base trench 157 deeper than the first trench 126 may cross the boundary portion 144 and reach the second semiconductor region 121B. This makes it possible to omit the step of forming the protrusion 145, thereby simplifying the manufacturing process and reducing materials and costs.

[0311] As with the semiconductor device 1A shown in FIG. 18, the rear surface protective film 176 may not be formed on the second main surface 103 of the semiconductor chip 101, and the second main surface 103 may be an exposed surface. (Modification common to semiconductor devices 1A and 1B) Each of the above embodiments can be modified and implemented as follows.

[0312] In the above-described embodiments, examples have been described in which the "first conductivity type" is "n-type" and the "second conductivity type" is "p-type." However, a structure in which the "first conductivity type" is "p-type" and the "second conductivity type" is "n-type" may also be adopted. A specific configuration in this case can be obtained by replacing "n-type region" with "p-type region" and "n-type region" with "p-type region" in the above description and accompanying drawings.

[0313] In the above-described embodiments, when the semiconductor chip 8, 101 includes a SiC single crystal, the semiconductor chip 8, 101 preferably includes a hexagonal SiC single crystal. The hexagonal SiC single crystal has multiple polytypes, including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, and 6H-SiC single crystal, depending on the period of the atomic arrangement. Of the multiple polytypes, the semiconductor chip 8, 101 preferably includes a 4H-SiC single crystal.

[0314] In this case, it is preferable that the first main surfaces 10, 102 are formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surfaces 11, 103 are formed by the carbon surface ((000-1) surface) of the SiC single crystal. Of course, the first main surfaces 10, 102 may be formed by the carbon surface, and the second main surfaces 11, 103 may be formed by the silicon surface. The (0001) and (000-1) surfaces of the SiC single crystal are called c-planes.

[0315] The first main surfaces 10, 102 may have an off angle inclined at a predetermined angle in a predetermined off direction with respect to the c-plane of the SiC single crystal. The off direction may be the a-axis direction ([11-20] direction) of the SiC single crystal. The off angle may be 0° or more and 5.0° or less. In this case, the first direction X may be the m-axis direction of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0316] (Addendum) The technical ideas that can be grasped from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0317] [Appendix 1] a semiconductor chip (8, 101) having a first main surface (10, 102) and a second main surface (11, 103) opposite to the first main surface; a first semiconductor region (46A, 121A) of a first conductivity type formed on the first main surface (10, 102) side of the semiconductor chip (8, 101); a second semiconductor region (46B, 121B) of a second conductivity type formed on the second main surface (11, 103) side of the first semiconductor region (46A, 121A); a trench structure (17, 123) including: a trench (48, 126) that penetrates from the first main surface (10, 102) through the first semiconductor region (46A, 121A) and that divides the first semiconductor region (46A, 121A) into a first region on one side and a second region on the other side in a cross-sectional view; a control insulating film (49, 127) that covers an inner wall of the trench (48, 126); and a control electrode (50, 128) that is embedded in the trench (48, 126) across the control insulating film (49, 127) and controls a channel (96, 184) in the second semiconductor region (46B, 121B) that conducts electricity between the first region and the second region in a lateral direction along the first main surface (10, 102); a third semiconductor region (46C, 121C) of the first conductivity type formed on the second main surface (11, 103) side of the second semiconductor region (46B, 121B) and positioned on the second main surface (11, 103) side of the trench structure (17, 123) with the second semiconductor region (46B, 121B) in between; A semiconductor device (1A, 1B) including the above.

[0318] [Appendix 2] The semiconductor device (1A, 1B) according to appendix 1, wherein the thickness of the second semiconductor region (46B, 121B) directly below the tip of the trench (48, 126) is not less than 0.01 μm and not more than 10 μm.

[0319] [Appendix 3] The first semiconductor region (46A, 121A) is a first contact region (22, 142) electrically connected to a first electrode (65, 148) in the first region; a second contact region (24, 143) electrically connected to the second electrode (69, 152) in the second region; The semiconductor device (1A, 1B) according to Appendix 1 or Appendix 2, wherein at least one of the thickness of the second semiconductor region (46B, 121B) directly below the first contact region (22, 142) and the thickness of the second semiconductor region (46B, 121B) directly below the second contact region (24, 143) is not less than 0.01 μm and not more than 10 μm.

[0320] [Appendix 4] The first semiconductor region (46A, 121A) is a first contact region (22, 142) electrically connected to a first electrode (65, 148) in the first region; a second contact region (24, 143) electrically connected to the second electrode (69, 152) in the second region; A semiconductor device (1A, 1B) according to any one of Appendices 1 to 3, wherein at least one of the thickness of the second semiconductor region (46B, 121B) directly below the first contact region (22, 142) and the thickness of the second semiconductor region (46B, 121B) directly below the second contact region (24, 143) is thinner than the thickness of the second semiconductor region (46B, 121B) directly below the tip of the trench (48, 126).

[0321] [Appendix 5] The semiconductor device (1A, 1B) according to any one of appendices 1 to 4, wherein the thickness of the third semiconductor region (46C, 121C) directly below the tip of the trench (48, 126) is 0.001 μm or more.

[0322] [Appendix 6] The semiconductor device (1A, 1B) according to any one of appendices 1 to 5, wherein the concentration of the first conductivity type impurities in the third semiconductor region (46C, 121C) is lower than the concentration of the first conductivity type impurities in the first semiconductor region (46A, 121A).

[0323] [Appendix 7] The semiconductor device (1A, 1B) according to any one of appendices 1 to 6, wherein the second semiconductor region (46B, 121B) electrically separates the first semiconductor region (46A, 121A) from the third semiconductor region (46C, 121C).

[0324] [Appendix 8] a drift region (21, 109) sandwiched between a pair of the trench structures (17, 123); the first region includes a first source / drain region (19, 107) facing the drift region (21, 109) across one of the trench structures (17, 123); the second region includes a second source / drain region (20, 108) facing the drift region (21, 109) across the other trench structure (17, 123); a first source-drain electrode (65, 148) electrically connected to the first source-drain region (19, 107); The semiconductor device (1A, 1B) according to any one of appendices 1 to 7, further comprising a second source-drain electrode (69, 152) electrically connected to the second source-drain region (20, 108).

[0325] [Appendix 9] When a direction in which the drift region (21, 109), the first source / drain region (19, 107), and the second source / drain region (20, 108) are arranged with the trench structure (17, 123) sandwiched therebetween is defined as a first direction, The semiconductor device (1A, 1B) described in Appendix 8, wherein the first direction length of the drift region (21, 109) is shorter than the first direction length of the first source / drain region (19, 107) and the first direction length of the second source / drain region (20, 108).

[0326] [Appendix 10] A semiconductor chip (91) has a first main surface (92) and a second main surface (93) opposite to the first main surface (92), and includes a first conductivity type region (91B) of a first conductivity type in a surface layer portion on the first main surface (92) side, and forms a trench (48, 126) in the first conductivity type region (91B) from the first main surface (92) side; forming a second conductivity type second semiconductor region (46B, 121B) that separates the first conductivity type region (91B) into a first conductivity type first semiconductor region (46A, 121A) located on the first main surface (92) side and a first conductivity type third semiconductor region (46C, 121C) located on the second main surface (93) side by introducing a second conductivity type impurity into the first conductivity type region through the trench (48, 126); forming a control insulating film (49, 127) that covers the inner wall of the trench (48, 126); forming a control electrode (50, 128) buried in the trench (48, 126) with the control insulating film (49, 127) interposed therebetween; A method for manufacturing a semiconductor device (1A, 1B) comprising: [Explanation of symbols]

[0327] 1A, 1B...Semiconductor device 4...Base terminal (external terminal) 5...Gate terminal (external terminal) 6...First source / drain terminal (external terminal) 7...Second source / drain terminal (external terminal) 8,101...Semiconductor chips 10,102...First main surface 11,103...Second main surface 12A, 104A…Side (1st side) 12B, 104B…Side (second side) 12C, 104C…Side (3rd side) 12D, 104D…Side (4th side) 14A...insulating side (first insulating side) 14B...insulating side (second insulating side) 14C...Insulated side (third insulating side) 14D...insulated side (fourth insulated side) 15,105…active area 16,106…Outer area 17,123...Trench structure (first trench structure) 18,124...Trench connection structure 19,107...First source / drain region 20,108...Second source / drain region 21,109...Drift area 22,142…First contact area 23...First lower contact 24,143...Second contact area 25...Second lower contact 26,120…First base contact 27,117...First gate contact 28,112...1st wiring layer 29,172…Second wiring layer 30,113...First gate wiring layer 31,169...1st lower wiring layer 32,170…Second lower wiring layer 33,114...First base wiring layer 34...Second gate wiring layer 35,173...First upper wiring layer 36,174...Second upper wiring layer 37...Second base wiring layer 38...Second gate contact 39...Second base contact 40...First upper contact 41...Second upper contact 42...Gate terminal contact 43...Base terminal contact 44...First terminal contact 45...Second terminal contact 46A, 121A...first semiconductor region 46B, 121B...Second semiconductor region 46C, 121C...Third semiconductor region 46D, 121D...Fourth semiconductor region 46B1,121B1…High concentration area 46B2,121B2…Low concentration area 48,126...1st Trench 49,127...Gate insulating film 50,128...gate electrodes 51,129...Buried insulator 52,130…Drawer section 53,131…First Mesa 54,132…Second Mesa 55,133…Drift Mesa 56,134...Connection trench 57,135...Connection insulating film 58,136...Connection electrode 59,145...Protrusion 60A, 60B, 144A…Boundary part 61...Contact area 62...Current area 63,146...first impurity region 64,147...Main surface insulating film 65,148...First electrode (first source / drain electrode) 66,149...First connection opening 67,150...First barrier film 68,151...First electrode body 69,152...Second electrode (second source / drain electrode) 70,153...Second connection opening 71,154...Second barrier film 72,155…Second electrode body 73,156...Second trench structure 74,159...Base connection opening 75,157...Base trench 76,158...Base electrode 77,160...Base barrier film 78,161...Base electrode body 79,162...silicide layer 80,163…Third electrode 81,164...Third connection opening 82,165...Third barrier film 83,166…Third electrode body 85,168...First interlayer insulating film 86,171...Second interlayer insulating film 87,175...Top insulating film 88,176…Backside protective film 89,177...1st pn junction 90,178...2nd pn junction 91...Wafer 91A, 91B...Semiconductor area 92...First wafer main surface 93...Second wafer main surface 94...first base insulating film 95...Second base insulating film 96,184…channels 97,185...Current path 97A, 185A...First current path 97B, 185B...Second current path

Claims

1. a semiconductor chip having a first main surface and a second main surface opposite to the first main surface; a first semiconductor region of a first conductivity type formed on the first main surface side of the semiconductor chip; a second semiconductor region of a second conductivity type formed on the second main surface side of the first semiconductor region; a trench structure including: a trench that penetrates the first semiconductor region from the first main surface and divides the first semiconductor region into a first region on one side and a second region on the other side in a cross-sectional view; a control insulating film that covers an inner wall of the trench; and a control electrode that is embedded in the trench across the control insulating film and controls a channel in the second semiconductor region that conducts electricity between the first region and the second region in a lateral direction along the first main surface; a third semiconductor region of the first conductivity type formed on the second main surface side of the second semiconductor region and positioned on the second main surface side of the trench structure with the second semiconductor region in between; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein the thickness of said second semiconductor region directly below the tip of said trench is not less than 0.01 [mu]m and not more than 10 [mu]m.

3. The first semiconductor region is a first contact region electrically connected to the first electrode in the first region; a second contact region electrically connected to the second electrode in the second region; 2. The semiconductor device according to claim 1, wherein at least one of a thickness of the second semiconductor region directly below the first contact region and a thickness of the second semiconductor region directly below the second contact region is 0.01 μm or more and 10 μm or less.

4. The first semiconductor region is a first contact region electrically connected to the first electrode in the first region; a second contact region electrically connected to the second electrode in the second region; 2. The semiconductor device according to claim 1, wherein at least one of the thickness of the second semiconductor region directly below the first contact region and the thickness of the second semiconductor region directly below the second contact region is thinner than the thickness of the second semiconductor region directly below the tip of the trench.

5. 2. The semiconductor device according to claim 1, wherein the thickness of said third semiconductor region directly below the tip of said trench is 0.001 [mu]m or more.

6. 2. The semiconductor device according to claim 1, wherein a concentration of the first conductivity type impurity in said third semiconductor region is lower than a concentration of the first conductivity type impurity in said first semiconductor region.

7. 2. The semiconductor device according to claim 1, wherein said second semiconductor region electrically separates said first semiconductor region and said third semiconductor region.

8. a drift region sandwiched between a pair of the trench structures; the first region includes a first source / drain region facing the drift region across one of the trench structures; the second region includes a second source / drain region facing the drift region across the other trench structure, a first source / drain electrode electrically connected to the first source / drain region; a second source / drain electrode electrically connected to the second source / drain region; The semiconductor device according to claim 1 .

9. When a direction in which the drift region, the first source / drain region, and the second source / drain region are arranged with the trench structure sandwiched therebetween is defined as a first direction, 9. The semiconductor device according to claim 8, wherein the length in the first direction of said drift region is shorter than the length in the first direction of said first source / drain region and the length in the first direction of said second source / drain region.

10. forming a trench in a semiconductor chip having a first conductivity type region of a first conductivity type in a surface layer portion on the first surface side, from the first surface side to the first conductivity type region; doping a second conductivity type impurity into the first conductivity type region through the trench to form a second conductivity type second semiconductor region that separates the first conductivity type region into a first conductivity type first semiconductor region located on the first main surface side and a first conductivity type third semiconductor region located on the second main surface side; forming a control insulating film covering the inner wall of the trench; forming a control electrode buried in the trench with the control insulating film interposed therebetween; and a method for manufacturing a semiconductor device, comprising:

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