Memory device

Abstract

To provide a memory device that detects broken wirings.SOLUTION: A memory device of one embodiment includes: a first block including a first memory string having a first transistor at one end; a second transistor having a first end connected to the gate of the first transistor; a first wiring connected to the gate of the second transistor; a block decoder connected to one end of the first wiring; a third transistor having a first end connected to the other end of the first wiring; and a power supply connected to the second end of the third transistor.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] Embodiments relate to memory devices. [Background technology]

[0002] NAND flash memory is known as a memory device capable of storing data non-volatilely. Memory devices like NAND flash memory employ a three-dimensional memory structure to achieve high integration and large capacity. Large-capacity memory devices require advance detection of defective memory areas due to wiring breaks and other reasons, and management to prevent the defective memory areas from affecting operation. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 9,443,610 [Patent Document 2] U.S. Patent No. 9,224,502 [Patent Document 3] US Patent Application Publication No. 2022 / 0351802 Summary of the Invention [Problem to be solved by the invention]

[0004] Detects broken wiring. [Means for solving the problem]

[0005] The memory device of the embodiment comprises a first block including a first memory string having a first transistor at an end thereof, a second transistor having a first end connected to a gate of the first transistor, a first wiring connected to a gate of the second transistor, a block decoder connected to one end of the first wiring, a third transistor having a first end connected to the other end of the first wiring, and a power supply connected to a second end of the third transistor. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing the configuration of a memory system including a memory device according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of a circuit configuration of a memory cell array according to the first embodiment. [Figure 3] FIG. 2 is a circuit diagram showing an example of connections between a row decoder module and its peripheral circuits according to the first embodiment. [Figure 4] FIG. 2 is a circuit diagram showing an example of a circuit configuration of a row decoder module according to the first embodiment. [Figure 5] FIG. 2 is a plan view showing an example of a planar layout of the row decoder according to the first embodiment. [Figure 6] 4 is a timing chart showing a first example of a disconnection detection operation in the memory device according to the first embodiment. [Figure 7] 10 is a timing chart showing a second example of the disconnection detection operation in the memory device according to the first embodiment. [Figure 8] 10 is a timing chart showing a third example of the disconnection detection operation in the memory device according to the first embodiment. [Figure 9] 6 is a graph showing an example of a resistance measurement operation in the memory device according to the first embodiment. [Figure 10] FIG. 10 is a circuit diagram showing an example of the configuration of a memory cell array according to a second embodiment. [Figure 11] FIG. 10 is a circuit diagram showing an example of connections between a row decoder module and its peripheral circuits according to a second embodiment. [Figure 12]FIG. 10 is a plan view showing an example of a planar layout of a row decoder module in a memory device according to a second embodiment. [Figure 13] FIG. 11 is a circuit diagram showing an example of connections between a row decoder module and its peripheral circuits according to a third embodiment. [Figure 14] FIG. 11 is a plan view showing an example of a planar layout of a row decoder module in a memory device according to a third embodiment. [Figure 15] FIG. 10 is a circuit diagram showing an example of connections between a row decoder module and its peripheral circuits according to a fourth embodiment. [Figure 16] FIG. 10 is a plan view showing an example of a planar layout of a row decoder module in a memory device according to a fourth embodiment. [Figure 17] FIG. 10 is a circuit diagram showing an example of a circuit configuration of a row decoder module according to a first modification. [Figure 18] FIG. 10 is a circuit diagram showing an example of a circuit configuration of a row decoder module according to a second modification. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. The dimensions and proportions of the drawings are not necessarily the same as those in reality.

[0008] In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. When elements having similar configurations are to be particularly distinguished from one another, different letters or numbers may be added to the end of the same reference numerals.

[0009] Furthermore, in this specification, when there is a symbol Xn, which is a symbol X followed by "n", it is assumed that a voltage level that is inverted relative to the voltage level applied to the symbol X is applied to the component corresponding to the symbol Xn. In other words, the signal Xn is an inverted signal of the signal X.

[0010] In addition, in this specification, a "node" may be read as a "wiring." A "logical level of a node" may be read as a "logical level of a signal supplied to a wiring."

[0011] 1. First embodiment A first embodiment will be described.

[0012] 1.1 Configuration The configuration according to the first embodiment will be described.

[0013] 1.1.1 Memory System FIG. 1 is a block diagram showing an example of the configuration of a memory system including a memory device according to the first embodiment. The memory system 1 is a storage device configured to be connected to an external host (not shown). The memory system 1 includes, for example, an SD TM The memory system 1 includes a memory controller 2 and a memory device 3. The memory system 1 may be a memory card, a universal flash storage (UFS), or a solid state drive (SSD).

[0014] The memory controller 2 is configured by an integrated circuit such as a system-on-a-chip (SoC). The memory controller 2 controls the memory device 3 based on a request from the host. Specifically, for example, the memory controller 2 writes data requested to be written by the host to the memory device 3. In addition, the memory controller 2 reads data requested to be read by the host from the memory device 3 and transmits the data to the host.

[0015] The memory device 3 is a nonvolatile memory, such as a NAND flash memory, that stores data in a nonvolatile manner.

[0016] The communication between the memory controller 2 and the memory device 3 is compliant with, for example, an SDR (single data rate) interface, a toggle DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0017] 1.1.2 Memory Devices The internal configuration of the memory device according to the first embodiment will now be described with reference to the block diagram shown in Fig. 1. The memory device 3 includes, for example, a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0018] The memory cell array 10 includes a plurality of blocks BLK0 to BLK(n-1) (n is an integer equal to or greater than 2). The number of blocks BLK included in the memory cell array 10 may be one. A block BLK is a collection of a plurality of memory cells. A block BLK is used, for example, as a unit for erasing data. The memory cell array 10 is also provided with a plurality of bit lines and a plurality of word lines. Each memory cell is associated with, for example, one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0019] The command register 11 stores the command CMD that the memory device 3 receives from the memory controller 2. The command CMD includes, for example, an instruction to make the sequencer 13 execute various operations including a read operation, a write operation, an erase operation, and the like.

[0020] The address register 12 stores address information ADD that the memory device 3 receives from the memory controller 2. The address information ADD includes, for example, a block address BAd, a page address PAd, and a column address CAd. For example, the block address BAd, the page address PAd, and the column address CAd are used to select a block BLK, a word line, and a bit line, respectively.

[0021] The sequencer 13 controls the overall operation of the memory device 3. For example, the sequencer 13 controls the driver module 14, the row decoder module 15, the sense amplifier module 16, etc. based on the command CMD stored in the command register 11 to perform read operations, write operations, erase operations, etc.

[0022] The driver module 14 generates voltages used in read operations, write operations, erase operations, etc. Then, the driver module 14 applies the generated voltages to a signal line corresponding to a selected word line based on, for example, a page address PAd stored in the address register 12.

[0023] The row decoder module 15 selects one block BLK in the corresponding memory cell array 10 based on the block address BAd stored in the address register 12. Then, the row decoder module 15 transfers, for example, a voltage applied to a signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0024] In a write operation, the sense amplifier module 16 applies a desired voltage to each bit line in accordance with the write data DAT received from the memory controller 2. In a read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line, and transfers the determination result to the memory controller 2 as read data DAT.

[0025] 1.1.3 Memory Cell Array Next, the configuration of the memory cell array according to the first embodiment will be described.

[0026] Fig. 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array according to the first embodiment. Fig. 2 shows one block BLK among a plurality of blocks BLK included in the memory cell array 10. As shown in Fig. 2, the block BLK includes, for example, four string units SU0 to SU3.

[0027] Each of the string units SU0 to SU3 includes a plurality of NAND strings NS associated with bit lines BL0 to BL(k-1) and BL(k) to BL(m-1) (k is an integer equal to or greater than 1, m is an integer equal to or greater than 2, and k=m / 2 in a normal configuration). The number of bit lines BL may be two to four. Each NAND string NS includes, for example, memory cell transistors MT0 to MT7 and select transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge storage film and stores data in a nonvolatile manner. Each of the select transistors ST1 and ST2 is used to select a string unit SU during various operations.

[0028] In each NAND string NS, the memory cell transistors MT0 to MT7 are connected in series. The drain of the select transistor ST1 is connected to the associated bit line BL. The source of the select transistor ST1 is connected to one end of the memory cell transistors MT0 to MT7 connected in series. The drain of the select transistor ST2 is connected to the other end of the memory cell transistors MT0 to MT7 connected in series. The source of the select transistor ST2 is connected to a source line SL.

[0029] In the same block BLK, the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. Of the select transistors ST1 in string units SU0 to SU3, the gates of the select transistors ST1 connected to bit lines BL0 to BL(k-1) are connected to select gate lines SGDi0 to SGDi3, respectively. Of the select transistors ST1 in string units SU0 to SU3, the gates of the select transistors ST1 connected to bit lines BLk to BL(m-1) are connected to select gate lines SGDo0 to SGDo3, respectively. The gates of the select transistor ST2 in string units SU0 to SU3 are connected to select gate line SGS.

[0030] A different column address is assigned to each of the bit lines BL0 to BL(m-1). Each bit line BL is shared by NAND strings NS that are assigned the same column address among multiple blocks BLK. Each of the word lines WL0 to WL7 is provided for each block BLK. The source line SL is shared, for example, among multiple blocks BLK.

[0031] A collection of memory cell transistors MT connected to a common word line WL within one string unit SU is called, for example, a cell unit CU. For example, the storage capacity of a cell unit CU including memory cell transistors MT each storing one bit of data is defined as "one page of data." A cell unit CU can have a storage capacity of two or more pages of data depending on the number of bits of data stored in the memory cell transistors MT.

[0032] The circuit configuration of the memory cell array 10 included in the memory device 3 according to the first embodiment is not limited to the configuration described above. For example, the number of string units SU included in each block BLK can be designed to be any number. The number of memory cell transistors MT and select transistors ST1 and ST2 included in each NAND string NS can be designed to be any number.

[0033] 1.1.4 Row Decoder Module 3 is a circuit diagram showing an example of the connection between a row decoder module and its peripheral circuits according to the first embodiment. As shown in FIG. 3, the row decoder module 15 includes a plurality of row decoders RD (RD0, RD1, ...) and a disconnection detection circuit ODC. The number of row decoders RD corresponds to the number of blocks BLK. In the example of FIG. 3, the configuration of the row decoder RD0 corresponding to block BLK0 is shown. The row decoder RD0 includes a block decoder BD0, a transfer switch XFER0, and a disconnection detection switch SW0.

[0034] Each of the row decoders RD has the same configuration. The configuration of a row decoder RD corresponding to a certain block BLK will be described below with reference to FIG.

[0035] 1.1.4.1 Transfer Switch First, the configuration of the transfer switch XFER will be described with reference to FIG.

[0036] The transfer switch XFER includes 26 transistors TR0 to TR25. Each of the transistors TR0 to TR25 is, for example, an N-type transistor.

[0037] A first end of each of the transistors TR0, TR1, TR2, and TR3 is connected to a corresponding block BLK via a select gate line SGDo0, SGDo1, SGDo2, and SGDo3, respectively. A second end of each of the transistors TR0, TR1, TR2, and TR3 is connected to the driver module 14 via a line SGDD0, SGDD1, SGDD2, and SGDD3, respectively. A gate of each of the transistors TR0, TR1, TR2, and TR3 is connected to a corresponding block decoder BD via a line BLKSEL.

[0038] A first end of the transistor TR4 is connected to the corresponding block BLK via a select gate line SGS. A second end of each of the transistors TR4 is connected to the driver module 14 via a line SGSD. A gate of the transistor TR4 is connected to the corresponding block decoder BD via a line BLKSEL.

[0039] A first terminal of each of the transistors TR5 to TR12 is connected to a corresponding block BLK via a word line WL0 to WL7, a second terminal of each of the transistors TR5 to TR12 is connected to the driver module 14 via a line CG0 to CG7, and a gate of each of the transistors TR5 to TR12 is connected to a corresponding block decoder BD via a line BLKSEL.

[0040] A first end of each of the transistors TR13, TR14, TR15, and TR16 is connected to a corresponding block BLK via select gate lines SGDi0, SGDi1, SGDi2, and SGDi3, respectively. A second end of each of the transistors TR13, TR14, TR15, and TR16 is connected to the driver module 14 via lines SGDD0, SGDD1, SGDD2, and SGDD3, respectively. A gate of each of the transistors TR13, TR14, TR15, and TR16 is connected to a corresponding block decoder BD via a line BLKSEL.

[0041] For example, transistors TR5 to TR12 may transfer a write voltage VPGM to word lines WL0 to WL7 during a write operation and a read voltage VREAD to word lines WL0 to WL7 during a read operation, respectively. The write voltage VPGM is a high voltage sufficient to raise the threshold voltage of memory cell transistor MT. The read voltage VREAD is a high voltage sufficient to turn on memory cell transistor MT regardless of the threshold voltage of memory cell transistor MT. Therefore, a voltage VPGMH higher than the write voltage VPGM and a voltage VREADH higher than the read voltage VREAD are supplied to the gates of transistors TR0 to TR16 via wiring BLKSEL. Therefore, transistors TR0 to TR16 are designed to have a high withstand voltage sufficient to operate normally when voltages VPGMH and VREADH are applied. Hereinafter, transistors having a high withstand voltage sufficient to operate normally when voltages VPGMH and VREADH are applied will also be referred to as "high-voltage transistors." For example, a high-voltage transistor that can operate up to 30 V is designed to have a gate oxide film thickness of about 40 nm. A transistor that has a lower withstand voltage than a high-voltage transistor is also called a "low-voltage transistor" or simply a "transistor." A low-voltage transistor is designed to have a gate oxide film thickness of 5 nm to 7 nm, for example.

[0042] Similarly, the transistors TR17, TR18, TR19, and TR20 are also high-voltage transistors. A first terminal of each of the transistors TR17, TR18, TR19, and TR20 is connected to the corresponding block BLK via select gate lines SGDo0, SGDo1, SGDo2, and SGDo3, respectively. A second terminal of each of the transistors TR17, TR18, TR19, and TR20 is connected to the driver module 14 via a line USGD. A gate of each of the transistors TR17, TR18, TR19, and TR20 is connected to the corresponding block decoder BD and the open-circuit detection switch SW via a line BLKSELn.

[0043] The transistor TR21 is also a high-voltage transistor. A first terminal of the transistor TR21 is connected to the corresponding block BLK via a select gate line SGS. A second terminal of the transistor TR21 is connected to the driver module 14 via a line USGS. A gate of the transistor TR21 is connected to the corresponding block decoder BD and the open-circuit detection switch SW via a line BLKSELn.

[0044] Similarly, the transistors TR22, TR23, TR24, and TR25 are also high-voltage transistors. The first terminals of the transistors TR22, TR23, TR24, and TR25 are connected to the corresponding blocks BLK via select gate lines SGDi0, SGDi1, SGDi2, and SGDi3, respectively. The second terminals of the transistors TR22, TR23, TR24, and TR25 are connected to the driver module 14 via a line USGD. The gates of the transistors TR22, TR23, TR24, and TR25 are connected to the corresponding block decoder BD and the open-circuit detection switch SW via a line BLKSELn.

[0045] The open circuit detection circuit ODC is connected to a plurality of block decoders BD corresponding to the plurality of blocks BLK via wiring PBUSBS. The open circuit detection circuit ODC is connected to a plurality of open circuit detection switches SW corresponding to the plurality of blocks BLK via wiring BSNOD_SUP.

[0046] 1.1.4.2 Block Decoder, Open Wire Detection Switch, and Open Wire Detection Circuit Next, the configurations of the block decoder BD, the disconnection detection switch SW, and the disconnection detection circuit ODC will be described.

[0047] 4 is a circuit diagram showing an example of the circuit configuration of the row decoder module according to the first embodiment, which shows a block decoder BD in a row decoder RD corresponding to a certain block BLK, a part of a transfer switch XFER, a disconnection detection switch SW, and a disconnection detection circuit ODC.

[0048] First, the configuration of the block decoder BD will be described.

[0049] The block decoder BD includes transistors T1 to T21, inverters INV1 to INV3, and a level shifter LSTP. The transistors T1, T2, T17, and T18 are, for example, P-type transistors. The transistors T3 to T16 and T19 to T21 are, for example, N-type transistors.

[0050] The transistor T1 has a first terminal supplied with the voltage VRD, a second terminal connected to the node N1, and a gate connected to the node RDEC. The transistor T2 has a first terminal supplied with the voltage VRD, a second terminal connected to the node N1, and a gate connected to the node RDEC_SEL. The voltage VRD corresponds to, for example, a logic high level in the row decoder RD.

[0051] The inverter INV1 has an input terminal connected to the node N1 and an output terminal connected to the node RDEC_SEL, that is, the inverter INV1 inverts the logic level of the node N1 and outputs it to the node RDEC_SEL.

[0052] Transistor T3 has a first terminal connected to node N1 and a gate connected to node AROWA. Transistor T4 has a first terminal connected to the second terminal of transistor T3 and a gate connected to node AROWB. Transistor T5 has a first terminal connected to the second terminal of transistor T4 and a gate connected to node AROWC. Transistor T6 has a first terminal connected to the second terminal of transistor T5 and a gate connected to node AROWD. Transistor T7 has a first terminal connected to the second terminal of transistor T6 and a gate connected to node AROWE.

[0053] Transistor T8 has a first terminal connected to the second terminal of transistor T7, a second terminal connected to node N2, and a gate connected to node RDEC. Transistor T9 has a first terminal connected to node N2, a second terminal grounded, and a gate connected to node ROMBAEN. Hereinafter, the ground voltage is referred to as voltage VSS. Voltage VSS is, for example, 0 V.

[0054] The transistor T10 has a first terminal connected to the node N2, a second terminal grounded, and a gate connected to the node GOOD. The transistor T11 has a first terminal connected to the node GOOD, a second terminal connected to the node N3, and a gate connected to the node RFSET. The transistor T12 has a first terminal connected to the node BAD, a second terminal connected to the node N3, and a gate connected to the node RFRST. The transistor T13 has a first terminal connected to the node N3, a second terminal connected to the line PBUSBS, and a gate connected to the node RDEC_SEL.

[0055] The inverter INV2 has an input terminal connected to the node GOOD and an output terminal connected to the node BAD. That is, the inverter INV2 inverts the logic level of the node GOOD and outputs it to the node BAD. The inverter INV3 has an input terminal connected to the node BAD and an output terminal connected to the node GOOD. That is, the inverter INV3 inverts the logic level of the node BAD and outputs it to the node GOOD.

[0056] When the corresponding block BLK is in a good state, the logic levels of the node GOOD and the node BAD are "H" and "L", respectively. When the corresponding block BLK is in a bad state, the logic levels of the node GOOD and the node BAD are "L" and "H", respectively.

[0057] The transistor T14 is a high-voltage transistor having a first terminal supplied with a voltage VRD and a second terminal connected to the node VRDEC. The transistor T15 is a high-voltage transistor having a first terminal supplied with a voltage VREADH and a second terminal connected to the node VRDEC. The transistor T16 is a high-voltage transistor having a first terminal supplied with a voltage VPGMH and a second terminal connected to the node VRDEC. The level shifter LSTP includes an input terminal connected to the node RDEC_SEL, an output terminal connected to the line BLKSEL, and a control terminal connected to the node VRDEC. The level shifter LSTP is configured to amplify the voltage input from the node RDEC_SEL according to the voltage level supplied to the node VRDEC via any of the transistors T14, T15, and T16, and supply the amplified voltage to the line BLKSEL.

[0058] The transistor T17 has a first terminal to which the voltage VRD is supplied and a gate connected to the node BSNOD_EN. The transistor T18 has a first terminal connected to the second terminal of the transistor T17, a second terminal connected to one end of the wiring BLKSELn, and a gate connected to the node RDEC_SEL. The transistor T19 has a first terminal connected to one end of the wiring BLKSELn, a second terminal connected to the node N4, and a gate connected to the node RDEC_SEL. The transistor T20 has a first terminal connected to the node N4, a second terminal grounded, and a gate connected to the node BSNOD_ENn. The transistor T21 has a first terminal connected to the node N4, a second terminal connected to the wiring PBUSBS, and a gate connected to the node BSNOD_EN. The transistors T17 to T21 form an inverter. As a result, when the transistors T17 to T21 function as inverters, they invert the logic level of the node RDEC_SEL and output it to the wiring BLKSELn.

[0059] Next, the configuration of the disconnection detection switch SW will be described.

[0060] The open circuit detection switch SW includes transistors T22 and T23, which are, for example, N-type transistors.

[0061] The transistor T22 has a first terminal connected to the other end of the wiring BLKSELn and a gate connected to the node RDEC_SEL. The transistor T23 has a first terminal connected to the second terminal of the transistor T22, a second terminal connected to the wiring BSNOD_SUP, and a gate connected to the node BSNOD_EN. Note that the transistor T22 does not necessarily have to be provided. In this case, the transistor T23 has a first terminal connected to the other end of the wiring BLKSELn, a second terminal connected to the wiring BSNOD_SUP, and a gate connected to the node BSNOD_EN.

[0062] Next, the configuration of the disconnection detection circuit ODC will be described.

[0063] The open-circuit detection circuit ODC includes transistors T24, T25, and T26, a control circuit CNT, a pad PAD, and a power supply BIAS. The transistor T24 is, for example, a P-type transistor. The transistors T25 and T26 are, for example, N-type transistors.

[0064] The transistor T24 has a first terminal supplied with the voltage VRD, a second terminal connected to the line PBUSBS, and a gate connected to the node PBUSBS_PREn. The transistor T25 has a first terminal connected to the line PBUSBS, a second terminal grounded, and a gate connected to the node PBUSBS_RST. The transistor T26 has a first terminal connected to the line PBUSBS, a second terminal connected to the pad PAD, and a gate connected to the node MON_EN.

[0065] The control circuit CNT has an input terminal connected to the wiring PBUSBS. The control circuit CNT has a function of determining whether the wiring BLKSELn is broken or not based on the voltage of the wiring PBUSBS. The control circuit CNT is a circuit used in the first and second examples of the broken line detection operation described later. Therefore, the control circuit CNT does not need to be provided when the third example of the broken line detection operation described later is applied.

[0066] The pad PAD has an output end configured to be connectable to a device external to the memory device 3. The pad PAD is connected to the wiring PBUSBS via the transistor T26, and is configured to output information for determining whether or not the wiring BLKSELn is disconnected to the device external to the memory device 3. The pad PAD and the transistor T26 are circuits used in a third example of a disconnection detection operation, which will be described later. Therefore, the pad PAD and the transistor T26 do not need to be provided when the third example, which will be described later, is not applied.

[0067] The power supply BIAS has an input terminal that is grounded and an output terminal that is connected to the line BSNOD_SUP. The power supply BIAS is configured to supply, for example, any voltage that is equal to or greater than the voltage VSS and equal to or less than the voltage VRD to the line BSNOD_SUP.

[0068] 1.1.4.3 Flat Layout Next, the planar layout of the row decoder RD will be described.

[0069] 5 is a plan view showing an example of the planar layout of a row decoder according to the first embodiment. In FIG. 5, an example of the planar layout of the row decoder RD on a substrate SUB constituting a memory device 3 is shown. Hereinafter, a plane parallel to the surface of the substrate SUB is referred to as the XY plane. In the XY plane, the direction in which the word lines WL extend is referred to as the X direction. In the XY plane, the direction in which the bit lines BL extend is referred to as the Y direction. The direction intersecting with the surface of the substrate SUB is referred to as the Z direction.

[0070] 5, the substrate SUB has regions R_XFER, R_BDi, and R_BDo. The row decoder RD is made up of regions R_XFER, R_BDi, and R_BDo.

[0071] The region R_XFER is a region of the row decoder RD where the transfer switches XFER are provided. The region R_XFER is located in the center of the substrate SUB in the X direction and extends in the Y direction.

[0072] The regions R_BDi and R_BDo are regions of the row decoder RD where the block decoder BD and the disconnection detection switch SW are provided. The regions R_BDi and R_BDo sandwich the region R_XFER in the X direction and each contacts the region R_XFER.

[0073] In the regions R_BDi and R_BDo, the block decoders BD and the disconnection detection switches SW are arranged so as to be aligned in the X direction with the corresponding transfer switches XFER.

[0074] 5 shows a case where the block decoder BDx corresponding to the block BLKx is arranged in the region R_BDi so as to be aligned in the X direction with the transfer switch XFERx corresponding to the block BLKx. In this case, the open circuit detection switch SWx corresponding to the block BLKx is arranged in the region R_BDo so as to be aligned in the X direction with the transfer switch XFERx corresponding to the block BLKx.

[0075] Furthermore, a block decoder BDy corresponding to a block BLKy different from the block BLKx may be arranged in the region R_BDo so as to be aligned in the X direction with the transfer switch XFERy corresponding to the block BLKy. In this case, the open circuit detection switch SWy corresponding to the block BLKy is arranged in the region R_BDi so as to be aligned in the X direction with the transfer switch XFERy corresponding to the block BLKy.

[0076] In this way, the block decoder BD and the open circuit detection switch SW corresponding to the same block BLK are arranged so as to sandwich the corresponding transfer switch XFER in the X direction. Then, of the wiring BLKSELn, the portion connecting the block decoder BD and the open circuit detection switch SW (hereinafter referred to as the "main portion") extends in the X direction from the block decoder BD across the transfer switch XFER and reaches the open circuit detection switch SW. In the above-mentioned planar layout, the main portion of the wiring BLKSELn has a length of, for example, several hundred μm or more in proportion to the number of transistors TR in the transfer switch XFER.

[0077] 1.2 Operation Next, the disconnection detection operation in the memory device according to the first embodiment will be described.

[0078] The disconnection detection operation is an operation for detecting a disconnection of the line BLKSELn by determining whether or not the voltage supplied from the power supply BIAS to the line BSNOD_SUP is transferred to the line PBUSBS via the line BLKSELn.

[0079] The following describes three types of disconnection detection operations in the memory device 3. Note that, hereinafter, the components (blocks BLK, wiring, etc.) that are targets of disconnection detection will be referred to as "target components."

[0080] 1.2.1 First Example 6 is a timing chart showing a first example of the disconnection detection operation in the memory device according to Embodiment 1. The first example corresponds to a case where the voltage VSS is supplied from the power supply BIAS to the line BSNOD_SUP.

[0081] At time t10, the row decoder module 15 is in a standby state, and the nodes AROWA, AROWB, AROWC, AROWD, and AROWE supply a block address corresponding to the block BLK accessed immediately before, and supply a "L" level signal to the nodes RDEC, ROMBAEN, RFSET, RFRST, and BSNOD_EN. This causes the voltage VSS to be supplied to the nodes RDEC_SEL of all blocks BLK. Therefore, the voltage VSS is supplied to the lines BLKSEL of all blocks BLK. Furthermore, the voltage VRD is supplied to the lines BLKSELn of all blocks BLK. If a break occurs in the line BLKSELn, the voltage VRD is supplied to the line BLKSELn on the line PBUSBS side of the break. Meanwhile, the line BLKSELn on the line BSNOD_SUP side of the break is in an undefined state.

[0082] Furthermore, the row decoder module 15 supplies a signal of "H" level to the nodes PBUSBS_PREn and PBUSBS_RST, and a signal of "L" level to the node MON_EN, thereby supplying the voltage VSS to the line PBUSBS.

[0083] Furthermore, the row decoder module 15 sets the power supply BIAS to the voltage VSS, whereby the voltage VSS is supplied to the line BSNOD_SUP.

[0084] At time t11, the row decoder module 15 supplies a signal indicating a block address corresponding to the target block BLK (target block address in FIG. 6) to nodes AROWA, AROWB, AROWC, AROWD, and AROWE. The row decoder module 15 supplies a signal of "H" level to node ROMBAEN. As a result, node RDEC_SEL of the non-target block BLK is maintained at "L" level. On the other hand, node RDEC_SEL of the target block BLK is in a state where it can transition to "H" level regardless of whether the state of the target block BLK is good or bad. At time t11, since node RDEC is maintained at "L" level, node RDEC_SEL of the target block BLK is maintained at "L" level.

[0085] Furthermore, the row decoder module 15 supplies a signal of "L" level to the nodes PBUSBS_PREn and PBUSBS_RST, thereby supplying the voltage VRD to the line PBUSBS.

[0086] At time t12, the row decoder module 15 supplies a signal of "H" level to the node PBUSBS_PREn, which causes the line PBUSBS to enter a floating state.

[0087] At time t13, the row decoder module 15 supplies "H" level signals to the nodes BSNOD_EN and RDEC. As a result, the voltage VRD is supplied to the node RDEC_SEL of the target block BLK. Therefore, the voltage of the node VRDEC (for example, the voltage VRD) is supplied to the line BLKSEL of the target block BLK. Furthermore, the line BLKSELn of the target block BLK is connected to the lines PBUSBS and BSNOD_SUP. Note that the node RDEC_SEL of the non-target blocks BLK (other blocks in FIG. 6) is maintained at the voltage VSS. Therefore, the line BLKSEL of the non-target block BLK is maintained at the voltage VSS. If the transistor T22 is present, the line BLKSELn of the non-target block BLK is kept disconnected from the line BSNOD_SUP and the transistor T17 is turned off, bringing the line BLKSELn into a floating state. If the transistor T22 is not present, the line BLKSELn is connected to the line BSNOD_SUP.

[0088] If no open circuit occurs in the wiring BLKSELn of the target block BLK, the voltage of the wiring BLKSELn of the target block BLK drops from voltage VRD to voltage VSS. Furthermore, the wiring PBUSBS transitions from a floating state to a state in which it is connected to the wiring BSNOD_SUP via the wiring BLKSELn of the target block BLK. Therefore, the voltage of the wiring PBUSBS drops to voltage VSS. The wiring BLKSELn of the non-target block BLK goes into a floating state if the transistor T22 is present, and drops to voltage VSS if the transistor T22 is not present.

[0089] On the other hand, if a break occurs in the wiring BLKSELn of the target block BLK, the portion of the wiring BLKSELn of the target block BLK on the wiring BSNOD_SUP side from the break location drops to the voltage VSS, but the portion on the wiring PBUSBS side from the break location becomes floating. As a result, the wiring PBUSBS is maintained in a floating state.

[0090] At time t14, the control circuit CNT of the row decoder module 15 determines whether or not the voltage VSS is supplied to the line PBUSBS. If the voltage VSS is not supplied to the line PBUSBS (i.e., the line PBUSBS is in a floating state), the control circuit CNT determines that a break has occurred in the line BLKSELn of the target block BLK. If the voltage VSS is supplied to the line PBUSBS, the control circuit CNT determines that a break has not occurred in the line BLKSELn of the target block BLK.

[0091] At time t15, the row decoder module 15 supplies a "L" level signal to the nodes RDEC, ROMBAEN, and BSNOD_EN. The row decoder module 15 supplies a "H" level signal to the node PBUSBS_RST. This completes the open circuit detection operation for the target block BLK.

[0092] The above-described operation from time t10 to time t15 is executed for all blocks BLK in order, thereby completing the disconnection detection operation for all blocks BLK.

[0093] 1.2.2 Second Example 7 is a timing chart showing a second example of the disconnection detection operation in the memory device according to Embodiment 1. The second example corresponds to the case where the voltage VRD is supplied from the power supply BIAS to the line BSNOD_SUP.

[0094] At time t20, the row decoder module 15 is in a standby state, and the nodes AROWA, AROWB, AROWC, AROWD, and AROWE supply a block address corresponding to the block BLK accessed immediately before, and supply a "L" level signal to the nodes RDEC, ROMBAEN, RFSET, RFRST, and BSNOD_EN. As a result, the voltage VSS is supplied to the nodes RDEC_SEL of all blocks BLK. Therefore, the voltage VSS is supplied to the lines BLKSEL of all blocks BLK. Furthermore, the voltage VRD is supplied to the lines BLKSELn of all blocks BLK. If a break occurs in the line BLKSELn, the voltage VRD is supplied to the line BLKSELn on the line PBUSBS side from the break location. Meanwhile, the line BLKSELn on the line BSNOD_SUP side from the break location is in an undefined state.

[0095] The row decoder module 15 also supplies a "H" level signal to the nodes PBUSBS_PREn and PBUSBS_RST. The row decoder module 15 supplies a "L" level signal to the node MON_EN. As a result, the voltage VSS is supplied to the line PBUSBS.

[0096] Furthermore, the row decoder module 15 sets the power supply BIAS to the voltage VSS, whereby the voltage VSS is supplied to the line BSNOD_SUP.

[0097] At time t21, the row decoder module 15 supplies a signal indicating a block address corresponding to the target block BLK (target block address in FIG. 7) to nodes AROWA, AROWB, AROWC, AROWD, and AROWE. The row decoder module 15 supplies a signal of "H" level to node ROMBAEN. As a result, node RDEC_SEL of the non-target block BLK is maintained at "L" level. On the other hand, node RDEC_SEL of the target block BLK is in a state where it can transition to "H" level regardless of whether the state of the target block BLK is good or bad. At time t21, since node RDEC is maintained at "L" level, node RDEC_SEL of the target block BLK is maintained at "L" level.

[0098] Furthermore, the row decoder module 15 sets the power supply BIAS to the voltage VRD, thereby supplying the voltage VRD to the line BSNOD_SUP.

[0099] At time t22, the row decoder module 15 supplies an "H" level signal to the node RDEC. As a result, the voltage VRD is supplied to the node RDEC_SEL of the target block BLK. Therefore, the voltage of the node VRDEC (for example, the voltage VRD) is supplied to the line BLKSEL of the target block BLK. Furthermore, the voltage VSS is supplied to the line BLKSELn of the target block BLK via the transistor T20. That is, if a break occurs in the line BLKSELn of the target block BLK, the portion of the line BLKSELn of the target block BLK on the line PBUSBS side from the break location drops to the voltage VSS, but the portion of the line BLKSELn on the line BSNOD_SUP side from the break location remains in an undefined state. Note that the node RDEC_SEL of the non-target block BLK (other blocks in FIG. 7) is maintained at the voltage VSS. Therefore, the lines BLKSEL and BLKSELn of the non-target block BLK are maintained at the voltages VSS and VRD, respectively.

[0100] At time t23, the row decoder module 15 supplies a signal of the "L" level to the node PBUSBS_RST, which causes the line PBUSBS to enter a floating state.

[0101] At time t24, the row decoder module 15 supplies an "H" level signal to the node BSNOD_EN. As a result, the line BLKSELn of the target block BLK is connected to the lines PBUSBS and BSNOD_SUP. If the transistor T22 is present, the line BLKSELn of the non-target block BLK is kept disconnected from the line BSNOD_SUP and becomes floating as the transistor T17 is turned off. If the transistor T22 is not present, the line BLKSELn is connected to the line BSNOD_SUP.

[0102] If no break occurs in the wiring BLKSELn of the target block BLK, the voltage of the wiring BLKSELn of the target block BLK rises from voltage VSS to voltage (VRD-Vth). Here, voltage Vth is the higher of the threshold voltages of transistors T23 and T22. Furthermore, wiring PBUSBS transitions from a floating state to a state in which it is connected to wiring BSNOD_SUP via wiring BLKSELn of the target block BLK. As a result, the voltage of wiring PBUSBS becomes an "H" level that is lower than voltage (VRD-Vth). Wiring BLKSELn of the non-target block BLK becomes a floating state if transistor T22 is present, and becomes voltage (VRD-Vth) if transistor T22 is not present.

[0103] On the other hand, if a break occurs in the wiring BLKSELn of the target block BLK, the voltage of the wiring BLKSELn of the target block BLK on the wiring BSNOD_SUP side from the break location rises to the voltage (VRD-Vth), but the voltage of the wiring PBUSBS side from the break location becomes floating. As a result, the wiring PBUSBS is maintained in a floating state.

[0104] At time t25, the control circuit CNT of the row decoder module 15 determines whether or not an "H" level signal of voltage (VRD-Vth) or less is supplied to the line PBUSBS. If an "H" level signal of voltage (VRD-Vth) or less is not supplied to the line PBUSBS (i.e., the line PBUSBS is in a floating state), the control circuit CNT determines that a break has occurred in the line BLKSELn of the target block BLK. If an "H" level signal of voltage (VRD-Vth) or less is supplied to the line PBUSBS, the control circuit CNT determines that a break has not occurred in the line BLKSELn of the target block BLK.

[0105] At time t26, the row decoder module 15 supplies a "L" level signal to the nodes RDEC, ROMBAEN, and BSNOD_EN. The row decoder module 15 supplies a "H" level signal to the node PBUSBS_RST. This completes the open circuit detection operation for the target block BLK.

[0106] The above-described operation from time t20 to time t26 is executed for all blocks BLK in order, thereby completing the disconnection detection operation for all blocks BLK.

[0107] 1.2.3 Third Example 8 is a timing chart showing a third example of the disconnection detection operation in the memory device according to the first embodiment. The third example corresponds to a case where a voltage Vapp that is equal to or higher than the voltage VSS and equal to or lower than the voltage VRD-Vth is supplied from the power supply BIAS to the line BSNOD_SUP, and a signal for determining whether or not a disconnection has been detected is output to the pad PAD.

[0108] At time t30, the row decoder module 15 is in a standby state, and the nodes AROWA, AROWB, AROWC, AROWD, and AROWE supply a block address corresponding to the block BLK accessed immediately before, and a low-level signal is supplied to the nodes RDEC, ROMBAEN, RFSET, RFRST, and BSNOD_EN. This causes the voltage VSS to be supplied to the nodes RDEC_SEL of all blocks BLK. Therefore, the voltage VSS is supplied to the lines BLKSEL of all blocks BLK. Furthermore, the voltage VRD is supplied to the lines BLKSELn of all blocks BLK. If a break occurs in the line BLKSELn, the voltage VRD is supplied to the line BLKSELn on the line PBUSBS side of the break. Meanwhile, the line BLKSELn on the line BSNOD_SUP side of the break is in an undefined state.

[0109] Furthermore, the row decoder module 15 supplies a signal of "H" level to the nodes PBUSBS_PREn and PBUSBS_RST, thereby supplying the voltage VSS to the line PBUSBS.

[0110] The row decoder module 15 also supplies a signal of the "L" level to the node MON_EN, which puts the pad PAD into an undefined state.

[0111] Furthermore, the row decoder module 15 sets the power supply BIAS to the voltage VSS, whereby the voltage VSS is supplied to the line BSNOD_SUP.

[0112] At time t31, the row decoder module 15 supplies a signal indicating a block address corresponding to the target block BLK (target block address in FIG. 8) to nodes AROWA, AROWB, AROWC, AROWD, and AROWE. The row decoder module 15 supplies a signal of "H" level to node ROMBAEN. As a result, node RDEC_SEL of the non-target block BLK is maintained at "L" level. On the other hand, node RDEC_SEL of the target block BLK is in a state where it can transition to "H" level regardless of whether the state of the target block BLK is good or bad. At time t31, since node RDEC is maintained at "L" level, node RDEC_SEL of the target block BLK is maintained at "L" level.

[0113] The row decoder module 15 also supplies a signal of "H" level to the node MON_EN, thereby supplying the voltage VSS to the pad PAD.

[0114] Furthermore, the row decoder module 15 sets the power supply BIAS to the voltage Vapp, thereby supplying the voltage Vapp to the line BSNOD_SUP.

[0115] At time t32, the row decoder module 15 supplies an “H” level signal to the node RDEC. As a result, the voltage VRD is supplied to the node RDEC_SEL of the target block BLK. Therefore, the voltage of the node VRDEC (for example, the voltage VRD) is supplied to the line BLKSEL of the target block BLK. Furthermore, the voltage VSS is supplied to the line BLKSELn of the target block BLK via the transistor T20. That is, if a break occurs in the line BLKSELn of the target block BLK, the portion of the line BLKSELn of the target block BLK on the line PBUSBS side from the break location drops to the voltage VSS, but the portion of the line BLKSELn on the line BSNOD_SUP side from the break location remains in an undefined state. Note that the node RDEC_SEL of the non-target block BLK (other blocks in FIG. 8) is maintained at the voltage VSS. Therefore, the lines BLKSEL and BLKSELn of the non-target block BLK are maintained at the voltages VSS and VRD, respectively.

[0116] At time t33, the row decoder module 15 supplies a signal of the "L" level to the node PBUSBS_RST, which causes the line PBUSBS and the pad PAD to enter a floating state.

[0117] At time t34, the row decoder module 15 supplies an "H" level signal to the node BSNOD_EN. As a result, the line BLKSELn of the target block BLK is connected to the lines PBUSBS and BSNOD_SUP. If the transistor T22 is present, the line BLKSELn of the non-target block BLK is kept disconnected from the line BSNOD_SUP and becomes floating as the transistor T17 is turned off. If the transistor T22 is not present, the line BLKSELn is connected to the line BSNOD_SUP.

[0118] If no break occurs in the wiring BLKSELn of the target block BLK, the voltage of the wiring BLKSELn of the target block BLK rises from voltage VSS to voltage Vapp (assuming VRD-Vth is less than or equal to VRD). Furthermore, the wiring PBUSBS and pad PAD transition from a floating state to a state in which they are connected to the wiring BSNOD_SUP via the wiring BLKSELn of the target block BLK. Therefore, the voltages of the wiring PBUSBS and pad PAD become "H" level, which is lower than voltage Vapp. The wiring BLKSELn of the non-target block BLK becomes a floating state if transistor T22 is present, and becomes voltage Vapp if transistor T22 is not present.

[0119] On the other hand, if an open circuit occurs in the wiring BLKSELn of the target block BLK, the portion of the wiring BLKSELn of the target block BLK on the wiring BSNOD_SUP side from the open circuit location rises to voltage Vapp, while the portion on the wiring PBUSBS side from the open circuit location remains floating. Therefore, unless a voltage or current is applied from an external device, the wiring PBUSBS and pad PAD remain floating at the VSS potential set at time t32, mainly due to the wiring capacitance from the wiring PBUSBS to the pad PAD, the wiring and input capacitance from the pad PAD to the external device input terminal, and any additional stabilizing capacitance added as necessary. At time t35, it is determined whether a high-level signal with a voltage lower than Vapp is being supplied to the pad PAD. If a high-level signal with a voltage lower than Vapp is not being supplied to the pad PAD (i.e., the wiring PBUSBS is floating), it can be determined that an open circuit has occurred in the wiring BLKSELn of the target block BLK. When a signal of "H" level equal to or lower than the voltage Vapp is supplied to the pad PAD, it can be determined that no break has occurred in the wiring BLKSELn of the target block BLK.

[0120] As another example, it is also possible to measure the resistance value of the disconnection part by applying a voltage and measuring the current (or applying a current and measuring the voltage) from an external device via the pad PAD. For example, during the period from time t35 to time t36 in FIG. 8, the external device of the memory device 3 determines whether a disconnection has occurred in the wiring BLKSELn by performing a resistance measurement operation via the pad PAD. In the resistance measurement operation, at least two measurements are made of the set P=(V, I) of the voltage V and current I at the pad PAD.

[0121] FIG. 9 is a graph showing an example of the resistance measurement operation in the memory device according to the first embodiment. In FIG. 9, when the voltage PAD_V applied to the pad PAD is taken as the horizontal axis and the current PAD_I flowing through the pad PAD is taken as the vertical axis, the measured values P1 to P5 are plotted on the graph.

[0122] For example, when the measured values P1=(V1, I1), P2=(Vapp, 0), and P3=(V2, I2) are measured via the pad PAD (V1<Vapp<V2, I1<0<I2), the external device of the memory device 3 calculates the resistance value R of the wiring BLKSELn of the target block BLK as R=(V2 - V1) / (I2 - I1). Thus, when the resistance value R is a significant value, the external device of the memory device 3 determines that no disconnection has occurred in the wiring BLKSELn of the target block BLK.

[0123] On the other hand, when the measured values P4=(V1, 0), P2=(Vapp, 0), and P5=(V2, 0) are measured via the pad PAD, the external device of the memory device 3 calculates that the resistance value R of the wiring BLKSELn of the target block BLK is ∞. Thus, when the resistance value R is an abnormally large value, the external device of the memory device 3 determines that a disconnection has occurred in the wiring BLKSELn of the target block BLK.

[0124] At time t36, the row decoder module 15 supplies a "L" level signal to the nodes RDEC, ROMBAEN, BSNOD_EN, and MON_EN. The row decoder module 15 supplies a "H" level signal to the node PBUSBS_RST. As a result, if there is no break in the wiring BLKSELn of the target block BLK, the voltage VRD is supplied to the wiring BLKSELn of the target block BLK. If there is a break in the wiring BLKSELn of the target block BLK, the portion of the wiring BLKSELn of the target block BLK on the wiring BSNOD_SUP side from the break location becomes floating, and the voltage VRD is supplied to the portion of the wiring BLKSELn of the target block BLK on the wiring PBUSBS side from the break location. In addition, the pad PAD becomes undefined. This completes the break detection operation for the target block BLK.

[0125] The above-described operation from time t30 to time t36 is executed for all blocks BLK in order, thereby completing the disconnection detection operation for all blocks BLK.

[0126] 1.3 Effects of the First Embodiment According to the first embodiment, the line BLKSELn has a first terminal connected to the gates of the transistors TR17 to TR25 of the transfer switch XFER, a second terminal connected to the transistors T18 and T19 of the block decoder BD, and a third terminal connected to the transistor T23 of the open-circuit detection switch SW. The transistor T23 is connected to the power supply BIAS via the line BSNOD_SUP. This allows the power supply BIAS to supply a voltage to the line BLKSELn via the transistor T23. Therefore, the control circuit CNT can determine whether or not there is an open circuit in the line BLKSELn based on the voltage of the line PBUSBS.

[0127] Additionally, if a break occurs in the wiring BLKSELn, for example, during a read operation, an "H" level signal is no longer supplied to transistors TR17 to TR25 in the transfer switch XFER corresponding to the unselected block BLK via the wiring BLKSELn. This prevents the select gate lines SGD and SGS corresponding to the unselected block BLK from connecting to the wiring USGD and USGS, respectively, potentially turning on the select transistors ST1 and ST2 in the unselected block BLK. Therefore, unnecessary current may flow through the bit line BL via the NAND string NS of the unselected block BLK, potentially causing a read error. For this reason, it is preferable to detect a break in the wiring BLKSELn and identify the chip as defective.

[0128] According to the first embodiment, the main portion of the line BLKSELn that connects the block decoder BD and the open-circuit detection switch SW includes a portion that passes above the transfer switch XFER on the substrate SUB. As a result, during open-circuit detection, if the line BLKSELn is not open, the line PBUSBS follows the voltage of the power supply BIAS. However, if the line BLKSELn is open, the line PBUSBS enters a floating state. Specifically, for example, in a first example of open-circuit detection in which the power supply BIAS supplies voltage VSS, if the line BLKSELn is not open, the line PBUSBS drops from voltage VRD to voltage VSS. Furthermore, for example, in a second example of open-circuit detection in which the power supply BIAS supplies voltage VRD, if the line BLKSELn is not open, the line PBUSBS rises from voltage VSS to voltage (VRD-Vth). Also, for example, in the third example of the open circuit detection operation in which the power supply BIAS supplies the voltage Vapp (≦VRD-Vth), if the line BLKSELn is not open, the line PBUSBS rises from the voltage VSS to the voltage Vapp. Therefore, the control circuit CNT in the open circuit detection circuit ODC or an external device of the memory device 3 connected to the pad PAD can determine whether or not there is an open circuit in the line BLKSELn.

[0129] Furthermore, the block decoder BD is arranged in one of the regions R_BDi and R_BDo, and the corresponding disconnection detection switch SW is arranged in the other of the regions R_BDi and R_BDo. As a result, the block decoder BD and the disconnection detection switch SW are arranged to sandwich the transfer switch XFER in the X direction and adjacent to the transfer switch XFER in the X direction. Therefore, the additional length of the main part of the wiring BLKSELn due to the provision of the disconnection detection switch SW can be shortened.

[0130] Even if the transistor T22 is not provided, the connection between the wiring BSNOD_SUP and the wiring BLKSELn can be controlled by the transistor T23. According to the embodiment, the open-circuit detection switch SW includes the transistor T22 between the wiring BLKSELn and the transistor T23. This prevents the potential of the wiring BSNOD_SUP from fluctuating due to the influence of the leakage when the wiring BLKSELn has a large leak. The transistor T22 also has a gate connected to the node RDEC_SEL. This causes the voltage supplied to the gate of the transistor T22 to be the voltage VRD. This allows the transistor T22 to be a low-voltage transistor, thereby preventing an increase in the circuit area. On the other hand, if the transistor T22 is not provided, wiring corresponding to the transistor T22 and the node RDEC_SEL is not required, thereby preventing an increase in chip costs.

[0131] 2. Second embodiment Next, a second embodiment will be described.

[0132] The second embodiment differs from the first embodiment in that the regions R_XFER and R_BD are located at both ends of the substrate SUB in the X direction. The following mainly describes configurations and operations that differ from the first embodiment. Descriptions of configurations and operations that are equivalent to those of the first embodiment will be omitted as appropriate.

[0133] 2.1 Memory cell array Fig. 10 is a circuit diagram showing an example of the circuit configuration of a memory cell array according to the second embodiment, which corresponds to Fig. 2 in the first embodiment.

[0134] 10, in the second embodiment, in the same string unit SU, the gate of the select transistor ST1 is connected to one select gate line SGD. That is, the gates of the select transistors ST1 in the string units SU0 to SU3 are connected to the select gate lines SGD0 to SGD3, respectively.

[0135] 2.2 Row Decoder Module 11 is a circuit diagram showing an example of connections between a row decoder module and its peripheral circuits according to the second embodiment, and corresponds to FIG. 3 in the first embodiment.

[0136] 11, the row decoder module 15 includes a plurality of row decoders RD (RD0, RD1, ...) and a disconnection detection circuit ODC. The number of row decoders RD corresponds to the number of blocks BLK. In the example of FIG. 11, the configuration of row decoder RD0 corresponding to block BLK0 is shown. Row decoder RD0 includes a block decoder BD0, a transfer switch XFER0, and a disconnection detection switch SW0.

[0137] Each of the row decoders RD has the same configuration. The configuration of a row decoder RD corresponding to a certain block BLK will be described below with reference to FIG.

[0138] The transfer switch XFER includes 18 transistors TR4 to TR16 and TR21 to TR25, which are, for example, high-voltage N-type transistors.

[0139] A first end of the transistor TR4 is connected to the corresponding block BLK via a select gate line SGS. A second end of each of the transistors TR4 is connected to the driver module 14 via a line SGSD. A gate of the transistor TR4 is connected to the corresponding block decoder BD via a line BLKSEL.

[0140] A first terminal of each of the transistors TR5 to TR12 is connected to a corresponding block BLK via a word line WL0 to WL7, a second terminal of each of the transistors TR5 to TR12 is connected to the driver module 14 via a line CG0 to CG7, and a gate of each of the transistors TR5 to TR12 is connected to a corresponding block decoder BD via a line BLKSEL.

[0141] A first end of each of the transistors TR13, TR14, TR15, and TR16 is connected to a corresponding block BLK via select gate lines SGD0, SGD1, SGD2, and SGD3, respectively. A second end of each of the transistors TR13, TR14, TR15, and TR16 is connected to the driver module 14 via lines SGDD0, SGDD1, SGDD2, and SGDD3, respectively. A gate of each of the transistors TR13, TR14, TR15, and TR16 is connected to a corresponding block decoder BD via a line BLKSEL.

[0142] A first end of the transistor TR21 is connected to the corresponding block BLK via a select gate line SGS. A second end of the transistor TR21 is connected to the driver module 14 via a line USGS. A gate of the transistor TR21 is connected to the corresponding block decoder BD and the open-circuit detection switch SW via a line BLKSELn.

[0143] A first end of each of the transistors TR22, TR23, TR24, and TR25 is connected to the corresponding block BLK via select gate lines SGD0, SGD1, SGD2, and SGD3, respectively. A second end of each of the transistors TR22, TR23, TR24, and TR25 is connected to the driver module 14 via a line USGD. A gate of each of the transistors TR22, TR23, TR24, and TR25 is connected to the corresponding block decoder BD and the open-circuit detection switch SW via a line BLKSELn.

[0144] The open circuit detection circuit ODC is connected to a plurality of block decoders BD corresponding to the plurality of blocks BLK via wiring PBUSBS. The open circuit detection circuit ODC is connected to a plurality of open circuit detection switches SW corresponding to the plurality of blocks BLK via wiring BSNOD_SUP. The configurations of the block decoders BD, open circuit detection switches SW, and open circuit detection circuit ODC are the same as those in the first embodiment.

[0145] 2.3 Planar Layout Fig. 12 is a plan view showing an example of a planar layout of a row decoder according to the second embodiment, which corresponds to Fig. 5 in the first embodiment.

[0146] 12, the substrate SUB has regions R_XFERi, R_XFERo, regions R_BDi, and regions R_BDo. The row decoder RD is made up of regions R_XFERi, R_XFERo, regions R_BDi, and regions R_BDo.

[0147] The regions R_XFERi and R_XFERo are regions of the row decoder RD where the transfer switches XFER and the disconnection detection switches SW are provided. The regions R_XFERi and R_XFERo are located at both ends of the substrate SUB in the X direction, and extend in the Y direction.

[0148] Regions R_BDi and R_BDo are regions of the row decoder RD where block decoders BD are provided. Region R_BDi borders region R_XFERi. Region R_BDo borders region R_XFERo. Each of regions R_BDi and R_BDo is divided into a plurality of partial regions SR spaced apart in the Y direction. In the example of FIG. 12, each of regions R_BDi and R_BDo is divided into three regions: partial region SR1 and two partial regions SR2 and SR3 that sandwich partial region SR1 in the Y direction. The width of partial region SR1 in the X direction is longer than the width of partial regions SR2 and SR3 in the X direction.

[0149] In the example of FIG. 12, a block decoder BDx corresponding to a block BLKx and a block decoder BDy corresponding to a block BLKy are arranged in the partial regions SR1 and SR2 of the region R_BDi, respectively.

[0150] The transfer switch XFERx and the open-circuit detection switch SWx corresponding to the block BLKx are arranged side by side in the X direction in, for example, a region of the region R_XFERi between the partial region SR1 and the partial region SR2 of the region R_BDi. That is, the transfer switch XFERx and the open-circuit detection switch SWx are arranged at a position offset in the Y direction from the block decoder BDx. Furthermore, the block decoder BDx and the block decoder BDy are arranged at positions offset in the X direction. The block decoder BDx is farther from the region R_XFERi in the X direction than the block decoder BDy. In this case, the main portion of the wiring BLKSELn corresponding to the block BLKx extends in the X direction within the partial region SR1 between the block decoder BDx and the region R_XFERi. Furthermore, the main portion of the wiring BLKSELn corresponding to the block BLKx extends between the block decoder BDx and the open-circuit detection switch SWx so as to pass through the transfer switch XFERx without branching. Therefore, the main portion of the wiring BLKSELn corresponding to the block BLKx has a portion extending in the Y direction and a portion extending in the X direction within the partial region SR1 between the block decoder BDx and the region R_XFERi.

[0151] On the other hand, the transfer switch XFERy and the open-circuit detection switch SWy corresponding to the block BLKy are arranged, for example, in a region of the region R_XFERi that is aligned in the X direction with the partial region SR2 of the region R_BDi. That is, the transfer switch XFERy and the open-circuit detection switch SWy are arranged at approximately the same position in the Y direction as the block decoder BDy. Furthermore, the block decoder BDy is adjacent to the transfer switch XFERy in the X direction. In this case, the main portion of the wiring BLKSELn corresponding to the block BLKy extends between the block decoder BDy and the open-circuit detection switch SWy so as to pass through the transfer switch XFERy without branching. Therefore, the main portion of the wiring BLKSELn corresponding to the block BLKy does not have a portion extending in the Y direction or a portion extending in the X direction within the partial region SR2 between the block decoder BDy and the region R_XFERi. Note that the main portion may have a portion extending in the X direction within the partial region SR2 between the block decoder BDy and the region R_XFERi. In this case, the portion extending in the X direction within the partial region SR2 between the block decoder BDy and the region R_XFERi is shorter than the portion extending in the X direction within the partial region SR2 between the block decoder BDx and the region R_XFERi.

[0152] In this way, the main portion of the wiring BLKSELn corresponding to the block BLKx is longer than the main portion of the wiring BLKSELn corresponding to the block BLKy.

[0153] 2.3 Effects of the Second Embodiment The block decoder BD has fewer layout constraints than other circuits such as the sense amplifier module 16, and therefore may not necessarily be arranged adjacent to the corresponding transfer switch XFER in the X direction. In this case, the block decoder BD and the corresponding transfer switch XFER may be provided at positions separated from each other in the Y direction. In such a case, the wiring BLKSELn becomes longer than when the block decoder BD and the corresponding transfer switch XFER are provided at approximately the same positions in the Y direction, which may increase the risk of disconnection.

[0154] According to the second embodiment, when a block decoder BD is arranged in a partial region SR1 of the region R_BDi, the corresponding disconnection detection switch SW and transfer switch XFER can be arranged at a position in the region R_XFERi that is offset in the Y direction from the partial region SR1. As a result, the main portion of the wiring BLKSELn further includes relatively long portions, such as a portion extending in the Y direction between the block decoder BD and the transfer switch XFER and a portion extending in the X direction within the partial region SR between the block decoder BD and the transfer switch XFER. Although the wiring length is increased, the portion extending in the X direction between the transfer switch XFER and the disconnection detection switch SW is relatively short. Therefore, the additional length of the main portion of the wiring BLKSELn due to the provision of the disconnection detection switch SW can be shortened.

[0155] 3. Third embodiment Next, a third embodiment will be described.

[0156] The third embodiment differs from the first and second embodiments in that there are multiple blocks BLK corresponding to one block decoder BD. The following mainly describes the configuration and operation that are different from the second embodiment. Descriptions of the configuration and operation that are equivalent to those of the second embodiment will be omitted as appropriate.

[0157] 3.1 Row Decoder Module Fig. 13 is a circuit diagram showing an example of connections between a row decoder module and its peripheral circuits according to the third embodiment, which corresponds to Fig. 11 in the second embodiment.

[0158] As shown in FIG. 13, the row decoder module 15 includes a plurality of transfer switches XFER (XFER0, XFER1, XFER2, XFER3, ...), a plurality of block decoders BD (BD(0-3), ...), a plurality of disconnection detection switches SW (SW(0-3), ...), and a disconnection detection circuit ODC. The number of transfer switches XFER corresponds to the number of blocks BLK. The number of block decoders BD and disconnection detection switches SW corresponds to 1 / 4 of the number of blocks BLK. In the example of FIG. 13, transfer switches XFER0, XFER1, XFER2, and XFER3 are shown as components corresponding to blocks BLK0, BLK1, BLK2, and BLK3, respectively. In addition, a block decoder BD(0-3) and a disconnection detection switch SW(0-3) are shown as components commonly corresponding to blocks BLK0, BLK1, BLK2, and BLK3.

[0159] The transfer switch XFER0 includes 18 transistors TR4a to TR16a and TR21a to TR25a. The transfer switch XFER1 includes 18 transistors TR4b to TR16b and TR21b to TR25b. The transfer switch XFER2 includes 18 transistors TR4c to TR16c and TR21c to TR25c. The transfer switch XFER3 includes 18 transistors TR4d to TR16d and TR21d to TR25d. Each of the transistors TR4a to TR16a, TR4b to TR16b, TR4c to TR16c, and TR4d to TR16d is a high-voltage N-type transistor. Each of the transistors TR21a to TR25a, TR21b to TR25b, TR21c to TR25c, and TR21d to TR25d is also a high-voltage N-type transistor.

[0160] First, the configuration of the transfer switch XFER0 will be described.

[0161] A first terminal of the transistor TR4a is connected to the block BLK0 via a select gate line SGSa. A second terminal of the transistor TR4a is connected to the driver module 14 via a line SGSDa. A gate of the transistor TR4a is connected to the block decoder BD(0-3) via a line BLKSEL.

[0162] The first terminals of the transistors TR5a to TR12a are connected to the block BLK0 via eight corresponding word lines WLa. The second terminals of the transistors TR5a to TR12a are connected to the driver module 14 via eight corresponding wirings CGa. The gates of the transistors TR5a to TR12a are connected to the corresponding block decoders BD(0-3) via wirings BLKSEL.

[0163] The first terminals of the transistors TR13a to TR16a are connected to the block BLK0 via four corresponding select gate lines SGDa. The second terminals of the transistors TR13a to TR16a are connected to the driver module 14 via four corresponding wirings SGDDa. The gates of the transistors TR13a to TR16a are connected to the corresponding block decoders BD(0-3) via wirings BLKSEL.

[0164] A first terminal of the transistor TR21a is connected to the block BLK0 via a select gate line SGSa. A second terminal of the transistor TR21a is connected to the driver module 14 via a line USGS. A gate of the transistor TR21a is connected to the block decoder BD(0-3) and the open-circuit detection switch SW(0-3) via a line BLKSELn.

[0165] A first terminal of each of the transistors TR22a to TR25a is connected to the block BLK0 via four corresponding select gate lines SGDa. A second terminal of each of the transistors TR22a to TR25a is connected to the driver module 14 via a line USGD. A gate of each of the transistors TR22a to TR25a is connected to the block decoder BD(0-3) and the open-circuit detection switch SW(0-3) via a line BLKSELn.

[0166] Next, the configuration of the transfer switch XFER1 will be described.

[0167] A first terminal of the transistor TR4b is connected to the block BLK1 via a select gate line SGSb. A second terminal of the transistor TR4b is connected to the driver module 14 via a line SGSDb. A gate of the transistor TR4b is connected to the block decoder BD(0-3) via a line BLKSEL.

[0168] The first terminals of the transistors TR5b to TR12b are connected to the block BLK1 via eight corresponding word lines WLb. The second terminals of the transistors TR5b to TR12b are connected to the driver module 14 via eight corresponding wirings CGb. The gates of the transistors TR5b to TR12b are connected to the corresponding block decoders BD(0-3) via wirings BLKSEL.

[0169] A first terminal of each of the transistors TR13b to TR16b is connected to the block BLK1 via four corresponding select gate lines SGDb. A second terminal of each of the transistors TR13b to TR16b is connected to the driver module 14 via four corresponding wirings SGDDb. A gate of each of the transistors TR13b to TR16b is connected to a corresponding block decoder BD(0-3) via wirings BLKSEL.

[0170] A first terminal of the transistor TR21b is connected to the block BLK1 via a select gate line SGSb. A second terminal of the transistor TR21b is connected to the driver module 14 via a line USGS. A gate of the transistor TR21b is connected to the block decoder BD(0-3) and the open-circuit detection switch SW(0-3) via a line BLKSELn.

[0171] A first terminal of each of the transistors TR22b to TR25b is connected to the block BLK1 via four corresponding select gate lines SGDb. A second terminal of each of the transistors TR22b to TR25b is connected to the driver module 14 via a line USGD. A gate of each of the transistors TR22b to TR25b is connected to the block decoder BD(0-3) and the open-circuit detection switch SW(0-3) via a line BLKSELn.

[0172] Next, the configuration of the transfer switch XFER2 will be described.

[0173] A first terminal of the transistor TR4c is connected to the block BLK2 via a select gate line SGSc. A second terminal of the transistor TR4c is connected to the driver module 14 via a line SGSDc. A gate of the transistor TR4c is connected to the block decoder BD(0-3) via a line BLKSEL.

[0174] The first terminals of the transistors TR5c to TR12c are connected to the block BLK2 via eight corresponding word lines WLc. The second terminals of the transistors TR5c to TR12c are connected to the driver module 14 via eight corresponding wirings CGc. The gates of the transistors TR5c to TR12c are connected to the corresponding block decoders BD(0-3) via wirings BLKSEL.

[0175] A first terminal of each of the transistors TR13c to TR16c is connected to the block BLK2 via four corresponding select gate lines SGDc. A second terminal of each of the transistors TR13c to TR16c is connected to the driver module 14 via four corresponding wirings SGDDc. A gate of each of the transistors TR13c to TR16c is connected to a corresponding block decoder BD(0-3) via wirings BLKSEL.

[0176] A first terminal of the transistor TR21c is connected to the block BLK2 via a select gate line SGSc. A second terminal of the transistor TR21c is connected to the driver module 14 via a line USGS. A gate of the transistor TR21c is connected to the block decoder BD(0-3) and the open-circuit detection switch SW(0-3) via a line BLKSELn.

[0177] A first terminal of each of the transistors TR22c to TR25c is connected to the block BLK2 via four corresponding select gate lines SGDc. A second terminal of each of the transistors TR22c to TR25c is connected to the driver module 14 via a line USGD. A gate of each of the transistors TR22c to TR25c is connected to the block decoder BD(0-3) and the open-circuit detection switch SW(0-3) via a line BLKSELn.

[0178] Next, the configuration of the transfer switch XFER3 will be described.

[0179] A first terminal of the transistor TR4d is connected to the block BLK3 via a select gate line SGSd. A second terminal of the transistor TR4d is connected to the driver module 14 via a line SGSDd. A gate of the transistor TR4d is connected to the block decoder BD(0-3) via a line BLKSEL.

[0180] The first terminals of the transistors TR5d to TR12d are connected to the block BLK3 via eight corresponding word lines WLd. The second terminals of the transistors TR5d to TR12d are connected to the driver module 14 via eight corresponding wirings CGd. The gates of the transistors TR5d to TR12d are connected to the corresponding block decoders BD(0-3) via wirings BLKSEL.

[0181] The first terminals of the transistors TR13d to TR16d are connected to the block BLK3 via four corresponding select gate lines SGDd. The second terminals of the transistors TR13d to TR16d are connected to the driver module 14 via four corresponding lines SGDDd. The gates of the transistors TR13d to TR16d are connected to the corresponding block decoders BD(0-3) via lines BLKSEL.

[0182] A first terminal of the transistor TR21d is connected to the block BLK3 via a select gate line SGSd. A second terminal of the transistor TR21d is connected to the driver module 14 via a line USGS. A gate of the transistor TR21d is connected to the block decoder BD(0-3) and the open-circuit detection switch SW(0-3) via a line BLKSELn.

[0183] A first terminal of each of the transistors TR22d to TR25d is connected to the block BLK3 via four corresponding select gate lines SGDd. A second terminal of each of the transistors TR22d to TR25d is connected to the driver module 14 via a line USGD. A gate of each of the transistors TR22d to TR25d is connected to the block decoder BD(0-3) and the open-circuit detection switch SW(0-3) via a line BLKSELn.

[0184] The open circuit detection circuit ODC is connected to a plurality of block decoders BD, including block decoder BD(0-3), via wiring PBUSBS. The open circuit detection circuit ODC is connected to a plurality of open circuit detection switches SW, including open circuit detection switch SW(0-3), via wiring BSNOD_SUP. The configurations of the block decoders BD(0-3), open circuit detection switch SW(0-3), and open circuit detection circuit ODC are equivalent to the configurations of the block decoders BD, open circuit detection switch SW, and open circuit detection circuit ODC in the second embodiment.

[0185] 3.2 Planar Layout Fig. 14 is a plan view showing an example of a planar layout of a row decoder according to the third embodiment, which corresponds to Fig. 12 in the second embodiment.

[0186] As shown in FIG. 14, the substrate SUB has regions R_XFERi, R_XFERo, and R_BD.

[0187] The region R_BD is a region where the block decoders BD are provided. The region R_BD is located on one of both ends of the substrate SUB in the X direction and extends in the Y direction. In the example of Fig. 14, the block decoders BD(x-x+3) corresponding to the blocks BLKx, BLK(x+1), BLK(x+2), and BLK(x+3) are arranged in the region R_BD.

[0188] The regions R_XFERi and R_XFERo are regions where the transfer switch XFER and the disconnection detection switch SW are provided. The region R_XFERo is located on one of both ends of the substrate SUB in the X direction, on which the region R_BD is not provided, and extends in the Y direction. The region R_XFERi is in contact with the region R_BD and extends in the Y direction.

[0189] The transfer switches XFERx and XFER(x+2) are arranged side by side in the Y direction in a region of the region R_XFERi that borders the block decoder BD(x-x+3). The transfer switches XFER(x+1) and XFER(x+3) are arranged side by side in the Y direction in a region of the region R_XFERo that is aligned with the block decoder BD(x-x+3) in the X direction.

[0190] The open circuit detection switch SW(x-x+3) is arranged in an area of ​​the region R_XFERo that is aligned with the transfer switches XFER(x+1) and XFER(x+3) in the X direction. The open circuit detection switch SW(x-x+3) and the block decoder BD(x-x+3) are arranged to sandwich the transfer switches XFERx, XFER(x+1), XFER(x+2), and XFER(x+3) in the X direction.

[0191] In this case, the main part of the wiring BLKSELn corresponding to the blocks BLKx, BLK(x+1), BLK(x+2), and BLK(x+3) extends between the block decoder BD(x-x+3) and the open circuit detection switch SW(x-x+3) so as to pass through the transfer switches XFERx, XFER(x+1), XFER(x+2), and XFER(x+3) without branching. That is, the main part of the wiring BLKSELn corresponding to the blocks BLKx, BLK(x+1), BLK(x+2), and BLK(x+3) in common runs from the block decoder BD(x-x+3) through the transfer switches XFERx and XFER(x+2) of the region R_XFERi in order, then through the transfer switches XFER(x+3) and XFER(x+1) of the region R_XFERo in order, and reaches the open circuit detection switch SW(x-x+3) of the region R_XFERo. Therefore, the main part of the wiring BLKSELn corresponding to the blocks BLKx, BLK(x+1), BLK(x+2), and BLK(x+3) in common has a portion extending in the X direction between the regions R_XFERi and R_XFERo. In the above-described planar layout, the main portion of the wiring BLKSELn has a length of, for example, about several thousand μm in order to sandwich the region having the memory cell array 10 between the region R_XFER0 and the region R_XFERi.

[0192] 3.3 Effects of the third embodiment According to the third embodiment, one block decoder BD and one disconnection detection switch SW collectively control four transfer switches XFER. In this configuration, the main portion of the wiring BLKSELn (i.e., the portion connecting the block decoder BD and the disconnection detection switch SW) includes a portion that extends in the X direction on the substrate SUB so as to pass above each of the corresponding four transfer switches XFER. This allows the control circuit CNT to detect the occurrence of a disconnection in the wiring BLKSELn, regardless of which transfer switch XFER the disconnection occurs above.

[0193] Additionally, if the portion of the wiring BLKSELn that passes above at least one of the four transfer switches XFER is not included in the main part (i.e., if the wiring BLKSELn is branched), even if a break occurs in the portion not included in the main part, the wiring BSNOD_SUP is connected to the wiring PBUSBS via the main part of the wiring BLKSELn. Therefore, the control circuit CNT cannot detect a break that occurs in the portion not included in the main part.

[0194] According to the third embodiment, the portions of the wiring BLKSELn that pass above the transfer switches XFER corresponding to the same block decoder BD are all included in the main portion of the wiring BLKSELn, so that the control circuit CNT can detect the occurrence of a break in the wiring BLKSELn, regardless of which transfer switch XFER the break occurs above.

[0195] 4. Fourth embodiment Next, a fourth embodiment will be described.

[0196] The fourth embodiment differs from the third embodiment in that the block decoders BD are arranged at both ends of the substrate SUB in the X direction. The following mainly describes the configuration and operation that differ from the third embodiment. Descriptions of the configuration and operation that are equivalent to those of the third embodiment will be omitted as appropriate.

[0197] 4.1 Row Decoder Module Fig. 15 is a circuit diagram showing an example of connections between a row decoder module and its peripheral circuits according to the fourth embodiment, which corresponds to Fig. 13 in the third embodiment.

[0198] As shown in FIG. 15, the row decoder module 15 includes a plurality of transfer switches XFER (XFER0, XFER1, XFER2, XFER3, ...), a plurality of block decoders BD (BD(0,2), BD(1,3) ...), a plurality of disconnection detection switches SW (SW(0,2), SW(1,3) ...), and a disconnection detection circuit ODC. The number of transfer switches XFER corresponds to the number of blocks BLK. The number of block decoders BD and disconnection detection switches SW corresponds to half the number of blocks BLK. In the example of FIG. 15, transfer switches XFER0, XFER1, XFER2, and XFER3 are shown as components corresponding to blocks BLK0, BLK1, BLK2, and BLK3, respectively. In addition, a block decoder BD(0,2) and a disconnection detection switch SW(0,2) are shown as components commonly corresponding to blocks BLK0 and BLK2. As components commonly corresponding to the blocks BLK1 and BLK3, a block decoder BD(1,3) and a disconnection detection switch SW(1,3) are shown.

[0199] The connections between the transfer switches XFER0 to XFER3 and the blocks BLK0 to BLK3 and the driver module 14 are the same as those in the third embodiment.

[0200] The gates of the transistors TR4a to TR16a are connected to the corresponding block decoders BD(0,2) via the wiring BLKSEL corresponding to the blocks BLK0 and BLK2, and the gates of the transistors TR21a to TR25a are connected to the block decoders BD(0,2) and the disconnection detection switch SW(0,2) via the wiring BLKSELn corresponding to the blocks BLK0 and BLK2.

[0201] The gates of the transistors TR4b to TR16b are connected to the corresponding block decoder BD(1,3) via the wiring BLKSEL corresponding to the blocks BLK1 and BLK3. The gates of the transistors TR21b to TR25b are connected to the block decoder BD(1,3) and the disconnection detection switch SW(1,3) via the wiring BLKSELn corresponding to the blocks BLK1 and BLK3.

[0202] The gates of the transistors TR4c to TR16c are connected to the corresponding block decoder BD(0,2) via the wiring BLKSEL corresponding to the blocks BLK0 and BLK2, and the gates of the transistors TR21c to TR25c are connected to the block decoder BD(0,2) and the open-circuit detection switch SW(0,2) via the wiring BLKSELn corresponding to the blocks BLK0 and BLK2.

[0203] The gates of the transistors TR4d to TR16d are connected to the corresponding block decoder BD(1,3) via the wiring BLKSEL corresponding to the blocks BLK1 and BLK3. The gates of the transistors TR21d to TR25d are connected to the block decoder BD(1,3) and the disconnection detection switch SW(1,3) via the wiring BLKSELn corresponding to the blocks BLK1 and BLK3.

[0204] The open circuit detection circuit ODC is connected to a plurality of block decoders BD, including block decoders BD(0,2) and BD(1,3), via wiring PBUSBS. The open circuit detection circuit ODC is connected to a plurality of open circuit detection switches SW, including open circuit detection switches SW(0,2) and SW(1,3), via wiring BSNOD_SUP. The configurations of the block decoders BD(0,2) and BD(1,3) are equivalent to the configuration of the block decoder BD(0-3) in the third embodiment. The configurations of the open circuit detection switches SW(0,2) and SW(1,3) are equivalent to the configuration of the open circuit detection switches SW(0-3) in the third embodiment.

[0205] 4.2 Planar Layout Fig. 16 is a plan view showing an example of a planar layout of a row decoder according to the fourth embodiment, which corresponds to Fig. 14 in the third embodiment.

[0206] As shown in FIG. 16, the substrate SUB has regions R_XFERi, R_XFERo, R_BDi, and R_BDo.

[0207] Regions R_BDi and R_BDo are regions where block decoders BD and disconnection detection switches SW are provided. Regions R_BDi and R_BDo are located at both ends of the substrate SUB in the X direction, and extend in the Y direction. In the example of FIG. 16, block decoders BD(x, x+2) and disconnection detection switches SW(x, x+2) corresponding to blocks BLKx and BLK(x+2) are arranged in region R_BDi so as to line up in the Y direction. Furthermore, block decoders BD(x+1, x+3) and disconnection detection switches SW(x, x+2) corresponding to blocks BLK(x+1) and BLK(x+3) are arranged in region R_BDo so as to line up in the Y direction.

[0208] The regions R_XFERi and R_XFERo are regions where the transfer switches XFER are provided. The region R_XFERi is in contact with the region R_BDi and extends in the Y direction. The region R_XFERo is in contact with the region R_BDo and extends in the Y direction.

[0209] The transfer switches XFERx and XFER(x+2) are arranged side by side in the Y direction in a region of the region R_XFERi that contacts the block decoder BD(x, x+2) and the disconnection detection switch SW(x, x+2). The transfer switches XFER(x+1) and XFER(x+3) are arranged side by side in the Y direction in a region of the region R_XFERo that contacts the block decoder BD(x+1, x+3) and the disconnection detection switch SW(x+1, x+3).

[0210] In this case, the main portion of the wiring BLKSELn corresponding to both the blocks BLKx and BLK(x+2) extends between the block decoder BD(x, x+2) and the disconnection detection switch SW(x, x+2) so as to pass through the transfer switches XFERx and XFER(x+2) without branching. That is, the main portion of the wiring BLKSELn corresponding to both the blocks BLKx and BLK(x+2) extends from the block decoder BD(x, x+2) of the region R_BDi, passes through the transfer switches XFERx and XFER(x+2) of the region R_XFERi in order, and then reaches the disconnection detection switch SW(x, x+2) of the region R_BDi. Therefore, the main portion of the wiring BLKSELn corresponding to both the blocks BLKx and BLK(x+2) has a portion that extends so as to turn back in the X direction between the regions R_BDi and R_XFERi.

[0211] Similarly, the main part of the wiring BLKSELn corresponding to both the blocks BLK(x+1) and BLK(x+3) extends between the block decoder BD(x+1, x+3) and the disconnection detection switch SW(x+1, x+3) so as to pass through the transfer switches XFER(x+1) and XFER(x+3) without branching. That is, the main part of the wiring BLKSELn corresponding to both the blocks BLK(x+1) and BLK(x+3) extends from the block decoder BD(x+1, x+3) in the region R_BDo, passes through the transfer switches XFER(x+1) and XFER(x+3) in the region R_XFERo in order, and then reaches the disconnection detection switch SW(x+1, x+3) in the region R_BDo. Therefore, the main portion of the wiring BLKSELn corresponding to both the blocks BLK(x+1) and BLK(x+3) has a portion that extends so as to turn back in the X direction between the regions R_BDo and R_XFERo.

[0212] 4.3 Effects of the Fourth Embodiment According to the fourth embodiment, one block decoder BD and one open-circuit detection switch SW collectively control two transfer switches XFER arranged in the Y direction. The open-circuit detection switch SW is arranged on the same side as the block decoder BD with respect to the two corresponding transfer switches XFER in the X direction. The main portion of the wiring BLKSELn (i.e., the portion connecting the block decoder BD and the open-circuit detection switch SW) includes a portion extending in the X direction on the substrate SUB so as to pass above the two corresponding transfer switches XFER. That is, the main portion of the wiring BLKSELn has a shape in which a portion passing above one of the two transfer switches XFER in the X direction and a portion passing above the other transfer switch XFER in the X direction are arranged in the Y direction. Even with this configuration, as in the third embodiment, the control circuit CNT can detect the occurrence of an open circuit in the wiring BLKSELn, regardless of which transfer switch XFER an open circuit occurs above.

[0213] 5. Modifications, etc. The first to fourth embodiments are not limited to the above examples, and various modifications can be applied.

[0214] In the above-described first to fourth embodiments, the case has been described in which the gate of the transistor T22 between the line BLKSELn and the transistor T23 in the disconnection detection switch SW is connected to the node RDEC_SEL, but the present invention is not limited to this.

[0215] 17 is a circuit diagram showing an example of a circuit configuration of a row decoder module according to a first modification. As shown in FIG. 17, the open circuit detection switch SW may include a transistor T24 instead of the transistor T22. The transistor T24 is a high-voltage N-type transistor. The transistor T24 has a first terminal connected to the other end of the line BLKSELn, a second terminal connected to the first terminal of the transistor T23, and a gate connected to the line BLKSELn.

[0216] The wiring BLKSEL is a wiring that extends in the X direction in the region R_XFER regardless of the presence or absence of the transistor T24. Therefore, according to the first modification, by providing the transistor T24, the additional extension length of the wiring connected to the gate of the transistor T24 can be reduced compared to the case where the wiring is connected to the node RDEC_SEL.

[0217] In the first to fourth embodiments described above, the block decoder BD includes a bad block latch that stores the state of the block BLK, but this is not limiting. The block decoder BD does not necessarily have to include a bad block latch.

[0218] 18 is a circuit diagram showing an example of the circuit configuration of a row decoder module according to the second modification. As shown in FIG. 18, the block decoder BD does not need to include transistors T9, T10, T11, T12, and T13 corresponding to the bad block latch, and inverters INV2 and INV3. In this case, the voltage supply to nodes ROMBAEN, RFSET, and RFRST can be omitted in the first to third examples of the open-circuit detection operation described with reference to FIGS. 6 to 8, respectively. This allows for effects equivalent to those of the first to fourth embodiments described above.

[0219] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents as defined in the claims. [Explanation of symbols]

[0220] 1. Memory system 2...Memory controller 3...Memory device 10...Memory cell array 11...Command register 12...Address register 13...Sequencer 14...Driver module 15...Row decoder module 16...Sense amplifier module Row decoder...RD Block decoder...BD Transfer switch…XFER Disconnection detection switch...SW Open circuit detection circuit (ODC)

Claims

1. a first block including a first memory string having a first transistor at an end thereof; a second transistor having a first end connected to the gate of the first transistor; a first wiring connected to the gate of the second transistor; a block decoder connected to one end of the first wiring; a third transistor having a first end connected to the other end of the first wiring; a power supply connected to the second end of the third transistor; A memory device comprising:

2. the block decoder and the third transistor are arranged on a substrate in a first direction with the second transistor; a main portion of the first wiring that connects the block decoder and the third transistor includes a portion that passes above the second transistor on the substrate in the first direction; The memory device of claim 1 .

3. the block decoder and the third transistor are arranged to sandwich the second transistor in a first direction; The memory device of claim 2 .

4. the block decoder and the third transistor are adjacent to the second transistor in the first direction; The memory device of claim 3.

5. the block decoder is spaced apart from the second transistor in a second direction intersecting the first direction; the main portion of the first wiring further includes a portion extending in the second direction between the block decoder and the second transistor; The memory device of claim 3.

6. a second block including a second memory string having a fourth transistor at an end thereof; a fifth transistor having a first terminal connected to the gate of the fourth transistor and a gate connected to the first wiring; Further provided with the second transistor and the fifth transistor are arranged on the substrate in a second direction intersecting the first direction, the main portion of the first wiring further includes a portion extending in the first direction so as to pass above the fifth transistor; The memory device of claim 2 .

7. the block decoder is adjacent to the second transistor and the fifth transistor in the first direction; the third transistor is spaced apart from the second transistor and the fifth transistor in the first direction; The memory device of claim 6.

8. the block decoder is spaced apart from the second transistor and the fifth transistor in the first direction; the third transistor is adjacent to the second transistor and the fifth transistor in the first direction; The memory device of claim 6.

9. the third transistor is arranged on the same side as the block decoder with respect to the second transistor and the fifth transistor in the first direction; The memory device of claim 6.

10. The block decoder a sixth transistor and a seventh transistor each having a first end connected to the one end of the first wiring and having mutually different conductivity types; an eighth transistor having a first terminal connected to the second terminal of the sixth transistor and a second terminal to which a first voltage is supplied; a ninth transistor having a first terminal connected to the second terminal of the seventh transistor; Including, a gate of the third transistor, a gate of the eighth transistor, and a gate of the ninth transistor are connected to a second wiring; The memory device of claim 1 .

11. a tenth transistor provided between the other end of the first wiring and the first end of the third transistor, a gate of the sixth transistor, a gate of the seventh transistor, and a gate of the tenth transistor are connected to a third wiring; The memory device of claim 10.

12. an eleventh transistor having a first end connected to the other end of the first wiring, a second end connected to the first end of the third transistor, and a gate connected to a fourth wiring; the block decoder includes a level shifter having an input terminal connected to the gate of the sixth transistor and the gate of the seventh transistor, and an output terminal connected to the fourth wiring; The memory device of claim 10.

13. a control circuit connected to a second terminal of the ninth transistor via a fifth wiring; The control circuit is configured to determine whether or not there is a break in the first wiring based on the voltage of the fifth wiring. The memory device of claim 10.

14. In an operation in which the power supply supplies a second voltage lower than the first voltage, the control circuit is configured to determine that there is no disconnection in the first wiring when the voltage of the fifth wiring drops from the first voltage to approach the second voltage; The memory device of claim 13.

15. In operation, the power supply supplies the first voltage, the control circuit is configured to determine that there is no disconnection in the first wiring when the voltage of the fifth wiring rises from a second voltage lower than the first voltage to approach the first voltage; The memory device of claim 13.

16. a pad connected to a second terminal of the ninth transistor via a fifth wiring; The memory device of claim 10.

17. the first memory string further includes a memory cell transistor having a gate connected to a word line; The first transistor connects the memory cell transistor and a bit line at the end of the first memory string. The memory device of claim 1 .

18. a twelfth transistor having a gate connected to the first wiring, the first memory string further includes a thirteenth transistor having a gate connected to the twelfth transistor and connecting between the memory cell transistor and a source line at an end opposite to the first transistor; 20. The memory device of claim 17.

19. The block decoder When the first block is selected, the second transistor is turned off via the first wiring; When the first block is not selected, the second transistor is turned on via the first wiring. It was configured as follows: The memory device of claim 1 .

20. a first block including a first memory string, wherein the first memory string has a memory cell transistor having a gate connected to a word line, and a first transistor connected between the memory cell transistor and a bit line and provided at an end of the first memory string; a second transistor having a first end connected to the gate of the first transistor; a first wiring connected to the gate of the second transistor; a block decoder connected to one end of the first wiring; a third transistor having a first end connected to the other end of the first wiring; a power supply connected to a second end of the third transistor and configured to supply a voltage to the first wiring from the other end; Equipped with The block decoder When the first block is selected, the second transistor is turned off via the first wiring; When the first block is not selected, the second transistor is turned on via the first wiring.

1. A memory device configured to:

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