Manufacturing method of semiconductor device

Abstract

To provide a manufacturing method of a semiconductor device that can suppress voids in an embedded portion.SOLUTION: A manufacturing method of a semiconductor device includes a preparation step of preparing a substrate 2 on which a first semiconductor chip 3 is mounted and a semiconductor chip 31 with an adhesive layer in which an adhesive layer 24 is laminated on a second semiconductor chip 4, and a formation step of thermocompression-bonding the semiconductor chip 31 with an adhesive layer to the substrate 2 with the adhesive layer 24 facing the substrate 2, thereby forming an embedding portion 5 in which the first semiconductor chip 3 is embedded between the substrate 2 and the second semiconductor chip 4, and in the formation step, a contact region R of the adhesive layer 24 that abuts against the first semiconductor chip is partially heated before the compression bonding.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] In recent years, stacked MCPs (Multi Chip Packages), which have high capacity due to semiconductor chips stacked in multiple stages, have become widespread. An example of a stacked MCP is a chip-embedded semiconductor package. A semiconductor package structure in which semiconductor chips are embedded in an adhesive film is called FOD (Film Over Die). One example of a semiconductor package that employs FOD is one in which a controller chip arranged on one surface of a substrate is embedded between the substrate and a memory chip by an embedding section using an adhesive film (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-175459 Summary of the Invention [Problem to be solved by the invention]

[0004] In the manufacturing of semiconductor packages with an FOD structure, it is required that the semiconductor chip is sufficiently embedded in the embedding section using an adhesive film (embedding). Regarding embedding, it is important to achieve both embedding and void suppression. Voids are a phenomenon in which air gaps occur in the embedding section between the substrate and the memory chip. If voids occur in the embedding section, it is thought that this will affect the reliability of the semiconductor package.

[0005] The present disclosure has been made to solve the above-mentioned problems, and has an object to provide a method for manufacturing a semiconductor device that can suppress voids in the buried portion. [Means for solving the problem]

[0006] The gist of the present disclosure is as follows.

[0007] [1] A method for manufacturing a semiconductor device, comprising: a preparation step of preparing a substrate on which a first semiconductor chip is mounted and a semiconductor chip with an adhesive layer in which an adhesive layer is laminated on a second semiconductor chip; and a formation step of thermocompression-bonding the semiconductor chip with the adhesive layer to the substrate with the adhesive layer facing the substrate, and forming an embedding portion in which the first semiconductor chip is embedded between the substrate and the second semiconductor chip, wherein in the formation step, a contact area of ​​the adhesive layer that abuts against the first semiconductor chip is partially heated before the bonding.

[0008] In this semiconductor device manufacturing method, in the process of forming the embedded portion, the contact area of ​​the adhesive layer that contacts the first semiconductor chip on the substrate is partially heated before compression bonding. By partially heating the adhesive layer before compression bonding, the adhesive layer may flow and deform due to load near the contact area during subsequent compression bonding. Therefore, this semiconductor device manufacturing method eliminates residual air around the first semiconductor chip and suppresses voids in the embedded portion.

[0009] [2] The method for manufacturing a semiconductor device according to [1], wherein the forming step includes heating the first semiconductor chip together with the substrate, bringing the contact area into contact with the first semiconductor chip and maintaining this contact for a predetermined time, and then compressing the semiconductor chip with the adhesive layer to the substrate. In this case, the amount of heat input to the adhesive layer can be controlled by adjusting the heating temperature of the first semiconductor chip and the contact time between the first semiconductor chip and the contact area. Therefore, partial heating of the adhesive layer can be easily performed.

[0010] [3] In the method for manufacturing a semiconductor device according to [1], in the forming step, the contact area is heated by irradiating a laser beam, and then the semiconductor chip with the adhesive layer is pressure-bonded to the substrate. In this case, the amount of heat input to the adhesive layer and the heated area can be controlled by the irradiation conditions of the laser beam. Therefore, partial heating of the adhesive layer can be easily performed. [Effects of the Invention]

[0011] According to the present disclosure, voids in the embedded portion can be suppressed. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a schematic cross-sectional view showing an example of a semiconductor package. [Figure 2] FIG. 1 is a schematic plan view showing an example of a laminated film. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. [Figure 4] 1A is a schematic cross-sectional view showing the bonding step, FIG. 1B is a schematic cross-sectional view showing the dicing step, and FIG. 1C is a schematic cross-sectional view showing the irradiation step. [Figure 5] FIG. 1(a) is a schematic cross-sectional view showing a pick-up step, and FIG. 1(b) is a schematic cross-sectional view showing a die-attach step. [Figure 6] FIG. 2 is a schematic cross-sectional view showing a void. [Figure 7] 1A and 1B are schematic cross-sectional views showing how voids are generated in a conventional method. [Figure 8] 1A and 1B are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to the present embodiment. [Figure 9] 10(a) and 10(b) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, a preferred embodiment of a method for manufacturing a semiconductor device according to one aspect of the present disclosure will be described in detail with reference to the drawings.

[0014] In the following description, the components (including steps, etc.) are not essential unless otherwise specified. The sizes of the components in each drawing are conceptual, and the relative relationships of the sizes between the components are not limited to those shown in each drawing. The exemplified numerical values ​​and their ranges do not limit the present disclosure.

[0015] In the following description, a numerical range indicated using "to" indicates a range that includes the numerical values ​​before and after "to" as the minimum and maximum values, respectively. Furthermore, in a numerical range that is stated in stages, the upper or lower limit value stated in one numerical range may be replaced with the upper or lower limit value of another numerical range that is stated in stages. The upper or lower limit value of a numerical range may be replaced with a value shown in the examples.

[0016] First, a semiconductor device manufactured using the semiconductor device manufacturing method according to this embodiment will be exemplified.

[0017] FIG. 1 is a schematic cross-sectional view showing an example of a semiconductor package. Here, a semiconductor device such as a NAND flash memory is shown as an example of the semiconductor package (semiconductor device) 1. As shown in FIG. 1, the semiconductor package 1 includes a substrate 2, a first semiconductor chip (semiconductor chip) 3, a second semiconductor chip (semiconductor chip) 4, an embedded portion 5, and a sealing portion 6. The substrate 2 is, for example, an organic substrate. It may also be a metal substrate such as a lead frame. Predetermined circuit patterns 7 and 8 are formed on one surface of the substrate 2.

[0018] The first semiconductor chip 3 is, for example, a controller chip. The first semiconductor chip 3 is electrically connected to a circuit pattern 7 via an adhesive layer 9. The first semiconductor chip 3 is electrically connected to a circuit pattern 8 via a first wire 10. The second semiconductor chip 4 is, for example, a memory chip. The second semiconductor chip 4 is disposed on one surface of the substrate 2 at a fixed distance from the first semiconductor chip 3. The second semiconductor chip 4 is electrically connected to the circuit pattern 8 via a second wire 11.

[0019] Between the second semiconductor chip 4 and the substrate 2, there is provided an embedded portion 5 formed by an adhesive layer 24 of a laminated film 21 described below. The first semiconductor chip 3, the circuit pattern 7, and the first wire 10 are each embedded by the embedded portion 5 between the second semiconductor chip 4 and the substrate 2. The first semiconductor chip 3, the second semiconductor chip 4, the first wire 10, and the second wire 11 are sealed on one surface of the substrate 2 by a sealing portion 6 that is outer than the embedded portion 5.

[0020] Next, examples of laminated films that can be used in the above-described method for manufacturing a semiconductor device will be described.

[0021] Fig. 2 is a schematic plan view showing an example of a laminated film. Fig. 3 is a cross-sectional view taken along line III-III in Fig. 2. The laminated film 21 shown in Figs. 2 and 3 is a long film used in the manufacturing process of the semiconductor package 1 described above, for example, to fix a semiconductor wafer in a dicing process and to form the embedded portion 5 in a die-attach process. The laminated film 21 is generally stored in a rolled state, and is unwound from the roll in the amount required for use.

[0022] 2 and 3, the laminate film 21 has a long base film 22 and label portions 23 provided on one surface of the base film 22 at predetermined intervals in the extending direction of the base film 22. The label portions 23 are composed of an adhesive layer 24 that overlaps the base film 22, a pressure-sensitive adhesive layer 25 that overlaps the adhesive layer 24, and a base layer 27 that overlaps the pressure-sensitive adhesive layer 25. The label portions 23 have, for example, a circular shape in a plan view.

[0023] The base film 22 is, for example, a resin film. Examples of resin materials constituting the base film 22 include polytetrafluoroethylene, polyethylene, polypropylene, polymethylpentene, polyethylene terephthalate, and polyimide. The thickness of the base film 22 may be, for example, 10 to 200 μm, or 30 to 170 μm. The surface of the base film 22 may be subjected to a release treatment using silicone or the like.

[0024] The adhesive layer 24 is, for example, a film-like portion called a die attach film. Examples of materials constituting the adhesive layer 24 include resins having electrical insulation properties. The resin constituting the adhesive layer 24 may be a thermosetting resin that hardens when heated. The adhesive layer 24 may be made of a single or multiple thermosetting resins, or a combination of a thermosetting resin and a thermoplastic resin, and may have a resin composition that is melted by a first heat and then hardened by a second heat. The first heat may be 70°C to 150°C, and the second heat may be 100°C to 200°C.

[0025] Examples of thermosetting resins include epoxy resins, bismaleimide resins, triazine resins, phenolic resins, unsaturated polyester resins, melamine resins, urea resins, polyisocyanate resins, furan resins, resorcinol resins, benzoguanamine resins, diallyl phthalate resins, silicone resins, siloxane-modified epoxy resins, cyanoacrylate resins, xylene resins, and acrylate resins. Examples of thermoplastic resins include polyimide resins, polyamide resins, polyurethane resins, polyvinyl butyral resins, and siloxane-modified polyamideimide resins. These can be used alone or in combination. The adhesive layer 24 may contain acrylic rubber.

[0026] The adhesive layer 25 and the base layer 27 are, for example, a film-like portion called a dicing tape. The adhesive layer 25 may be a single layer or multiple layers. The adhesive layer 25 preferably has adhesive strength at room temperature and sufficient adhesion to an adherend. The adhesive layer 25 preferably has the property of being cured (i.e., its adhesive strength is reduced) by high-energy rays such as radiation or heat. More preferably, the adhesive layer 25 is easily peelable from the base film 22 and the adhesive layer 24 without the application of high-energy rays such as radiation or heat. The adhesive layer 25 may be a pressure-sensitive adhesive layer. The adhesive layer 25 can be formed using, for example, an acrylic resin, various synthetic rubbers, natural rubber, or a polyimide resin. The base layer 27 is formed from, for example, a resin such as polyolefin, polypropylene, or ionomer. The thickness of the adhesive layer 25 including the base layer 27 may be, for example, 10 μm to 200 μm, or 20 μm to 150 μm.

[0027] 2 and 3, in the label part 23, the adhesive layer 25 and the base material layer 27 have an annular protruding portion P that protrudes outward beyond the edge of the adhesive layer 24. The protruding portion P overlaps one surface of the base material film 22. As a result, the adhesive layer 24 on one surface of the base material film 22 is covered by the adhesive layers 25 and 27.

[0028] In this embodiment, a protective portion 26 is provided to surround the periphery of the label portion 23. The protective portion 26 protects the label portion 23 from pressure when the laminate film 21 is wound into a roll. The protective portions 26 are arranged symmetrically in the width direction at both edge portions in the width direction of one surface of the base film 22, and extend in the extension direction of the base film 22. In this embodiment, the protective portion 26 is composed of an adhesive layer 25 and a base layer 27. The label portion 23 and the protective portion 26 are formed by laminating the adhesive layer 25 and the base layer 27 so as to cover the adhesive layer 24 on one surface of the base film 22, pre-cutting the adhesive layer 25 and the base layer 27 in a predetermined pattern, and peeling off the unnecessary portions from one surface of the base film 22.

[0029] Next, a method for manufacturing the semiconductor package 1 will be described.

[0030] The method for manufacturing the semiconductor package 1 of this embodiment includes a bonding step, a dicing step, an irradiation step, a pick-up step, and a die-attach step. The bonding step is a step of bonding the adhesive layer 24, the pressure-sensitive adhesive layer 25, and the base material layer 27 to the semiconductor wafer W. In the bonding step, as shown in FIG. 4(a), the label portion 23 is attached to one side of the semiconductor wafer W so that the adhesive layer 24 faces the semiconductor wafer W, and then the base material film 22 is peeled off from the label portion 23. In the bonding step, the peripheral edge of the pressure-sensitive adhesive layer 25 is fixed to a ring frame (not shown), and the semiconductor wafer W is supported inside the ring frame.

[0031] The dicing process is a process of dicing the semiconductor wafer W to form semiconductor chips 31 with adhesive layers. In the dicing process, a cutting means such as a blade or laser light is used to cut the semiconductor wafer W together with the adhesive layer 24 in a predetermined pattern (e.g., a grid pattern), as shown in FIG. 4(b). As a result, a plurality of semiconductor chips 31 with adhesive layers are formed on the adhesive layer 25. The chip portion 32 of the semiconductor chip 31 with adhesive layers becomes the above-mentioned second semiconductor chip 4 in the semiconductor package 1 to be manufactured. When cutting the semiconductor wafer W and the adhesive layer 24, by drawing a cutting line that reaches the adhesive layer 25, adjacent semiconductor chips 31 with adhesive layers can be more reliably separated from each other.

[0032] The irradiation process is a process of irradiating the adhesive layer 25 with light to harden it. In the irradiation process, as shown in FIG. 4(c), ultraviolet light V is irradiated onto the adhesive layer 25 to reduce the adhesive strength of the adhesive layer 25. The pick-up process is a process of picking up the semiconductor chip 31 with the adhesive layer from the adhesive layer 25. In the pick-up process, a pick-up means such as a collet C is used to pick up the semiconductor chip 31 with the adhesive layer from the adhesive layer 25 whose adhesive strength has been reduced, as shown in FIG. 5(a).

[0033] The die-attach process is a process of placing the semiconductor chip 31 with an adhesive layer on the substrate 2. In the example of FIG. 5(b), the first semiconductor chip 3 is electrically connected to the circuit pattern 7 of the substrate 2 via the adhesive layer 9, and the first semiconductor chip 3 is electrically connected to the circuit pattern 8 via the first wire 10. In this state, the semiconductor chip 31 with the adhesive layer is thermocompression-bonded with the adhesive layer 24 facing the substrate 2. As a result, embedded portions 5 are formed between the second semiconductor chip 4 and the substrate 2, in which the first semiconductor chip 3, the circuit pattern 7, and the first wire 10 are embedded.

[0034] Thereafter, the second semiconductor chip 4 is electrically connected to the circuit pattern 8 by the second wire 11, and the first semiconductor chip 3, the second semiconductor chip 4, the first wire 10, and the second wire 11 are sealed with the sealing portion 6, thereby obtaining the semiconductor package 1 shown in FIG. 1. The sealing portion 6 can be formed by, for example, injection molding using a mold. After the sealing portion 6 is formed, the sealing portion 6 may be further heated to promote curing of the sealing portion 6. In this case, the heating temperature may be 165°C to 185°C. The heating time may be 0.5 hours to 8 hours.

[0035] In manufacturing the semiconductor package 1 as described above, it is required that the first semiconductor chip 3 is sufficiently embedded (embeddability) in the embedding portion 5 using the adhesive layer 24 in the die-attach process. With regard to embeddability, suppression of voids is important. FIG. 6 is a schematic cross-sectional view showing voids. For simplicity of explanation, the circuit pattern on the substrate 102, the adhesive layer between the substrate 102 and the first semiconductor chip 103, and the wires are omitted from FIG. 6 (the same applies to FIGS. 7 to 9 described later).

[0036] 6, a void is a phenomenon in which a gap G occurs in the embedded portion 105 between the substrate 102 and the second semiconductor chip 104. When a void occurs, there is a risk of a decrease in reliability due to poor embedding of the first semiconductor chip 103, and further, a phenomenon in which the embedded portion 105 bulges together with the second semiconductor chip 104 in a convex shape (bowing) depending on the volume of the gap G may occur.

[0037] 7(a) and 7(b) are schematic cross-sectional views showing how voids are generated in a conventional method. As shown in FIG. 7(a), in the conventional method, first, a substrate 102 on which a first semiconductor chip 103 is mounted and a semiconductor chip 131 with an adhesive layer, in which an adhesive layer 124 is laminated on a second semiconductor chip 104, are prepared. Next, the substrate 102 is heated to the melting temperature of the resin that makes up the adhesive layer 124. By heating the substrate 102, the first semiconductor chip 103 on the substrate 102 is also heated to a similar temperature.

[0038] After heating the substrate 102 and the first semiconductor chip 103, the semiconductor chip 131 with the adhesive layer is thermocompression bonded to the substrate 102 using a collet C with the adhesive layer 124 facing the substrate 102, thereby forming an embedding portion 105 for embedding the first semiconductor chip 103 between the substrate 102 and the second semiconductor chip 104. A constant load is applied by the collet C to the semiconductor chip 131 with the adhesive layer, for example, in the range of 15N to 45N. The total time for thermocompression bonding is, for example, about 1 second to 3 seconds, and is set to 2 seconds here.

[0039] In the initial stage of thermocompression bonding, adhesive layer 124 comes into contact with first semiconductor chip 103 and is pressed into it, which causes deformation of adhesive layer 124 so that the portion in contact with first semiconductor chip 103 becomes concave, as shown in Fig. 7(a). At this time, only the surface of adhesive layer 124 that comes into contact with first semiconductor chip 103 is heated. For this reason, deformation of adhesive layer 124 occurs earlier than the entire adhesive layer 124 melts, and adhesive layer 124 deforms as an elastic body while maintaining its film shape.

[0040] 7B, the adhesive layer 124 begins to deform, and the edge of the adhesive layer 124 comes into contact with the substrate 102. As a result, the adhesive layer 124 is heated by both the first semiconductor chip 103 and the substrate 102. However, at this point, the adhesive layer 124 is still deformed as an elastic body, and therefore, a gap G may be formed around the first semiconductor chip 103.

[0041] For example, after 0.1 seconds from when adhesive layer 124 comes into contact with first semiconductor chip 103, adhesive layer 124 melts entirely due to heat from both first semiconductor chip 103 and substrate 102, and flows due to its own weight and the load from collet C. However, the flow of adhesive layer 124 around first semiconductor chip 103 is likely to be insufficient, leaving gaps G around first semiconductor chip 103, which can result in voids in embedded portion 105 that is finally formed (see FIG. 6).

[0042] To address this issue, the manufacturing method of the semiconductor device according to this embodiment aims to suppress voids in the embedded portion 5 by partially heating the contact area R of the adhesive layer 24 that contacts the first semiconductor chip 3 before pressure bonding.

[0043] 8(a) and 8(b) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to this embodiment. As shown in FIG. 8(a), in this embodiment, first, a substrate 2 on which a first semiconductor chip 3 is mounted and a semiconductor chip 31 with an adhesive layer, in which an adhesive layer 24 is laminated on a second semiconductor chip 4, are prepared (preparation step). Next, the substrate 2 is heated to about 120°C. By heating the substrate 2, the first semiconductor chip 3 on the substrate 2 is also heated to a similar temperature.

[0044] After heating the substrate 2 and the first semiconductor chip 3, a collet C is used to thermocompress the semiconductor chip 31 with the adhesive layer to the substrate 2 with the adhesive layer 24 facing the substrate 2, thereby forming an embedding portion 5 for embedding the first semiconductor chip 3 between the substrate 2 and the second semiconductor chip 4 (forming step). A constant load is applied by the collet C to the semiconductor chip 31 with the adhesive layer, for example, in the range of 15N to 45N. The total time for thermocompression bonding is, for example, about 1 to 3 seconds, and is set to 2 seconds here.

[0045] In this embodiment, when thermocompression bonding the semiconductor chip 31 with the adhesive layer to the substrate 2, as shown in FIG. 8( a), the contact region R of the adhesive layer 24 is brought into contact with the first semiconductor chip 3 and held there for a predetermined time. At this time, no load is applied to the adhesive layer 24 from the collet C, and the adhesive layer 24 is partially melted by heat from the first semiconductor chip 3, including in the thickness direction of the adhesive layer 24, centered on the contact region R that contacts the first semiconductor chip 3. The time during which the contact region R of the adhesive layer 24 is held in contact with the first semiconductor chip 3 is set according to the physical properties of the resin material constituting the adhesive layer 24, and is set to a time sufficient to soften the portion centered on the contact region R. The time during which the contact region R of the adhesive layer 24 is held in contact with the first semiconductor chip 3 can be, for example, approximately 0.1 seconds or more.

[0046] After the adhesive layer 24 is partially melted around the contact region R, as shown in FIG. 8(b), a load is applied to the semiconductor chip 31 with the adhesive layer by a collet C, and the adhesive layer 24 is pressed onto the substrate 2 and the first semiconductor chip 3. The pressing time is set according to the physical properties of the resin material constituting the adhesive layer 24 and is set to a time sufficient for the portion centered around the contact region R to flow. At the beginning of pressing, only the portion of the adhesive layer 24 that is partially melted around the contact region R flows due to its own weight and the load from the collet C. This causes the adhesive layer 24 to flow sufficiently around the first semiconductor chip 3, filling the periphery of the first semiconductor chip 3 with the adhesive layer 24 without any gaps. Therefore, voids are suppressed in the embedded portion 5 that will ultimately be formed.

[0047] As described above, in this semiconductor device manufacturing method, in the step of forming the embedded portion 5, the contact region R of the adhesive layer 24 that contacts the first semiconductor chip 3 on the substrate 2 is partially heated before compression bonding. By partially heating the adhesive layer 24 before compression bonding, the adhesive layer 24 may flow and deform due to the load near the contact region R of the adhesive layer 24 during the subsequent compression bonding. Therefore, in this semiconductor device manufacturing method, residual air around the first semiconductor chip 3 is eliminated, and voids in the embedded portion 5 can be suppressed.

[0048] Furthermore, in this semiconductor device manufacturing method, the contact region R of the adhesive layer 24 is partially heated before compression bonding, and as a result, the adhesive layer 24 flows only in the partially melted portion centered on the contact region R due to its own weight and the load from the collet C. After that, other portions of the adhesive layer 24 also melt due to heat from the substrate 2 and the first semiconductor chip 3, but compared to conventional methods in which the entire adhesive layer 124 is melted at once, spreading of the adhesive layer 24 in the in-plane direction of the substrate 2 during compression bonding can be suppressed. Therefore, in addition to suppressing voids, this semiconductor device manufacturing method also suppresses bleeding (a phenomenon in which the embedded portion 5 protrudes from between the substrate 2 and the second semiconductor chip 4).

[0049] In this embodiment, the first semiconductor chip 3 is heated together with the substrate 2, the contact region R of the adhesive layer 24 is brought into contact with the first semiconductor chip 3 and held for a predetermined time, and then the semiconductor chip 31 with the adhesive layer is pressure-bonded to the substrate 2. This method allows the amount of heat input to the adhesive layer 24 to be controlled by the heating temperature of the first semiconductor chip 3 and the contact time between the first semiconductor chip 3 and the contact region R. Therefore, partial heating of the adhesive layer 24 can be easily performed.

[0050] The present disclosure is not limited to the above-described embodiment. For example, in the above-described embodiment, the vicinity of the contact region R of the adhesive layer 24 is partially heated by contacting the contact region R with the first semiconductor chip 3 and maintaining the contact for a predetermined time. However, partial heating of the vicinity of the contact region R may be performed by other methods. For example, as shown in FIGS. 9(a) and 9(b), the contact region R may be heated by irradiating it with laser light L, and then the semiconductor chip 31 with the adhesive layer may be pressure-bonded to the substrate 2. In this example, as shown in FIG. 9(a), the contact region R of the adhesive layer 24 of the semiconductor chip 31 with the adhesive layer held by the collet C is irradiated with laser light L to partially melt the adhesive layer 24 centered around the contact region R. The laser light L may be irradiated at one or more points in the contact region R, or may be scanned in the in-plane direction of the surface of the adhesive layer 24 in the contact region R. The irradiation position of the laser light L may be outside and surrounding the contact region R.

[0051] After partially melting the adhesive layer 24 around the contact region R, as shown in Fig. 9(b), a load is applied to the semiconductor chip 31 with the adhesive layer by the collet C, and the adhesive layer 24 is pressed against the substrate 2 and the first semiconductor chip 3. As a result, flow occurs only in the partially melted portion around the contact region R due to its own weight and the load from the collet C. Therefore, sufficient flow of the adhesive layer 24 occurs around the first semiconductor chip 3, and the periphery of the first semiconductor chip 3 is filled with the adhesive layer 24 without any gaps.

[0052] In this method, as in the above embodiment, sufficient flow of the adhesive layer 24 occurs around the first semiconductor chip 3, and the adhesive layer 24 fills the periphery of the first semiconductor chip 3 without leaving any gaps. Therefore, voids in the finally formed embedded portion 5 are suppressed. Furthermore, since the adhesive layer 24 can be suppressed from spreading in the in-plane direction of the substrate 2 during pressure bonding, not only voids but also bleeding can be suppressed. Furthermore, the amount of heat input to the adhesive layer 24 and the heated area can be controlled by the irradiation conditions of the laser light L. Therefore, partial heating of the adhesive layer 24 can be easily performed.

[0053] Furthermore, in each of the above embodiments, from the viewpoint of more reliably causing the adhesive layer 24 to flow only in the part that is partially melted around the contact region R during pressure bonding, a method may be adopted in which the temperature of the area of ​​the adhesive layer 24 other than the contact region R is not increased or the area other than the contact region R is cooled. For example, the formation process for forming the embedded portion 5 may be performed at a temperature lower than room temperature (20°C), and gas at a temperature lower than room temperature may be blown from the side of the semiconductor chip 31 with the adhesive layer during the formation process.

[0054] From the same viewpoint, the size of the support surface of the collet C may be made slightly smaller than the size of the semiconductor chip 31 with the adhesive layer. In this case, the load applied to the partially melted portion centered on the contact region R can be made larger than the load applied to the outer portion. This makes it possible to more reliably cause the adhesive layer 24 to flow only in the partially melted portion centered on the contact region R during pressure bonding.

[0055] In the above embodiment, in the formation process, the first semiconductor chip 3 is heated together with the substrate 2, and the contact region R of the adhesive layer 24 is brought into contact with the first semiconductor chip 3 and held for a predetermined time, thereby partially melting the adhesive layer 24 centered on the contact region R, but it is not necessary to hold the adhesive layer 24 in contact with the first semiconductor chip 3. The adhesive layer 24 may be pressed into the first semiconductor chip 3 at a low speed (low load) within a range that causes partial melting of the adhesive layer 24 centered on the contact region R.

[0056] In the above embodiment, the semiconductor device is exemplified as a semiconductor package 1 in which the first semiconductor chip 3 is connected to the circuit pattern 8 via the first wire 10, but the configuration of the semiconductor device is not limited to this. For example, the semiconductor device may be a semiconductor package in which the first semiconductor chip 3 and the circuit pattern 8 are flip-chip connected. [Explanation of symbols]

[0057] 1...semiconductor package (semiconductor device), 2...substrate, 3...first semiconductor chip, 4...second semiconductor chip, 5...embedded portion, 24...adhesive layer, 31...semiconductor chip with adhesive layer, L...laser light, R...contact area.

Claims

1. a preparation step of preparing a substrate on which a first semiconductor chip is mounted and a semiconductor chip with an adhesive layer in which an adhesive layer is laminated on a second semiconductor chip; a forming step of thermocompressing the semiconductor chip with the adhesive layer to the substrate with the adhesive layer facing the substrate, and forming an embedding portion for embedding the first semiconductor chip between the substrate and the second semiconductor chip, In the forming step, a contact area of ​​the adhesive layer that contacts the first semiconductor chip is partially heated before pressure bonding.

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the forming process, the first semiconductor chip is heated together with the substrate, the contact area is brought into contact with the first semiconductor chip and held for a predetermined time, and then the semiconductor chip with the adhesive layer is pressed onto the substrate.

3. 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the forming step, the contact area is heated by irradiation with laser light, and then the semiconductor chip with the adhesive layer is pressure-bonded to the substrate.

Images