Non-volatile semiconductor storage device

Abstract

To provide a non-volatile semiconductor storage device to prevent erroneous storage contents from being written to memory cells that are not to be erased when erasing the contents of memory cells that are to be erased.SOLUTION: Each of a plurality of memory cells includes: control capacitors 11, 31 for controlling potentials of floating gates 20, 40; tunneling capacitors 12, 32 for extracting charge from the floating gates 20, 40; and write capacitors 13, 33 for injecting charge into the floating gates 20, 40. Tunneling lines TL connected to the tunneling capacitors 12, 32 are connected to each of a plurality of blocks, with one line commonly connected to each of several memory cells within one block. A data line DL connected to the write capacitors 13, 33 is commonly connected to the plurality of memory cells within the plurality of blocks that are written at different times.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to a nonvolatile semiconductor memory device. [Background technology]

[0002] Nonvolatile memory devices such as flash memories are configured to store information by injecting charges into a floating gate that is electrically insulated from other parts by an insulating film. Some such nonvolatile semiconductor memory devices are configured to inject or extract charges into or from the floating gate using the Fowler-Nordheim (FN) tunneling effect (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-120044 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in such a nonvolatile semiconductor memory device, if a tunnel line connected to a tunnel capacitance for injecting and extracting charge is commonly connected to memory cells in a block to be erased and memory cells in a block not to be erased, charge will be injected into the floating gate from the source terminal of the read transistor for reading whether charge has been injected into the floating gate, resulting in a problem of erroneous writing to memory cells in the block not to be erased when erasing memory cells in the block to be erased.

[0005] Therefore, an object of the present invention is to provide a nonvolatile semiconductor memory device that can prevent erroneous writing, in which incorrect memory contents are written to memory cells that are not to be erased, when erasing the memory contents of memory cells that are to be erased. [Means for solving the problem]

[0006] In order to solve the above problems, the nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that is configured with a plurality of memory cells that retain information depending on whether or not charges are injected into floating gates that are electrically insulated from other parts, The plurality of memory cells are configured into a plurality of blocks each configured as a unit for collectively writing and erasing stored information, each of the plurality of memory cells includes a control capacitance for controlling a potential of a floating gate, a tunnel capacitance for extracting charges from the floating gate, and a write capacitance for injecting charges into the floating gate; The tunnel lines connected to the tunnel capacitance are connected to each of the plurality of blocks, and are commonly connected to a plurality of memory cells within one block. A data line connected to the write capacitor is commonly connected to a plurality of memory cells in the plurality of blocks to which writing is performed at different timings. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing a memory array configuration of a nonvolatile semiconductor memory device 100 as a comparative example. [Figure 2] 2 is a diagram showing a memory cell configuration of the nonvolatile semiconductor memory device 100 of the comparative example shown in FIG. 1. FIG. [Figure 3] 2 is a diagram for explaining an erase operation in the nonvolatile semiconductor memory device 100 of the comparative example shown in FIG. 1. FIG. [Figure 4] 2 is a diagram for explaining a write operation in the nonvolatile semiconductor memory device 100 of the comparative example shown in FIG. 1. FIG. [Figure 5] 1 is a diagram showing a memory array configuration of a nonvolatile semiconductor memory device 10 according to an embodiment of the present invention. [Figure 6]6 is a diagram showing a memory cell configuration of the nonvolatile semiconductor memory device 10 according to the embodiment of the present invention shown in FIG. 5. FIG. [Figure 7] 6 is a diagram for explaining an erase operation in the nonvolatile semiconductor memory device 10 of the embodiment of the present invention shown in FIG. 5. FIG. [Figure 8] 6 is a diagram for explaining a write operation in the nonvolatile semiconductor memory device 10 of the embodiment of the present invention shown in FIG. 5. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0008] Next, an embodiment of the present invention will be described in detail with reference to the drawings.

[0009] First, before describing the nonvolatile semiconductor memory device of this embodiment, a nonvolatile semiconductor memory device of a comparative example will be described.

[0010] FIG. 1 is a diagram showing the memory array configuration of a nonvolatile semiconductor memory device 100 as this comparative example.

[0011] As shown in Figure 1, this comparative example of nonvolatile semiconductor memory device 100 is configured with 36 blocks (4 x 9), each consisting of a plurality of memory cells (hereinafter sometimes simply referred to as cells). In nonvolatile semiconductor memory device 100, each of the plurality of cells has a complementary cell configuration consisting of a main cell and a complementary cell that store information whose logic is inverted from each other, and one bit of information is stored by two cells. Therefore, each block is configured with 16 bits / 32 cells, and writing and erasing are performed in block units.

[0012] The nonvolatile semiconductor memory device 100 is composed of a plurality of memory cells that retain information depending on whether or not an electric charge is injected into a floating gate that is electrically insulated from other parts, and these memory cells are configured into a plurality of blocks that are each configured as a unit for writing and erasing the retained information collectively.

[0013] In this comparative example, one word line WL, one read line RL, and one source line SL are connected to each block, and are commonly connected to 16 bits / 32 cells in each block. The memory cell configuration of the nonvolatile semiconductor memory device 100 of the comparative example shown in Figure 1 is shown in Figure 2. Of the 36 blocks shown in Figure 1, only blocks 0 and 4 are shown in Figure 2.

[0014] As shown in Figure 2, one tunnel line TL is connected to one cell, so 32 tunnel lines TL are required for one block, and they are connected in common to the cells of all blocks in the vertical direction. Since there are 16 main cells and 16 complementary cells in one block, the tunnel lines TL connected to complementary cells are represented with a C, and the tunnel lines TL connected to main cells are represented without the C. Note that the tunnel lines TL and TLC are sometimes collectively referred to as tunnel lines TL.

[0015] The primary cell is composed of a control capacitance 11, a tunnel capacitance 12, a floating gate 20, a read transistor (Tr) 21, and a select transistor (Tr) 22. The complementary cell is composed of a control capacitance 31, a tunnel capacitance 32, a floating gate 40, a read transistor (Tr) 41, and a select transistor (Tr) 42.

[0016] Similarly to the tunnel lines TL, the bit lines BL connected to the drain terminals of the select transistors 22 and 42 are represented with a C if they are connected to a complementary cell, and without a C if they are connected to a primary cell.

[0017] In the following description, the same reference numerals will be used to denote corresponding circuit configurations in different blocks.

[0018] The read transistors 21 and 41 are transistors for reading whether or not charges are injected into the floating gates 20 and 40.

[0019] The select transistors 22 and 42 have gate terminals connected to a read line RL and are transistors for selecting a memory cell from which data is to be read.

[0020] Here, floating gates 20 and 40 are respectively formed by one electrode of each of control capacitors 11 and 31 and tunneling capacitors 12 and 32 and the gate electrodes of read transistors 21 and 41. Specifically, the gate electrodes of control capacitors 11 and 31, tunneling capacitors 12 and 32, and read transistors 21 and 41 are formed from a common polyelectrode, which serves as floating gates (FG) 20 and 40. Since these floating gates (FG) 20 and 40 are not electrically connected to any terminal, the voltage of the floating gates 20 and 40 during writing and erasing (hereinafter sometimes referred to as the FG voltage) is determined by the coupling between control capacitors 11 and 31 and tunneling capacitors 12 and 32. However, the capacitance value of control capacitors 11 and 31 is significantly larger than the capacitance value of tunneling capacitors 12 and 32. Therefore, the voltage difference between word line WL and tunnel line TL is approximately equal to the voltage of floating gates 20 and 40.

[0021] The control capacitors 11 and 31 are connected to a word line WL, and the tunnel capacitors 12 and 32 are connected to tunnel lines TL / TLC. The source terminals of the read transistors 21 and 41 are connected to a source line SL, and the drain terminals are connected to bit lines BL / BLC via the select transistors 22 and 42.

[0022] In the nonvolatile semiconductor memory device 100 of this comparative example, writing and erasing to a memory cell is performed by applying a VPP voltage (high voltage) to each of the word line WL and the tunnel line TL, making the potential difference between FG and TL a high voltage, and injecting and extracting charges from the tunnel capacitors 12 and 32 by the FN tunneling effect. Injecting charges is writing, and extracting charges is erasing.

[0023] The erase operation of the nonvolatile semiconductor memory device 100 of this comparative example is shown in Fig. 3, and the write operation is shown in Fig. 4. In Fig. 3 and Fig. 4, the voltage conditions for write and erase are explained using a case where block 0 is a block to be written or erased, and block 4 is a block not to be written or erased.

[0024] As shown in FIG. 3, during erasure, VPP voltage is applied to a total of 32 tunnel lines TL0-15 / TLC0-15 connected to block 0 to be erased, and 0V is applied to word line WL0, which is commonly connected to the 16 bits / 32 cells of block 0 to be erased. Also, 0V is applied to source line SL. With these voltages applied, the voltages of floating gates 20 and 40 in block 0 become approximately 0V (≒0V). Since tunnel line TL is at VPP voltage, charge is extracted from floating gates 20 and 40 to tunnel line TL. Since tunnel line TL is connected to all vertical blocks 4, 8, ..., 32 not to be erased, as shown in FIG. 1, VPP voltage is also applied to tunnel line TL of block 4, etc., which may result in erroneous erasure. Therefore, VPP voltage is also applied to all word lines WL4, 8, ..., 32 of vertical blocks not to be erased, etc., to set the relative voltage to tunnel line TL to 0V, thereby preventing erroneous erasure.

[0025] In other words, when erasing, 0V is applied to word line WL0 of block 0 to be erased, and VPP voltage is applied to word lines WL4, 8, ... 32 of blocks 4, 8, ... 32 not to be erased, thereby erasing only the memory cells in block 0 to be erased.

[0026] As shown in FIG. 4, during writing, the VPP voltage is applied to word line WL0 of block 0 to be written. Since nonvolatile semiconductor memory device 100 has a complementary cell configuration, an inverted value must be written to the correct and complementary cells. For a cell with an expected value of "0" (the complementary cell in FIG. 4), applying 0V to TLC0 causes the voltage of floating gate 40 to be approximately VPP (≒VPP). Since tunnel line TLC0 is 0V, charge is injected into floating gate 40 from tunnel line TLC0. For a cell with an expected value of "1" (the correct cell in FIG. 4), applying 3V, for example, to tunnel line TL0 makes the voltage between floating gate 20 and tunnel line TL0 lower than that of the complementary cell, preventing charge injection. Specifically, when VPP is, for example, 9V, the voltage between floating gate 40 and tunnel line TLC0 is approximately 9V, but the voltage between floating gate 20 and tunnel line TL0 is 9-3=6V. A voltage higher than a certain level is required to inject charges by the FN tunneling effect via the tunneling capacitance 12. Therefore, by keeping the voltage between the floating gate 20 and the tunnel line TL0 low at around 6V, charges are prevented from being injected from the tunnel line TL0 via the tunneling capacitance 12 into the floating gate 20.

[0027] The state in which charges (electrons) are injected into the floating gates 20 and 40 is "0", and the state in which charges (electrons) are not injected is "1".

[0028] Here, one tunnel line TL is required for each cell, and 32 lines for each block, because control is required for each cell in order to write the expected value 1 / 0.

[0029] However, as mentioned above, during erasure, the VPP voltage is applied to the tunnel lines TL connected in the vertical direction, and to prevent erroneous erasure, the VPP voltage must also be applied to the word lines WL of the vertical blocks 4 and other blocks not to be erased that intersect with the tunnel lines TL. This means that the FG voltage of the blocks 4 and other blocks becomes approximately VPP. As a result, in the blocks 4 and other blocks not to be erased, the potential difference between the floating gates 20, 40 and the source lines SL becomes large, causing charges to be injected from the source lines SL of the read transistors 21, 41, resulting in erroneous writing to memory cells in the blocks not to be erased when erasing memory cells in a block to be erased. This problem occurs because the read transistors 21, 41 form a so-called MOS capacitor between the floating gates 20, 40 and the source line SL4.

[0030] If the VPP voltage is applied to the source line SL, the potential difference disappears, but the readout Tr does not have the withstand voltage, so a high voltage cannot be applied.

[0031] Furthermore, in the nonvolatile semiconductor memory device 100, during writing and erasing, it is desirable to fix all word lines WL and tunnel lines TL of non-target blocks to 0V and make the FG voltage ≒ 0V, but since the tunnel lines TL are connected to all blocks in the vertical direction, it was not possible to control the voltage in the target and non-target blocks.

[0032] Therefore, in one embodiment of the nonvolatile semiconductor memory device, the following memory cell / array configuration is used, which makes it possible to prevent erroneous writing, in which incorrect memory contents are written to memory cells that are not to be erased, when erasing the memory contents of memory cells that are to be erased.

[0033] [One embodiment of the present invention] The memory array configuration of a nonvolatile semiconductor memory device 10 according to one embodiment of the present invention is shown in Fig. 5. The memory cell configuration of the nonvolatile semiconductor memory device 10 according to this embodiment shown in Fig. 5 is shown in Fig. 6.

[0034] As shown in Figures 5 and 6, in the nonvolatile semiconductor memory device 10 of this embodiment, the tunnel lines TL are also arranged to run parallel to the word lines WL, with only one line connected per block and commonly connected to 16 bits / 32 cells.

[0035] Furthermore, in the nonvolatile semiconductor memory device 10 of this embodiment, new data lines DL are added. These data lines DL are composed of data lines DL for primary cells and data lines DLC for complementary cells, and are commonly connected among multiple blocks arranged in the vertical direction. For example, a total of 32 data lines DL, namely data lines DL0 to DLC15 and DLC0 to DLC15, are commonly connected to nine blocks, namely blocks 0, 4, ..., 32.

[0036] As shown in FIG. 6, a write capacitor 13 is added to each of the primary cells of the memory cells in each block, and a write capacitor 33 is added to each of the complementary cells.

[0037] Therefore, in the nonvolatile semiconductor memory device 10 of this embodiment, the floating gates 20, 40 are formed by one electrode of each of the control capacitors 11, 31, tunnel capacitor 12, and write capacitors 13, 33 and the gate electrodes of the read transistors 21, 41.

[0038] The write capacitors 13 and 33 are connected to the data lines DL / DLC, which are connected in common to the memory cells of all blocks arranged in the vertical direction, like the tunnel lines TL / TLC in the conventional nonvolatile semiconductor memory device 100, as described above.

[0039] As described above, in this embodiment, each of the plurality of memory cells includes a control capacitance 11, 31 for controlling the potential of the floating gate 20, 40, a tunnel capacitance 12, 32 for extracting charge from the floating gate 20, 40, and a write capacitance 13, 33 for injecting charge into the floating gate 20, 40. Tunnel lines TL connected to the tunnel capacitances 12, 32 are connected to each of the plurality of blocks, and are commonly connected to a plurality of memory cells within one block. Data lines DL connected to the write capacitances 13, 33 are commonly connected to a plurality of memory cells within the plurality of blocks to which data is written at different timings.

[0040] 1 and 2, both injection of charges into the floating gates 20, 40 and extraction of charges from the floating gates 20, 40 are performed via the tunneling capacitances 12, 32. However, the nonvolatile semiconductor memory device 10 of this embodiment is different in that it is configured such that injection of charges into the floating gates 20, 40 is performed via the write capacitances 13, 33, and extraction of charges from the floating gates 20, 40 is performed via the tunneling capacitances 12, 32.

[0041] Next, the operation during erasure in the nonvolatile semiconductor memory device 10 of this embodiment will be described with reference to Fig. 7. In this embodiment as well, the operation will be described when block 0 is a block to be written or erased and block 4 is a block not to be written or erased.

[0042] In the nonvolatile semiconductor memory device 10 of this embodiment, during erasure, for block 0, which is the block to be erased, 0V is applied to word line WL0 and VPP voltage is applied to tunnel line TL0. For block 4, which is the block not to be erased, 0V is applied to word line WL4 and 0V is also applied to tunnel line TL4. 0V is also applied to source line SL.

[0043] By applying such a voltage, the voltage of the floating gates 20, 40 in the block 0 to be erased becomes approximately 0V (≈0V), and since the tunnel line TL0 is at the VPP voltage, charges are extracted from the floating gates 20, 40 to the tunnel line TL0.

[0044] In this embodiment, since the tunnel lines TL can be controlled on a block-by-block basis, by applying the VPP voltage only to TL0 of block 0 to be erased and applying 0V to the tunnel lines TL4, 8, ..., 32 of blocks 4, 8, ..., 32 that are not to be erased, there is no need to apply the VPP voltage to the word lines WL of blocks 4, 8, ..., 32 that are not to be erased.

[0045] If the word line WL is set to 0V, the FG voltage becomes approximately 0V, eliminating the potential difference between the floating gates 20, 40 and the source line SL, and no erroneous write occurs. In other words, in the nonvolatile semiconductor memory device 10 of this embodiment, when erasing memory cells in block 0, which is the erase target, no erroneous write occurs to memory cells in block 4, which is not the erase target.

[0046] However, if the same tunnel line TL is commonly connected to all memory cells in the same block, a problem occurs in that it becomes impossible to write the expected value 1 / 0 cells using the tunnel line TL during writing.

[0047] Therefore, in this embodiment, write capacitors 13, 33 and data lines DL / DLC are added, and during writing, a VPP voltage is applied to the word line WL0 and tunnel line TL0, the potential difference between the floating gates 20, 40 and the data lines DL / DLC is set to a high voltage, and charge is injected from the write capacitors 13, 33. Furthermore, since the data line DL is connected to the primary cell and the data line DLC is connected to the complementary cell, the voltage difference between the voltages applied to the data lines DL / DLC makes it possible to write the expected value 1 / 0, just as in the case of using conventional tunnel lines TL / TLC.

[0048] Finally, the write operation in the nonvolatile semiconductor memory device 10 of this embodiment will be described with reference to FIG.

[0049] As described above, in the nonvolatile semiconductor memory device of this embodiment, during writing, VPP voltage is applied to word line WL0 and tunnel line TL0 of block 0 to be written, and 0V is applied to DLC0 of a cell whose expected value is "0" (the complementary cell in FIG. 8). With this voltage application, the voltage of floating gate 40 becomes approximately VPP voltage (≈VPP voltage), and since data line DLC0 is at 0V, charge is injected into floating gate 40 from data line DLC0 via write capacitor 33. For a cell whose expected value is "1" (the correct cell in FIG. 8), for example, 3V is applied to data line DL0, making the voltage between floating gate 20 and data line DL0 lower than that of the complementary cell, preventing charge injection.

[0050] In this embodiment, by connecting the data lines DL / DLC to the primary cell and the complementary cell, respectively, the voltage difference between the voltages applied to the data lines DL / DLC makes it possible to write the expected value 1 / 0, just as in the case of using the conventional tunnel lines TL / TLC. [Explanation of symbols]

[0051] 10 Nonvolatile semiconductor memory device 11 Control capacitance 12 Tunnel capacity 13 Write capacity 20 Floating Gate 21 Readout transistor 22 Select transistor 31 Control capacity 32 Tunnel Capacity 33 Write capacity 40 Floating Gate 100 Nonvolatile semiconductor memory device

Claims

1. A nonvolatile semiconductor memory device comprising a plurality of memory cells that retain information depending on whether or not charges are injected into floating gates that are electrically isolated from other parts, the plurality of memory cells are configured into a plurality of blocks each configured as a unit for collectively writing and erasing stored information; each of the plurality of memory cells includes a control capacitance for controlling a potential of a floating gate, a tunnel capacitance for extracting charges from the floating gate, and a write capacitance for injecting charges into the floating gate; the tunnel lines connected to the tunnel capacitance are connected to each of the plurality of blocks, and are commonly connected to a plurality of memory cells within one block; a data line connected to the write capacitor is commonly connected to a plurality of memory cells in the plurality of blocks to which writing is performed at different timings; A nonvolatile semiconductor memory device.

2. a read transistor for reading whether or not a charge is injected into the floating gate; the floating gate is composed of one electrode of each of the control capacitance, the tunnel capacitance, and the write capacitance, and a gate electrode of the read transistor; 2. The nonvolatile semiconductor memory device according to claim 1.

3. Each of the plurality of memory cells is composed of a true cell and a complementary cell that store information whose logic is inverted with respect to each other, The data lines are composed of a data line for the primary cell and a data line for the complementary cell.

2. The nonvolatile semiconductor memory device according to claim 1.

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