Memory device

Abstract

To improve characteristics of a memory device.SOLUTION: A memory device according to one embodiment includes a voltage generation circuit to which a first external voltage VCC and a second external voltage VPP higher than the first external voltage are supplied and which generates an operation voltage of a memory cell array. An operation mode of the voltage generation circuit includes a first mode in which a first period T1 and a second period T2 after the first period T1 are included in generating a first voltage value of the operation voltage, and the operation voltage is generated by using the first external voltage VCC in the first period T1 and using the second external voltage VPP in the second period T2.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to memory devices. [Background technology]

[0002] NAND flash memories capable of storing data in a nonvolatile manner are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2016 / 0099072 [Patent Document 2] US Patent Application Publication No. 2018 / 0129601 [Patent Document 3] US Patent Application Publication No. 2021 / 0143732 Summary of the Invention [Problem to be solved by the invention]

[0004] Improve the characteristics of memory devices. [Means for solving the problem]

[0005] The memory device of the embodiment comprises a memory cell array including a plurality of memory cells, and a voltage generation circuit that is supplied with a first external voltage and a second external voltage higher than the first external voltage and generates an operating voltage for the memory cell array, and the operating modes of the voltage generation circuit include a first period and a second period after the first period when generating a first voltage value of the operating voltage, and includes a first mode in which the operating voltage is generated using the first external voltage in the first period and the second external voltage in the second period. [Brief explanation of the drawings]

[0006] [Figure 1]FIG. 1 is a block diagram showing a system including a memory device according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of the configuration of a memory cell array of the memory device according to the first embodiment. [Figure 3] 1 is a cross-sectional view showing a structural example of a memory cell array of a memory device according to a first embodiment. [Figure 4] 3 is a cross-sectional view showing a structural example of a memory pillar of the memory device according to the first embodiment. [Figure 5] FIG. 1 is a diagram showing the relationship between data and the threshold voltage of a memory cell. [Figure 6] FIG. 2 is a circuit diagram showing a configuration example of a voltage generating circuit of the memory device according to the first embodiment. [Figure 7] FIG. 2 is a cross-sectional view showing an example of the structure of an element of a voltage generating circuit of the memory device according to the first embodiment. [Figure 8] FIG. 2 is a diagram showing operation modes of the voltage generating circuit of the memory device according to the first embodiment. [Figure 9] FIG. 2 is a diagram for explaining an example of the operation of the memory device according to the first embodiment. [Figure 10] FIG. 2 is a diagram for explaining an example of the operation of the memory device according to the first embodiment. [Figure 11] FIG. 2 is a diagram for explaining an example of the operation of the memory device according to the first embodiment. [Figure 12] FIG. 2 is a diagram for explaining an example of the operation of the memory device according to the first embodiment. [Figure 13] FIG. 4 is a diagram showing verification results of the memory device according to the first embodiment. [Figure 14] FIG. 4 is a diagram showing verification results of the memory device according to the first embodiment. [Figure 15] FIG. 4 is a diagram showing verification results of the memory device according to the first embodiment. [Figure 16] FIG. 4 is a diagram showing verification results of the memory device according to the first embodiment. [Figure 17] FIG. 10 is a circuit diagram showing an example of the configuration of a memory device according to a second embodiment. [Figure 18] FIG. 10 is a circuit diagram showing an example of the configuration of a memory device according to a second embodiment. [Figure 19]FIG. 10 is a diagram for explaining an example of the operation of the memory device according to the second embodiment. [Figure 20] FIG. 10 is a diagram for explaining an example of the operation of the memory device according to the second embodiment. [Figure 21] FIG. 10 is a circuit diagram showing an example of the configuration of a memory device according to a third embodiment. [Figure 22] FIG. 10 is a diagram for explaining an example of the operation of the memory device according to the third embodiment. [Figure 23] FIG. 10 is a diagram for explaining an example of the operation of the memory device according to the third embodiment. [Figure 24] FIG. 10 is a cross-sectional view showing a modification of the memory device according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] 1 to 24, memory devices according to embodiments will be described. In the following description, elements having the same function and configuration will be designated by the same reference numerals. Furthermore, in the following embodiments, when components (e.g., circuits, wiring, various voltages and signals, etc.) designated by reference numerals with distinguishing numbers / letters at the end are not necessarily distinguished from one another, the reference numerals will be omitted.

[0008] (1) First embodiment A memory device and a method for controlling the memory device according to the first embodiment will be described with reference to FIGS.

[0009] (a) Configuration example An example of the configuration of a memory device according to the first embodiment will be described with reference to FIGS.

[0010] FIG. 1 is a block diagram for explaining an example of the configuration of a memory system SYS including a memory device 1 according to this embodiment.

[0011] 1, the memory system SYS is connected to a host device 9 via a host bus. The memory system SYS can be requested by the host device 9 to write data, read data, and erase data.

[0012] The host device 9 is, for example, a personal computer, an embedded device, or a server. The embedded device is, for example, a smartphone, a mobile terminal, or a digital camera. The host bus is, for example, an SD TM The interface is a bus based on an interface standard such as SAS (Serial attached SCSI (small computer system interface)), SATA (Serial ATA (advanced technology attachment)), PCIe (Peripheral component interconnect express), or NVMe (Non-volatile memory express). The memory system SYS may be connected to the host device 9 via wireless communication.

[0013] The memory system SYS includes the memory device 1 of this embodiment and a memory controller 5.

[0014] The memory controller 5 is electrically coupled to the memory device 1. The memory controller 5 sends a command CMD, an address ADD, data DT, and a plurality of control signals to the memory device 1.

[0015] The memory device 1 is a nonvolatile semiconductor memory device, for example, a NAND flash memory.

[0016] The memory device 1 receives a command CMD, an address ADD, data DT, and a number of control signals. The data DT is transferred between the memory device 1 and the memory controller 5. In the following, during a write sequence, the data DT transferred from the memory controller 5 to the memory device 1 is referred to as write data. The write data DT is written into the memory device 1. During a read sequence, the data DT transferred from the memory device 1 to the memory controller 5 is referred to as read data. The read data DT is read from the memory device 1.

[0017] The memory device 1 includes, for example, a memory cell array 110, a command register 120, an address register 130, a row control circuit 140, a sense amplifier circuit 150, a voltage generation circuit 170, an input / output circuit 180, and a sequencer 190.

[0018] The memory cell array 110 stores data. A plurality of bit lines and a plurality of word lines are provided within the memory cell array 110. The memory cell array 110 includes a plurality of blocks BLK (BLK0, . . . , BLKk-1). Each block BLK is a collection of a plurality of memory cells. Each memory cell is associated with one bit line and one word line. The memory cell array 110 includes a plurality of select gate lines for selecting a control unit within the memory cell array 110. The internal configuration of the memory cell array 110 will be described later.

[0019] The command register 120 temporarily stores a command CMD from the memory controller 5. The command CMD is, for example, a signal including an instruction for causing the sequencer 190 to execute a read sequence, a write sequence, an erase sequence, or the like.

[0020] The address register 130 temporarily stores an address (selected address) ADD from the memory controller 5. The address ADD includes, for example, a block address, a page address (word line address), and a column address. The block address, page address, and column address are used to select a block BLK, a word line, and a bit line (column), respectively. Hereinafter, a block selected based on a block address is referred to as a selected block. A word line selected based on a page address is referred to as a selected word line.

[0021] The row control circuit 140 controls operations related to rows in the memory cell array 110. The row control circuit 140 selects one block BLK in the memory cell array 110 based on a block address. The row control circuit 140 transfers, for example, a voltage applied to a wiring corresponding to a selected word line to the selected word line in the selected block BLK. The row control circuit 140 controls the selection (activation) and deselection (deactivation) of a select gate line based on an address ADD. The row control circuit 140 includes a transfer gate HV of a high-voltage transistor. The transfer gate HV transfers a voltage generated by a voltage generation circuit 170 (described later) to the wiring in the memory cell array 110. The transfer gate (high-voltage transistor) HV has a withstand voltage of 10 V or more, more specifically, a withstand voltage (e.g., a dielectric withstand voltage) of approximately 20 V to 30 V.

[0022] The sense amplifier circuit 150 controls operations related to columns of the memory cell array 110. In a write sequence, the sense amplifier circuit 150 applies a voltage to each bit line provided in the memory cell array 110 in accordance with write data DT from the memory controller 5. In a read sequence, the sense amplifier circuit 150 determines the data stored in the memory cell based on the presence or absence of current generation in the bit line or a fluctuation in the potential of the bit line. The sense amplifier circuit 150 transfers data based on this determination result to the memory controller 5 as read data DT. The sense amplifier circuit 150 includes a sense amplifier unit, a data latch circuit, a cache circuit, etc.

[0023] The voltage generation circuit 170 generates and outputs multiple voltages (hereinafter also referred to as operating voltages) for various operations of the memory device 1. The voltage generation circuit 170 receives an external voltage VCC and an external voltage VPP from outside the memory device 1. The voltage generation circuit 170 receives a ground voltage VGND from outside the memory device 1. The voltage generation circuit 170 generates an operating voltage having a desired voltage value using at least one of the external voltage VCC and the external voltage VPP. The external voltage VCC is supplied to a voltage node (external voltage terminal) ND0. The external voltage VPP is supplied to a voltage node ND1. The ground voltage VGND is supplied to a voltage node NDg. The external voltages VCC and VPP are higher than the ground voltage VGND and have positive voltage values. The voltage value of the external voltage VPP is higher than that of the external voltage VCC. For example, the external voltage VCC has a voltage value of approximately 2.5V to 3.3V. For example, the external voltage VPP has a voltage value of approximately 6V to 12V. As a more specific example, the external voltage VPP has a voltage value within a voltage range of approximately 12 V±10%. Note that the external voltage VPP may have a voltage value higher than 12 V. The ground voltage VGND has a voltage value of approximately 0 V. Depending on the usage environment of the memory system SYS, the external voltage VPP may not be supplied to the voltage generation circuit 170.

[0024] A current Icc corresponding to the external voltage VCC flows through the voltage node ND0, and a current Ipp corresponding to the external voltage VPP flows through the voltage node ND1.

[0025] The voltage generating circuit 170 includes a plurality of charge pump circuits 171 (171A, 171B, 171C, 171D, and 171E), a negative voltage generating circuit 175, and a regulator 179.

[0026] The multiple charge pump circuits 171 output voltages having positive voltage values. Each of the multiple charge pump circuits 171 generates a voltage in a different range (voltage value). Each charge pump circuit 171 boosts the voltage VCC using multiple boosting stages (pump stages) to generate a desired voltage. The charge pump circuit 171A generates a program voltage VPGM supplied to a selected word line during a program operation and a voltage VPGMH equal to or greater than the program voltage VPGM. The charge pump circuit 171B generates a read voltage VCGRV supplied to a selected word line during a read operation. The charge pump circuit 171C generates an erase voltage VERA applied to a word line during an erase operation. The charge pump circuit 171D generates a non-select voltage VREAD supplied to non-selected word lines during a read operation and a verify operation, and a non-select voltage VPASS supplied to non-selected word lines during a program operation. The charge pump circuit 171E generates a voltage VX supplied to the sense amplifier circuit 150. In the following, the various voltages generated by each of the charge pump circuits 171 are also referred to as charge pump voltages.

[0027] The negative voltage generating circuit 175 generates an operating voltage having a negative voltage value. The negative voltage generating circuit 175 generates an operating voltage having a negative voltage value using an external voltage VCC.

[0028] The regulator 179 receives the voltage output from the charge pump circuit 171 and the external voltage VPP. The regulator 179 adjusts the magnitude of the voltage output from the charge pump circuit 171 and the magnitude of the supplied external voltage VPP. For example, the regulator 179 can step down the external voltage VPP to generate an operating voltage having a certain voltage value. Hereinafter, the voltage output from the regulator 179 will also be referred to as a regulator voltage. Note that the regulator 179 can be provided inside each charge pump circuit 171 as a component of the charge pump circuit 171.

[0029] For example, the voltage generating circuit 170 includes a low-voltage transistor LV. The low-voltage transistor LV has a withstand voltage (for example, a dielectric withstand voltage) of about 3V to 5V.

[0030] The input / output circuit 180 functions as an interface circuit on the memory device 1 side between the memory device 1 and the memory controller 5. When the memory device 1 is a NAND flash memory, the input / output circuit 180 is an ONFI The memory device 1 communicates with the memory controller 5 based on a NAND interface standard such as the Open NAND flash interface (NAND flash interface). A command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, a ready / busy signal RBn, an input / output signal DQ, and the like are used for communication between the memory device 1 and the memory controller 5.

[0031] The command latch enable signal CLE is a signal indicating that the input / output signal DQ received by the memory device 1 is a command CMD. The address latch enable signal ALE is a signal indicating that the input / output signal DQ received by the memory device 1 is an address ADD. The write enable signal WEn is a signal that instructs the memory device 1 to input the input / output signal DQ (data write operation). The read enable signal REn is a signal that instructs the memory device 1 to output the input / output signal DQ from the memory device 1 to the memory controller 5 (host device 9).

[0032] The ready / busy signal RBn is a signal that is sent from the memory device 1 to the memory controller 5 to notify whether the memory device 1 is in a ready state where it can accept commands from the memory controller 5, or in a busy state where it cannot accept commands.

[0033] The input / output signals DQ are, for example, an 8-bit wide signal set, and may include a command CMD, an address ADD, data DT, and the like.

[0034] The sequencer 190 controls the operation of the entire memory device 1. The sequencer 190 controls each circuit based on the command CMD in the command register 120. For example, the sequencer 190 holds parameters PRM for controlling the operation of the memory device 1 in a register 191. When the power of the memory device 1 (and the memory system SYS) is turned on, the parameters PRM are read from a ROM (Read Only Memory) block in the memory device 1 to the register 191 in the sequencer 190. The parameters PRM may be supplied to the memory device 1 from the memory controller 5.

[0035] For example, a control unit called a plane may be provided within the memory device 1. One plane includes a memory cell array 110, a row control circuit 140, and a sense amplifier circuit 150. In the example of FIG. 1, the memory device 1 includes one plane. The memory device 1 may also include multiple planes.

[0036] (a-1) Memory cell array FIG. 2 is a circuit diagram showing the circuit configuration of one block BLK in the memory cell array 110 in the memory device 1 of this embodiment.

[0037] 2, when the memory device 1 is a NAND flash memory, one block BLK includes multiple (e.g., four) string units SU (SU0, . . . , SU3). Each string unit SU includes multiple NAND strings NS. The number of blocks BLK in the memory cell array 110, the number of string units SU in the block BLK, and the number of NAND strings NS in the string unit SU are arbitrary.

[0038] Each NAND string NS includes a plurality of memory cells MT (MT0, MT1, MT2, . . . , MTn-3, MTn-2, MTn-1) and a plurality of select transistors ST1 and ST2, where n is a natural number equal to or greater than 2. The memory cells MT are connected in series between the source of the select transistor ST1 and the drain of the select transistor ST2.

[0039] A memory cell (also called a memory cell transistor) MT is a field-effect transistor having a control gate and a charge storage layer, and stores one or more bits of data in a substantially non-volatile manner.

[0040] The gate of the select transistor ST1 in each of the string units SU0, . . . , SU3 is connected to a corresponding one of the plurality of drain-side select gate lines SGD (SGD0, . . . , SGD3).

[0041] The gates of the select transistors ST2 in each of the string units SU0, . . . , SU3 are commonly connected to one source-side select gate line SGS, for example, or may be connected to different source-side select gate lines SGS for each of the string units SU0, . . . , SU3.

[0042] The control gates of memory cells MT0,...,MTn-1 belonging to the same block BLK are each connected to a corresponding one of multiple word lines WL (WL0, WL1, WL2,...,WLn-3, WLn-2, ​​WLn-1).

[0043] The drains of the select transistors ST1 of the NAND strings NS belonging to the same column in the memory cell array 110 are connected to corresponding ones of the multiple bit lines BL (BL0, BL1, . . . , BLm-1), where m is a natural number of 2 or more.

[0044] The sources of the select transistors ST2 are commonly connected to a source line SL.

[0045] A string unit SU is a collection of NAND strings NS connected to different bit lines BL and the same drain-side select gate line SGD. A block BLK is a collection of multiple string units SU that share multiple word lines WL. A memory cell array 110 is a collection of multiple blocks BLK that share multiple bit lines BL.

[0046] In the following, among the string units SU, a group of memory cells MT commonly connected to the same word line WL (a group of memory cells) is also called a cell unit CU (or a memory group).

[0047] FIG. 3 is a cross-sectional view showing an example of the structure of the memory cell array of the memory device 1 of this embodiment.

[0048] 3, the memory cell array 110 further includes a substrate 20, conductive layers 21, 22 (22a, 22b, 22c), 25, and insulating layers 32a, 32, 34, 38. The memory cell array 110 has a structure (stacked wiring) 300 in which a plurality of conductive layers 22 are stacked in the Z direction.

[0049] An insulating layer 38 is provided on the upper surface of the substrate 20. The substrate 20 is a semiconductor substrate or an insulator (for example, a resin).

[0050] A conductive layer 21 is provided on the upper surface of the insulating layer 38. The conductive layer 21 is, for example, a plate-shaped layer extending along the XY plane. The conductive layer 21 is used as a source line SL. The conductive layer 21 includes, for example, silicon doped with phosphorus.

[0051] An insulating layer 32a is provided on the upper surface of the conductive layer 21. A conductive layer 22a is provided on the upper surface of the insulating layer 32a. The conductive layer 22a is, for example, a plate-shaped layer extending along the XY plane. The conductive layer 22a is used as a source-side select gate line SGS. The conductive layer 22a includes, for example, tungsten.

[0052] On the upper surface of the conductive layer 22a, insulating layers 32 and conductive layers 22b are alternately stacked in the Z direction. The conductive layer 22b is, for example, a plate-like layer extending along the XY plane. The stacked conductive layers 22b are used as word lines WL0, . . . , WLn-1, respectively, in order from the substrate 20 side. The conductive layer 22b contains, for example, tungsten.

[0053] A conductive layer 22c is provided above the uppermost conductive layer 22b with an insulating layer 32 interposed therebetween. The conductive layer 22c is, for example, a plate-shaped layer extending along the XY plane. The conductive layer 22c is used as the drain-side select gate line SGD. The conductive layer 22c includes, for example, tungsten.

[0054] An insulating layer 34 is provided on the upper surface of the conductive layer 22c. The insulating layer 34 may be composed of multiple insulating layers. A conductive layer 25 is provided on the upper surface of the insulating layer 34. The conductive layer 25 is, for example, a linear layer extending in the Y direction. The conductive layer 25 is used as a bit line BL. In a region not shown, multiple conductive layers 25 are arranged along the X direction. The conductive layer 25 includes, for example, copper.

[0055] Each memory pillar MP extends along the Z direction and is provided in the stacked wiring 300. The memory pillar MP penetrates the insulating layer 32 and the conductive layer 22. The bottom of the memory pillar MP is in contact with the conductive layer 21. The portion where the memory pillar MP intersects with the conductive layer 22a functions as a select transistor ST2. The portion where the memory pillar MP intersects with one conductive layer 22b functions as one memory cell transistor MT. The portion where the memory pillar MP intersects with the conductive layer 22c functions as a select transistor ST1.

[0056] Each memory pillar MP includes, for example, a core member 40, a semiconductor layer 41, and a stacked film 42. The core member 40 is provided extending along the Z direction. For example, the upper end of the core member 40 is included in a layer above the conductive layer 22c. The lower end of the core member 40 reaches the conductive layer 21. The semiconductor layer 41 covers the periphery of the core member 40. At the bottom of the memory pillar MP, a portion of the semiconductor layer 41 contacts the conductive layer 21. The stacked film 42 covers the side and bottom surfaces of the semiconductor layer 41 except for the portion where the semiconductor layer 41 and the conductive layer 21 contact each other. The core member 40 includes, for example, an insulator such as silicon oxide. The semiconductor layer 41 includes, for example, silicon.

[0057] Pillar-shaped contacts CV are provided on the top surface of the semiconductor layer 41 in the memory pillars MP. Two contacts CV corresponding to two of the six memory pillars MP are shown in the illustrated region. The contacts CV are connected to the memory pillars MP that do not overlap with the slits SHE and are not connected to the contacts CV in a region not illustrated (for example, a region toward the front or back of the page).

[0058] One conductive layer 25 (one bit line BL) is in contact with the upper surface of the contact CV. In each space separated by the slits SLT and the slits SHE, one contact CV is connected to one conductive layer 25. Each conductive layer 25 is electrically connected to a memory pillar MP provided between adjacent slits SLT, SHE and a memory pillar MP provided between two adjacent slits SHE.

[0059] The slit SLT has, for example, a portion provided along the XZ plane, and divides the conductive layer 22. The contact LI in the slit SLT is provided along the slit SLT. A portion of the upper end of the contact LI is in contact with the insulating layer 34. The lower end of the contact LI is in contact with the conductive layer 21. The contact LI is, for example, a conductor used as a part of the source line SL. A spacer SP is provided at least between the contact LI and the conductive layer 22. The contact LI is separated and insulated from the conductive layer 22 by the spacer SP. The spacer SP is an insulating layer. The slit SLT may be filled with an insulator.

[0060] The slit SHE has, for example, a portion provided along the XZ plane, and divides at least the conductive layer 22c. The upper end of the slit SHE is in contact with the insulating layer 34. The lower end of the slit SHE is in contact with the insulating layer 32 between the uppermost conductive layer 22b and the conductive layer 22c. The slit SHE includes, for example, an insulator such as silicon oxide.

[0061] 4 is a cross-sectional view showing an example of the cross-sectional structure of a memory pillar MP in the memory device 1 of this embodiment. Fig. 4 shows the cross-sectional structure of the memory pillar MP in a layer that is parallel to the surface of the substrate 20 and includes the conductive layer 22b.

[0062] As shown in FIG. 4, the stacked film 42 includes, for example, a tunnel insulating film 43, a charge trapping film 44, and a block insulating film 45.

[0063] In a cross section including the conductive layer 22b, the core member 40 is provided in the center of the memory pillar MP. The semiconductor layer 41 surrounds the side surface of the core member 40. The tunnel insulating film 43 surrounds the side surface of the semiconductor layer 41. The charge trap film 44 surrounds the side surface of the tunnel insulating film 43. The block insulating film 45 surrounds the side surface of the charge trap film 44. The conductive layer 22b surrounds the side surface of the block insulating film 45. The tunnel insulating film 43 contains, for example, silicon oxide. The charge trap film 44 contains, for example, silicon nitride. The block insulating film 45 contains, for example, silicon oxide or aluminum oxide.

[0064] In each of the memory pillars MP described above, the semiconductor layer 41 is used as the channel region (current path) of the memory cell transistors MT0, . . . , MTn-1 and the select transistors ST1, ST2. The charge trap film 44 is used as the charge storage layer of the memory cell transistor MT. By turning on the memory cell transistors MT0, . . . , MTn-1 and the select transistors ST1, ST2, the memory device 1 can pass a current between the bit line BL and the contact LI (source line SL) via the memory pillar MP.

[0065] A single memory cell MT can store one or more bits of data depending on the association between the threshold voltage of the memory cell MT and the data to be stored. A memory cell MT that stores one bit of data is called SLC. A memory cell MT that stores two bits of data is called MLC. A memory cell MT that stores three bits of data is called TLC. A memory cell MT that stores four bits of data is called QLC. A memory cell MT that stores five bits of data is called PLC.

[0066] 5 is a diagram showing an example of the relationship between the threshold voltage of a memory cell MT and data. The horizontal axis of the graph in FIG. 5 represents the threshold voltage (voltage value) Vth of the memory cell MT. The vertical axis of the graph in FIG. 5 represents the number of memory cells. FIG. 5 shows an example in which the memory cells are QLC.

[0067] 5, when one memory cell MT stores 4-bit data, the threshold voltage distribution of the memory cell MT has 16 different states. In this embodiment, these 16 states are called "Q0", "Q1", "Q2", "Q3", "Q4", "Q5", "Q6", "Q7", "Q8", "Q9", "Q10", "Q11", "Q12", "Q13", "Q14", and "Q15" states, respectively, in order from lowest to highest threshold voltage Vth. Different 4-bit data is assigned to each of the "Q0", "Q1", ..., "Q15" states.

[0068] If the threshold voltage of the memory cell MT is higher than the applied read voltage, the memory cell MT is turned off. If the threshold voltage of the memory cell MT is equal to or lower than the applied read voltage, the memory cell MT is turned on. In this way, the magnitude relationship of the threshold voltage of the memory cell relative to the applied read voltage can be determined by turning the memory cell MT on or off in response to the application of the read voltage.

[0069] The unselect voltage VREAD is a voltage applied to unselected word lines WL during a read operation. The voltage value of the unselect voltage VRED is higher than the threshold voltage of the highest state Q15. Therefore, when the unselect voltage VREAD is applied to the gate of a memory cell MT, the memory cell MT is turned on regardless of the data stored therein.

[0070] Of the multiple threshold voltage distributions, the threshold voltage distributions of the five lowest states Q0, Q1, Q2, Q3, and Q4 have voltage values ​​below 0 V (negative voltage values). The threshold voltage distributions of states Q5, Q6, . . . , Q15 have voltage values ​​above 0 V (positive voltage values). Note that the number of states with negative threshold voltages is arbitrary.

[0071] In this way, depending on the allocation of data to the threshold voltages of the memory cells MT, the memory cells MT into which data is programmed may have a negative threshold voltage.

[0072] (a-2) Voltage generation circuit An example of the configuration of the voltage generating circuit 170 in the memory device 1 of this embodiment will be described with reference to FIGS.

[0073] 6 is a circuit diagram showing the circuit configuration of the voltage generating circuit 170 of the memory device 1 of this embodiment. In FIG. 6, the circuit configuration of the voltage generating circuit 170 in a certain voltage system including a charge pump circuit 171 is shown.

[0074] 6, a charge pump circuit 171 (171D) is provided in a certain voltage system in the voltage generation circuit 170. For example, the charge pump circuit 171D in FIG. 6 generates an intermediate level voltage (hereinafter referred to as an intermediate voltage) VM among various operating voltages used in the operation of the memory device 1, such as the non-selection voltage VREAD or the non-selection voltage VPASS.

[0075] The charge pump circuit 171D includes a charge pump (pump group) 99, switch circuits 173A and 173B, a local pump 174, and a regulator 179Z.

[0076] The input node of the charge pump 99 is connected to a voltage node (also referred to as an input node or a power supply node) ND0 of the voltage generating circuit 170. An external voltage VCC is applied to the voltage node ND0. The output node of the charge pump 99 is connected to an input node of a regulator 179 via a switch circuit 173A. The charge pump 99 generates a charge pump voltage VPUMP by boosting the external voltage VCC. The charge pump 99 outputs the generated charge pump voltage VPUMP.

[0077] The switch circuit 173A controls the electrical connection between the charge pump 99 and the regulator 179Z. The switch circuit 173A turns on and off in response to a control signal CNT.

[0078] The external voltage VPP is applied to a voltage node ND1 of the voltage generating circuit 170. The voltage node ND1 is connected to the input node of a regulator 179Z via a switch circuit 173B.

[0079] The switch circuit 173B controls the electrical connection between the voltage node ND1 and the regulator 179Z. The switch circuit 173B is turned on and off in response to a control signal bCNT. For example, the control signal bCNT has a complementary relationship with the control signal CNT. The signal levels of the control signals CNT and bCNT are controlled by the sequencer 190.

[0080] One node of the local pump 174 is connected to the control node of the switch circuit 173B. The other node of the local pump 174 is connected to the voltage node ND1. The local pump 174 boosts the external voltage VPP. The local pump 174 supplies the boosted voltage to the switch circuit 173B. The switch circuit 173B is driven by the boosted voltage. This allows the switch circuit 173B to transfer the external voltage VPP.

[0081] The input node of the regulator 179Z is connected to the switch circuit 173A and the switch circuit 173B. The regulator 179 receives either the external voltage VPP or the charge pump voltage VPUMP depending on the states of the switch circuits 173A and 173B.

[0082] The regulator 179Z adjusts the magnitude of the voltage supplied to the input node of the regulator 179Z, thereby outputting an operating voltage having a desired voltage value to the row control circuit 140 or the sense amplifier circuit 150.

[0083] The sequencer 190 controls the signal levels of the control signals CNT and bCNT according to the operation mode (hereinafter also referred to as the voltage generation mode) set in the voltage generation circuit 170. As a result, the voltage supplied to the regulator 179Z is selected from the external voltage VPP and the charge pump voltage VPUMP according to the voltage generation mode of the charge pump circuit 171D.

[0084] Depending on the voltage output from the charge pump circuit 171D (voltage generating circuit 170) to other circuits, the voltage generated by the charge pump 99 may be output directly to the outside of the charge pump circuit 171D without going through the regulator 179Z.

[0085] 7 is a cross-sectional view showing an example of the structure of elements constituting the voltage generating circuit 170 in the memory device 1 of this embodiment. Note that in FIG. 7, an interlayer insulating film covering the elements of the voltage generating circuit 170 is omitted.

[0086] In the memory device 1 of this embodiment, the voltage generating circuit 170 includes a transistor TR (TR1, TR2) with a triple-well structure. The transistor TR is a low-voltage transistor LV. The threshold voltage of the transistor TR (low-voltage transistor LV) is lower than the threshold voltage of the transfer gate HV. For example, the threshold voltage (gate-source voltage) of the transistor TR is approximately 0.5V to 1.0V, and the threshold voltage of the transfer gate HV is approximately 1V to 2V.

[0087] The transistors TR1 and TR2 are provided on a P-type semiconductor substrate 60. For example, the semiconductor substrate 60 is provided below the memory cell array 110 in the Z direction.

[0088] An N-type well 61 is provided in a semiconductor substrate 60. A P-type well 62 is provided in the N-type well 61. The N-type well 61 surrounds the P-type well 62. The bottom of the N-type well 61 is located deeper than the bottom of the P-type well 62 in the Z direction.

[0089] The transistor TR1 is disposed on the P-type well 62. The transistor TR1 is an N-type field effect transistor. The transistor TR1 includes two source / drain layers 71n, a gate insulating film 72n, and a gate electrode 73n.

[0090] An N-type source / drain layer (diffusion layer, impurity region) 71n is provided in the P-type well 62. A gate insulating film 72n is provided on the P-type well 62. The gate insulating film 72n is disposed on a channel region between the two source / drain layers 71n. A gate electrode 73n is provided on the gate insulating film 72n. The gate electrode 73n faces the channel region via the gate insulating film 72n.

[0091] A contact plug 75n is provided on the source / drain layer 71n. A wiring 76n is provided on the contact plug 75n. The wiring 76n is connected to the source / drain layer 71n via the contact plug 75n.

[0092] A contact plug 77n is provided on the gate electrode 73n. A wiring 78n is provided on the contact plug 77n. The wiring 78n is connected to the gate electrode 73n via the contact plug 77n. A gate voltage is applied to the gate electrode 73n via the wiring 78n and the contact plug 77n.

[0093] An N-type well 65 is provided in the semiconductor substrate 60. The N-type well 65 is adjacent to the N-type well 61 in the Y direction.

[0094] The transistor TR2 is disposed on the N-type well 65. The transistor TR2 is a P-type field effect transistor. The transistor TR2 includes two source / drain layers 71p, a gate insulating film 72p, and a gate electrode 73p.

[0095] For example, the N-type well 65 is formed in a separate process from the N-type well 61. Therefore, the depth of the N-type well 65 (the position of the bottom of the well 65 in the Z direction) is different from the depth of the N-type well 61. Furthermore, the impurity concentration (concentration of the N-type dopant) of the N-type well 65 is different from the impurity concentration of the N-type well 61. The impurity concentration of the N-type well 61 is lower than the impurity concentration of the N-type well 65. However, the N-type well 65 may be formed in the same process as the N-type well 61, and the depth of the N-type well 65 may be the same as the depth of the N-type well 61.

[0096] A P-type source / drain layer (diffusion layer, impurity region) 71p is provided in the N-type well 65. A gate insulating film 72p is provided on the N-type well 65. The gate insulating film 72p is disposed on a channel region between the two source / drain layers 71p. A gate electrode 73p is provided on the gate insulating film 72p. The gate electrode 73p faces the channel region via the gate insulating film 72p.

[0097] A contact plug 75p is provided on the source / drain layer 71p. A wiring 76p is provided on the contact plug 75p. The wiring 76p is connected to the source / drain layer 71p via the contact plug 75p.

[0098] A contact plug 77p is provided on the gate electrode 73p. A wiring 78p is provided on the contact plug 77p. The wiring 78p is connected to the gate electrode 73p via the contact plug 77p. A gate voltage is applied to the gate electrode 73p via the wiring 78p and the contact plug 77p.

[0099] A P-type diffusion layer 63a is provided in the P-type well 62. A contact plug 65a is provided on the diffusion layer 63a. A wiring 66a is provided on the contact plug 65a. The wiring 66a is connected to the diffusion layer 63a via the contact plug 65a.

[0100] An N-type diffusion layer 64a is provided in the N-type well 61. A contact plug 67a is provided on the diffusion layer 64a. The contact plug 67a is connected to a wiring 66a. The wiring 66a is connected to the diffusion layer 64a via the contact plug 67a. The diffusion layer 64a is connected to the diffusion layer 63a via contact plugs 65a and 67a and a wiring 66a. A certain voltage is applied to the N-type well 61 and the P-type well 62 via the wiring 66a, the contact plugs 65a and 67a, and the diffusion layers 63a and 64a.

[0101] An N-type diffusion layer 64b is provided in the N-type well 65. A contact plug 67b is provided on the diffusion layer 64b. A wiring 68b is provided on the contact plug 67b. The wiring 68b is connected to the diffusion layer 64b via the contact plug 67b. A certain voltage is applied to the N-type well 65 via the wiring 68b, the contact plug 67b, and the diffusion layer 64b.

[0102] A P-type diffusion layer 63b is provided in the semiconductor substrate 60 between the N-type well 61 and the N-type well 65. A contact plug 65b is provided on the diffusion layer 63b. A wiring 66b is provided on the contact plug 65b. The wiring 66b is connected to the diffusion layer 63b via the contact plug 65b. A certain voltage is applied to the semiconductor substrate 60 via the wiring 66b, the contact plug 65b, and the diffusion layer 63b. A voltage lower than that applied to the N-type well 61 and the N-type well 65 is applied to the diffusion layer 63b and the semiconductor substrate 60, thereby preventing a forward bias from being applied to the PN junction. The diffusion layer 63b suppresses latch-up and functions as a guard ring.

[0103] A PNP junction bipolar transistor is parasitically formed within the semiconductor substrate 60 by the P-type semiconductor substrate 60, the N-type well 65, and the P-type diffusion layer (source / drain layer) 71p. An NPN junction bipolar transistor is parasitically formed within the semiconductor substrate by the N-type well 61, the P-type semiconductor substrate 60, and the N-type well 65. However, these parasitic bipolar transistors do not adversely affect the operation of the transistor TR by applying a voltage to the diffusion layer 63b lower than that applied to the N-type well 61 and the N-type well 65.

[0104] In the voltage generating circuit 170, the transistor TR having a triple well structure is used, for example, as a charge transfer switch in the charge pump circuit 171. The transistor TR having a triple well structure allows the voltage generating circuit 170 to use a low-breakdown-voltage transistor for transferring charge (voltage). This enables the voltage generating circuit 170 to achieve high-speed charge transfer and a reduced circuit size.

[0105] Furthermore, in the transistor TR having a triple well structure, by controlling the voltage of the substrate 60 and the voltages of the wells 61, 62, and 65, an increase in the threshold voltages of the N-type and P-type transistors TR1 and TR2 due to the back bias effect can be avoided.

[0106] In the memory device 1 of this embodiment, the charge pump circuit 171 of the voltage generating circuit 170 generates and outputs various operating voltages used for operating the memory device 1 in a plurality of operating modes (voltage generating modes).

[0107] FIG. 8 is a schematic diagram for explaining the voltage generation mode of the charge pump circuit 171 in the voltage generation circuit 170 of the memory device 1 of this embodiment.

[0108] As shown in (a), (b), and (c) of Figures 8, in the voltage generation circuit 170 of the memory device 1 of this embodiment, the charge pump circuit 171 (171D) generates an operating voltage using one of three voltage generation modes.

[0109] As shown in (a) of Figure 8, in the first voltage generation mode, the charge pump circuit 171 uses a charge pump 99 as a voltage generation source to boost the external voltage VCC across multiple pump stages to generate an operating voltage having a predetermined voltage value.

[0110] For example, in the first voltage generation mode, the voltage generation circuit 170 boosts the external voltage VCC using i (i is a natural number equal to or greater than 1) pump stages of the charge pump 99. As a result, during a certain operation period (a certain time tx), the voltage generation circuit 170 generates a voltage (voltage value) V1.

[0111] After the generated voltage reaches voltage V1, charge pump circuit 171 increases the number of pump stages and boosts external voltage VCC by j pump stages (j is a natural number greater than i) of charge pump 99. This generates voltage V2 (voltage value) higher than voltage V1.

[0112] The charge pump circuit 171 increases the number of pump stages used in the charge pump 99 from j to k (k is a natural number greater than j), and boosts the external voltage VCC to a voltage equal to or greater than voltage V2 using the k pump stages of the charge pump 99.

[0113] In this way, the charge pump circuit 171 in the first voltage generation mode gradually boosts the external voltage VCC to generate a predetermined operating voltage.

[0114] 8(b), in the second voltage generation mode, the charge pump circuit 171 generates a predetermined operating voltage using an external voltage VPP higher than the external voltage VCC as a voltage generation source. For example, the charge pump circuit 171 generates an operating voltage having a predetermined voltage value by stepping down the external voltage VPP having a constant voltage value using the regulator 179Z.

[0115] In this way, the charge pump circuit 171 in the second voltage generation mode adjusts the external voltage VPP to generate a predetermined operating voltage.

[0116] 8(c), in the third voltage generation mode, the charge pump circuit 171 generates a voltage having a predetermined voltage value using the voltage boosted by the charge pump 99 and the external voltage VPP. For example, in the third voltage generation mode, the charge pump circuit 171 boosts the external voltage VCC using i pump stages in the charge pump 99 to generate a voltage V1 during a period T1 from the start of voltage generation (time 0) to time tx. The voltage value of the voltage V1 is lower than the voltage value of the external voltage VPP.

[0117] In each voltage generation mode, when the charge pump voltage VPUMP is selected, the voltage used as the power supply is set to the external voltage VCC, and the external voltage VCC is boosted. When the external voltage VPP is selected and a voltage higher than the external voltage VPP is generated, the external voltage VPP is set to the voltage used as the power supply, and the external voltage VPP is boosted by the charge pump 99.

[0118] During a period T2 after voltage V1 is reached, the charge pump circuit 171 in the third voltage generation mode changes the external voltage used to generate a voltage from external voltage VCC to external voltage VPP. As a result, in the charge pump circuit 171 in the third voltage generation mode, the voltage generation source switches from the charge pump 99 to external voltage VPP. For example, if the voltage to be generated (e.g., voltage VREAD or voltage VPASS) is approximately 6V, the voltage is boosted by the charge pump 99 from 4V to approximately 5V, and any voltage above 5V is generated by stepping down the external voltage VPP. In this case, period T1 may be longer than period T2. However, period T2 may be longer than period T1 depending on the magnitude of the voltage to be generated.

[0119] As a result, the charge pump circuit 171 in the third voltage generation mode generates an operating voltage having a predetermined voltage value using the external voltage VPP after time tx when the generated voltage reaches voltage V1.

[0120] As described above, the memory device 1 of this embodiment selects one of the three voltage generation modes of the charge pump circuit of the voltage generation circuit 170. The memory device 1 of this embodiment generates a voltage for operating the memory device 1 by the charge pump circuit 171, which operates based on the selected voltage generation mode.

[0121] (b) Example of operation An example of the operation of the memory device 1 of this embodiment will be described with reference to Figures 9, 10, 11, and 12. The example of the operation of the memory device 1 of this embodiment corresponds to a method of controlling the memory device 1.

[0122] (b-1) Setting the voltage generation mode With reference to FIG. 9, the setting of the voltage generation mode of the charge pump circuit 171 of the voltage generation circuit 170 in the memory device 1 of this embodiment will be described.

[0123] FIG. 9 is a schematic diagram for explaining the process for setting and changing the voltage generation mode in the memory device 1 of this embodiment.

[0124] As shown in FIG. 9, in this embodiment, setting and changing of the voltage generation mode is performed by a command CMD based on the interface of the memory device 1 (here, the NAND interface).

[0125] When setting or changing the voltage generation mode, the memory controller 5 sends a command (SetFeature command) CMD of "EFh" to the memory device 1. Following the command CMD, the memory controller 5 sends an address ADD of a storage area for storing a parameter PRM to the memory device 1. Thereafter, the memory controller 5 sends to the memory device 1 a parameter (data) PRM indicating the voltage generation mode to be set in the memory device 1.

[0126] The memory device 1 receives the command CMD, the address ADD, and the parameter PRM in sequence.

[0127] The memory device 1 changes the signal level of the ready / busy signal RBn from "H" level to "L" level, and the state of the memory device 1 is set to the busy state.

[0128] During a busy state, the memory device 1 stores the parameters PRM in a storage area indicated by the address ADD based on the command CMD. During operation of the memory system SYS, the parameters PRM are temporarily stored in a register 191 of the sequencer 190.

[0129] This sets the voltage generation mode to be used in the memory device 1.

[0130] As described above, the memory device 1 of this embodiment sets the voltage generation mode of the voltage generation circuit 170.

[0131] The voltage generation mode indicated by the parameter PRM may be two modes: a first voltage generation mode and a third voltage generation mode.

[0132] (b-2) Operation of the voltage generation circuit in each mode The operation of the charge pump circuit 171 (171D) of the voltage generating circuit 170 in the memory device 1 of this embodiment will be described with reference to FIGS.

[0133] (b-2-1) First voltage generation mode FIG. 10 is a schematic diagram showing the operating state of the charge pump circuit 171D in the first voltage generation mode in the voltage generation circuit 170 of the memory device 1 of this embodiment.

[0134] As shown in FIG. 10, in the first voltage generation mode set in accordance with the parameter PRM, the switch circuit 173A is turned on and the switch circuit 173B is turned off based on the control signals CNT and bCNT.

[0135] The voltage node ND1 of the external voltage VPP is electrically isolated from the regulator 179Z by the switch circuit 173B in the OFF state. The charge pump 99 is electrically connected to the regulator 179Z via the switch circuit 173A in the ON state.

[0136] The charge pump 99 performs a boosting operation of the external voltage VCC. For example, the charge pump (VMPUMP) 99 generates a non-selection voltage VREAD during a read operation or a non-selection voltage VPASS during a program operation.

[0137] 8(a), the charge pump 99 boosts the external voltage VCC using i pump stages in a voltage range (low voltage range) from 0 V to a certain voltage V1. The charge pump 99 boosts the voltage using j pump stages in a voltage range from voltage V1 to voltage V2. The charge pump 99 boosts the voltage using k pump stages in a voltage range higher than voltage V2.

[0138] By boosting the external voltage VCC using these multiple pump stages, the charge pump 99 generates a charge pump voltage VPUMP having a desired voltage value. The charge pump 99 supplies the generated charge pump voltage VPUMP to the regulator 179Z via the switch circuit 173A, which is in the ON state.

[0139] The regulator 179Z adjusts the supplied charge pump voltage VPUMP. The regulator 179Z outputs the adjusted voltage (or an unadjusted voltage) to the row control circuit 140. When the voltage output from the regulator 179Z is supplied to the sense amplifier circuit 150, the sense amplifier circuit 150 uses the supplied voltage to control the voltage of the bit line BL.

[0140] As a result, various operating voltages for the operations to be performed are supplied to the word lines WL and bit lines BL in the memory cell array 110.

[0141] (b-2-2) Second voltage generation mode FIG. 11 is a schematic diagram showing the operating state of the charge pump circuit 171D in the second voltage generation mode in the voltage generation circuit 170 of the memory device 1 of this embodiment.

[0142] As shown in FIG. 11, in the second voltage generation mode set in accordance with the parameter PRM, the switch circuit 173A is turned off and the switch circuit 173B is turned on based on the control signals CNT and bCNT.

[0143] Voltage node ND1, to which external voltage VPP is applied, is electrically connected to regulator 179Z via switch circuit 173B, which is in the ON state. Charge pump 99 is electrically isolated from regulator 179Z by switch circuit 173A, which is in the OFF state.

[0144] 8(b), external voltage VPP is supplied to regulator 179Z via switch circuit 173B in the ON state. The voltage path (wiring) between voltage node ND1 and regulator 179Z is gradually charged in accordance with the output of local pump 174 (gate voltage of switch circuit 173B) through negative feedback control of the monitoring result of the voltage supplied to regulator 179Z. At this time, current Ipp is generated by charging the wiring with voltage VPP.

[0145] The regulator 179Z adjusts the voltage value of the supplied external voltage VPP. For example, the regulator 179Z reduces the voltage of the supplied external voltage VPP. The regulator 179Z outputs the adjusted voltage (or an unadjusted voltage) to the row control circuit 140 or the sense amplifier circuit 150.

[0146] As a result, various operating voltages for the operations to be performed are supplied to the word lines WL and bit lines BL in the memory cell array 110.

[0147] (b-2-3) Third voltage generation mode FIG. 12 is a schematic diagram showing the operating state of the charge pump circuit 171D in the voltage generating circuit 170 of the memory device 1 of this embodiment in the third voltage generating mode.

[0148] 12(a) shows a state during a period (first period) in which the voltage VPUMP from the charge pump 99 is supplied to the regulator 179Z in the third voltage generation mode. FIG. 12(b) shows a state during a period (second period) in which the external voltage VPP is supplied to the regulator 179Z in the third voltage generation mode.

[0149] 12(a), the charge pump circuit 171D starts operation in a third voltage generation mode set according to the parameter PRM. During a first period T1 (in other words, a range of voltage values ​​within which the voltage supply source is switched) set in advance in the third voltage generation mode, the switch circuit 173A is turned on and the switch circuit 173B is turned off based on the control signals CNT and bCNT.

[0150] The voltage node ND1 of the external voltage VPP is electrically isolated from the regulator 179Z by the switch circuit 173B in the OFF state. The charge pump 99 is electrically connected to the regulator 179Z via the switch circuit 173A in the ON state.

[0151] The charge pump 99 performs a boosting operation of the external voltage VCC.

[0152] The charge pump 99 boosts the external voltage VCC by using i pump stages in a voltage range (low voltage range) from 0 V to a certain voltage V1. The charge pump 99 supplies the boosted charge pump voltage VPUMP to the regulator 179Z.

[0153] Regulator 179Z outputs a regulated charge pump voltage (or an unregulated charge pump voltage) VPUMP.

[0154] By boosting the voltage, the magnitude of the charge pump voltage VPUMP reaches the voltage V1.

[0155] During operation in the third voltage generation mode, the charge pump circuit 171D switches the voltage path for the regulator 179Z under the control of the sequencer 190 at time tx when the magnitude of the charge pump voltage VPUMP reaches the voltage V1.

[0156] At time tx, the sequencer 190 changes the signal levels of the control signals CNT and bCNT.

[0157] As shown in FIG. 12(b), during the second period T2 of the set third voltage generation mode, the switch circuit 173A is turned off and the switch circuit 173B is turned on based on the control signals CNT and bCNT.

[0158] Voltage node ND1, to which external voltage VPP is applied, is electrically connected to regulator 179Z via switch circuit 173B, which is in the ON state. Charge pump 99 is electrically isolated from regulator 179Z by switch circuit 173A, which is in the OFF state.

[0159] The external voltage VPP is supplied to the regulator 179Z via the switch circuit 173B in the ON state. The voltage value of the external voltage VPP is higher than the voltage value V1 of the charge pump voltage VPUMP at time tx.

[0160] In this way, the voltage supplied to the regulator 179Z changes from the charge pump voltage VPUMP to the external voltage VPP by switching the two switch circuits 173A and 173B on and off at time tx.

[0161] For example, the time tx at which the charge pump voltage VPUMP (external voltage VCC) is switched to the external voltage VPP is a preset time. As an example, the time tx is set before shipping the memory device 1. Note that the time tx may be variably set based on the monitoring results of the voltage value of the charge pump voltage VPUMP.

[0162] The regulator 179Z adjusts (for example, steps down) the supplied external voltage VPP and outputs the adjusted voltage (or an unadjusted voltage) to the row control circuit 140 or the sense amplifier circuit 150.

[0163] As a result, various operating voltages for the operations to be performed are supplied to the word lines WL and bit lines BL in the memory cell array 110.

[0164] As described above, in the third voltage generation mode, the charge pump circuit 171D switches the voltage supplied to the regulator 179Z from the charge pump voltage VPUMP to the external voltage VPP during voltage generation, and outputs the generated operating voltage. That is, the charge pump circuit 171D generates a voltage using the charge pump 99 in a low voltage range equal to or lower than voltage V1, and generates a voltage using the external voltage VPP in a voltage range higher than voltage V1.

[0165] In the above example, the non-select voltage VREAD during a read operation is generated using the charge pump voltage VPUMP or the external voltage VPP. However, in the memory device 1 of this embodiment, the charge pump circuit 171 can generate the program voltage VPGM, the erase voltage VERA, the read voltage VCGRV, the non-select voltage VPASS, the verify voltage, or the voltage VX supplied to the sense amplifier circuit 150 using the first, second, and third voltage generation modes.

[0166] For example, in an erase operation, a third voltage generation mode is applied in which the charge pump voltage VPUMP is switched to the external voltage VPP for the voltage generation (boost) of the erase voltage VERA supplied to the bit line BL and the source line SL. For example, in a program operation of a write operation, a voltage generation mode is applied in which the charge pump voltage VPUMP is switched to the external voltage VPP for the voltage generation of the non-selection voltage VPASS supplied to the non-selection word line.

[0167] The wiring capacitance of the bit line BL and the wiring capacitance of the unselected word line WL are relatively large, and the voltage rise time is relatively long. Therefore, there is time to switch from the charge pump voltage VPUMP to the external voltage VPP during the erase and program operations. Therefore, the third voltage generation mode can be applied to the erase and program operations.

[0168] (c) Verification The results of verifying the operation of the memory device of this embodiment will be described with reference to FIGS. 13, 14, 15 and 16. FIG.

[0169] 13 shows waveforms of voltage characteristics in each voltage generation mode of the memory device 1 of this embodiment. In Fig. 13, the horizontal axis of the graph corresponds to time, and the vertical axis of the graph corresponds to the voltage value of the voltage VGEN output from the voltage generation circuit 170.

[0170] Figure 13(a) shows the voltage characteristics in the first voltage generation mode, Figure 13(b) shows the voltage characteristics in the second voltage generation mode, and Figure 13(c) shows the voltage waveform in the third voltage generation mode.

[0171] 13(a), in the first voltage generation mode, the charge pump circuit 171 outputs the voltage VPUMP generated by the charge pump 99 as the output voltage VGEN. For example, ripple occurs in the output voltage VGEN due to a delay between detecting the voltage value and pausing operation when the desired voltage value is reached.

[0172] 13(b), in the second voltage generation mode, the charge pump circuit 171 outputs a voltage generated from the external voltage VPP as the output voltage VGEN. The voltage value of the output voltage VGEN gradually increases as the voltage path (wiring) is charged by the supply of the external voltage VPP.

[0173] 13(c), the regulator 179 outputs the charge pump voltage VPUMP as the output voltage VGEN during a period T1 until time tx. At time tx, the voltage supply source for the regulator 179 is switched from the charge pump 99 to the voltage node ND1 of the external voltage VPP.

[0174] During a period T2 from time tx to time tz, the regulator 179 outputs a voltage according to the external voltage VPP as the output voltage VGEN.

[0175] Even if switching from the charge pump voltage VPUMP to the external voltage VPP occurs while the voltage VGEN is being output, the regulator 179 can output the voltage VGEN while maintaining the continuity of the voltage output.

[0176] 14, 15, and 16 are waveform diagrams showing currents generated when the voltage generating circuit 170 generates a voltage in the memory device 1 of this embodiment.

[0177] 14, 15, and 16 show waveforms of currents generated during a read operation when one memory cell MT stores 3 bits of data (when the memory cell is a TLC). The TLC stores data for an upper page (upper bit), a middle page (middle page), and a lower page (lower bit). In the examples of FIGS. 14, 15, and 16, the current Icc generated during a read operation of data from the middle page is shown.

[0178] Regarding the eight types of TLC states (threshold voltage distributions), reading of "AR", "BR", "CR", "DR", "ER", "FR", and "GR" is executed as a state read in order from the lowest state to the highest state. Reading each state classifies high threshold distributions above a certain level and threshold distributions below a certain level. For example, reading "CR" classifies states above the "C" state and states below the "B" state (states below the "C" state). In this way, data of the Middle page is read.

[0179] FIG. 14 shows the current waveform of the current generated from the memory device 1 in the first voltage generation mode. The solid current waveform in FIG. 14 shows the waveform of the current Icc. The current Icc flows to the voltage node ND0 (or the current sink node of the chip). Note that the current Icc is the current of the entire chip of the memory device 1. Therefore, the current Icc includes currents generated by operations other than those using the charge pump circuit 171 (for example, cell currents during sense operations). Therefore, the current Icc is also generated in the voltage generation mode using the external voltage VPP described below.

[0180] 14, at time t0, the operation of the charge pump circuit 171 begins. In the first voltage generation mode, the charge pump 99 operates to generate a voltage. The current value of the current Icc gradually increases over time.

[0181] During a period Ta from time t0, a large peak PK1a of the current Icc occurs due to the operation of the charge pump 99.

[0182] For example, in a read operation of the Middle page of TLC, after the non-selection voltage VREAD is applied to the selected word line WL, reading of "BR", "DR", and "FR" is executed in sequence.

[0183] By applying the non-selection VREAD during the period Ta, all memory cells connected to the selected word line WL are turned on, which generates a current Icc having a large current value (peak PK1a).

[0184] Reading "BR" is performed by applying a read voltage for the "B" state (hereinafter also referred to as read voltage VBR). Memory cells having threshold voltages equal to or lower than the applied read voltage VBR (memory cells in states lower than the "B" state) are turned on.

[0185] After reading "BR", reading "DR" is performed by applying a read voltage for the "D" state (hereinafter also referred to as a read voltage VDR). The read voltage VDR for the "D" state is higher than the read voltage VBR for the "B" state. Memory cells MT having a threshold voltage equal to or lower than the applied read voltage VDR are turned on.

[0186] After reading "DR", reading "FR" is performed by applying a read voltage for the "F" state (hereinafter also referred to as a read voltage VFR). The read voltage VFR for the "F" state is higher than the read voltage VDR for the "D" state. Memory cells having a threshold voltage equal to or lower than the applied read voltage VFR are turned on.

[0187] 15 shows the current waveform of the current generated by the memory device 1 in the second voltage generation mode. The solid current waveform in FIG. 15 shows the waveform of the current Icc. The dashed current waveform in FIG. 5 shows the current Ipp. The current Ipp is the current that flows through the voltage node ND1 to which the external voltage VPP is applied.

[0188] 15, at time t0, the charge pump circuit 171 starts operating, generating a current Icc. In the second voltage generation mode, the current Icc flows in response to the supply of the external voltage VPP. During a period Tb from time t0, a current peak PK1b of the current Icc occurs. The period Tb is shorter than the period Ta. For example, the value of the current peak PK1b is smaller than the value of the current peak PK1a.

[0189] The supply of voltage VPP causes current Ipp to flow, and the peak PK2b of current Ipp occurs after the peak of current Icc (after period Tb has elapsed).

[0190] 16 shows the current waveform of the current generated by the memory device 1 in the third voltage generation mode. The solid current waveform in FIG. 16 shows the waveform of the current Icc. The dashed current waveform in FIG. 5 shows the current Ipp.

[0191] 16, at the start of operation of the charge pump circuit 171 in the third voltage generation mode, a current peak PK1c of the current Icc occurs in a period Tc due to the operation of the charge pump 99. The period Tc is, for example, shorter than the period Ta and longer than the period Tb.

[0192] At time tx, the source of the voltage in the charge pump circuit 171 is switched from the charge pump 99 to the external voltage VPP.

[0193] At time tx, current peak PK1c of current Icc converges (decreases) due to the interruption of the voltage supply from charge pump 99 (stopping of charge pump 99). At this time tx, current peak PK2c of current Ipp occurs due to the supply of external voltage VPP. The timing of occurrence of current peak PK2c of current Ipp in the third voltage generation mode is later than the timing of occurrence of current peak PK2b of current Ipp in the second voltage generation mode. For example, the timing of occurrence of current peak PK2c of current Ipp in the third voltage generation mode is a time (period) after time tx.

[0194] In this way, the waveforms of the currents Icc and Ipp generated at the start of voltage generation differ depending on the voltage generation mode of the charge pump circuit 171 in the voltage generation circuit 170.

[0195] (d) Summary A typical memory device performs a predetermined operation by selecting one of two modes: a mode in which an operating voltage is generated by boosting an external voltage VCC, and a mode in which an operating voltage is generated by adjusting (e.g., stepping down) an external voltage VPP that is higher than the external voltage VCC.

[0196] Furthermore, as a result of adopting negative voltages as the threshold voltages of memory cells, the upper limit values ​​of intermediate voltages such as the non-selection voltages VREAD and VPASS for which the external voltage VPP is used tend to decrease.

[0197] When the voltage generating circuit generates a voltage for operating the memory device using the external voltage VPP, it is difficult to reduce the power consumption of the memory device.

[0198] For example, as one indicator, when the ratio of the external voltage VCC to the external voltage VPP (VCC / VPP) is greater than the current efficiency (Ieff) of the charge pump, the power consumption in the operation mode using the external voltage VPP is smaller than the power consumption in the operation mode using the charge pump.

[0199] More specifically, it is shown by the following formulas (F1) to (F5).

[0200] When an external voltage VPP is used, the power consumption Ppp in the power supply of the external voltage VPP is expressed by the following formula (F1).

[0201] Ppp=VPP×Iout1 (F1) In equation (F1), "Iout1" is the current generated by the external voltage VPP.

[0202] When a voltage obtained by boosting an external voltage VCC using a charge pump is used, the power consumption Pext of the charge pump is expressed by the following equation (F2).

[0203] Pext=VCC×Iext =VCC × (Iout2 / Ieff) (F2) In equation (F2), "Iext" is the current flowing from the voltage terminal of the external voltage VCC to the input node of the charge pump, and "Iout2" is the current output from the output node of the charge pump.

[0204] From Equation (F2), the current efficiency of the charge pump is expressed as in the following Equation (F3).

[0205] Ieff = Iout2 / Iext ···(F3) When the relationship where the power consumption Ppp is less than the power consumption Pext (Ppp < Pext) is satisfied, the relationship of the following Equation (F4) is obtained.

[0206] VPP × Iout1 < VCC × (Iout2 / Ieff) ···(F4) Thus, based on Equation (F4), the relationship of the following Equation (F5) is obtained.

[0207] Ieff < VCC / VPP ···(F5) In this way, when the relationship of Equation (F5) is satisfied, the power consumption in the operation mode using the external voltage VPP becomes smaller than the power consumption in the operation mode using the charge pump.

[0208] The memory device 1 of the present embodiment includes a plurality of voltage generation modes. The memory device 1 of the present embodiment executes a voltage generation mode in which, during the generation of the operating voltage (during the output of the operating voltage) in the charge pump circuit 171 (voltage generation circuit 170), the operation is switched from the voltage generation by the charge pump 99 to the voltage generation by the external voltage VPP.

[0209] In this way, the memory device 1 of the present embodiment executes the voltage generation by the charge pump 99 before the voltage generation by the external voltage VPP during the voltage generation operation. As a result, the memory device 1 of the present embodiment can appropriately switch the operation mode of the voltage generation in the low voltage range of the charge pump circuit 171 of the voltage generation circuit 170. As a result, the memory device 1 of the present embodiment can reduce the power consumption generated when generating a voltage using the external voltage VPP.

[0210] Furthermore, when one of multiple modes for generating voltage can be selected, as in the memory device 1 of this embodiment, the memory device 1 can be operated in a mode that is more suitable for the specifications of the memory device and memory system.

[0211] As described above, the memory device of this embodiment can improve the characteristics of the memory device.

[0212] (2) Second embodiment A memory device according to a second embodiment will be described with reference to FIGS.

[0213] (a) Configuration example FIG. 17 is a circuit diagram showing the internal configuration of a charge pump circuit 171E of a voltage generating circuit 170 in the memory device 1 of this embodiment.

[0214] In FIG. 17, when the charge pump circuit 171E operates using the external voltage VPP, the charge pump circuit 171E charges the internal node of the charge pump 99 with the external voltage VPP.

[0215] As shown in FIG. 17, the charge pump circuit 171E includes a charge pump 99 and a regulator 179A.

[0216] The charge pump 99 includes a plurality of pump circuits 10 (10 <1> ,···,10 <p-1> ,10 ), and a switch circuit 15.

[0217] p pump circuits 10 <1> ,···,10 <p-1> ,10< / p-1> are connected in series between the voltage node ND0 of the voltage generating circuit 170 (charge pump circuit 171E) and the output node ND9 of the charge pump circuit 171E. p is a natural number equal to or greater than 2. One pump circuit 10 corresponds to one pump stage.

[0218] First (first stage) pump circuit 10 <1> The input node of the pth (final stage) pump circuit 10 is connected to the voltage node ND0. The output node of the charge pump 99 is connected to an output node ND9.

[0219] The switch circuit 15 is connected to the (p-1)th pump circuit 10 <p-1> and pth pump circuit 10< / p-1> The switch circuit 15 is provided between the output node ND9 and the voltage node ND0 supplied with the external voltage VCC. Substantially similar to the switch circuit 173A described above, the switch circuit 15 controls connection and isolation between the voltage node ND0 supplied with the external voltage VCC and the output node ND9. The switch circuit 15 includes a transistor TR0 and a level shifter LS.

[0220] The transistor TR0 is, for example, an N-type field effect transistor. One end of the current path of the transistor TR0 is connected to the (p-1)th pump circuit 10. <p-1> The other end of the current path of the transistor TR0 is connected to the output node of the p-th pump circuit 10< / p-1> is connected to the input node of

[0221] The output node of the level shifter LS is connected to the gate of the transistor TR0. The input node of the level shifter LS is connected to the output node of the p-th pump circuit. An enable signal ENB is supplied to the control node of the level shifter LS.

[0222] The level shifter LS is activated in response to the enable signal ENB. The activated level shifter LS converts the level of the voltage supplied to the input node of the level shifter LS. The activated level shifter LS supplies the voltage whose level has been converted from the output node of the level shifter LS to the gate of the transistor TR0.

[0223] The transistor TR0 is turned on or off depending on the voltage from the level shifter LS.

[0224] For example, when the charge pump voltage VPUMP of the charge pump 99 is selected according to the voltage generation mode of the charge pump circuit 171E, the level shifter LS is activated by the enable signal ENB, and the transistor TR0 is set to the ON state. is turned on by the transistor TR0 of the (p-1)th pump circuit 10 <p-1>is connected to.

[0225] For example, when the external voltage VPP is selected according to the voltage generation mode of the charge pump circuit 171E, the level shifter LS is deactivated by the enable signal ENB, and the transistor TR0 is set to the off state. is turned off by the transistor TR0 of the (p-1)th pump circuit 10 <p-1>is separated from

[0226] The regulator 179A is a linear regulator. The regulator 179A monitors the voltage (potential) of the output node ND9. The regulator 179A controls the voltage (potential) of the node ND10 by negative feedback control.

[0227] Regulator 179A includes operational amplifier OP1, transistors TR10 and TR11, and resistors R1, R2, and R3.

[0228] One node of the resistor R1 is connected to an output node ND9 of the charge pump circuit 171E. The other node of the resistor R1 is connected to a node ND10. One node of the resistor R2 is connected to the node ND10. The other node of the resistor R2 is connected to the ground node.

[0229] One input node (inverting input terminal) of operational amplifier OP1 is connected to node ND10. The other input node (non-inverting input terminal) of operational amplifier OP1 receives voltage VREF1. The output node of operational amplifier OP1 is connected to the gate of transistor TR10.

[0230] One end of the current path of the transistor TR10 is connected to the ground node, and the other end of the current path of the transistor TR10 is connected to a node ND11.

[0231] One node of the resistor R3 is connected to a node ND11, and the other node of the resistor R3 is connected to a voltage node ND1 of the voltage generating circuit 170 (charge pump circuit 171E).

[0232] The gate of the transistor TR11 is connected to the node ND11. One end of the current path of the transistor TR11 is connected to the voltage node ND1. The other end of the current path of the transistor TR11 is connected to the final stage pump circuit 10. and the output node of the switch circuit 15.

[0233] The external voltage VPP is applied to the voltage node ND1. The external voltage VPP is supplied from the regulator 179A to the final stage pump circuit 10. will be output.

[0234] The regulator 179A adjusts the magnitude (voltage value) of the voltage output from the charge pump circuit 171E according to the result of monitoring the voltage of the output node ND9.

[0235] In this embodiment, each pump circuit 10 includes at least two charge transfer switches SW1 and SW2, a capacitor Cap, and transistors DI1 and DI2.

[0236] Two charge transfer switches SW1 and SW2 are connected in series within the pump circuit 10. One node of one charge transfer switch SW1 is connected to the input node of the pump circuit 10. The other node of one charge transfer switch SW1 is connected to an internal node NDx of the pump circuit 10. One node of the other charge transfer switch SW2 is connected to the internal node NDx. ​​The other node of the other charge transfer switch SW2 is connected to the output node of the pump circuit 10.

[0237] One node of the capacitor Cap is connected to an internal node NDx. ​​The other node of the capacitor Cap is connected to a node (clock node) to which a clock signal (or an inverted signal of the clock signal) CLK is supplied. The other end of the capacitor Cap may be connected to a voltage node to which a predetermined voltage (for example, a voltage VCC) is applied.

[0238] The transistors DI (DI1, DI2) are connected in parallel to the charge transfer paths (current paths) of the charge transfer switches SW1 and SW2. The transistors DI are diode-connected. One end (drain) of the current path of the transistor DI is connected to the gate of the transistor DI. Hereinafter, the diode-connected transistors will also be referred to as diode-connected transistors.

[0239] One end of the current path of diode-connected transistor DI1 is connected to one node of charge transfer switch SW1, and the other end of the current path of diode-connected transistor DI1 is connected to the other node of charge transfer switch SW1.

[0240] One end of the current path of diode-connected transistor DI2 is connected to one node of charge transfer switch SW2, and the other end of the current path of diode-connected transistor DI2 is connected to the other node of charge transfer switch SW2.

[0241] The first to (p-1)th pump circuits 10 <1> ,···,10 <p-1>may not include the diode-connected transistor DI.

[0242] The charge transfer switches SW1 and SW2 include transistors TR1 and TR2 having the triple-well structure shown in FIG.

[0243] FIG. 18 is a circuit diagram showing a specific example of the internal configuration of the pump circuit 10.

[0244] As shown in FIG. 18, the pump circuit 10 includes charge transfer switches SW1-1, SW1-2, SW2-1, and SW2-2, transistors DI1-1, DI1-2, DI2-1, DI2-2, DI3-1, and DI3-2, transistors TR15-1, TR15-2, TR16-1, and TR16-2, and capacitors Cap-1, Cap-2, CapA-1, CapA-2, CapB-1, and CapB-2.

[0245] The charge transfer switch SW1-1 is an N-type field effect transistor. One end of the charge transfer path of the charge transfer switch SW1-1 is connected to the input node NDin of the pump circuit 10. The other end of the charge transfer path of the charge transfer switch SW1-1 is connected to an internal node NDx-1. The gate of the charge transfer switch SW1-1 receives a signal GNLH that corresponds to the potential fluctuation of a capacitor CapA-1 (described later) and the operation of a transistor TR15-1 (described later).

[0246] The charge transfer switch SW2-1 is a P-type field effect transistor. One end of the charge transfer path of the charge transfer switch SW2-1 is connected to an internal node NDx-1. The other end of the charge transfer path of the charge transfer switch SW2-1 is connected to an output node NDout of the pump circuit 10. The gate of the charge transfer switch SW2-1 receives a signal GPLH that corresponds to the potential fluctuation of a capacitor CapB-1 (described later) and the operation of a transistor TR16-1 (described later).

[0247] One node of the capacitor Cap-1 is connected to the internal node NDx-1, and the other node of the capacitor Cap-1 is connected to the clock node to which the clock signal CLK is supplied.

[0248] One node of the capacitor CapA-1 is connected to the gate of the charge transfer switch SW1-1, and the other node of the capacitor CapA-1 is connected to the clock node.

[0249] One node of the capacitor CapB-1 is connected to the gate of the charge transfer switch SW2-1, and the other node of the capacitor CapB-1 is connected to a node (inverted clock node) to which an inverted clock signal / CLK is supplied.

[0250] The transistor TR15-1 is an N-type field effect transistor. One end of the current path of the transistor TR15-1 is connected to the input node NDin. The other end of the current path of the transistor TR15-1 is connected to the gate of the charge transfer switch SW1-1. The gate of the transistor TR15-1 receives a control signal GNHL. The control signal GNHL is a signal that corresponds to the potential fluctuation of a capacitor CapA-2 (described later) and the operation of the transistor TR15-2 (described later).

[0251] The transistor TR16-1 is a P-type field effect transistor. One end of the current path of the transistor TR16-1 is connected to the gate of the charge transfer switch SW2-1. The other end of the current path of the transistor TR16-1 is connected to the output node NDout. The gate of the transistor TR16-1 receives a control signal GPHL. The control signal GPHL is a signal that corresponds to the potential fluctuation of a capacitor CapB-2 (described later) and the operation of the transistor TR16-2 (described later).

[0252] The diode-connected transistor DI1-1 is an n-type field effect transistor. The diode-connected transistor DI1-1 is connected in parallel to the charge transfer path (current path) of the charge transfer switch SW1-1. One end of the current path of the diode-connected transistor DI1-1 is connected to one end of the charge transfer path of the charge transfer switch SW1-1. The other end of the current path of the diode-connected transistor DI1-1 is connected to the other end of the charge transfer path of the charge transfer switch SW1-1. The gate of the diode-connected transistor DI1-1 is connected to one end of the current path of the diode-connected transistor DI1-1.

[0253] The diode-connected transistor DI2-1 is a p-type field effect transistor. The diode-connected transistor DI2-1 is connected in parallel to the charge transfer path of the charge transfer switch SW2-1. One end of the current path of the diode-connected transistor DI2-1 is connected to the other end of the charge transfer path of the charge transfer switch SW2-1. The other end of the current path of the diode-connected transistor DI2-1 is connected to one end of the charge transfer path of the charge transfer switch SW2-1. The gate of the diode-connected transistor DI2-1 is connected to one end of the current path of the diode-connected transistor DI2-1.

[0254] The diode-connected transistor DI3-1 is an n-type field effect transistor. The diode-connected transistor DI3-1 is connected in parallel to the current path of the transistor TR15-1. One end of the current path of the diode-connected transistor DI3-1 is connected to one end of the current path of the transistor TR15-1. The other end of the current path of the diode-connected transistor DI3-1 is connected to the other end of the current path of the transistor TR15-1. The gate of the diode-connected transistor DI3-1 is connected to one end of the current path of the diode-connected transistor DI3-1.

[0255] The charge transfer switch SW1-2 is an N-type field effect transistor. One end of the current path of the charge transfer switch SW1-2 is connected to the input node NDin of the pump circuit 10. The other end of the current path of the charge transfer switch SW1-2 is connected to an internal node NDx-2. The charge transfer switch SW1-2 receives a control signal GNHL.

[0256] The charge transfer switch SW2-2 is a P-type field effect transistor. One end of the current path of the charge transfer switch SW2-2 is connected to the internal node NDx-2. The other end of the current path of the charge transfer switch SW2-2 is connected to the output node NDout of the pump circuit 10. The charge transfer switch SW2-2 receives a control signal GPHL.

[0257] The charge transfer paths of the series-connected charge transfer switches SW1-2 and SW2-2 are connected in parallel to the charge transfer paths of the series-connected charge transfer switches SW1-1 and SW2-1.

[0258] One node of the capacitor Cap-2 is connected to the internal node NDx-2, and the other node of the capacitor Cap-2 is connected to the inverted clock node.

[0259] One node of the capacitor CapA-2 is connected to the gate of the charge transfer switch SW1-2, and the other node of the capacitor CapA-2 is connected to the inverted clock node.

[0260] One node of the capacitor CapB-2 is connected to the gate of the charge transfer switch SW2-2, and the other node of the capacitor CapB-2 is connected to the clock node.

[0261] The transistor TR15-2 is an N-type field effect transistor. One end of the current path of the transistor TR15-2 is connected to the input node NDin. The other end of the current path of the transistor TR15-2 is connected to the gate of the charge transfer switch SW1-2. The gate of the transistor TR15-2 receives the control signal GNLH.

[0262] The transistor TR16-2 is a P-type field effect transistor. One end of the current path of the transistor TR16-2 is connected to the gate of the charge transfer switch SW2-2. The other end of the current path of the transistor TR16-2 is connected to the output node NDout. The gate of the transistor TR16-2 receives the control signal GPLH.

[0263] The diode-connected transistor DI1-2 is an n-type field effect transistor. The diode-connected transistor DI1-2 is connected in parallel to the charge transfer path of the charge transfer switch SW1-2. One end of the current path of the diode-connected transistor DI1-2 is connected to one end of the charge transfer path of the charge transfer switch SW1-2. The other end of the current path of the diode-connected transistor DI1-2 is connected to the other end of the charge transfer path of the charge transfer switch SW1-2. The gate of the diode-connected transistor DI1-2 is connected to one end of the current path of the diode-connected transistor DI1-2.

[0264] The diode-connected transistor DI2-2 is a p-type field effect transistor. The diode-connected transistor DI2-2 is connected in parallel to the charge transfer path of the charge transfer switch SW2-2. One end of the current path of the diode-connected transistor DI2-2 is connected to the other end of the charge transfer path of the charge transfer switch SW2-2. The other end of the current path of the diode-connected transistor DI2-2 is connected to one end of the charge transfer path of the charge transfer switch SW2-2. The gate of the diode-connected transistor DI2-2 is connected to one end of the current path of the diode-connected transistor DI2-2.

[0265] The diode-connected transistor DI3-2 is an n-type field effect transistor. The diode-connected transistor DI3-2 is connected in parallel to the current path of the transistor TR15-2. One end of the current path of the diode-connected transistor DI3-2 is connected to one end of the current path of the transistor TR15-2. The other end of the current path of the diode-connected transistor DI3-2 is connected to the other end of the current path of the transistor TR15-2. The gate of the diode-connected transistor DI3-2 is connected to one end of the current path of the diode-connected transistor DI3-2.

[0266] A diode-connected transistor may be connected in parallel to the current paths of the transistors TR16-1 and TR16-2. Instead of the diode-connected transistor DI, a diode such as a PN junction diode may be connected in parallel to the charge transfer path of the charge transfer switch SW.

[0267] The operation of transistor TR15-1 is controlled by a control signal GNHL, the operation of transistor TR15-2 is controlled by a control signal GNLH, the operation of transistor TR16-1 is controlled by a control signal GPHL, and the operation of transistor TR16-2 is controlled by a control signal GPLH.

[0268] The pump circuit 10 performs a voltage boost (pumping operation) using a clock signal CLK supplied to the clock node and an inverted clock signal / CLK supplied to the inverted clock node.

[0269] When the operating voltage is generated using the external voltage VPP, the operation of the pump circuit 10 of the charge pump 99 is stopped.

[0270] When the external voltage VPP is selected as the output voltage of the charge pump circuit 171E, the external voltage VPP is supplied to the pump circuit 10 at the final stage of the charge pump 99. is output to the outside of the charge pump circuit 171E (voltage generating circuit 170) via the

[0271] The external voltage VPP is supplied to the final pump circuit 10 Pump circuit 10 In the pump circuit 10, the external voltage VPP passes through the current path of the diode-connected transistor DI. The pump circuit 10 functions as a path switch (voltage path) between the output node ND9 and the regulator 179A.

[0272] Final stage pump circuit 10 The nodes NDx, NDin, and NDout are charged by the supply of an external voltage VPP.

[0273] (b) Example of operation An example of the operation of the memory device 1 of this embodiment will be described with reference to FIGS.

[0274] FIG. 19 is a schematic diagram for explaining the operating state of the charge pump circuit 171E when the charge pump voltage VPUMP from the charge pump 99 is selected (output).

[0275] 19, the level shifter LS is activated by an enable signal ENB at a first level (for example, "H" level), which turns on the transistor TR0.

[0276] Final stage (pth) pump circuit 10 is supplied to the pump circuit 10 via the transistor TR0 in the on state. <1> ,···,10 <p-1>is connected to.

[0277] Voltage node ND1 is electrically isolated from charge pump 99 and node ND9 by switch circuit 173B in the off state.

[0278] The charge pump 99 boosts the external voltage VCC using a plurality of pump-stage pump circuits 10. The charge transfer switches SW1-1, SW1-2, SW2-1, and SW2-2 are activated by the control signals GNLH, GNHL, GPLH, and GPHL.

[0279] As a result, the charge pump voltage VPUMP is output from the charge pump 99 through the charge transfer path of the charge transfer switch SW.

[0280] The regulator 179A is connected to the pump circuit 10 This allows regulator 179A to adjust the voltage at node ND10 through negative feedback control.

[0281] The charge pump circuit 171E outputs a voltage VX from an output node ND9. For example, the voltage VX is supplied to the sense amplifier circuit 150.

[0282] FIG. 20 is a schematic diagram for explaining the operating state of the charge pump circuit 171E when the external voltage VPP is selected (output).

[0283] 20, the level shifter LS is deactivated by the enable signal ENB at a second level (for example, "L" level) different from the first level, which turns off the transistor TR0.

[0284] Final stage pump circuit 10 The transistor TR0 in the off state drives the pump circuit 10 <1> ,···,10 <p-1> The switch circuit 15 is electrically isolated from the pump circuit 10.< / p-1> The supply of external voltage VCC to

[0285] Voltage node ND1 is electrically connected to charge pump 99 and node ND9 by switch circuit 173B in the on state.

[0286] The external voltage VPP is supplied to the pump circuit 10 via the transistor TR11. are supplied to.

[0287] When the external voltage VPP is output in the voltage generation mode, the clock signal supplied to the clock node is stopped.The charge transfer switches SW1 and SW2 are deactivated by the control signals GNHL and GPHL.

[0288] As described above, in the voltage generating circuit 170 of the memory device 1 of this embodiment, the pump circuit 10 of the charge pump circuit 171E includes diode-connected transistors (diodes) DI1 and DI2 connected in parallel to the charge transfer switches SW1 and SW2.

[0289] Pump circuit 10 In the pump circuit 10 The external voltage VPP supplied to the pump circuit 10 passes through a diode-connected transistor DI. is transferred from the input node NDin to the output node NDout.

[0290] Final stage pump circuit 10 The nodes NDin, NDout, and NDx are charged by the external voltage VPP. This charges the source / drain layers 71 of the charge transfer switches SW1 and SW2. The voltage transfer path of the external voltage VPP via the voltage transfer circuit 179A is gradually charged by the monitoring operation of the regulator 179A.

[0291] In the regulator 179A, the operational amplifier OP1 supplies a signal corresponding to the voltage of the node ND10 to the gate of the transistor TR10. The transistor TR10 passes a current of a magnitude corresponding to the signal from the operational amplifier OP3. This causes the voltage of the node ND11 to fluctuate. The transistor TR11, with a driving force corresponding to the voltage of the node ND11, drives the external voltage VPP to the pump circuit 10. and transfers it to output node ND9 via

[0292] In this embodiment, the external voltage VPP is applied to the pump circuit 10 at the final stage of the charge pump 99. and output from the charge pump circuit 171E (voltage generating circuit 170).

[0293] In the second embodiment, an example of a charge pump circuit 171E that generates a voltage VX supplied to the sense amplifier circuit 150 is shown, but the circuit configurations of FIGS. 17 and 18 and the operations of FIGS. 19 and 20 may be applied to other charge pump circuits 171A, 171B, 171C, and 171D.

[0294] (c) Summary Depending on the operation mode of the charge pump circuit 171 in the voltage generating circuit 170, an external voltage VPP higher than the external voltage VCC is supplied to the output node ND9 of the voltage generating circuit 170 (charge pump circuit 171).

[0295] In a charge pump of a voltage generation circuit of a general memory device, when a low-voltage transistor is used as a charge transfer switch, a high external voltage VPP is applied to the source / drain of the low-voltage transistor in the final stage pump circuit. If the application of the external voltage VPP causes a breakdown of the low-voltage transistor, the low-voltage transistor may be destroyed.

[0296] In the memory device 1 of this embodiment, in the charge pump 99 in the charge pump circuit 171, the diode-connected transistor DI is connected in parallel to the charge transfer path of the charge transfer switch SW including a low-voltage transistor.

[0297] When the charge pump 99 is inactive (not driven), the diode-connected transistor DI charges the nodes NDx, NDin, and NDout of the charge transfer switch (low-voltage transistor) SW with the external voltage VPP transferred to the output node ND9 of the charge pump circuit 171E.

[0298] This allows the memory device 1 of this embodiment to avoid a breakdown voltage violation of the low breakdown voltage transistor SW(LV) in the voltage generating circuit 170 when generating a voltage.

[0299] As a result, the memory device 1 of this embodiment can prevent damage to the circuits within the memory device 1.

[0300] The memory device 1 of this embodiment can improve the reliability of the memory device 1 by suppressing damage to the circuits in the memory device 1.

[0301] As described above, the memory device 1 of this embodiment can improve the characteristics of the memory device.

[0302] (3) Third embodiment A memory device according to a third embodiment will be described with reference to FIGS.

[0303] (a) Configuration example FIG. 21 is a circuit diagram showing the internal configuration of the charge pump circuit 171A of the voltage generating circuit 170 in the memory device 1 of this embodiment.

[0304] 21 generates a program voltage VPGM and a voltage VPGMH equal to or greater than the program voltage VPGM during a program operation. The voltage VPGMH is supplied to a control terminal (gate terminal) of a transfer gate HV in the row control circuit 140. The supply of the voltage VPGMH enables the transfer gate HV to transfer the program voltage VPGM.

[0305] The charge pump circuit 171A in FIG. 21 can perform an operation for generating a voltage in an operation mode (hereinafter referred to as a low ripple mode) in which it is possible to output a voltage VPGM (and program voltage VPGM) with a low ripple.

[0306] As shown in FIG. 21, the charge pump circuit 171A includes a charge pump 99, regulators 179B and 179C, and a switch SX.

[0307] The charge pump 99 includes a plurality of pump circuits 10. As shown in Figures 17 and 18, the pump circuit 10 includes a plurality of charge transfer switches SW1 and SW2, a capacitor Cap, and a diode-connected transistor DI. The diode-connected transistor DI is connected in parallel to the charge transfer path of the charge transfer switch SW.

[0308] For example, in a charge pump 99 that generates a program voltage VPGM, an external voltage VPP may be supplied to the charge pump 99. A switch circuit 173B is provided between a voltage node ND1 and the charge pump 99. A switch circuit 173A is provided between a voltage node ND0 and the charge pump 99. The charge pump 99 boosts the supplied external voltage VPP to generate a voltage (for example, a voltage VPGMH) higher than the external voltage VPP.

[0309] The external voltage VPP may be transferred to the output nodes ND9A and ND9B of the charge pump circuit 171A (voltage generating circuit 170) without passing through the charge pump 99, depending on the voltage generating mode.

[0310] The regulator 179B is a linear regulator and includes an operational amplifier OP2, transistors TR20 and TR21, a variable resistor VR1, and resistors R20 and R21.

[0311] The transistor TR20 is an N-type field effect transistor. One end of the current path of the transistor TR20 is connected to an output node ND9A of the charge pump circuit 171A (the output node of the charge pump 99). The other end of the current path of the transistor TR20 is connected to a node ND20. The gate of the transistor TR20 is connected to a node ND21. The node ND20 is connected to an output node ND9B of the charge pump circuit 171A (the output node of the regulator 179B).

[0312] One node of the variable resistor VR1 is connected to a node ND20, and the other node of the variable resistor VR1 is connected to a node ND22.

[0313] One node of the resistor R20 is connected to the node ND22, and the other node of the resistor R20 is connected to the ground node.

[0314] One input node (non-inverting input terminal) of operational amplifier OP2 is connected to node ND22. The other input node (inverting input terminal) of operational amplifier OP2 receives voltage VREF2. The output node of operational amplifier OP2 is connected to the gate of transistor TR21.

[0315] The transistor TR21 is an N-type field effect transistor. One end of the current path of the transistor TR21 is connected to a node ND21. The other end of the current path of the transistor TR22 is connected to the ground node.

[0316] One node of the resistor R21 is connected to the node ND21, and the other node of the resistor R21 is connected to the output node ND9A.

[0317] The regulator 179B receives the voltage VPGMH. The regulator 179B adjusts and steps down the voltage VPGMH through the operation of the operational amplifier OP2. As a result, the regulator 179B outputs a program voltage VPGM that is equal to or lower than the voltage VPGMH.

[0318] The regulator 179C is a linear regulator and includes operational amplifiers OP3, OP4, and OP5, transistors TR25 and TR26, a variable resistor VR2, resistors R25, R26, R27, and R28, and switches S20 and S21.

[0319] One node of the variable resistor VR2 is connected to the output node ND9A, and the other node of the variable resistor VR2 is connected to the node ND25.

[0320] One node of the resistor R25 is connected to a node ND25, and the other node of the resistor R25 is connected to the ground node.

[0321] One input node (non-inverting input terminal) of operational amplifier OP3 is connected to node ND25. The other input node (inverting input terminal) of operational amplifier OP3 receives voltage VREF3. The output terminal of operational amplifier OP3 is connected to the gate of transistor TR25.

[0322] The transistor TR25 is an N-type field effect transistor. One end of the current path of the transistor TR25 is connected to the ground node. The other end of the current path of the transistor TR25 is connected to a node ND26.

[0323] One node of the resistor R26 is connected to a node ND26, and the other node of the resistor R26 is connected to a node ND27.

[0324] The transistor TR26 is a depletion-type transistor. The gate of the transistor TR26 is connected to a node ND26. One end of the current path of the transistor TR26 is connected to a node ND27. The other end of the current path of the transistor TR26 is connected to one node of a switch S20. The other node of the switch S20 is connected to an output node ND9A of the charge pump circuit 171A. The switch S20 is turned on and off in response to a control signal CNT20.

[0325] One node of the switch S21 is connected to the node ND27. The other node of the switch S21 is connected to the (p-1)th pump circuit 10 <p-1>and an input node of the switch circuit 15. The switch S21 is turned on and off in response to a control signal CNT21.

[0326] One node of the resistor R27 is connected to a node ND27. The other node of the resistor R27 is connected to a node ND28. One node of the resistor R28 is connected to the node ND28. The other node of the resistor R28 is connected to the ground node.

[0327] The operational amplifier OP4 is a comparator. One input node of the operational amplifier OP4 is connected to the node ND28. The other input node of the operational amplifier OP4 receives the voltage VREF4. The output node of the operational amplifier OP4 is connected to one input node of the multiplexer MX.

[0328] The operational amplifier OP5 is a comparator. One input node of the operational amplifier OP5 is connected to the node ND25. The other input node of the operational amplifier OP5 receives the voltage VREF5. The output node of the operational amplifier OP5 is connected to the other input node of the multiplexer MX.

[0329] The output node of the multiplexer MX is connected to the control node of each pump circuit 10. The multiplexer MX selects one of the outputs of the two operational amplifiers OP4 and OP5 in response to a control signal SEL. The pump circuit 10 performs an operation according to the output signal of the multiplexer MX.

[0330] The regulator 179C adjusts the voltage in the low ripple mode. The regulator 179C adjusts the voltage in the (p-1)th pump circuit 10 in the low ripple mode. <p-1>For example, the voltage generated in low ripple mode is adjusted by adjusting the voltage output from the first pump circuit 10. <1> to (p-1)th pump circuit 10 <p-1>It is generated by the operations up to

[0331] One node of the switch SX is connected to the output node ND9A. The other node of the switch SX is connected to the pump circuit 10 in the final stage. The switch SX is connected between the input node of the (p-1)th pump circuit 10 and the switch circuit 15. The switch SX is turned on and off in response to a control signal CNTX. The switch SX is set to an off state when the charge pump circuit 171A is operating to generate voltages in the above-mentioned multiple voltage generation modes. The switch SX is set to an on state when the charge pump circuit 171A is in the low ripple mode. The on-state switch SX controls the (p-1)th pump circuit 10 <p-1> The output voltage of the final stage pump circuit 10 in the inactive state (non-driving state)< / p-1> The voltage from the switch SX is supplied to the pump circuit 10 In this state, the charge transfer switch SW including the low-voltage transistor is charged.

[0332] (b) Example of operation An example of the operation of the memory device of this embodiment will be described with reference to FIGS.

[0333] (b-1) Voltage generation mode FIG. 22 is a schematic diagram for explaining the operating state of the charge pump circuit 171A when the charge pump 99 outputs the charge pump voltage VPUMP.

[0334] As shown in FIG. 22, in the regulator 179C, the switches S20 and S21 are set to the off state by the control signals CNT20 and CNT21. The switch SX is set to the off state by the control signal CNTX. For example, in the regulator 179C, the multiplexer MX selects the signal from the operational amplifier OP5 by the control signal SEL. The operational amplifier OP5 outputs a signal having a level corresponding to the voltage of the node ND25 to the multiplexer MX. The multiplexer MX supplies the selected signal as a control signal to each pump circuit 10. The pump circuits 10 operate in response to the signal from the multiplexer MX.

[0335] The switch circuit 15 is set to the ON state. is the pump circuit 10 in the latter stage. <p-1>In the charge pump 99, the external voltage VCC is boosted by a plurality of pump circuits 10. The charge pump 99 supplies the boosted voltage to output nodes ND9A and ND9B.

[0336] The charge pump circuit 171A outputs the charge pump voltage VPUMP as a voltage VPGMH from an output node ND9A to the row control circuit 140.

[0337] The regulator 179B adjusts (e.g., steps down) the charge pump voltage VPUMP. In the regulator 179B, the operational amplifier OP2 supplies a signal corresponding to the voltage of the node ND22 to the gate of the transistor TR21. The transistor TR21 passes a current corresponding to the signal from the operational amplifier OP2. The transistor TR20 passes a current corresponding to the voltage of the node ND21. This adjusts the magnitude of the voltage supplied to the output node ND9B according to the driving force of the transistor TR20.

[0338] The charge pump circuit 171A outputs the voltage regulated by the regulator 179B to the row control circuit 140 from the output node ND9B as the program voltage VPGM.

[0339] In this manner, the charge pump voltage VPUMP from the charge pump 99 is supplied to the memory cell array 110.

[0340] The external voltage VPP may be boosted by a charge pump 99 to generate the voltages VPGMH and VPGM.

[0341] In addition, when the memory device 1 is in operation and the operation of the charge pump 99 (or a part of the charge pump 99) is stopped, the external voltage VPP is supplied to the final stage pump circuit 10 by the diode-connected transistor DI. The voltage may be supplied to the source / drain of the charge transfer switch SW in the semiconductor device, thereby preventing the charge transfer switch SW from being destroyed.

[0342] (b-2) Low ripple mode FIG. 23 is a schematic diagram for explaining the operating state of the charge pump circuit 171A in the low ripple mode in the memory device 1 of this embodiment.

[0343] As shown in FIG. 23, when the charge pump circuit 171A operates in the low ripple mode, the switches S20 and S21 are set to the on state by the control signals CNT20 and CNT21.

[0344] The switch circuit 15 is set to the OFF state. is electrically isolated from the voltage node ND0. The pump circuit 10 in the previous stage <p-1>The voltage supply from

[0345] (p-1)th pump circuit 10 <p-1>are connected to the output nodes ND9A and ND9B via the switches S20 and S21 that are in the ON state. <p-1>supplies the voltage VLL to the output nodes ND9A and ND9B via the regulator 179C.

[0346] The regulator 179C is connected to the pump circuit 10 <p-1>The regulator 179C monitors the voltage output from the node ND25 (the voltage at the output node ND9A). In the regulator 179C, the operational amplifiers OP3 and OP5 operate in response to the voltage at the node ND25. The operational amplifier OP3 supplies a signal corresponding to the voltage at the node ND25 to the gate of the transistor TR25. The transistor TR25 passes a current whose magnitude corresponds to the signal from the operational amplifier OP3. The voltage at the node ND26 fluctuates in response to the current passed by the transistor TR25. The transistor TR26 operates by a driving force corresponding to the voltage at the node ND26, <p-1>Transfers voltage from

[0347] The multiplexer MX selects the output of the operational amplifier OP4 based on the control signal SEL. The operational amplifier OP4 outputs a signal having a level corresponding to the voltage of the node ND28 to the multiplexer MX. The multiplexer MX supplies the signal from the operational amplifier OP4 to the pump circuit 10. The pump circuit 10 operates in response to the signal from the multiplexer MX.

[0348] The regulator 179C sends the regulated voltage VLL to the output node ND9A. The voltage VLL is output from the charge pump circuit 171A.

[0349] The regulator 179B further adjusts the voltage VLL output from the regulator 179C. The charge pump circuit 171A outputs the adjusted voltage from the output node ND9B.

[0350] In the low rip mode, the charge pump circuit 171A of the voltage generating circuit 170 supplies the generated voltage to the word lines WL in the memory cell array 110 via the row control circuit 140.

[0351] In this embodiment, in the low ripple mode, the switch SX is set to the on state by the control signal CNTX. The input node of is connected to the output node of regulator 179C.

[0352] The switch SX in the ON state receives the voltage output from the regulator 179C (pump circuit 10 <p-1> The voltage output from the pump circuit 10< / p-1> Supply to.

[0353] Pump circuit 10 in an inactive state (non-driven state) In the pump circuit 10, the diode-connected transistor DI supplies the voltage transferred from the switch SX to the source / drain (node) of the charge transfer switch SW. This charges the source / drain of the charge transfer switch SW. As a result, Each node in is charged.

[0354] In this embodiment, an example of a charge pump circuit 171A that generates various voltages VPGMH and VPGM during program operation is shown, but the circuit configurations and operations shown in Figures 21 to 23 may be applied to other charge pump circuits 171B, 171C, 171D, and 171E.

[0355] (c) Summary In the memory device 1 of this embodiment, the pump circuit 10 of the charge pump 99 includes a diode-connected transistor DI. The diode-connected transistor DI is connected in parallel to the charge transfer path of the charge transfer switch SW.

[0356] In the low ripple mode, the final stage pump circuit 10 is the pump circuit 10 in the previous stage. <p-1>is electrically isolated from

[0357] In this embodiment, the switch SX is connected to the pump circuit 10 and a regulator 179C that outputs a voltage VLL.

[0358] The voltage VLL generated by the low ripple mode is supplied to the final stage pump circuit 10 via the switch SX. The diode-connected transistor DI couples the voltage VLL to the pump circuit 10 This causes the internal nodes (e.g., source / drain) of the charge transfer switches of the pump circuit 10 to be charged.

[0359] As a result, the memory device 1 of this embodiment can prevent breakdown of the charge transfer switch SW in the charge pump 99 during operation in a low ripple mode or the like.

[0360] As described above, the memory device 1 of this embodiment can improve the characteristics of the memory device.

[0361] (4) Variations A modification of the memory device of this embodiment will be described with reference to FIG.

[0362] 24 is a cross-sectional view showing the structure of a modified example of the memory device 1 of this embodiment. In FIG. 24, the interlayer insulating film that covers the elements and wiring of the memory device 1 is omitted.

[0363] As shown in FIG. 24, the memory device 1 of the embodiment may have a laminated structure.

[0364] The laminated memory device 1 has a structure in which a chip (hereinafter referred to as a memory cell array chip) 1000 on which a memory cell array 110 is formed is laminated to a chip (hereinafter referred to as a CMOS chip) 2000 on which a CMOS circuit is formed. Peripheral circuits of the memory device 1, such as a row control circuit 140, a sense amplifier circuit 150, and a voltage generation circuit 170, are formed on the CMOS chip 2000.

[0365] For example, the transfer gate (high-voltage transistor) HV of the row control circuit 140 is provided on the semiconductor substrate 60 together with the transistor TR used in the charge pump circuit 171.

[0366] The transfer gate HV has a triple well structure. In the area where the transfer gate HV is formed, an N-type well 61X is provided in the semiconductor substrate 60. A P-type well 62X is provided in the N-type well 61X. The N-type well 61X surrounds the P-type well 62X.

[0367] The transfer gate HV is disposed on the P-type well 62X. The transfer gate HV includes two source / drain layers 71X, a gate insulating film 72X, and a gate electrode 73X.

[0368] A source / drain layer (diffusion layer, impurity region) 71X is provided in a P-type well 62X. A gate insulating film 72X is provided on the P-type well 62X. The gate insulating film 72X is disposed on a channel region between two source / drain layers 71X. A gate electrode 73X is provided on the gate insulating film 72X. The gate electrode 73X faces the channel region via the gate insulating film 72X.

[0369] The thickness tkn of the gate insulating film 72n of the transistor TR1 and the thickness tkp of the gate insulating film 72p of the transistor TR2 are thinner than the thickness tkx of the gate insulating film 72X of the transfer gate HV. This makes the breakdown voltage of the transfer gate HV higher than the breakdown voltages of the transistors TR1 and TR2.

[0370] In the memory device 1 with a bonded structure, the two chips 1000 and 2000 are in contact with each other at a surface BF between the chips (hereinafter referred to as a bonding surface).

[0371] At the bonding surface BF, the memory cell array chip 1000 includes a plurality of pads (hereinafter referred to as bonding pads) BP1 for bonding the chips 1000 and 2000 together on one surface of the chip in the Z direction (for example, the top surface of the chip 1000).

[0372] At the bonding surface BF, the CMOS chip 2000 includes a plurality of pads (bonding pads) BP2 for bonding the chips 1000 and 2000 together on one surface of the chip 2000 in the Z direction (for example, the top surface of the chip 2000).

[0373] The bonding pads BP1 and BP2 are conductors containing copper (Cu), and include active pads connected to elements (wiring) and dummy pads not connected to elements.

[0374] The bonding pad BP1 of the memory cell array chip 1000 is bonded to the bonding pad BP2 of the CMOS chip 2000 by covalent bonds formed between the members forming the pads BP1 and BP2.

[0375] As a result, the memory cell array chip 1000 is bonded to the CMOS chip 2000 in the memory device 1 of this embodiment.

[0376] The memory device 1 of this modification includes the above-described voltage generating circuit 170 and charge pump circuit 171. The memory device 1 of this modification can obtain the effects of the above-described embodiment.

[0377] (5) Other In the memory devices of the above-described embodiments, a voltage generation circuit including a charge pump and a regulator for generating a specific voltage is exemplified. However, the configuration and function of the voltage generation circuit in the memory device of the present embodiment are not limited to the type of charge pump and the type of regulator.

[0378] The memory device of this embodiment may be a memory device other than a NAND flash memory.

[0379] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0380] 1: memory device, 110: memory cell array, 170: voltage generation circuit, 171, 171A, 171B, 171C, 171D, 171E: charge pump circuit, 179, 179A, 179B, 179C, 179Z: regulator, 10: pump circuit, SW1, SW2: charge transfer switch, DI: diode-connected transistor. < / p-1>

Claims

1. a memory cell array including a plurality of memory cells; a voltage generating circuit that receives a first external voltage and a second external voltage higher than the first external voltage and generates an operating voltage for the memory cell array; Equipped with an operation mode of the voltage generating circuit including a first mode in which a first voltage value of the operating voltage is generated, the first mode including a first period and a second period after the first period, the first external voltage being used in the first period, and the second external voltage being used in the second period; Memory device.

2. an operation mode of the voltage generating circuit that increases the first external voltage during the first period and decreases the second external voltage during the second period; The memory device of claim 1 .

3. a first terminal to which the first external voltage is supplied and through which a first current flows; a second terminal to which the second external voltage is supplied and through which a second current flows; In the first mode, the first current has a first peak during the first period from the start of generating the operating voltage; the second current has a second peak within the second period; The memory device of claim 1 .

4. the operation modes of the voltage generation circuit further include a second mode in which the operation voltage is generated using the first external voltage when generating the first voltage value of the operation voltage; In the second mode, the first current has a third peak during a third period from the start of generating the operating voltage; the first period is shorter than the third period; The memory device of claim 3 .

5. The voltage generating circuit a charge pump that boosts the first external voltage; a regulator that adjusts the second external voltage; a first switch circuit provided between the charge pump and the regulator; a second switch circuit provided between the regulator and a voltage node to which the second external voltage is supplied; Including, The memory device of claim 1 .

6. the charge pump includes a first transistor; The first transistor is a semiconductor substrate of a first conductivity type; a first well of a second conductivity type different from the first conductivity type provided in the semiconductor substrate; a second well of the first conductivity type provided within the first well; first and second source / drain layers provided in the second well; a first gate insulating film provided on a channel region between the first and second source / drains; a first gate electrode provided on the first gate insulating film; Including, The memory device of claim 5 .

7. A transfer gate connected to a word line of the memory cell array Furthermore, the first gate insulating film is thinner than the gate insulating film of the transfer gate; The memory device of claim 6.

8. the voltage generation circuit generates a voltage to be applied to an unselected word line in the memory cell array during a read operation or a write operation; The memory device of claim 1 .

9. a memory cell array including a plurality of memory cells; a voltage generating circuit including a first node to which a first external voltage is supplied, a second node to which a second external voltage higher than the first external voltage is supplied, and a third node to which an operating voltage of the memory cell array is output, the voltage generating circuit generating the operating voltage using at least one of the first and second external voltages; Equipped with the voltage generating circuit includes a plurality of pump circuits connected in series between the first node and the third node, and configured to boost the first external voltage; A first pump circuit of the plurality of pump circuits connected to the third node comprises: one or more charge transfer switches connected between the first node and the third node; one or more diode-connected transistors connected in parallel to the charge transfer path of the charge transfer switch; Including, Memory device.

10. The voltage generating circuit a second pump circuit disposed between the first node and the first pump circuit; a first switch provided between an input node of the first pump circuit and an output node of the second pump circuit; Including, The memory device of claim 9.

11. When the first pump circuit is stopped, the charge transfer path of the charge transfer switch is charged via the diode-connected transistor. The memory device of claim 9.

12. the voltage generating circuit further includes a first regulator that adjusts the second external voltage; the charge transfer path of the charge transfer switch is charged by a voltage supplied from the first regulator to the first pump circuit via the diode-connected transistor; The memory device of claim 9.

13. The voltage generating circuit a second pump circuit disposed between the first node and the first pump circuit; a first switch provided between an input node of the first pump circuit and an output node of the second pump circuit; a second regulator provided between an output node of the second pump circuit and the third node; a second switch connected between an output node of the second regulator and the input node of the first pump circuit; further comprising: The memory device of claim 9.

14. When the first switch is in an off state and the second switch is in an on state, the second regulator supplies a voltage from the second pump circuit to the charge transfer switch of the first pump circuit via the second switch in an on state; The memory device of claim 13.

15. The charge transfer switch a first well of a second conductivity type provided in a semiconductor substrate of a first conductivity type; a second well of the first conductivity type provided within the first well; first and second source / drain layers provided in the second well; a first gate insulating film provided on a channel region between the first and second source / drains; a first gate electrode provided on the first gate insulating film; Including, The memory device of claim 9.

16. A transfer gate connected to a word line of the memory cell array Furthermore, a gate insulating film of the charge transfer switch is thinner than a gate insulating film of the transfer gate; The memory device of claim 9.

17. the first pump circuit further includes a first capacitor; the one or more charge transfer switches include a first charge transfer switch and a second charge transfer switch; the one or more diode-connected transistors include a first diode-connected transistor and a second diode-connected transistor; one end of a charge transfer path of the first charge transfer switch is connected to an input node of the first pump circuit, and the other end of the charge transfer path of the first charge transfer switch is connected to an internal node of the first pump circuit; one end of the charge transfer path of the second charge transfer switch is connected to the internal node, and the other end of the charge transfer path of the second charge transfer switch is connected to an output node of the first pump circuit; one end of the first diode-connected transistor is connected to the one end of the charge transfer path of the first charge transfer switch, the other end of the first diode-connected transistor is connected to the other end of the charge transfer path of the first charge transfer switch, and a gate of the first diode-connected transistor is connected to the one end of the first diode-connected transistor; one end of the second diode-connected transistor is connected to the other end of the charge transfer path of the second charge transfer switch, the other end of the second diode-connected transistor is connected to the one end of the charge transfer path of the second charge transfer switch, and a gate of the second diode-connected transistor is connected to the one end of the second diode-connected transistor; one end of the first capacitor is connected to the internal node; The memory device of claim 9.

18. the first pump circuit further includes a first transistor, a second transistor, a second capacitor, and a third capacitor; the one or more diode-connected transistors further include a third diode-connected transistor; one end of the first transistor is connected to the one end of the charge transfer path of the first charge transfer switch, and the other end of the first transistor is connected to a gate of the first charge transfer switch; one end of the second transistor is connected to the other end of the charge transfer path of the second charge transfer switch, and the other end of the second transistor is connected to a gate of the second charge transfer switch; one end of the third diode-connected transistor is connected to the one end of the charge transfer path of the first charge transfer switch, the other end of the third diode-connected transistor is connected to the gate of the first charge transfer switch, and the gate of the third diode-connected transistor is connected to the one end of the third diode-connected transistor; one end of the second capacitor is connected to the gate of the first charge transfer switch; one end of the third capacitor is connected to the gate of the second charge transfer switch; 20. The memory device of claim 17.

19. a memory cell array including a plurality of memory cells; a voltage generating circuit including a first node to which a first external voltage is supplied, a second node to which a second external voltage higher than the first external voltage is supplied, and a third node to which an operating voltage of the memory cell array is output, the voltage generating circuit generating the operating voltage using at least one of the first and second external voltages; Equipped with the voltage generating circuit boosts the first external voltage and includes a plurality of pump circuits connected in series between the first node and the third node; When generating the operating voltage using the second external voltage, the voltage generating circuit charges a first pump circuit connected to the third node among the plurality of pump circuits. Memory device.

20. the voltage generating circuit further includes a first regulator that adjusts the second external voltage; a charge transfer path of the first pump circuit is charged by a voltage output from the first regulator; 20. The memory device of claim 19.

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